Intel Xeon E5450 manuel d'utilisation

318589-005 Quad-Core Intel® Xeon® Processor 5400 Series Datasheet August 2008[...]

2 Quad-Core Intel® Xeon® Processor 5400 Series Datasheet INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL ® PRODUCTS. NO LIC ENSE, EXPRESS OR IMPLIED , BY ESTOPPEL OR O THERWISE, TO ANY INTELLECTUAL PROPER TY RIGHTS IS GRANTED BY THIS DOCUMENT . EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDIT IONS OF SALE FOR SUCH PRODU CTS[...]

Quad-Core Intel® Xeon® Processor 5400 Series Datasheet 3 Contents 1I n t r o d u c t i o n ......... ............. ............... ............ ............... ............. .............. ............. ...... 9 1.1 Terminology ........... ............ ............... ............... ............... ............ ............... ...... 10 1.2 Stat[...]

4 Quad-Core Intel® Xeon® Processor 5400 Series Datasheet 6.2.1 Intel ® Thermal M onitor Features ................. ............... .............. ............... .. 90 6.2.2 On-Demand Mod e ......... ............... ............. ............... .............. ............. .... 92 6.2.3 PROCHOT# Signal ...... ............... ............. .....[...]

Quad-Core Intel® Xeon® Processor 5400 Series Datasheet 5 Figures 2-1 Input Device Hy steresis ............ .............. ............... ............... ............... .............. 25 2-2 Quad-Core Intel® Xe on® Processor X5482 Load Current versus Time .............. ........ 30 2-3 Quad-Core Intel® Xe on® Processor X5400 Series Load Curr[...]

6 Quad-Core Intel® Xeon® Processor 5400 Series Datasheet Tables 1-1 Quad-Core Intel® X eon® Processor 5400 Series . ................... ................ ...............10 2-1 Core Frequency to FSB Multiplier Configuration .... .............. ............. ............... ........ 17 2-2 BSEL[2:0 ] Frequency Table ..... ............... .........[...]

Quad-Core Intel® Xeon® Processor 5400 Series Datasheet 7 Revision History § Revision Description Date 001 Initial release November 2007 002 Added product information fo r the Quad-Core Intel® X eon® Processor L5408. March 2008 003 Added product information fo r the Quad-Core Intel® X eon® Processor L5400 Series. April 2008 004 Corrected L1 c[...]

8 Quad-Core Intel® Xeon® Processor 5400 Series Datasheet[...]

9 1 Introduction The Quad-Core Intel® X eon® Proce ssor 5400 Se ries is a server/workstation processor utilizing four 45-nm Hi-k next generation Intel® Core™ microarchitecture cores. The processor is manufactured on Intel’ s 45 nanometer process technology combining high performance with the power efficiencies of a low-power microarchitectur[...]

10 solutions. Intel Virtualization T echnology is used in conjunction with Virtual Machine Monitor software enabling multiple, independent softw are environments inside a single platform. Further details on Intel Virtualization T echnology can be found at http://developer .intel.com/technology/platform-technology/virtualization/index.htm . The Quad[...]

11 Commonly used terms are explained here for clarification : • Quad-Core Intel® Xeon® Processor 5400 Series - Intel 64-bit microprocessor intended for dual processor servers and workstations based on Intel’ s 45 nanometer process, in the PC-LGA 771 pack age with four processor cores. For this document “processors” is used as the ge neric[...]

12 • Processor core – Processor core with integrated L1 cache. L2 cache and system bus interface are shared between the two core s on the die. All AC timing and signal integrity specifications are at the pads of the system bus interface. • Front Side Bus (FSB) – The electrical interface that connects the processor to the chipset. Also refer[...]

13 • VRM (Volt age Regulato r Module) – DC-DC converter built onto a module that interfaces with a card edge socket and supplies the correct voltage and cu rrent to the processor based on the logic state of the processor VID bits. • EVRD (Enterprise Voltag e Regulator Down) – DC -DC converter integr ated onto the system board that provides [...]

14[...]

15 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 2 Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 2.1 Front Side Bus and GTLREF Most Quad-Core Intel® X eon® Processor 5400 Series FSB signals use Assisted Gunning T ransceiver Logic (AGTL+) signalin g technology . This technology provides improv[...]

Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 16 2.2 Power and Ground Lands For clean on-chip processor core power distribution, the processor has 223 V CC (power) and 267 V SS (ground) inputs. All V CC lands must be connected to the processor power plane, while all V SS lands must be connected to the system ground plane[...]

17 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core freque ncy of the processor . As in previous processor ge nerations, the Quad-Core Intel® Xeon® Processor 5400 Series core frequency is a m[...]

Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 18 2.4.2 PLL Power Supply An on-die PLL filter solution is implemented on the Quad-Core Intel® Xeon® Processor 5400 Series. The V CCPLL input is used for this configuration in Quad-Cor e Intel® Xeon® Processor 5400 Series-based platforms. Please refer to Ta b l e 2 - 1 2 [...]

19 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications The Quad-Core Intel® Xeon® Processor 5400 Series provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (V CC ). This will represent a DC shift in the load line. It should be noted that a low-to-high or high-to-lo[...]

Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 20 Notes: 1. When the “111111” VID pattern is observed, th e voltage regulator output should be disabled. 2. Shading denotes the expected VID range of the Quad-Core Intel® Xeon® Processor 5400 Series . 3. The VID r ange includes VID tr ansitions th at may be initiated b[...]

21 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications Note: The LL_ID[1:0] si gnals are used to select t he correct loadline s lope for the proces sor . Note: The MS_ID[1:0] signals are provided to indicate the Market Segment for the processor an d may be used for future processor co mpatibi lity or for keying. 2.6 Reserved, [...]

Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 22 The TESTHI signals must use individual pull-up resistors as detailed below . A matched resistor must be used for each signal: • TESTHI10 – cannot be groupe d with other TESTHI signals • TESTHI11 – cannot be groupe d with other TESTHI signals • TESTHI12 - cannot b[...]

23 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications Notes: 1. Refer to Chapter 5 for signal descriptions. 2. These signals ma y be driven simultane ous ly by multiple agents (Wired-OR). Ta b l e 2 - 7 outline s the signals which include on-die termination (R TT ). Ta b l e 2 - 8 outlines non AGTL+ signals including open dra[...]

Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 24 2.8 CMOS Asynchronous and Open Drain Asynchronous Signals Legacy input signals such as A20M#, IGNNE#, INIT#, SMI# , and STPCLK# utilize CMOS input buffers. Legacy output sign al s such as FERR#/PBE#, IERR#, PROCHOT#, and THERMTRIP# utilize open drain output bu ffers. All o[...]

25 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications Note: 1. V TT supplies the PECI interface. PECI behavior does not affect V TT min/max specifications. 2. The leakage specification applies to p owered devices on the PECI bus. 3. One node is counted for each client and one node for the sys tem host. Extended tr ace lengths[...]

Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 26 2.11 Mixing Processors Intel supports and validates dual proce ssor configurations only in which both processors operate with the same FSB frequency , core frequency , power segments, and have the same internal cache siz es. Mixing components operating at different interna[...]

27 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications Notes: 1. For functio nal operation, all processor electri cal, sign al quality , mechanical and thermal specifications must be satisfied. 2. Overshoot and u ndershoot volta ge guidelines for input, output, an d I/O signals a re outlined in Chapter 3 . Excessive overshoot [...]

Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 28 Table 2-12. Voltage and Current Sp ecifications (Sheet 1 of 2) Symbol Parameter Min Typ Max Unit Notes 1, 11 VID VID range 0.850 1.3500 V V CC V CC for processor core Launch - FMB See Ta b l e 2 - 1 3 and Ta b l e 2 - 1 4 ; Figure 2-7 , Figur e 2-8 , Figure 2-9 , Figure 2-[...]

29 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications Notes: 1. Unless otherwise noted, all specifications in this table are based on final silic on characterization data. 2. These voltages are targets only . A variable vo ltage source should exist on syste ms in the event that a different voltage is required. See Section 2.5[...]

Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 30 3. The voltage spec ification requirem ents are meas ured ac ross the VCC_D IE_SENSE and VSS_DIE_SENSE lands and across the VCC_DIE_SENSE2 and VSS_DIE _SE NSE2 lands with an osci lloscope set to 100 MHz bandwidth, 1.5 pF maximum p robe capacitance, and 1 M Ω minimum imped[...]

31 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications Notes: 1. Processor or V oltage Regulator thermal protec tion circuitry should not trip for load cur rents greater than I CC_TDC . 2. Not 100% tested. Specified by design characterization. Notes: 1. Processor or V oltage Regulator thermal protec tion circuitry should not t[...]

Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 32 Notes: 1. Processor or V oltage Regulator thermal protectio n circ uitry should not trip for load currents greater than I CC_TDC . 2. Not 100% tested. Specified by design characterization. Figure 2-5. Quad-Core Intel® Xeon® Processor L5400 Series Load Current versus Time[...]

33 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications Notes: 1. The V CC_MIN and V CC_MA X loadlines represent stati c and transient limits. Please see Section 2.13.2 for V CC over shoot specification s. 2. This table is intended to ai d in reading discre te points on Figure 2-7 . 3. The loadlines specify voltage limits at th[...]

Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 34 Notes: 1. The V CC_MIN and V CC_MAX loadlines represent static an d transient limits. Please see Section 2.13.2 for V CC overshoot specifications. 2. This table is intended to ai d in reading discrete points on Figure 2-8 and Figure 2-9 . 3. The loadlines specify v oltage [...]

35 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications Figure 2-7. Qu ad-Core Intel® Xeon® Processor X5482 V CC Static and Transient Tolerance Load Lines VI D - 0.00 0 VI D - 0.05 0 VI D - 0.10 0 VI D - 0.15 0 VI D - 0.20 0 VI D - 0.25 0 0 5 10 15 20 25 30 35 40 45 5 0 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 1[...]

Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 36 Figure 2-8. Quad-Core Intel® Xe on® Processor X5400 Series V CC Static and Transient Tolerance Load Lines Figure 2-9. Quad-Core Intel® Xe on® Processor E5400 Series V CC Static and Transient Tolerance Load Lines VID - 0. 000 VID - 0. 020 VID - 0. 040 VID - 0. 060 VID -[...]

37 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications Notes: 1. The V CC_MIN and V CC_MAX loadlines represent static and transient limits. Pleas e see Section 2.13.2 for VCC over shoot specification s. 2. Refer to Ta b l e 2 - 1 2 for processor VID information. 3. Refer to Ta b l e 2 - 1 3 for V CC Static and T r ansient T ol[...]

Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 38 Notes: 1. Unless otherwise noted, all specifications in this table apply to a ll processor freque ncies. 2. The V TT referred to in these specifications refers to ins tantaneous V TT . 3. Refer to t he processor I/O Buffer Models for I/V char acteristics. 4. Measured at 0.[...]

39 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications Notes: 1. VOS is the measur ed overshoot voltage. 2. TOS is the measured time duration above VID . 2.13.3 Die Voltage Validation Core voltage (VCC) overshoot events at the processor must meet the specifications in Ta b l e 2 - 1 8 when measured across the VCC_DIE_ SENSE an[...]

Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 40 The AGTL+ reference voltages (GTLREF _DA T A_MID, GTLREF_DA T A_END, GTLREF_ADD_MID, and GTLREF_ADD_END) must b e generated on the baseboard using high precision voltage divider circuits. R efer to the appropriate platform design guidelines for implementation details. Note[...]

41 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 7. Threshold R egion is defined as a region entered aroun d the crossi ng point voltag e in which the differential receiver sw itches. I t includes input threshold hysteresis. 8. The crossing point must me et the absolute and rela tive crossin g point specif ications simul[...]

Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 42 § Figure 2-14. Diffe rential Cloc k Crosspoint Specification Figure 2-15. D ifferential Risi ng and Falling Edge Rat es 660 670 680 690 700 7 10 720 730 740 750 760 770 780 790 800 810 820 830 840 850 200 250 300 350 400 450 500 550 600 650 VHavg (mV) Cr oss ing Po in t ([...]

43 Mechanical Specifications 3 Mechanical Specifications The Quad-Core Intel® Xeon® Processor 5400 Series is packaged in a Flip Chip Land Grid Array (FC -LGA) package that interfaces to the baseboard via a LGA771 socket. The package consists of a processor core mounted on a pinless substrate with 771 lands. An integrated h eat spreader (IHS) is a[...]

Mechanical Specifications 44 Note: Guidelines on potential IHS flatne ss v ariation with socket load plate actuation and installatio n of the cooling solution are available in the processor Ther ma l/Mechanical Desi gn Guidelines. Figure 3-2. Quad-Core Intel® Xeon® Pr ocessor 5400 Series Package Drawing (Sheet 1 of 3 )[...]

45 Mechanical Specifications Figure 3-3. Quad-Core Intel® Xeon® Pr oces sor 5400 Series Package Drawing (Sheet 2 of 3)[...]

Mechanical Specifications 46 Note: The optional dimpl e packing marking highlighted b y Detail F from the above dr awing may only be found on initial processo rs. Figure 3-4. Quad-Core Intel® Xeon® Pr ocessor 5400 Series Package Drawing (Sheet 3 of 3 )[...]

47 Mechanical Specifications 3.2 Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements. Decoupling capacitors are typically mounted to either the topside or landside of the package substrate. See Figure 3-4 for keepout zones. 3.3 Package Loading Specifications Ta b l [...]

Mechanical Specifications 48 3.4 Package Handling Guidelines Ta b l e 3 - 2 includes a list of guidelines on a pa ckage handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experien ced during heatsink removal. Notes: 1. A shear load is defined as a load ap plied to[...]

49 Mechanical Specifications Note: 2D matrix is required for engineerin g samples only ( encoded with A TPO-S/N). 3.9 Processor Land Coordinates Figure 3-6 and Figure 3-7 show the top and bottom view of the processor land coordinates, respectively . The coordinates are referred to throughout the document to identify processor lands. Figure 3-5. Pro[...]

Mechanical Specifications 50 § Figure 3-7. Processor Land Coordinates, Bottom View V TT / Clocks 1 2 3 4 5 6 7 8 9 1 0 1 11 2 1 31 41 51 61 7 1 81 9 2 02 1 2 22 32 42 52 62 72 82 93 0 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN 1 2 3 4[...]

51 Land Listing 4 Land Listing 4.1 Quad-Core Intel® Xeon® Processor 5400 Series Pin Assignments This sect ion provid es sorted la nd list in Ta b l e 4 - 1 and Ta b l e 4 - 2 . Ta b l e 4 - 1 is a listing of all proc essor lands ordered alphabetically by land name. Ta b l e 4 - 2 is a listing of all processor lands ordered by land number . 4.1.1 [...]

Land Listing 52 BSEL0 G29 CMOS ASync Output BSEL1 H30 CM OS ASync Output BSEL2 G30 CM OS Async Output COMP0 A13 Power/Other Input COMP1 T1 Power/Other Input COMP2 G2 Power/Other Inpu t COMP3 R1 Power/Other Input D00# B4 Source Sync Input/Output D01# C5 Source Sync Input/Output D02# A4 Source Sync Input/Output D03# C6 Source Sync Input/Output D04# A[...]

53 Land Listing DP2# H16 Common Clk Input/Ou tput DP3# J17 Common Clk Input/Output DRDY# C1 Common Clk Input/Output DSTBN0# C8 Source Sync Input/Output DSTBN1# G12 Source S ync Input/Output DSTBN2# G20 Source S ync Input/Output DSTBN3# A16 Source Sync Input/Output DSTBP0# B9 Source Sync Input/Output DSTBP1# E12 Source Sync Input/Output DSTBP2# G19 [...]

Land Listing 54 RESERVED G24 RESERVED F24 RESERVED F26 RESERVED F25 RESERVED G25 RESERVED W3 RESERVED AM2 RESET# G23 Common Clk Input RS0# B3 Common Clk Input RS1# F5 Common Clk Input RS2# A3 Common Clk Input RSP# H4 Common Clk Input SKTOC C# AE8 Power/Other Output SMI# P2 CMOS ASync Input STPCLK# M3 CMOS ASync Input TCK AE1 T AP Input TDI AD1 T AP[...]

55 Land Listing VCC AG30 Power/Other VCC AG8 Power/Oth er VCC AG9 Power/Oth er VCC AH11 Power/Other VCC AH12 Power/Other VCC AH14 Power/Other VCC AH15 Power/Other VCC AH18 Power/Other VCC AH19 Power/Other VCC AH21 Power/Other VCC AH22 Power/Other VCC AH25 Power/Other VCC AH26 Power/Other VCC AH27 Power/Other VCC AH28 Power/Other VCC AH29 Power/Othe[...]

Land Listing 56 VCC AN8 Power/Other VCC AN9 Power/Other VCC J10 Power/Other VCC J11 Power/Other VCC J12 Power/Other VCC J13 Power/Other VCC J14 Power/Other VCC J15 Power/Other VCC J18 Power/Other VCC J19 Power/Other VCC J20 Power/Other VCC J21 Power/Other VCC J22 Power/Other VCC J23 Power/Other VCC J24 Power/Other VCC J25 Power/Other VCC J26 Power/[...]

57 Land Listing VCC W8 Power/Other VCC Y23 Power/Other VCC Y24 Power/Other VCC Y25 Power/Other VCC Y26 Power/Other VCC Y27 Power/Other VCC Y28 Power/Other VCC Y29 Power/Other VCC Y30 Power/Other VCC Y8 Powe r/Other VCC_DIE_SENSE AN3 Pow er/Other Output VCC_DIE_SENSE2 AL8 P ower/Other Output VCCPLL D23 Powe r/Other Input VID_SELECT AN7 Power/Other O[...]

Land Listing 58 VSS AF29 Power/Other VSS AF3 Power/Ot her VSS AF30 Power/Other VSS AF6 Power/Ot her VSS AG10 Power/Other VSS AG13 Power/Other VSS AG16 Power/Other VSS AG17 Power/Other VSS AG20 Power/Other VSS AG23 Power/Other VSS AG24 Power/Other VSS AG7 Po wer/Other VSS AH1 Power/Ot her VSS AH10 P ower/Oth er VSS AH13 P ower/Oth er VSS AH16 P ower[...]

59 Land Listing VSS B11 Power/Other VSS B14 Power/Other VSS B17 Power/Other VSS B20 Power/Other VSS B24 Power/Other VSS B5 Power/Other VSS B8 Power/Other VSS C10 Power/Oth er VSS C13 Power/Oth er VSS C16 Power/Oth er VSS C19 Power/Oth er VSS C22 Power/Oth er VSS C24 Power/Oth er VSS C 4 Power/Other VSS C 7 Power/Other VSS D12 Power/Oth er VSS D15 P[...]

Land Listing 60 VSS L7 Power/Other VSS M1 Power/Other VSS M7 Power/Other VSS N3 Power/Other VSS N6 Power/Other VSS N7 Power/Other VSS P23 Power/Other VSS P24 Power/Other VSS P25 Power/Other VSS P26 Power/Other VSS P27 Power/Other VSS P28 Power/Other VSS P29 Power/Other VSS P30 Power/Other VSS P4 Power/Oth er VSS P7 Power/Oth er VSS R2 Power/Other V[...]

61 Land Listing 4.1.2 Land Listing by Land Number Table 4-2. Land Listin g by Land Number (Sheet 1 of 20) Pin No. P in Name Signal Buffe r Type Directio n A10 D08# Source Sync Input/Output A11 D09# Source Sync Input/Output A12 VSS Power/Other A13 COMP0 Power /Other Input A14 D50# Source Sync Input/Output A15 VSS Power/Other A16 DSTBN3# Source S ync[...]

Land Listing 62 AD26 VCC P ower/Other AD27 VCC P ower/Other AD28 VCC P ower/Other AD29 VCC P ower/Other AD3 BINIT# Common Clk Input/Outp ut AD30 VCC P ower/Other AD4 VSS Power/Other AD5 ADSTB1# Source Sync Input/Output AD6 A22# Source S ync Input/Output AD7 VSS Power/Other AD8 VCC Power/Oth er AE1 TCK T AP Input AE10 VSS Power/Other AE11 VCC Power/[...]

63 Land Listing AG18 VCC Power/Other AG19 VCC Power/Other AG2 BPM3# Comm on Clk Input/Output AG20 VSS Power/Other AG21 VCC Power/Other AG22 VCC Power/Other AG23 VSS Power/Other AG24 VSS Power/Other AG25 VCC Power/Other AG26 VCC Power/Other AG27 VCC Power/Other AG28 VCC Power/Other AG29 VCC Power/Other AG3 BPM5# Comm on Clk Input/Output AG30 VCC Pow[...]

Land Listing 64 AJ9 VCC P ower/Other AK1 RESERVED AK10 VSS Power/Othe r AK11 VCC Power/Oth er AK12 VCC Power/Oth er AK13 VSS Power/Othe r AK14 VCC Power/Oth er AK15 VCC Power/Oth er AK16 VSS Power/Othe r AK17 VSS Power/Othe r AK18 VCC Power/Oth er AK19 VCC Power/Oth er AK2 VSS Power/Ot her AK20 VSS Power/Othe r AK21 VCC Power/Oth er AK22 VCC Power/[...]

65 Land Listing AM26 VCC Power/Other AM27 VSS Power/Other AM28 VSS Power/Other AM29 VCC Power/Other AM3 VID2 CMOS Async Output AM30 VCC Power/Other AM4 VSS Power/Oth er AM5 VID6 CMOS Async Output AM6 RESERVED AM7 VSS Power/Oth er AM8 VCC P ower/Ot her AM9 VCC P ower/Ot her AN1 VSS Power/Ot her AN10 VSS Power/Other AN11 VCC Power/Other AN12 VCC Powe[...]

Land Listing 66 C2 BNR# Common Clk Input/O utput C20 DBI3# Source Sync Input/Output C21 D58# Source Sync Input/Output C22 VSS P ower/ Other C23 RESERVED C24 VSS P ower/ Other C25 VT T Power/ Other C26 VT T Power/ Other C27 VT T Power/ Other C28 VT T Power/ Other C29 VT T Power/ Other C3 LOCK# Common Clk Input/O utput C30 VT T Power/ Other C4 VSS Po[...]

67 Land Listing F10 VSS Power/Other F11 D23# Source Sync Input/Output F12 D24# Source Sync Input/Output F13 VSS Power/Other F14 D28# Source Sync Input/Output F15 D30# Source Sync Input/Output F16 VSS Power/Other F17 D37# Source Sync Input/Output F18 D38# Source Sync Input/Output F19 VSS Power/Other F2 GTLREF_ADD_ MID Power /Other Input F20 D41# Sou[...]

Land Listing 68 H27 VSS Power/Ot her H28 VSS Power/Ot her H29 VSS Power/Ot her H3 VSS Power/Other H30 BSEL1 CMOS Async Output H4 RSP# Common Clk Input H5 BR1# Common Clk Input H6 VSS Power/Other H7 VSS Power/Other H8 VSS Power/Other H9 VSS Power/Other J1 VTT_OUT Power/Other Output J10 VCC Power/Other J11 VCC Power/Other J12 VCC Power/Other J13 VCC [...]

69 Land Listing M28 VCC Power/Other M29 VCC Power/Other M3 STPCLK# CMOS Async Input M30 VCC Power/Other M4 A07# Source Sync Input/Output M5 A03# Source Sync Input/Output M6 RE Q2# Source Sync Inpu t/Outpu t M7 VSS Power/Other M8 VCC Power/Other N1 PWRGOOD Power/Other Input N2 IGNNE# CMOS Async Input N23 VCC Power/Other N24 VCC Power/Other N25 VCC P[...]

Land Listing 70 § U28 VCC P ower/Other U29 VCC P ower/Other U3 AP1# Common Clk Input/Output U30 VCC P ower/Other U4 A13# Source Sync Input/Output U5 A12# Source Sync Input/Output U6 A10# Source Sync Input/Output U7 VSS Power/O ther U8 VCC P ower/Other V1 MS_ID1 P ower/Other Output V2 LL_ID0 Power/Other Output V23 VSS Power/Other V24 VSS Power/Othe[...]

71 Signal Definitions 5 Signal Definitions 5.1 Signal Definitions Table 5-1. Signal Definitions (She et 1 of 8) Name Type Description Notes A[37:3]# I/O A[37:3]# (Address) define a 2 38 -byte physical memory address space. In sub-phase 1 of the ad dress phase, these signals transmit the address of a trans action. In sub-phase 2, these signals tr an[...]

Signal Definitions 72 BCLK[1:0] I The differential bus clock pair BCLK[1:0] (Bus Clock) determines the FSB frequency . All processor FS B agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to t he rising edge of BCLK0 crossing V CROSS . 3 BINIT# I/O BINIT# (Bus [...]

73 Signal Definitions BSEL[2:0] O The BCLK[1:0] frequency select signal s BSEL[2:0] are used to select the proces sor input cl ock freque ncy . Ta b l e 2 - 2 defines the p ossible combinations of the signals and the frequency associated wit h each combination. The required freq uency is determined by the processors, chi pset, and clock synthesizer[...]

Signal Definitions 74 DEFER# I DEFER# is asserted by an agent to indicate that a tr ansaction cannot be guaranteed in-order co mpletion. Assertion of DEFE R# is normally the responsibility of the addressed me mory or I/O agent. This signal must connect the app ropriate pins of all processor FSB agents. 3 DP[3:0]# I/O DP[3:0]# (Data Parity) provide [...]

75 Signal Definitions GTLREF_DA TA_MID GTLREF_DA TA_END I GTLREF_DA TA determines the signal reference level for AGTL+ data input lands. GTLREF_DA TA is us ed by the AGTL+ receivers to determine if a signal is a logical 0 or a logical 1. Please refer to Ta b l e 2 - 1 9 and the appropriate p latform design guidelines for additional details. HIT# HI[...]

Signal Definitions 76 MCERR# I/O MCERR# (Machine Check Error ) is asserted to indicate an unrecover able error without a bus pro tocol violation. It may be driv en by all processor FSB agents. MCERR# assertion conditions are configurable at a system lev el. Assertion options are d efined by the following opti ons: • Enabled or disabled. • Asser[...]

77 Signal Definitions RSP# I RSP# (Response Parity) is driven by the response agent (the agent responsible for comp letion of the current tr ansaction) during assertion of RS[2:0]#, the si gnals for which RSP# provides parity protection. It must connect to th e appropriate pins of all processor FSB agents. A correct parity signal is high if an ev e[...]

Signal Definitions 78 Notes: 1. For this pr ocessor land on the Quad-Core Intel® Xeon ® Processor 5400 Series, the maximum number of symmetric agents is one . Maximum number of pr iority agents is zero . 2. For this pr ocessor land on the Quad-Core Intel® Xeon ® Processor 5400 Series, the maximum number of symmetric agents is two. Maximum nu mb[...]

79 Thermal Specifications 6 Thermal Specifications 6.1 Package Thermal Specifications The Quad-Core Intel® Xeon® Processor 5400 Series requires a the rmal solution to maintain temperatures within its operating limits. Any attempt to oper ate the processor outside these operating limits ma y result in permanent damage to the processor and potentia[...]

Thermal Specifications 80 Processor Thermal Features). Systems that implement fan speed control must be designed to use this data. Systems that do n ot alter the fan speed only need to guarantee the case temperature meets the thermal profile specifications. The Quad-Core Intel® X eon® Processor X5482, and Quad-Core Intel® Xeon® Processor E5400 [...]

81 Thermal Specifications power dissipation is currently planned. Intel® Thermal Moni to r 1 and Inte l® Thermal Monitor 2 feature must be enable d for the processor to remain within its specifications. Notes: 1. These values are specified at V CC_MAX for all processor frequencies. S ystems must be designed to ensure the processo r is not to be s[...]

Thermal Specifications 82 Table 6-2 . Quad-Core Intel ® Xeon® Processor X549 2 and X5482 (C-step) Thermal Profile Table Power (W ) T CASE_MA X ( ° C) 0 35.0 5 35.9 10 36.9 15 37.8 20 38.7 25 39.7 30 40.6 35 41.5 40 42.5 45 43.0 50 44.4 55 45.3 60 46.2 65 47.2 70 48.1 75 49.0 80 50.0 85 50.9 90 51.8 95 52.8 100 53.7 105 54.6 110 55.6 115 56.5 120[...]

83 Thermal Specifications Notes: 1. These values are specified at V CC_MAX for all processor frequencies. S ystems must be designed to ensure the process or is not to be subjected to an y static V CC and I CC combination wherein V CC exceeds V CC_MAX at specified ICC. Please refer to the loadline specifications in Section 2.13.1 . 2. Thermal Design[...]

Thermal Specifications 84 Table 6-4. Quad-Core Intel® Xeon® Processor X5400 Series Ther mal Profile A Table Power (W ) T CASE_MA X ( ° C) 0 42.8 5 43.6 10 44.5 15 45.3 20 46.2 25 47.0 30 47.8 35 48.7 40 49.5 45 50.0 50 51.2 55 52.0 60 52.9 65 53.7 70 54.6 75 55.4 80 56.2 85 57.1 90 57.9 95 58.8 100 59.6 105 60.4 110 61.3 115 62.1 120 63.0[...]

85 Thermal Specifications Notes: 1. These values are specified at V CC_MAX for all processor frequencies. S ystems must be designed to ensure the processor i s not to be subjected to an y static VCC and ICC combination where in VCC exceeds V CC_MAX at specified ICC. Please refer to the loadline specific ations in Section 2.13 . 2. Thermal Design P [...]

Thermal Specifications 86 Notes: 1. Please refer to Ta b l e 6 - 7 for discrete points that constitute the thermal profile. 2. Implementation of the Quad-Core Intel® X eon® Pr ocessor 5400 Series Thermal Profile shoul d result in virtually no TCC activ ation. Furthermore, utilization of thermal solutions that do not meet the processor Thermal Pro[...]

87 Thermal Specifications Notes: 1. These values are specified at V CC_MAX for all processor frequencies. S ystems must be designed to ensure the processor i s not to be subjected to an y static VCC and ICC combination where in VCC exceeds V CC_MAX at specified ICC. Please refer to the loadline specific ations in Section 2.13 . 2. Thermal Design P [...]

Thermal Specifications 88 Notes: 1. These values are spec ified at V CC_MA X for all processor frequencies. Syst ems must be designed to en sure the processor is not to be s ubjected to any static VCC and ICC combination where in VCC exceeds V CC_MAX at specified ICC. Please refer to the loadline spec ifications in Sect ion 2.13 . 2. Thermal Design[...]

89 Thermal Specifications Notes: 1. Please refer to Ta b l e 6 - 1 1 for discrete points that constitute the thermal profile. 2. Implementation of the Quad-Core Intel® X eon® Processor L5408 Thermal Profile should result in virtually no TCC activ ation. Furthermore, ut ilization of thermal solutions that do not m eet the processor Thermal Profile[...]

Thermal Specifications 90 6.1.2 Thermal Metrology The minimum and maximum case temper atures (T CASE ) are specified in Ta b l e 6 - 2 , Ta b l e 6 - 4 , Ta b l e 6 - 5 , and Ta b l e 6 - 7 , and Ta b l e 6 - 9 and Ta b l e 6 - 1 1 are measured at the geometric top center of the processo r integr ated heat spreader (IHS). Fi gure 6- 6 illustrates t[...]

91 Thermal Specifications needed by modulating (starting and stopping) the internal processor core clocks. The temperature at which the Intel® Thermal Monitor 1 activ ates the thermal control circuit is not user configurable and is not software visible. Bus tr affic is snooped in the normal manner , and interrupt requests are latched (and serviced[...]

Thermal Specifications 92 The second operating po int consists of both a lower operating frequency and v oltage. The lowest operating frequency is determined by the lowest supported bus r atio (1/6 for the Quad-Core Intel® X eon® Processor 540 0 Series). When the T CC is activated, the processor automatically transitions to th e new frequency . T[...]

93 Thermal Specifications Series must not rely on software usage of this mechanism to limit the processor temperature. If bit 4 of the IA32_CLOCK _MODULA TION MSR is set to a ‘1’ , the processor will immediately reduce its power consumption via modulation (starting and stopping) of the internal core clock, inde pendent of the processor temperat[...]

Thermal Specifications 94 6.2.5 THERMTRIP# Signal Regardless of wh ether or not Intel® Thermal Monitor 1 or Intel® Thermal Monitor 2 i s enabled, in the event of a catastrophic c ooling failure, the proce ssor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Ta b l e 5 - 1 ).[...]

95 Thermal Specifications should utilize the relative temperature v alue de livered over PECI in conjunction with the T CONTROL MSR value to control or o ptimize fan speeds. Figure 6-9 shows a conceptual fan control diagr am using PECI temperatures. The relative temperature v alue reported over PECI represents the data below the onset of thermal co[...]

Thermal Specifications 96 6.3.2 PECI Specifications 6.3.2.1 PECI Device Address The PECI device address for socket 0 is 0x30 and soc ket 1 is 0x31. Please note that each address also supports two domains (Domain0 and Domain1). For more information on PECI domains, please refer to the Platform Environment Con trol Interface (PECI) Specification . 6.[...]

97 Features 7 Features 7.1 Power-On Configuration Options Several configur ation options can be config ured by hardware. The Quad-Core Intel® X eon® Processor 5400 Series samples its hardware configuration at reset, on the active-to-inactive tr ansition of RESET#. For specifics on these options, please refer to Ta b l e 7 - 1 . The sampled inform[...]

Features 98 7.2.1 Normal State This is the normal operating state for the processor . 7.2.2 HALT or Extended HALT State The Extended HAL T state (C1E) is enabled via the BIOS. The Extended HALT state must be enabled for the process or to remain within its specifications. The Extended HAL T state requires support for dynamic VID t ransitions in the [...]

99 Features Notes: 1. Processors runn ing in the lowest bus r atio supported as sh own in Ta b l e 2 - 1 , will enter the HAL T State whe n the processor h as executed the HAL T or MWAIT instruction since the proces sor is already operating in th e lowest core frequency and v oltage operating point. 2. The specification is at T case = 4 0 o C and n[...]

Features 100 7.2.3 Stop-Grant State When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered no later than 20 bus clocks afte r the response phase of the processor issued Stop Grant Acknowledge special bus cycle. By defaul t, the Quad-Core Intel® X eon® Processor 5400 Series will issue two Stop Grant Acknowledge special [...]

101 Features While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor , and only serviced when the pr ocessor returns to the Normal state. Only one occurrence of each ev ent will be recognized upon return to the Normal state. While in Stop-Grant state, the processor will process snoops on the front side bus [...]

Features 102 Enhanced Intel SpeedStep T echnology creates processor performance states (P-states) or voltage/frequency oper ating points which are lower power capability states within the Normal state (see Figure 7-1 for the Stop Clock State Machine for supported P- states). Enhanced Intel SpeedStep T echno logy enables rea l-time dynamic switching[...]

103 Boxed Processor Specifications 8 Boxed Processor Specifications 8.1 Introduction Intel box ed processors are intended for system integrators who build systems from components av ailable through distribution channels. The Quad-Core In tel® Xeon® Processor 5400 Series will be offered as an Intel boxed processor . Intel will offer the Quad-Core [...]

Boxed Processor Specifications 104 Figure 8-1. Boxed Quad-Core Inte l® Xeon® Processor 5400 Series 1U Passive/3U+ Active Combination Heat Sink (With Removable Fan) Figure 8-2. Boxed Quad-Core Intel® Xeon® Pr ocessor 5400 Series 2U Passive Heat Sink[...]

105 Boxed Processor Specifications Notes: 1. The heat sinks re presented in these images are for referen ce only , and may not rep resent the final boxed processor heat s inks. 2. The screws, springs, and standoffs will be captive to the heat sink. This image shows all of the components in an exploded view. 3. It is intended that the CEK spring wil[...]

Boxed Processor Specifications 106 Figure 8-4. Top Si de Board Keepout Zones (Part 1)[...]

107 Boxed Processor Specifications Figure 8-5. Top Side Board Keepout Zones (Part 2)[...]

Boxed Processor Specifications 108 Figure 8-6. Bottom Side Board Keepout Zones[...]

109 Boxed Processor Specifications Figure 8-7. Board Mounting-Hole Keepout Zones[...]

Boxed Processor Specifications 110 Figure 8-8. Volumetric Height Keep-Ins[...]

111 Boxed Processor Specifications Figure 8-9. 4-Pin Fan Cable Connec tor (For Active CEK Heat Sink)[...]

Boxed Processor Specifications 112 Figure 8-10. 4-Pi n Base Board Fan Header (F or Active CEK Heat Sink)[...]

113 Boxed Processor Specifications 8.2.2 Boxed Processo r Heat Sink Weight 8.2.2.1 Thermal Solution Weight The 1U passive/3U+ active combination heat sink solution and the 2U passive heat sink solution will not exceed a mass of 1050 grams. Note that this is per processor , a dual processor system will have up to 2010 grams total mass in the heat si[...]

Boxed Processor Specifications 114 The fan power header on the baseboard must be positioned to allow the fan heat sink power cable to reach it. The fan power head er identification and location must be documented in the suppliers platform documentation, or on the baseboard itself . The baseboard fan power header should be positioned within 177.8 mm[...]

115 Boxed Processor Specifications around the heatsink. It is assumed that a 40°C T LA is met. This requires a superior chassis design to limit the T RISE at or below 5°C with an external ambient temper ature of 35°C. These specifications apply to both coppe r and aluminum heatsink solutions. Following these guidelines allows the designer to mee[...]

Boxed Processor Specifications 116 §[...]

117 Debug Tools Specifications 9 Debug Tools Specifications Please refer to the appropriate platform de sign guidelines for information regarding debug tool specifications. Section 1.3 provides collateral details. 9.1 Debug Port System Requirements The Quad-Core Intel® Xeon® Processor 5400 Series debug port is the comm and and control interface f[...]

Debug Tools Specifications 118 9.3.1 Mechanical Considerations The LAI is installed between the processor so cket and the pro cessor . The LAI plugs into the socket, while the processor plugs into a socket on th e LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer . [...]