Mitel MT90840 manuel d'utilisation

2-231  Features • Time slot interchange function between eight pairs of ST -BUS/GCI/MVIP  streams (512 channels) and parallel data por t • Programmab le data rates on the parallel port (19.44, 16.384, or 6.480 Mbyte/s) • Programmab le data rates on the serial por t (2.048 Mbps, 4.096 Mbps or 8.192 Mbps) • Suppor ts star and point-to-p[...]

MT90840 Preliminar y Inf or mation 2-232 Figure 2 - Pin Connections NC NC NC NC NC 74 56 58 60 62 64 68 70 72 66 12 28 26 24 22 18 16 14 20 32 30 54 10 8 6 4 2 84 82 80 78 76 34 36 38 40 42 44 46 48 50 52 84 PIN PLCC 100 PIN PQFP 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 22 24 26 28 30 32 34 36 38 40 44 46 48 42 82 100 98 96 94 92 88 86 84 90[...]

Preliminar y Inf or mation MT90840 2-233 Pin Description Pin # Name Description 84 100 34 3 DS/RD Data Strobe/Read (Input ). In Motorola m ultiplex ed-b us mode this pin is DS, an active high input which w orks with CS to enable read and write operation. In Intel/ National multiple x ed-bus mode this pin is RD , an active lo w input which enables a[...]

MT90840 Preliminar y Inf or mation 2-234 22 66 F0i/o Serial P ort Frame Synchronization (Bidirectional). This 8 kHz frame pulse signal indicates the TDM 125 µ sec fr ame boundar y on the serial data por t. This pin is compatible with both ST -B US/MVIP and GCI formatted framing signals. In TM1 this pin is an input, and the MT90840 senses the polar[...]

Preliminar y Inf or mation MT90840 2-235 59 10 TRST T est Reset ( Input ). Asynchronously initializes the JT AG T AP controller , placing it in the T est-Logic-Reset state. This pin is pulled high internally when not dr iv en. This pin should be pulsed low on po wer-up , or held low continuously , to ensure that the MT90840 is in the normal functio[...]

MT90840 Preliminar y Inf or mation 2-236 Functional Description The MT90840 Distributed Hyperchannel Switch is a large s witching, multiple xing, and rate-adapting de vice. The MT90840 bridges ser ial-b us telecom components, using the Mitel ST -BUS or other industr y-standard serial buses , onto a higher speed “backbone”. Mix ed data, voice an[...]

Preliminar y Inf or mation MT90840 2-237 Figure 3 - Serial P ort Interface Functional Timing Figure 4 - P arallel Data P or t Functional Timing C4/8R1&2 Serial I/O 2 Mbps Serial I/O 4 Mbps Frame Boundary Established by F0 Ch. 31 Bit 1 Ch. 31 Bit 0 Ch. 0 Bit 7 Ch. 0 Bit 6 Ch. 63 Bit 2 Ch. 63 Bit 1 Ch. 63 Bit 0 Ch. 0 Bit 7 Ch. 0 Bit 6 Ch. 0 Bit 5[...]

MT90840 Preliminar y Inf or mation 2-238 an address-value in the path’ s Data Memor y . A given output time slot is controlled by prog ramming the Connection Memor y control-address with the address-value of the source input time slot. At the same control-address the output time slot is enabled or tri-stated and other per-channel functions set up[...]

Preliminar y Inf or mation MT90840 2-239 programmed to s witch parallel inputs to parallel outputs. F or each parallel output channel control-address, the Tx P ath Connection Memor y is programmed with the 12-bit address-v alue of the desired parallel input channel. Serial Data P ort The serial por t consists of 16 bidirectional ser ial data lines [...]

MT90840 Preliminar y Inf or mation 2-240 Register enables the internal divider , and the SPCK o output (and inter nal 4.096 MHz clocks) are driv en by the clock divided-do wn from PCKR. At 16.384 MHz, this is a simple divide-by-4, and the SPCK o output jitter will depend on the PCKR input jitter . At 19.44 MHz, the SPCK o output jitter will be larg[...]

Preliminar y Inf or mation MT90840 2-241 streams, and trigger the PPCE interrupt bit. PPCE will be triggered by PPFRi moving from the e xpected time, b ut PPCE will not be triggered by a missing PPFRi. If the PPFRi input is held asser ted, the parallel I/O will “loc k up” and operation will be disrupted (including CPU access to the TPCM). The P[...]

MT90840 Preliminar y Inf or mation 2-242 TM1. This allows f or fle xible round-trip data dela ys in star or ring type networks. An elastic buff er on the receive par allel por t compensates for the diff erence in phase between PPFRi/PCKR and F0i/C4. The elastic buff er can also tolerate up to 50 µ sec +/- 25 µ sec) of clock drift and jitter bef [...]

Preliminar y Inf or mation MT90840 2-243 The transmit path does not pro vide an elastic buff er , and theref ore the ser ial por t cloc k must be tightly lock ed (in frequency) to the parallel por t cloc k (PCKR). (Jitter less than +/- 100nsec.) This ma y be achie ved in one of two w a ys: use of the internal clock divider (INTCLK set high), or use[...]

MT90840 Preliminar y Inf or mation 2-244 Timing Mode 3 (TM3) - Bus Slave Synchronous P arallel P or t With ST -BUS Clock Slav e Timing Mode 3 is used where the main TDM clock ref- erence resides on the parallel por t side of the system, and where the receive par allel por t and the transmit parallel por t are aligned. (An e xample is a node on a ba[...]

Preliminar y Inf or mation MT90840 2-245 Timing Mode 4 (TM4) - P arallel Data Switching Timing Mode 4 is used to provide s witching of up to 2430 parallel input channels to the same number of parallel output channels. P arallel TDM data is clock ed in at PDi0-7 by PCKR, fr amed by PPFRi. Switching is perf or med as programmed in the Tx P ath Connec[...]

MT90840 Preliminar y Inf or mation 2-246 T able 1 - MT90840 Thr oughput Delay Summary Naming rules: ELD: ELastic Dela y , measured from PPFRi to F0i (4.4 to 129.4 µ sec). P/S:P arallel-to-Serial data path. Pi:P arallel Input channel time, e xpressed in delay after PPFRi (0 to 125 µ sec) . P o:P arallel Output channel time, e xpressed in delay aft[...]

Preliminar y Inf or mation MT90840 2-247 TPCM High location is output on the corresponding CT o pin once ev er y frame. See Figure 9. The control outputs can be used to control other de vices, such as buff ers, to allow sharing of the parallel por t data bus. P er-channel T ri-state (Ser ial and P arallel) The MT90840 provides per-channel tri-state[...]

MT90840 Preliminar y Inf or mation 2-248 all 16 serial streams can be individually controlled, so that up to 512 channels can be either transmitted or received. As an e xample, if all DC bit locations of RPCM High are set HIGH, all 512 channels on ST o0-7 and STi0-7 will be configured as outputs. If all DC bits are LO W , then all 512 channels wil[...]

Preliminar y Inf or mation MT90840 2-249 Figure 12a - 2.048 Mbps Add/Drop Mode TPDM Addressing Figure 12b - 2.048 Mbps Add/Drop Mode RPCM Addressing 4.096 Mbps Mode The 4.096 Mbps mode has 8 input and 8 output streams, and 64 channels per stream. Theref ore 3 bits are used to address the 8 streams, and 6 bits are used to address the 64 channels. Fi[...]

MT90840 Preliminar y Inf or mation 2-250 Figure 14a - 8.192 Mbps TPDM Addressing Figure 14b - 8.196 Mbps RPCM Addressing Micropr ocessor P or t An 8-bit multiple x ed parallel microprocessor por t is provided on the MT90840 to allo w an attached CPU to configure and read inter nal registers and memories. The MT90840 CPU interf ace is compatible wi[...]

Preliminar y Inf or mation MT90840 2-251 shor t, or a signal contention, pre vents the DT A pin from reaching a valid logic HIGH, it will contin ue to drive f or appro ximately 15 nsec before s witching to high-impedance. Accessing Internal Memories The Data and Connection memories of the MT90840 are connected to the various TDM data por ts, and sy[...]

MT90840 Preliminar y Inf or mation 2-252 the DT A pin will be asser ted (as the data is stored in the write-pipeline) but the ne xt CPU access will not see DT A asser ted. No clocks are necessar y f or register accesses (but if the write-pipeline is hung, the registers cannot be accessed). If the MT90840 is hung due to a CPU read of a memor y with [...]

Preliminar y Inf or mation MT90840 2-253 DR1-0 and FDC in the IMS register) bef ore programming the RPCM. b) The GPM Register is written. The CPU sets the Block-Prog ramming Enable (BPE) bit to HIGH and the Block-Prog ramming Data (BPD7-4) bits to the desired value . This action causes the contents of the BPD7-4 bits to be loaded into the f our mos[...]

MT90840 Preliminar y Inf or mation 2-254 I/O pin of the IC . The operation of the boundar y-scan circuitr y is controlled b y a T est Access P or t (T AP) Controller . T est Access P or t (T AP) The T est Access P or t (T AP) has five signals and provides access to the test logic defined b y the JT A G standard. The T AP has the following connect[...]

Preliminar y Inf or mation MT90840 2-255 T est Data Registers As specified in the IEEE 1149.1 Standard, the MT90840 JT AG interf ace contains two test data registers: • The Boundar y Scan Register consists of a series of Boundar y-Scan Cells arranged to f orm a scan path around the boundar y of the core logic of the MT90840. • The Bypass Regis[...]

MT90840 Preliminar y Inf or mation 2-256 Register Description Interface Mode Selection Register (IMS) - READ/WRITE 76543210 DR1 DR0 PPS1 PPS0 ODE 0 0 FDC DR1-0 Serial P or t Data Rate Selection. Select one of three different data rates at the serial inputs and outputs of the MT90840. DR1 DR0 Data Rate 0 0 2.048 Mbps 0 1 4.096 Mbps 1 0 8.192 Mbps 1 [...]

Preliminar y Inf or mation MT90840 2-257 General Purpose Mode Register (GPM) - READ/WRITE 76543210 BPD6 BPD5 BPD4 PPFP SPFP BPD7 DIN BPE BPD7-4 Block-Progr amming Data bits 7-4. These bits carr y the value to be loaded into the TPCM-High or RPCM-High memory when the Memor y Block-Programming f eature is activated. When BPE is set HIGH, the contents[...]

MT90840 Preliminar y Inf or mation 2-258 This register selects which 128 byte page of which internal memor y will be accessed by the CPU when the address bit AD<7> is high. (When address bit AD<7> is low , the control registers are accessed.) SEL2-0 Memory Select bits. Used by the CPU to select the internal memor ies of the MT90840 for [...]

Preliminar y Inf or mation MT90840 2-259 Internal Memory Description OE/CT o0 Output Enable. Pro vides per channel tristate control on the parallel por t side. It controls the MT90840 parallel output drivers to disable (tristate, when LO W) or enable (when HIGH) the transmission of data from the device . The contents of this bit will also be clock [...]

MT90840 Preliminar y Inf or mation 2-260 MC Message Channel: The message channel contents are provided b y the CPU in bits AB0-7 in the Rx Path Connection Memory Low . If MC is HIGH, the contents of the corresponding location of RPCM Low are output on this serial por t channel. If MC is LOW , the contents of the corresponding location in RPCM Low a[...]

Preliminar y Inf or mation MT90840 2-261 Applications Distributed Isoc hronous Netw ork Low latency isochronous bac kbones provide f or the deplo yment of systems that require cost effectiv e implementation, high bandwidth, predictable data transf er dela ys and direct synchronization with the wide area network. Some applications in Computer T elep[...]

MT90840 Preliminar y Inf or mation 2-262 synchronization scheme ma y be used in applications such as the proposed MVIP multi-chassis le v el 3 interf ace (MC-3 system) utilizing point-to-point or point-to-multipoint s witching connections. When the MT90840 operates in a ring application, the P arallel Data Bypass mode is provided to allo w all or p[...]

Preliminar y Inf or mation MT90840 2-263 A C Electrical Characteristics - V oltages are with respect to ground (V SS ) unless otherwise stated. Characteristics Sym Min T yp ‡ Max Units T est Conditions 1 C4/8 Input - Clock P er iod: 4.096 MHz (2.048 & 4.096 Mbps) 8.192 MHz (8.192 Mbps) SPCK o Output - Clock P eriod from inter nal divider (2.0[...]

MT90840 Preliminar y Inf or mation 2-264 ‡ T ypical figures are at 25 ° C and are f or design aid only: not guaranteed and not subject to production testing. Figure 17 - Output T est Load 10 ST o Dela y from High-Z to Active 2.048 and 4.096 Mbps (TM2 &TM3) 2.048 and 4.096 Mbps (TM1) 8.192 Mbps (STio0-3) t za 38 50 26 ns ns ns C L =30pF , R [...]

Preliminar y Inf or mation MT90840 2-265 Figure 18 - Serial P ort Timing for 2.048 Mbps Operation - TM2 (SFDi = 1) and TM1 C4/8R1 t frw STi0-7 STo0-7 (4.096 MHz) bit 7, ch. 0 bit 0, ch. 31 bit 7, ch. 0 bit 0, ch. 31 t stih t stis t clkh Serial Port with Negative Polarity F0 (ST-BUS) t sod t frh t frs t clk t clkl t T STo0-7 C4/8R1 (4.096 MHz) STi0-[...]

MT90840 Preliminar y Inf or mation 2-266 Figure 19 - Serial P ort Timing for 2.048 Mbps - TM2 (SFDi = 0) and TM3 t sod STo0-7 SPCKo (4.096 MHz) STi0-7 t stis t stih F0o output bit 7, ch. 0 bit 6, ch. 0 bit 7, ch.0 bit 0, ch.31 bit 0, ch. 31 Serial Port with Positive Polarity F0 (GCI) t df (8 kHz) t df t t t clkh t clkl t clk SPCKo t T STi0-7 STo0-7[...]

Preliminar y Inf or mation MT90840 2-267 Figure 20 - Serial P ort Timing for 4.096 Mbps Operation - TM2 (SFDi = 1) and TM1 STo0-7 C4/8R1 (4.096 MHz) STi0-7 F0i input bit 0, ch. 63 bit 7, ch. 0 bit 6, ch. 0 bit 7, ch. 0 STo0-7 C4/8R1 (4.096 MHz) STi0-7 F0i input bit 7, ch. 0 (8 kHz) (8 kHz) Serial Port with Negative Polarity F0 (ST-BUS) Serial Port [...]

MT90840 Preliminar y Inf or mation 2-268 Figure 21 - Serial P ort Timing for 4.096 Mbps Operation - TM2 (SFDi = 0) and TM3 STo0-7 SPCKo (4.096 MHz) STi0-7 F0o output bit 7, ch. 0 bit 6, ch. 0 bit 7, ch. 0 STo0-7 SPCKo (4.096 MHz) STi0-7 F0o output bit7, ch. 0 (8 kHz) (8 kHz) F0 Frame Sync with Negative Polarity (SPFP = 0) F0 Frame Sync with Positiv[...]

Preliminar y Inf or mation MT90840 2-269 Figure 22 - Serial P ort Timing for 8.192 Mbps - TM1 and TM2 (SFDi = 1) Figure 23 - P er-Channel T ristate Characteristics at all Data Rates STo0-7 C4/8R1 (8.192 MHz) STi0-7 F0i input bit 0, ch.127 bit 7, ch. 0 bit 6, ch. 0 bit 7 (8 kHz) Note: Polarity of F0i is automatically detected in TM1. t stis t stih t[...]

MT90840 Preliminar y Inf or mation 2-270 Figure 24 - Serial P ort Timing for 8.192 Mbps - Timing Modes 2 and 3 STo0-7 C4/8R1** (8.192 MHz STi0-7 F0o output bit 0, ch.127 bit 7, ch. 0 bit 6, ch. 0 bit 7 (8 kHz) Frame Sync with Positive Polarity (SPFP = 1) t stis t stih t df t df t sod t t t clkh t clk t clkl STo0-7 C4/8R1** (8.192 MHz STi0-7 F0o out[...]

Preliminar y Inf or mation MT90840 2-271 Figure 25 - Timing for the P arallel Port External Control Lines CT o0-3 Figure 26 - TM1 P arallel P or t T ransmit Timing (TM1 & PFDI = 1, PPFT is an input) Figure 27 - P arallel P or t T ransmit Timing (PFDI = 0, PPFT is an output) PDo0-7 CTo0-3 PCKT/PCKR TCP controls the clock-edge on which the output[...]

MT90840 Preliminar y Inf or mation 2-272 Figure 28 - P arallel P or t Receive Timing ‡ T ypical figures are at 25 ° C and are f or design aid only: not guaranteed and not subject to production testing. A C Electrical Characteristics - Parallel Data P or t Characteristics Sym Min T yp ‡ Max Units T est Conditions 1 PCKT/PCKR clock period t clk[...]

Preliminar y Inf or mation MT90840 2-273 Figure 29 - P arallel P or t in Timing Mode 4 Figure 30 - Phase V ariation Between C4/8R1 & C4/8R2 and PCKT Inputs for TM1 Operation Figure 31 - Phase V ariation Between C4 and PCKR Inputs for TM2 Operation PPFRi PPFT PCKR TCP = 0 PPFT TCP = 1 Note: For the PPFT depicted above, PPFP = HIGH. If PPFP is LO[...]

MT90840 Preliminar y Inf or mation 2-274 † Timing is over recommended temperature & po wer supply voltages . ‡ T ypical figures are at 25 ° C and are f or design aid only: not guaranteed and not subject to production testing. * High Impedance is measured b y pulling to the appropr iate rail with R L , with timing corrected to cancel time [...]

Preliminar y Inf or mation MT90840 2-275 Figure 32 - Intel/National Multiplexed Bus Timing ALE AD0- AD7 CS RD WR DT A t alw t ads t adh DATA ADDRESS t alrd t csrw t dhr t dhw t csw t alwr t akd t ddr t akh 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V t dsw t csr t rst t rdd[...]

MT90840 Preliminar y Inf or mation 2-276 † Timing is over recommended temperature & po wer supply voltages . ‡ T ypical figures are at 25 ° C and are f or design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with R L , with timing corrected to cancel time ta[...]

Preliminar y Inf or mation MT90840 2-277 Figure 33 - Motorola Multiple xed Bus Timing CS DT A AD0-13 RD DS R/ W AS ADDRESS ADDRESS DATA DATA t rwh t rws t asw t dsh t ads t adh t dhw t dhr t css t csh t akd t akh t ddr 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V AD0-7 WR t dss[...]

MT90840 Preliminar y Inf or mation 2-278 Figure 34 - Boundary Scan T est Port Timing Figure 35 - RESET Timing A C Electrical Characteristics - Boundar y-Scan T est P or t and RESET Pin P arameter Symbol Min Max Units T est Conditions 1 TCK period width t tclk 100 ns 2 TCK period width LOW t tclkl 40 ns 3 TCK period width HIGH t tclkh 40 ns 4 TDI se[...]

Preliminar y Inf or mation MT90840 2-279 Figure 36 - 84 PLCC Mechanical Drawing Figure 37 - 100 Pin PQF Mechanical Dra wing F D 1 D H E 1 I A 1 A G D 2 E E 2 Dim Min Max A 0.165 (4.20) 0.200 (5.08) A 1 0.090 (2.29) 0.130 (3.30) D/E 0.185 (30.10) 1.195 (30.35) D 1 /E 1 1.150 (29.210) 1.158 (29.413) D 2 /E 2 1.090 (27.69) 1.130 (28.70) F 0.026 (0.661[...]

MT90840 Preliminar y Inf or mation 2-280 Notes:[...]