Mitsubishi Electronics Q10UD(E)HCPU manuel d'utilisation

QCPU User's Manual (Multiple CPU System) -Q00CPU -Q100UDEHCPU -Q01CPU -Q02(H)CPU -Q06HCPU -Q12HCPU -Q25HCPU -Q02PHCPU -Q06PHCPU -Q12PHCPU -Q25PHCPU -Q00UCPU -Q01UCPU -Q02UCPU -Q03UDVCPU -Q03UD(E)CPU -Q04UDVCPU -Q04UD(E)HCPU -Q06UDVCPU -Q06UD(E)HCPU -Q10UD(E)HCPU -Q13UDVCPU -Q13UD(E)HCPU -Q20UD(E)HCPU -Q26UDVCPU -Q26UD(E)HCPU -Q50UDEHCPU[...]

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1 SAFETY PRECAUTIONS (Read these pre cautions before using this product.) Before using this product, p lease read this manual and the relevant manuals carefu lly and pay full attention to safety to handle the product correctly . In this manual, the safety pr ecautions are classified into two levels: " W ARNING" and " CAUTION". U[...]

2 [Design Precautions] [Design Precautions] W ARNING ● In an output mod ule, when a load current exceedi ng the rated curre nt or an overcurrent caused by a load short-circuit flows for a lo ng time, it may ca use smoke and fire. T o prevent this, configure an external safety circuit, such as a fuse. ● Configure a circuit so that the prog ramma[...]

3 [Inst allation Precautions] [Wiring Precautions] CAUTION ● Use the programmable controller in an environme nt that meets the general specifications in the QCPU User's Manual (Har dware Design, Maintenance and Inspection). Failure to do so may result in electric shock, fire, malf unction, or damage to or deter ioration of the product. ● T[...]

4 [Wiring Precautions] CAUTION ● Individually ground the FG and LG terminals of the progra mmable controller with a ground resistance of 100  or less . Failure to do so may resu lt in electric s hock or malfunction. ● Use applicable solderless terminals an d tighten them within the specified torque range. If any spade solderless terminal is [...]

5 [S t artup and Maintenance Precautions] [S t artup and Maintenance Precautions] W ARNING ● Do not touch an y terminal whi le power is on. D oing so will caus e electric sho ck or malfunctio n. ● Correctly connect the battery connect or . Do not charge, disassemble, heat, short-circuit, solder , or throw the battery into the fi re. Also, do no[...]

6 [Disposal Precautions] [T ransport ation Precautions] CAUTION ● When disposing of this produ ct, trea t it as industrial waste. When di sposing of batteries, separate them from other wastes according to the local regul ations. (For the Ba ttery Directive in EU member states, refer to the QCPU User's Manual (H ardware Design, Mainte nance a[...]

7 CONDITIONS OF USE FOR THE PRODUCT (1) Mitsubishi programmable con troller ("the PRODUCT") shall be used in conditions; i) where any problem, fault or failure occurring in the PRODUCT , if any , shall not lead to any major or serious accident; and ii) where the backup and fail-safe function are syst ematically or automatical ly provided [...]

8 INTRODUCTION This manual describes the system conf igurations, function s, and communication method s with external devices required in a multiple CPU system. Before using this product, please re ad this manual and the relevant man uals carefully and develop familiarity with the functions and performance of the Q serie s progra mmable controller [...]

9 Memo[...]

CONTENTS 10 CONTENTS SAFETY PRECAUTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 CONDITIONS OF USE FOR THE PRODUCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . .[...]

11 CHAPTER 5 ACCESS BETWEEN CPU MODULE S AND OTHER MODULES 104 5.1 Access to Con trolled Mo dules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.2 Access to Non -controlled Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.2.1 Loading input [...]

12 MANUALS T o understand the main specifications , functions, and usage of the CPU modu le, refe r to the basic manuals. Read other manuals as well when using a different type of CP U module and its functions. Order each ma nual as needed, referring to the following lists. The numbers in the "CPU module " and the respective modules are a[...]

13 (2) Programming manual (3) Operating manual Manual name <manual nu mber (model code)> Descriptio n CPU module 1) 2) 3) 4) MELSEC-Q/L Programming Manual (Common Instruction) <SH-080809ENG (13JW10)> Detailed description and usage of instructions used in programs ●●●● MELSEC-Q/L/QnA Programming Manual (SFC) <SH-080041 (13JF60[...]

14 MANUAL P AGE ORGANIZA TION In this manual, pages are organized a nd the symbols are used as shown belo w . The following page illustration is for explanation purp ose only , and is different from the actual pages. *1 The mouse operation example is provide d below . (For GX Works2) The section of the current page is shown. The chapter of the curr[...]

15 TERMS Unless otherwise specified, this manual uses th e following generic terms and abbrevia tions. *  indicates a part of the model or version. Ex. Q33B, Q35B, Q38B, Q312B  Q3  B Te r m Description  Series Q series The abbreviation for Mitsubishi ME LSEC-Q series programmable controller AnS series The abbreviation for compact types [...]

16 QnUDVCPU A generic term for the Q03UDVCPU, Q 04UDVCPU, Q06UDVCPU, Q13UDVC PU, and Q26UDVCPU QnUDE(H)CPU A generic term for the Q03UDECP U, Q 04UDEHCPU, Q06UDEHCPU, Q10UDEHCPU, Q13UDEHCPU, Q20UDEHCPU, Q26UDE HCPU, Q50UDEHCPU, and Q100UDEHCPU Q172CPUN(-T) A generic term for the Q172CPUN and Q172CPUN-T Q173CPUN(-T) A generic term for the Q173CPUN a[...]

17 A series power supply module A generic term for the A61P , A61PN, A62P , A63P , A68P , A61PEU, and A62PEU power supply modules Slim type power supply module The abbreviation for the Q61SP slim type power supply module Redundant power supply module A generic term for the Q63RP and Q64RP redu ndant power supply modules Life detection power supply [...]

18 CHAPTER 1 OVER VIEW In a multiple CPU system, more than one CPU module is mounted on the main ba se unit and each CPU module controls I/O modules and intellig ent function modules separately . QCPUs, Motion CPUs, C Controller modules, and PC CPU m odules can be used in multiple CPU systems. ( Page 31, CHAPTER 3 ) Remark This manual describes the[...]

19 CHAPTER 1 OVERVIEW 1 (a) Distribution of processing The overall system scan time can be reduced by distri buting the high-load processi ng performed in a single CPU module over multiple CPU modules. (b) Distribution of memory The memory cap acity used for the entire system can be increased by di stributing the memory areas over multiple CPU modu[...]

20 (2) Configuring sequence control and mo tion control systems on the same base unit In a multiple CPU system consisting of a QCPU and Motion CPU, sequence control and motion control can be implemented together to achiev e a high-level motion system. Interaction with Moti on CPUs for motion control is enhanced in Universal mode l QCPUs. (a) H igh-[...]

21 CHAPTER 1 OVERVIEW 1 (b) Synchronous processing with a motion control An interrupt program which is synchronized with the operation cycle of a Motion CPU (multiple CPU synchronous interrupt program) can be executed. Comm and input or ou tput from a Motion CPU ca n be synchronized with the operation cycle of th e Motion CPU, which enables high-sp[...]

22 (c) C hecking dat a send/receive timing between CPU modules With the sa mpling trace function o f Universal model QCPUs, the data communications timing with a Motion CPU can be checked . T iming can also be checked b etween Universal model QCPUs. The sampling trace function facilitates the processing for chec king the data send/receive timing be[...]

23 CHAPTER 1 OVERVIEW 1 (3) Dat a communications among CPU modules The following data communications can be performe d among CPU modules in a multiple CPU system. (a) T ransferring data among CPU modules Data can be transferred among CPU modules by setting auto refresh using a programming tool. ( Page 122, Section 6.1.1 to Page 135 , Section 6.1.2)[...]

24 CHAPTER 2 CONCEPT OF MUL TIPLE CPU SYSTEM 2.1 CPU Numbers CPU numbers are assigned to i dentify CPU modules cont ained in a multiple CPU system. A CPU module mounted in the CPU slot of a main base unit will be CPU No.1. CPU No.2 , No.3, and No.4 will be assigned se quentially to th e right of CPU No.1. (1) A vailable CPU numbers Available CPU nu[...]

25 CHAPTER 2 CONCEPT OF MUL TIPLE CPU SYSTEM 2 2.1 CPU Numbers (2) Uses of CPU numbers CPU numbers are used for the following purpose s. (a) Setting control CPUs CPU numbers are used to set a control CPU for each I/O module and intelligent func tion module. Set control CP Us in PLC pa rameter ("I/O Assignment"). Project window [Parameter][...]

26 (b) Specifyin g a connection t arget using a programming tool (personal computer) CPU numbers are used to specify a CPU module to which a p rogramming tool is connected. (3) Checking the host CPU number The host CPU number of a QCPU is stored in SD395 (Mult iple CPU system information). A host CPU number check program (refer to an example below)[...]

27 CHAPTER 2 CONCEPT OF MUL TIPLE CPU SYSTEM 2 2.2 I/O Number Assignment 2.2.1 I/O numbers of I/O modules and intellige nt function modules 2.2 I/O Number Assignment A multiple CPU system uses the following two I/O numbers. • I/O numbers used by CPU modules to communicate with I/O modules and intelligent functi on modules ( Page 27, Section 2.2.1[...]

28 ● Some CPU modules occupy two or more slots. When th is ty pe of CPU module is used, the second slot and after are treated as empty slots. In the case of a PC CPU module, for example, the right slot of th e occupied two slots is treated as an empty slot having 16 points. (An empty slot oc cupies 16 points by default.) For this reason, the star[...]

29 CHAPTER 2 CONCEPT OF MUL TIPLE CPU SYSTEM 2 2.2 I/O Number Assignment 2.2.1 I/O numbers of I/O modules and intellige nt function modules Ex. Example of I/O number assig nment 4th extension Q series power supply module CPU No.1 CPU No.2 CPU No.3 CPU No.4 1st extension 2nd extension 3rd extension Q312B (12 slots occupied) Q612B (12 slots occupied)[...]

30 2.2.2 I/O numbers of CPU modules In multiple CPU systems, I/O numbers are assigned to each CPU module to specify mounted CPU mo dules. The I/O number for each CPU module is fixed at the corresponding slot, and cannot be chan ged in PLC parameter ("I/O Assignment"). The following is the list of I/O numbers that can be assigned to CPU mo[...]

31 CHAPTER 3 SYSTEM CONFIGURA TION 3 CHAPTER 3 SYSTEM CONFIGURA TION In a multiple CPU system , QCPUs, motion CPUs, C Cont roller modules, and PC CPU modules can be mounted in the CPU slot to slot 2 of the main base unit. I/O modules and intelligent functi on modules are mounted to the right of CPU modules. This chapter describes the system configu[...]

32 3.1 System Using Basic Model QCPU as CPU No.1 This section describes the system configurat ion usin g a Basic model QCPU as CPU No.1. 3.1.1 A vailable CPU modules, base un it s, power supply modules, and extension cables Available CPU modules and the number of mountabl e modules differ depending on the main base unit used. (1) When a main base u[...]

33 CHAPTER 3 SYSTEM CONFIGURA TION 3 3.1 System Using Basic Model QCPU as CPU No.1 3.1.1 Available CPU modules , base units, power supply modules, and extension cables (b) Precautions • If I/O modules are mounted exceeding the maximum number , "SP .UNIT LA Y ERR" (error code: 2124) occurs. • "Number of CPU modules" indicates[...]

34 (2) When a redundant power main base unit (Q3  RB) is used (a) Available m odules, the number of extension base unit s, and the number of mount able modules (b) Precautions • If I/O modules are mounted exceeding the maximu m number , "SP .UNIT LA Y ERR" (error code: 2124) occurs. • "Number of CPU modules" indicates the[...]

35 CHAPTER 3 SYSTEM CONFIGURA TION 3 3.1 System Using Basic Model QCPU as CPU No.1 3.1.1 Available CPU modules , base units, power supply modules, and extension cables (3) When a slim type main base unit (Q3  SB) is used (a) Availa ble modules, the number of extension base unit s, and the number of mount able modules (b) Precautions Slim type ma[...]

36 (4) When a multiple CPU high speed main base unit (Q3  DB) is use d (a) Available m odules, the number of extension base unit s, and the number of mount able modules *1 For the CPU modules that can be combined and their mounting positions, refer to Page 37, Section 3.1.2. (b) Precautions • If I/O modules are mounted exceeding the maximu m n[...]

37 CHAPTER 3 SYSTEM CONFIGURA TION 3 3.1 System Using Basic Model QCPU as CPU No.1 3.1.2 CPU module combinations and mou nting positions 3.1.2 CPU module combinations and mounting positions This section describes the combinations and mounting po sitions of CPU modules when a Basic model QCPU is used as CPU No.1. Note that the CPU modules that can b[...]

38 (c) C Controller module or PC CPU module Either a C Controller module or PC CPU module c an be mounted on the extrem e right of the other CPU module(s). No CPU module can b e mounted on the righ t of the C Controller module or PC CPU module. (d) Empty slot setting Empty slots can be reserved for future addition of CPU mo dules. Set the number of[...]

39 CHAPTER 3 SYSTEM CONFIGURA TION 3 3.1 System Using Basic Model QCPU as CPU No.1 3.1.2 CPU module combinations and mou nting positions ● When a Basic model QCPU is used, "PLC (Empty) " can be set between CPU modules. Th is is useful when adding a Motion CPU to the system where a Basic model QCPU and a C Controller module or PC CPU mod[...]

40 3.1.3 A vailable I/O modules and intelligent function modules This section describes I/O mo dules and intelligent function modu les that can be used. (1) I/O modules and interrupt module I/O modules (QX  and QY  ) and interrupt module (QI60) can be used. Any CPU module can be set as a control CPU. (2) Intelligent function modules Intellige[...]

41 CHAPTER 3 SYSTEM CONFIGURA TION 3 3.2 System Using High Performance Model QCPU or Process CPU as CPU No.1 3.2.1 Available CPU modules , base units, power supply modules, and extension cables 3.2 System Using High Performance Model QCPU or Process CPU as CPU No.1 This section describes the system c onfiguration using a High Performance model QCPU[...]

42 *1 For the CPU modules that can be combined and their mounting positions, refer to Page 47, Section 3.2.2. *2 When using a Motion CPU, install operating system soft ware on the CPU module. For models and versions of the operating system, refer to the manual for the Motion C PU used. *3 These units cannot be used in a multiple CPU system includin[...]

43 CHAPTER 3 SYSTEM CONFIGURA TION 3 3.2 System Using High Performance Model QCPU or Process CPU as CPU No.1 3.2.1 Available CPU modules , base units, power supply modules, and extension cables (2) When a redundant power main base unit (Q3  RB) is used (a) Availa ble modules, the number of extension base unit s, and the number of mount able modu[...]

44 (3) When a slim type main base unit (Q3  SB) is used (a) Available m odules, the number of extension base unit s, and the number of mount able modules *1 For the CPU modules that can be combined and their mounting positions, refer to Page 47, Section 3.2.2. (b) Precautions • Slim type main base uni ts do not have an extensio n cable conne c[...]

45 CHAPTER 3 SYSTEM CONFIGURA TION 3 3.2 System Using High Performance Model QCPU or Process CPU as CPU No.1 3.2.1 Available CPU modules , base units, power supply modules, and extension cables (4) When a multiple CPU hi gh speed main base unit (Q3  DB) is used (a) Availa ble modules, the number of extension base unit s, and the number of mount [...]

46 (b) Precautions • If I/O modules are mounted exceeding the maximu m number , "SP .UNIT LA Y ERR" (error code: 2124) occurs. • "Number of CPU modules" indicates the number set in "No. of PLC" of PLC parameter ("Multiple CPU Setting") . • A C Controller module (Q24DHCCPU-V) occupies three slots. When t[...]

47 CHAPTER 3 SYSTEM CONFIGURA TION 3 3.2 System Using High Performance Model QCPU or Process CPU as CPU No.1 3.2.2 CPU module combinations and mou nting positions 3.2.2 CPU module combinations and mounting positions This section describes the combinations and mounting positions of CPU modules when a High Performance model QCPU or Process CPU is use[...]

48 (2) Mounting positions The following shows the possible co mbinations of mountin g positions of CPU modules in a multiple CPU system. *1 The QCPU used as CPU No.1 indicates a Hi gh Performance model QCPU or Process CPU. The QCPU used as CPU No.2 or later indicates a High Pe rformance model QCPU, Proce ss CPU, or Universal model QCPU (except the [...]

49 CHAPTER 3 SYSTEM CONFIGURA TION 3 3.2 System Using High Performance Model QCPU or Process CPU as CPU No.1 3.2.2 CPU module combinations and mou nting positions (a) High Performance model QCPU or Process CPU Up to four High Performance model QCPUs and/o r Process CPUs can be mounted in th e CPU slot (the slot on the right of the power supply modu[...]

50 (f) Empty slot setting Empty slots can be reserved for future addition of CPU modules. Set the n umber of CPU modules including empty slots in "No. of PLC" of PLC parameter ("Multiple CPU Setting"). Then, set "PLC (Empty)" to the type of a target slot from the right in PLC parameter ("I/O Assignment"). Ex.[...]

51 CHAPTER 3 SYSTEM CONFIGURA TION 3 3.2 System Using High Performance Model QCPU or Process CPU as CPU No.1 3.2.3 Available I/O modules and intelligent function modules 3.2.3 A vailable I/O modules and in telligent funct ion modules This section describes the I/O modules and in telligen t function modules that can be used. (1) I/O modules, interr [...]

52 (3) Number of mount able modules Refer to Page 68, Section 3.5. (4) Access ranges of controlled and non-controlled modules. Refer to the system configuration using a Basic model QCPU as CPU No.1. ( Page 40, Section 3.1.3 (4))[...]

53 CHAPTER 3 SYSTEM CONFIGURA TION 3 3.3 System Using Universal Model QCPU as CP U No.1 3.3.1 Available CPU modules , base units, power supply modules, and extension cables 3.3 System Using Universal Model QCPU as CPU No.1 This section describes the system configuratio n using a Universal model QCPU as CP U No.1. 3.3.1 A vailable CPU modules, base [...]

54 *1 For the CPU modules that can be combined and their mounting positions, refer to Page 60, Section 3.3.2. *2 When the Q00UCPU, Q01UCPU, or Q02UCPU is used as CPU No.1, one more CPU module (CPU No.2) can be mounted. The following CPU modul es can be mounted as CPU No.2. *3 These modules and units can be used when a Universal model QCPU with a se[...]

55 CHAPTER 3 SYSTEM CONFIGURA TION 3 3.3 System Using Universal Model QCPU as CP U No.1 3.3.1 Available CPU modules , base units, power supply modules, and extension cables (b) Precautions • If I/O modules are mounted exceeding the maximum number , "SP .UNIT LA Y ERR" (error code: 2124) occurs. • "Number of CPU modules" indi[...]

56 (2) When a main base unit (Q3  B) is used (a) Available m odules, the number of extension base unit s, and the number of mount able modules Item Description Number of CPU modules 4 CPU modules Applicable CPU module *1 Universal model QCPU Q00UCPU, Q01 UCPU, Q02UCPU The modules can be used as CPU No.1. *2 Q03UD(E)CPU, Q03UDVCPU, Q04UD(E)HCPU, [...]

57 CHAPTER 3 SYSTEM CONFIGURA TION 3 3.3 System Using Universal Model QCPU as CP U No.1 3.3.1 Available CPU modules , base units, power supply modules, and extension cables *1 For the CPU modules that can be combined and their mounting positions, refer to Page 60, Section 3.3.2 . *2 When the Q00UCPU, Q01U CPU, or Q0 2UCPU is use d as CPU No.1, two [...]

58 (3) When a redundant power main base unit (Q3  RB) is used (a) Available m odules, the number of extension base unit s, and the number of mount able modules *1 For the CPU modules that can be combined and their mounting positions, refer to Page 60, Section 3.3.2. *2 When the Q00UCPU, Q01UCPU, or Q02UCPU is used as CPU No.1, one more CPU modul[...]

59 CHAPTER 3 SYSTEM CONFIGURA TION 3 3.3 System Using Universal Model QCPU as CP U No.1 3.3.1 Available CPU modules , base units, power supply modules, and extension cables (4) When a slim type main base unit (Q3  SB) is used (a) Availa ble modules, the number of extension base unit s, and the number of mount able modules *1 For the CPU modules [...]

60 3.3.2 CPU module combinations and mounting posit ions This section describes the combinati ons and mounting positions of CPU modules when a Universal model QC PU is used as CPU No.1. Note that the CPU modu les that can be mounted di ffer depending on the main base unit used. ( Page 53, Section 3.3.1) (1) Combinations *1 A C Controller module and[...]

61 CHAPTER 3 SYSTEM CONFIGURA TION 3 3.3 System Using Universal Model QCPU as CP U No.1 3.3.2 CPU module combinations and mou nting positions (2) Mounting positions The following shows the possible combin ations of mounti ng positions of CPU modules in a multiple CPU system. • When the Q00UCPU, Q01UCPU, or Q02UCPU is used as CPU No.1 *1 The QCPU [...]

62 • When a CPU module other than the Q00UCPU, Q01UCPU, or Q02UCPU is used as CPU No.1 *1 The QCPU used as CPU No.1 indicates a Universal model QCPU (except the Q00UC PU, Q01UCPU, and Q02UCPU). The QCPU used as CPU No.2 or later indicates a High Pe rformance model QCPU, Proce ss CPU, or Universal model QCPU (except the Q00UCPU, Q01UCPU, and Q02UC[...]

63 CHAPTER 3 SYSTEM CONFIGURA TION 3 3.3 System Using Universal Model QCPU as CP U No.1 3.3.2 CPU module combinations and mou nting positions (a) Universal model QCPU Only one Q00UCPU, Q01UCPU, or Q02U C PU can be mo unted in the CPU slo t (the slot o n the right of the power supply module). Up to four Universal model QCPUs other than the Q0 0UCPU,[...]

64 (f) Empty slot setting Empty slots can be reserved for future addition of CPU modules. Set the n umber of CPU modules including empty slots in "No. of PLC" of PLC parameter ("Multiple CPU Setting"). Then, set "PLC (Empty)" to the type of a target slot in PLC parameter ("I/O Assignment"). Ex. Setting "[...]

65 CHAPTER 3 SYSTEM CONFIGURA TION 3 3.4 Applicable Software 3.4 Applicable Sof tware This section describes software p ackage s applicable in a multiple CPU system. (1) Applicable GX Works2, GX Developer , and PX Developer The following table lists the applicable versions of GX Works2, GX Developer , and PX Developer . *1 T o use GX Works2 in comb[...]

66 (2) Applicable GX Configurator The following tables list the applicable versions of GX C onfigurator. Applicable GX Conf igurator versi ons differ depending on the intellig ent function module used. ( Manual for the intelligent function module used) (a) When a Basic model QCPU, High Performance model QCPU, or Process CPU is used *1 T o use GX Co[...]

67 CHAPTER 3 SYSTEM CONFIGURA TION 3 3.4 Applicable Software (b) When a Universal model QCPU is used *1 The software can be used by installing GX Developer version 8.48A or later . *2 The software can be used by installing GX Developer version 8.62Q or later . *3 The software can be used by installing GX Developer version 8.68W or later . *4 The so[...]

68 3.5 Precautions for System Configuration This section describes restrictions and precautions on system configuration. (1) Number of mount able modules The number of mo untable modules and suppo rted function s are restricted depending on the CPU module used. For the numb er of modules that can be connected to each Motion CPU, C Control ler modul[...]

69 CHAPTER 3 SYSTEM CONFIGURA TION 3 3.5 Precautions for System Configuration (b) When a High Performance model QCPU or Process CPU is used *1 One CPU module can control the following n umber of modules by setting CC-Link network parameters. • CPU module with a serial numb er (first five digits) of "08031" or earlier: Up to 4 modules ?[...]

70 Remark For the restrictions on mounting A-series modules on the QA6  B or QA6ADP+A5  B/A6  B, refer to the following. QA65B/QA68B Extension Base Unit User's Manual QA6ADP QA Conversion A dapter Module User's Manual For the restrictions on mounting AnS-se ries modules on the QA1S6ADP+A1S5  B/A1S6  B, refer to the followin[...]

71 CHAPTER 3 SYSTEM CONFIGURA TION 3 3.5 Precautions for System Configuration (c) When a Universal model QCPU is used Product Model Maximum number of modu les/units per system CC-Link IE Controller Network module *4 • QJ71GP21-SX • QJ71GP21S-SX Up to 4 modules in total With the Q00UCPU, Q01UCPU, or Q02UCPU, the maximum number of connectable mod[...]

72 *1 One CPU module can control t he following number of modules by setting C C-Link network parameters. • Q00UCPU or Q01UCPU: Up to 2 modules • Q02UCPU: Up to 4 modules • Other CPU modules: Up to 8 modules There is no restriction on the number of mounted modules w hen the parameters are set with the CC-Link dedicated instructions. *2 For th[...]

73 CHAPTER 3 SYSTEM CONFIGURA TION 3 3.5 Precautions for System Configuration (2) Modules that have restrictions when used with an Universal model QCPU For modules that have restrictions when used with an Uni versal model QCPU, refer to the following manual. QnUCPU User's Manual (Functio n Explanation, Program Fun damentals) (3) Combinations o[...]

74 (7) Precautions for connecting a GOT The following GOT series can be used. • GOT -A900 se ries *1 • GOT -F900 series (The Q-mode compatible operating sys tem and communication driver must be installed.) *1 • GOT1000 series The GOT800 series, A77GOT , and A64GOT cannot be used. *1 Universal model QCPUs do not support the GOT -A900 and GOT-F[...]

75 CHAPTER 4 ST ARTING UP MUL TIPLE CPU SYSTEM 4 4.1 Procedure Before Operation CHAPTER 4 ST ARTING UP MUL TIPLE CPU SYSTEM This chapter describes the procedure fo r st arting up a multiple CPU system. 4.1 Procedure Before Operation Check box Determine the role (controls and functions) of each CPU module used in a multiple CPU system. Study details[...]

76 *1 When a PC CPU module is used, the QCPU can be bus-connec ted to a programming tool by installing the programming tool in the PC CPU module. Select "Q Series Bus" for the "PC side I/F" setting in the "Transfer Setup" window using the programming tool. *2 If an error has occurred, check the error cause us ing th e [...]

77 CHAPTER 4 ST ARTING UP MUL TIPLE CPU SYSTEM 4 4.2 Operation Settings 4.2 Operation Settings This section describes the settings r equired to operate a multip le CPU system. A system wher e three Universal model QCPUs are mounted shall be used as an exampl e. (1) Parameters required (a) Basic model QCPU, High Performance model QCPU, and Process C[...]

78 (b) Universal model QCPU Settings of parameters in double-lin ed squares, except some parameters, must be the same in all the CPU modules used in a multiple C PU system. ( Page 172, Appendix 1.1) *1 Universal model QCPUs do not support the online change func tion, but the set ting is r equired to replace modules controlled by the Process CPU on [...]

79 CHAPTER 4 ST ARTING UP MUL TIPLE CPU SYSTEM 4 4.2 Operation Settings 4.2.1 System configuration example 4.2.1 System configuration example This section describes the procedure fo r setting p arameters required in a mu ltiple CPU system, us ing the following system as an example. 1 1 2 3 1 1 222 3 3 3 CPU 0 4 5 6 7 Slot number Control CPU setting[...]

80 4.2.2 Parameter settings This section describes p arameters required for the syst em configurat ion on Page 79, Section 4.2.1. Use a programming tool to set parameters. • Settings of parameters in double-lined squares on P age 77, Section 4.2 (1) must be the same in all the CPU modules in a multiple CPU system. • The necessity of p arameters[...]

81 CHAPTER 4 ST ARTING UP MUL TIPLE CPU SYSTEM 4 4.2 Operation Settings 4.2.2 Parameter settings Item Description Default No. of PLC Set the number of CPU modules mounted on the main base unit in the multiple CPU system. The number of modules differs depending on the CPU module used as CPU No.1 and the main base unit used. ( Page 31, CHAPTER 3) Thi[...]

82 Match "No. of PLC" with the number of CPU modules actually mounted. If the numbers do no t match, an error will occur . Online Module Change (1) Basic model QCPU This parameter is not supported. (2) Proces s CPU Check the checkbox to enable online module change. (3) High Performance model QCPU and Univer sal model QCPU Check the checkb[...]

83 CHAPTER 4 ST ARTING UP MUL TIPLE CPU SYSTEM 4 4.2 Operation Settings 4.2.2 Parameter settings 3. Set the types and point s for the mounted modules in the "I/O Assignment" wind ow of PLC parameter . Project window [Parameter] [PLC Parameter] [I/O Assignmen t] Item Description Default Ty p e Select the type of a mounted module. T o reser[...]

84 4. Click the button in the "I/O Assignment" window , and set a control CPU for each I/O module and intelligen t function module. 5. Set other p arameters requir ed. 6. Save the project using the progr amming tool so that the multiple CPU system parameter settings can be used in othe r CPU modules. [Project] [Save As] Item Description D[...]

85 CHAPTER 4 ST ARTING UP MUL TIPLE CPU SYSTEM 4 4.2 Operation Settings 4.2.2 Parameter settings (2) Using the multiple CPU system para meters set to another CPU module 1. Click the button in the "Multiple CP U Setting" window of PL C p arameter . Select and open the project file fro m which the settings will be imported . Project window [...]

86 4. Check the "Points Occupied by Empty Slot" setting in the "PLC System" window of PLC par a m et e r. Project windo w [Param eter] [PLC paramet e r] [PLC System] "Points Occupied by Empty slots" 5. Check the settings in the "I/O Assign ment" window of PLC parameter . Project window [Parameter] [PLC parame[...]

87 CHAPTER 4 ST ARTING UP MUL TIPLE CPU SYSTEM 4 4.3 Program Examples for Communications by Auto Refresh 4.3.1 Program examples for Basic model QCPU, High Performance model QCPU, and Process CPU 4.3 Program Examples for Communications by Auto Refresh 4.3.1 Program examples for Basic mo del QCPU, High Performance model QCPU, and Process CPU This sec[...]

88 (b) Auto refresh setting Set auto refresh paramete rs. ( Page 123, Section 6.1.1 (2)) Project window [Parameter] [PLC Parame ter] [Multiple CPU Setting] "Communicati on Area Setting (Refresh Setting)"[...]

89 CHAPTER 4 ST ARTING UP MUL TIPLE CPU SYSTEM 4 4.3 Program Examples for Communications by Auto Refresh 4.3.1 Program examples for Basic model QCPU, High Performance model QCPU, and Process CPU (2) Program examples (a) Sending bit data and word da t a from CPU No.1 to CPU No.2 • Devices used in CPU modules • Program example of CPU No.1 • Pro[...]

90 (b) Continuously sending dat a from CPU No.1 to CPU No.2 • Devices used in CPU modules For handshake between CPU No.1 and No.2, refer to Page 132, Section 6.1.1 (3). • Program example of CPU No.1 • Program example of CPU No.2 Device used in CPU No.1 Device used in CPU No.2 M40 Send data from CPU No.2 to CPU No.1 M40 Send data from CPU No.2[...]

91 CHAPTER 4 ST ARTING UP MUL TIPLE CPU SYSTEM 4 4.3 Program Examples for Communications by Auto Refresh 4.3.1 Program examples for Basic model QCPU, High Performance model QCPU, and Process CPU (c) Continuously reading/writing dat a between CPU No.1 and No.2 using the use r setting area Data can be read/write between CPU modu les by program s usin[...]

92 • Devices used in CPU modules • Program example of CPU No.2 • Program example of CPU No.1 Device used in CPU No.1 Device used in CPU No.2 M31 Send data from CPU No.1 to CPU No.2 M31 Send data from CPU No.1 to CPU No.2 M63 Send data from CPU No.2 to CPU No.1 M63 Send data from CPU No.2 to CPU No.1 D100 to D149 S torage de vice for data rece[...]

93 CHAPTER 4 ST ARTING UP MUL TIPLE CPU SYSTEM 4 4.3 Program Examples for Communications by Auto Refresh 4.3.2 Program examples for Universal model QCPU 4.3.2 Program examples for Universal model QCPU This section provide s program examples for communicating data by a uto refresh (using th e multiple C PU high speed transmission area) betw een the [...]

94 (b) Auto refresh setting Set auto refresh parameters. ( Page 138, Section 6.1.2 (3)) Project window [Parameter] [PLC Parameter] [Multiple CPU Setting] "Multiple CPU High S peed T r ansmission Area Setti ng" Setting of CPU No.1 Setting of CPU No.2[...]

95 CHAPTER 4 ST ARTING UP MUL TIPLE CPU SYSTEM 4 4.3 Program Examples for Communications by Auto Refresh 4.3.2 Program examples for Universal model QCPU (2) Program examples (a) Sending bit data and word da t a from CPU No.1 to CPU No.2 • Devices used in CPU modules • Program example of CPU No.1 • Program example of CPU No.2 Device used in CP[...]

96 (b) Continuously sending dat a from CPU No.1 to CPU No.2 • Devices used in CPU modules For handshake between CPU No.1 and No.2, refer to Page 148, Section 6.1.2 (5). • Program example of CPU No.1 • Program example of CPU No.2 Device used in CPU No.1 Device used in CPU No.2 M40 Send data from CPU No.2 to CPU No.1 M40 Send data from CPU No.2[...]

97 CHAPTER 4 ST ARTING UP MUL TIPLE CPU SYSTEM 4 4.3 Program Examples for Communications by Auto Refresh 4.3.2 Program examples for Universal model QCPU (c) Continuously reading/writing dat a between CPU No.1 and CPU No.2 using the user setting area in the multiple CPU high speed trans mission area Data can be read/write between CPU modules using t[...]

98 • Devices used in CPU modules • Program example of CPU No.2 • Program example of CPU No.1 Device used in CPU No.1 Device used in CPU No.2 M31 Send data from CPU No.1 to CPU No.2 M31 Send data from CPU No.1 to CPU No.2 M63 Send data from CPU No.2 to CPU No.1 M63 Send data from CPU No.2 to CPU No.1 D100 to D149 S torage de vice for data rece[...]

99 CHAPTER 4 ST ARTING UP MUL TIPLE CPU SYSTEM 4 4.4 Clock Data 4.4.1 Clock data of CPU modules 4.4 Clock Dat a This section describes clock data of CPU modules and intelligent function modules. 4.4.1 Clock dat a of CPU modules Set clock data to CPU No.1 in the multip le CPU system using th e programming tool. [Online] [Set Clock] The clock data se[...]

100 4.4.2 Clock dat a of intelligent function modules When an error has occurre d, some intelligent function mo dul es store the code and time (clock data read from th e QCPU) corresponding to the error into the buffer memory . Th ose modules store the clo ck data of CPU No .1 as the error time regardless of whether the mo dul es are co ntrolled by[...]

101 CHAPTER 4 ST ARTING UP MUL TIPLE CPU SYSTEM 4 4.5 Resetting a Multiple CPU System 4.5 Resetting a Multiple CPU System In a multiple CPU system, resetting the QCPU used as CPU No.1 resets all th e modules (CPU modules, I/O modules, and intelligent functi on modules) in the system. (1) If a stop error exists any of the CPU modules in the multiple[...]

102 4.6 System Operation When a S top Error Occurs The multiple CPU system operati on differs depending on the CPU module where a stop error has occurred. (1) When a stop error has occurred in CPU No.1 "MUL TI CPU DOWN" (error co de: 7000) occurs in all the other CPU modules and the operation of the multiple CPU system stops. (2) When a s[...]

103 CHAPTER 4 ST ARTING UP MUL TIPLE CPU SYSTEM 4 4.6 System Operation When a Stop Error Occu rs If a stop error occurs, "MUL T I CPU DOWN" (error code: 7000) will occur in the CPU module where the stop error has been detected. Depending on the timing of error detection, " MUL TI CPU DOWN" may be detected in anoth er CPU module [...]

104 CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES This chapter describes the access between CPU modules an d other module s (I/O modules a nd intelligent function modules). 5.1 Access to Controlled Modules In a multiple CPU system, CPU modules access I/O modules a nd intelligent fu nction modules in the same way as in a single CPU system. [...]

105 CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES 5 5.2 Access to Non-controlled Module s 5.2.1 Loading input (X) da ta 5.2.1 Loading input (X) dat a Data in the input (X) of input modules and intelligent function modul es controlled by other CPU mo dules can be loaded in accordance with the "I/O Sharing When Using Mu ltiple CPUs"[...]

106 (a) M odules that can load input (X) dat a Data in the input (X) can be loaded from the followin g modules mounted on the ma in base unit or extension base unit. *1 When input (X) of the QX48Y57 (I/O combined mo dule) is ta rgeted, data in Xn8 to XnF (output part) are loaded as all points off. *2 When input (X) of an output module is targeted, [...]

107 CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES 5 5.2 Access to Non-controlled Module s 5.2.2 Loading output (Y) data 5.2.2 Loading output (Y) dat a Data in the output (Y) of output modules and intelligent function modules controlled by other CPU modules can be loaded in accordance with the "I/O S haring When Using Multiple CPUs&quo[...]

108 (a) M odules that can load output (Y) dat a Data in the output (Y) can be loade d from the follo win g modules mounted on the main base unit or extension base unit. (b) Modules that cannot load output (Y) dat a Output data of empty slots and MELSECNET/H or CC-Link network remote stations controlled by other CPU modules cannot be loaded. T o use[...]

109 CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES 5 5.2 Access to Non-controlled Module s 5.2.3 Output to output modules and intelligent function modules 5.2.3 Output to output mo dules and intelligent function modules The on/off data cannot be output to non-controlled modules. If the output status of the output module or intelligent funct[...]

110 5.2.4 Access to the intelligent fun ction module buffer memory Data in the buffer memory of intelligent function modules controlled by other CPU module s can be read regardless of the "I/O Sharing When Using Multiple CPUs" sett ing in PLC parameter ("Multiple CPU Setting"). (1) Reading dat a from the buffer memory Data can b[...]

111 CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES 5 5.2 Access to Non-controlled Module s 5.2.5 Access using t he link direct device 5.2.5 Access using the li nk direct de vice Only the control CPU can execute instru ctions using the link direct device to access I/O modules and intelligent function modules. The link direct device cannot be[...]

112 5.3 Access From a Programming T ool This section describes access from a programmi ng tool to modules in a multiple CPU system. (1) Access to QCPUs A programming tool can read/write parameters and prog rams from/to the QCPU connected a s well as mo nitor and test the entire system. T o access another QCPU via the QC PU connected, specify the ta[...]

113 CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES 5 5.3 Access From a Programming Tool (2) Access to controlled and non-controlled modules A programming tool can access modules both cont rolled and not controlled by the QCPU connected. The programming tool connected to one QCPU can access all the modules controlled by any QCPU in the multi[...]

114 (3) Access from the prog ramming tool connected to another station The programming tool connected to another station in the same network can access all the QCPUs in the multiple CPU system. Ex. Over MELSECNET/H PLC to PLC network Control CPU setting Control CPU setting MELSECNET/H PLC to PLC network Station No. 2 (normal station) Station No. 1([...]

115 CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES 5 5.4 Accessible QCPUs when GOT is connected 5.4 Accessible QCPUs when GOT is connected For the connected GOT , QCPUs that can be accessed di ffer depending on the connection method. ( Manual for the GOT used)[...]

116 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES This chapter describes data co mmunications among CP U modules in a multiple CPU system. (1) Communication methods The following table li sts the communication methods av ailable among CPU modules. Item Description Reference Communications using the CPU shared memory Data communications is performed a[...]

117 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 (2) Communications among CPU modules Communications availability differs depending on th e CPU modules used as the communication sour ce and target. : Communications available ×: Communications not available *1 There are restrictions on available instructions de pending on the version of the Motion[...]

118 6.1 Communications Using the CPU Shared Memory This section describes data communica tions among CPU m odules in a multiple CPU system using the CPU shared memory . (1) CPU shared memory The CPU shared memory is a data storage area in a CPU modul e and used to read/write data among CPU modules in a multiple CPU system. The CPU shared memory con[...]

119 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.1 Communications Using the CPU Shared Memory (2) CPU shared memory configuration and availability of dat a communications by programs The following shows the CPU shared me mory configurat ion and th e availability of data communications by programs using the CPU shared memory . • Basic model QCP[...]

120 • Universal model QCPU *1 The Q00UCPU, Q01UCPU, and Q02UCPU do not have th e use-prohibited area and the multiple CPU high sp eed transmission area. Host CPU operation information area System area Auto refresh area User setting area CPU shared memory (0 H ) ( 1FF H ) to ( 200 H ) ( 7FF H ) to ( 800 H ) (FFF H ) to G0 G 51 1 to G 512 G 2047 to[...]

121 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.1 Communications Using the CPU Shared Memory (3) Host CPU operation information area (a) Information stored The following information about the host CPU module is stored in this area. *1 In a single CPU system, all the values are set to 0. *1 Motion CPUs do not use the areas 5 H to 1C H . If data [...]

122 6.1.1 Communications by auto refresh (using the auto refresh area) This section describes data communications by auto refres h using the auto refresh area in the CPU sha red memory . Data communications by auto refresh can also be performed us ing the auto refresh area in the multiple CPU high speed transmission area. Use of the multiple CPU hi[...]

123 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.1 Communications Using the CPU Shared Memory 6.1.1 Communications by auto refr esh (using the auto refresh area) (b) Executing auto refresh Auto refresh is executed when the CP U modules are in RUN, STOP , or P A USE status. Auto refresh cannot be executed when a stop error has occurred in any of [...]

124 (a) "Change Screens" Up to four auto refresh ranges can be set. Set and switch the ranges in this parameter . With different settings, on/off data in bit devices and other data in word devices can be auto-refreshed separately . (b) "CPU Spe cific Send Range" Set the number of points in the CPU shared memory in incr ements of[...]

125 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.1 Communications Using the CPU Shared Memory 6.1.1 Communications by auto refr esh (using the auto refresh area) Ex. T o refresh data in B0 to B1F (32 points) of CPU No.1 and B20 to B3F (32 points) of CPU No.2, set "2" in "Points" because the link relay (B) is a bit device. [Au[...]

126 (c) "PLC Side Device" Set auto refresh target devices. The following devices can be set. There are two auto refresh device range setting methods. *1 • Setting device ranges sequentially from the st art device number of CPU No.1 • Setting device ranges for each CPU module freely *1 Auto refresh devices of the following QCPUs can on[...]

127 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.1 Communications Using the CPU Shared Memory 6.1.1 Communications by auto refr esh (using the auto refresh area) • Dif ferent devices can be set for Setting 1 to 4. The same device can also be set as long as the device ranges fo r Setting 1 to 4 are not overlapped. [Auto refresh processing] Sett[...]

128 • Devices of Setting 1 to 4 can be set independently for each CPU module. For example, while t he link relay (B) is set for CPU No.1, the internal relay (M) can be set for CPU No.2. [Auto refresh processing] Refresh setting of CPU No.1 The same number of points is set for all the CPU modules. Refresh setting of CPU No.2 The same device is set[...]

129 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.1 Communications Using the CPU Shared Memory 6.1.1 Communications by auto refr esh (using the auto refresh area) Ex. Operations when executing auto refresh of four ranges (Setting 1: link relay (B), Settin g 2: link register (W), Setting 3: dat a register (D), Setting 4: internal relay (M)) Settin[...]

130 • There are following advantages if device ranges are set for each CPU module freely . • T he order of the send ranges can be changed for each CPU modu le. • Since unnecessary refresh can set to be di sab led, the system scan time will be reduced. Ex. Changing the order of send ranges for each CPU module The following is a setting example[...]

131 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.1 Communications Using the CPU Shared Memory 6.1.1 Communications by auto refr esh (using the auto refresh area) Ex. Disabling unnecessary refresh Unnecessary refresh can set to be disabled by n ot setting the device ranges of other CPU modules where auto refresh is not required. The device ranges[...]

132 (3) Precautions (a) Local device setting (except the Basic model QCPU) Device ranges set for the auto refresh target cannot be set as local devices. If se t, the refresh dat a will not be updated. (b) Using the same file name as that of the program in the file register (except the Basic model QCPU) Do not set the file register of each program a[...]

133 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.1 Communications Using the CPU Shared Memory 6.1.1 Communications by auto refr esh (using the auto refresh area) Ex. Auto refresh between a QCPU and a Motion CPU The following are the program examples for the Basic model QCPU and Motion CPU whe n PLC parameters ("Communica tion Area Setting ([...]

134 Ex. Auto refresh between QCPUs The following are the program examples for the High Performance mo del QCPUs when PLC parameters ("Communication Area Setting (Refresh Setting)" of "Multiple CP U Setting") ar e set as shown bel ow . [Parameter setting] Use D0.0 as an interlock device of CPU No.1 (data setting complete bit) and[...]

135 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.1 Communications Using the CPU Shared Memory 6.1.2 Communications by auto refresh (using the multiple CPU high speed transmission ar ea) 6.1.2 Communications by auto refres h (using the multiple CPU high speed transmission area) This section describes data communications by auto refres h using the[...]

136 (2) Communications by auto refresh (a) Overview Auto refresh communicates data using the auto refresh area of the multiple CPU high speed transmission area in the CPU shared memory . The data written to the au to refresh area of the multiple CPU high speed transmission area is sent to that of the other CPU modules at regular intervals (multiple[...]

137 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.1 Communications Using the CPU Shared Memory 6.1.2 Communications by auto refresh (using the multiple CPU high speed transmission ar ea) (b) Memory configuration of the multiple CPU high sp eed transmission area The following shows the memory configuration of the multiple CPU high speed transmissi[...]

138 (3) Multiple CPU high speed transmission area settings T o perform auto refresh of data in the CPU shared memory , set the ranges (number of points) to be sent by each CPU module ("CPU S pe cific Send Range") and the devices for storing da ta ("Auto Refresh Setting") in PLC parameter ("Multiple CPU Setting"). Proje[...]

139 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.1 Communications Using the CPU Shared Memory 6.1.2 Communications by auto refresh (using the multiple CPU high speed transmission ar ea) T o check the auto refresh directions, spec ify the CPU n umber in "Host St ation" of PLC parameter ("Multiple CPU Setting"). • Multiple CP[...]

140 (a) "CPU Specific Send Range" Set the number of points for the multiple CPU high speed transmission area used in each CPU module. *1 The following number of points is set by default. *2 Set the number of points so that the total points of al l the CPU modules will be the following points or less. • When two CPU modules are mounted: [...]

141 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.1 Communications Using the CPU Shared Memory 6.1.2 Communications by auto refresh (using the multiple CPU high speed transmission ar ea) The number of points for the system area used by dedicated instructions can be changed to 2K points by checking the "Advanced Setting" checkbox. This i[...]

142 (b) "Auto Refresh Setting" Set auto refresh target devices to communicate data by auto refresh using the multiple CPU high speed transmission area. Up to 32 ranges can be set for each CPU modul e. *1 Set the number of points within the points set for the "CPU Specific Send Range" of each CPU module. *2 Bit devices can be spe[...]

143 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.1 Communications Using the CPU Shared Memory 6.1.2 Communications by auto refresh (using the multiple CPU high speed transmission ar ea) (4) Auto refresh setting examples and dat a flow The data flow among CPU modules will be as follows in a multiple CPU system containing three CPU modules with tw[...]

144 (b) Flow of dat a sent from CPU No.1 to other CPU modules <Parameter setting> Refer to those related to the data communications of CPU No.1 ((a) to (c)) among the au to refresh setting examples on Page 143, Section 6.1.2 (4) (a). <Flow of data sent from CP U No.1 to other CPU modules> • CPU No.1 writes dat a (CPU No.1 send dat a) [...]

145 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.1 Communications Using the CPU Shared Memory 6.1.2 Communications by auto refresh (using the multiple CPU high speed transmission ar ea) (c) Flow of data s ent from CPU No.2 to other CPU modules <Paramet er setting > Refer to those related to the data communications of CPU No.2 ((d) to (f)) [...]

146 (d) Flow of dat a sent from CPU No.3 to other CPU modules <Parameter setting> Refer to those related to the data communications of CPU No.3 ((g) to (i)) among the auto refresh setting examples on Page 143, Section 6.1.2 (4) (a). <Flow of data sent from CP U No.3 to other CPU modules> • CPU No.3 writes dat a (CPU No.3 send dat a) i[...]

147 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.1 Communications Using the CPU Shared Memory 6.1.2 Communications by auto refresh (using the multiple CPU high speed transmission ar ea) If "S tart" and "End" fields are left blank in "Auto Refresh Sett ing", auto refresh is not performed. ( Only the receive area can [...]

148 (5) Precautions (a) Local device setting Device ranges set for the auto refresh target cannot be set as local devices. If se t, the refresh dat a will not be updated. (b) Using the same file name as that o f the program in the file register Do not set the file register of each program as an auto refresh target device. If set, data are automatic[...]

149 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.1 Communications Using the CPU Shared Memory 6.1.2 Communications by auto refresh (using the multiple CPU high speed transmission ar ea) Ex. Program example for providing an interloc k between CPU No.1 and No.2 [Parameter setting] Use M0 as an interlock devic e of CPU No.1 (data setting complete b[...]

150 6.1.3 Communications by programs using the CPU shared memory This section describes data communications by programs using the CPU shared memory . The QCPU in the multiple CPU system communicates data by executing programs in the following cases. • T o read/write data from/t o other CPU module (QCPU, C Controlle r module, or PC CPU module) in [...]

151 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.1 Communications Using the CPU Shared Memory 6.1.3 Communications by programs using the CPU shared memor y (2) Instructions used to read/write dat a from/to th e CPU shared memory The QCPU in the multiple CPU system communicates da ta with other CPU modules by executing read/write instructions. Th[...]

152 (4) Overview (when the user setting area is used) The data written to the CPU shared memory in the host CPU module by a write instruction can be read by other CPU modules b y a read instru ction. Unlike the auto refresh using the CPU shared memory , the up-t o-date data at the time of an instruction execution can be read directly . The followin[...]

153 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.1 Communications Using the CPU Shared Memory 6.1.3 Communications by programs using the CPU shared memor y (5) Overview (when the user setting area in the multiple CPU high speed communication area is used) The data written to the multiple CPU high speed transmissi on area of the host CPU module b[...]

154 (6) Parameter settings T o use the user setti ng area in the multiple CPU high sp eed transmission area, set the ranges (number of points) to be sent by each CPU module ("CPU S pecific Send Range ") in PLC parameter ("Multiple CPU Setting"). For setting details, refer to Page 135, Section 6.1.2. (7) Assurance of send data Ol[...]

155 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.1 Communications Using the CPU Shared Memory 6.1.3 Communications by programs using the CPU shared memor y (b) Preventing inconsistency of dat a exceeding 32 bit s • When the user setting area is used The read instruction reads data in order starting fr om the start address to the end address of[...]

156 • When the user settin g area in the mul tip le CPU high spe ed transmission area i s used The read instru ction reads dat a in order of those we re written to the user setting area. T o prevent data inconsistency , use the device w ritten after the transfe r data as an interlock regardless of the device type and address. Ex. Program example [...]

157 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.1 Communications Using the CPU Shared Memory 6.1.3 Communications by programs using the CPU shared memor y (8) Precautions (a) St art I/O numbers of CPU modules Set the following start I/O numbers to each CP U module for the read /write instructions. (b) Wri ting dat a to the CPU shared memory Do [...]

158 (g) Writing dat a to the CPU shared memory of it s own • Basic model QCPU Data can be written with any write instruction. • Hig h Performance model QCPU or Process CPU Data can be written with the S.TO instruction. However , data cannot be written with i nstructions using the cyclic transmissi on area device (U3EnG  ). If used, "SP[...]

159 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.1 Communications Using the CPU Shared Memory 6.1.4 Communications among CPU m odules when an er ror is detected 6.1.4 Communications among CPU modules when an error is detected This section describes the operations performed when an error is detected duri ng data communications among CPU modules u[...]

160 6.2 Control Directions from QCPU to Motion CPU Control directions can be issued from the QCPU to Motion CPU in a multiple CP U system by using the following motion dedicated instructions. (Control directions canno t be issued from th e Motion CPU to another Motion CPU.) For details on the motion d edicated instructions and their a vailabilities[...]

161 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.2 Control Directions from QCPU to Motion CPU Remark C Controller modules have functions t hat direct control to Motion CPUs. ( Manual for the C Con troller module used) Ex. S.SFCS instruction The motion SFC programs in a Motion CPU can be started up from the QCPU. One QCPU can execute up to total [...]

162 6.3 Communications Among CPU Modules By Dedicated Instructions 6.3.1 Reading/writing device dat a from/to Motion CPU The QCPU can read/write device data from/to the Motion CPU by executing the mu ltiple CPU transmission dedicated instructions and multiple CPU high-speed transmission dedica ted instructions. (The Moti on CPU cannot read/write de[...]

163 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.3 Communications Among CPU Modules By Dedicated Instr uctions 6.3.1 Reading/writing device data from/to Motion CPU (2) Multiple CPU high-speed tran smission dedicated instructions The Universal model QCPU reads/writes device da ta from/to the Q172DCPU(-S1), Q173DCPU(-S1), Q172DSCPU, and Q173DSCPU [...]

164 6.3.2 St arting interrupt programs from QCPU to C Controller module/PC CPU module The QCPU can start interrupt programs to the C controll er unit/PC CPU module by executing the multiple CPU transmission dedicated instructions and multiple CP U high-speed transmission dedicated instructions. Interrupt programs can be started from a C Controller [...]

165 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.3 Communications Among CPU Modules By Dedicated Instr uctions 6.3.3 Reading/writing device data between QCPUs 6.3.3 Reading/writing device dat a between QCPUs The Universal model QCPU can read/write device da ta fr om/to another Universal model QCPU by executing the multiple CPU high-spe ed transm[...]

166 6.4 Multiple CPU Synchronous Interrupt This function executes interrupt p rograms (multiple CPU syn chronous interrupt programs) at the start timing of each multiple CPU high speed transmission cycle. The functi on enabl es data communications among CPU modules i n synchronization with th e multiple CPU high s peed transmission cycles. Since th[...]

167 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.4 Multiple CPU Synchronous Interrupt (3) Applicable CPU modules The multiple CPU synch ronous in terrupt function can be executed when an y of the following CPU modul es is used. • Universal model QCPU (except th e Q00UCPU, Q01UCPU, and Q02UCPU) • Motion CPU (Q172DCPU(-S1), Q173DCP U(-S1 ), Q1[...]

168 6.5 Multiple CPU synchronous st artup This function synchronizes the st ar tups of CPU No.1 to No.4 . Since the functi on monitors the startup of each CPU module, an interlock program normally used to check the startup of another CPU module before accessing is no lo nger required. This function, however , synchronizes the startups with the slow[...]

169 CHAPTER 6 COMMUNICA TIONS AMONG CPU MODULES 6 6.5 Multiple CPU synchronous startup (3) Precautions If a CPU module that does not support this function is used, uncheck the checkbox of the corres ponding CPU number in PLC parameter . Ex. When High Performance model QCPUs are used as CPU No.2 and No.4 Uncheck the checkboxes of CPU No.2 and No.4. [...]

170 APPENDICES Appendix 1 Parameters for a Multiple CPU System (1) Parameters required For a multiple CPU system, the following PLC parameters shall be set additionally to those for a single CPU system. • "Multiple CPU Setting" • "Control PLC" setting in "Detailed Setting" of "I/O Assignment" The same PLC[...]

171 APPENDICES A Appendix 1 Parameters for a Multiple CPU System (3) Checking the multiple In a multiple CPU system, wheth er the same multiple CPU parameters are set to all the CP U modules is checked at the following timing. • When a multiple CPU system is powered on • When CPU No.1 is reset • When the operating status of the CPU modules ar[...]

172 Appendix 1.1 List of p arameters (1) For Basic model QCPU, High Perf ormance model QCPU, and Process CPU The following table lists PLC pa rameters need to be set for a Basic model QCPU, High Performance QCPU, or Process CPU. *3 For a Basic model QCPU, the onli ne modu le change setting is disabled. High Performance model QCPUs do not support th[...]

173 APPENDICES A Appendix 1 Parameters for a Multiple CPU System Appendix 1.1 List of parameters (2) For Universal model QCPU The following table lists PLC parameters need to be set for a Universal model QCPU . PLC p arameter Setting *1 Consistency *2 Reference I/O Assignment I/O Assignment Ty p e - QnUCPU User's Manual (Function Explanation, [...]

174 *1 : Item that must be set in a multiple CPU system (A system does not op erate without setting.) : Item that is set if needed in a multiple CPU system - : Item that is the same as in a single CPU system *2 : Item that must have same settings among al l the C PU modules in a multiple CPU system : Item that must have same settings among all the [...]

175 APPENDICES A Appendix 2 Comparison with a Single CPU System Appendix 2 Comp arison with a Single CPU System This section describes comparison between a single CPU system and multiple CPU system. (1) When a Basic model QCPU is used *1 "Number of CPU modules" indicates the number set in "No . of PLC" of PLC parameter ("Mu[...]

176 *1 When a CPU module occupying two slots is mounted, the slot on the right of the CPU module will be 10 H . When a CPU module occupying three slots is mounted, the slot on the right of the CPU module will be 20 H . Item Single CPU system Multiple CPU system Reference Concept Number of CPU modules and mounting position Only 1 modu le in the CPU [...]

177 APPENDICES A Appendix 2 Comparison with a Single CPU System Item Single CPU system Multiple CPU system Reference Communications among CPU modules Communications by auto refresh using the CPU shared memory Not supported Basic model QCPU = 320 points, Motion CPU = 2048 points, C Controller module = 2048 points, PC CPU module = 2048 points, T otal[...]

178 (2) When a High Performan ce model QCPU is used *1 "Number of CPU modules" indicates the number set in "No. of PLC" of PLC parameter ("Multiple CPU Setting"). *2 When a module occupying two slots is mounted, the ma xi mum number of mountable I/O modules is the number obtained by "65 - (Number of CPU modules + [...]

179 APPENDICES A Appendix 2 Comparison with a Single CPU System Item Single CPU system Multiple CPU system Reference Access range Access from CPU module(s) to other modules All modules can be controlled. Relations between CPU modules and other modules must be set in "Control PLC" of PLC parameter . Page 104, CHAPTER 5 Access from G OT s A[...]

180 Scan time Factors that increase scan time • Writing data during RUN • Time reserved for communication processing • Writing data during RUN • Time reserved for communication processing • Refresh processing among CPU modules in the multiple CPU system • Waiting time Page 192, Appendix 4 Paramete r Parameters added for a multiple CPU s[...]

181 APPENDICES A Appendix 2 Comparison with a Single CPU System (3) When a Process CPU is used. *1 "Number of CPU modules" indicates the number set in "No . of PLC" of PLC parameter ("Multiple CPU Setting"). *2 When a module occupying two slots is mounted, the maximum number of mountable I/O modules is the number obtai[...]

182 Item Single CPU system Multiple CPU system Reference Access range Access from CPU module(s) to other modules All modules can be controlled. Relations between CPU modules and other modules must be set in "Control PLC" of PLC parameter . Page 104, CHAPTER 5 Access from GOT s Accessible A GOT can access a Process CPU of the specified CPU[...]

183 APPENDICES A Appendix 2 Comparison with a Single CPU System Scan time Factors that increase scan time • Writing data during RUN • Time reserved for communication processing • Writing data during RUN • Time reserved for communication processing • Refresh processing am ong CPU modules in a multiple CPU system • Waiting time Page 192, [...]

184 (4) When a Universa l model QCPU is used *1 "Number of CPU modules" indicates the number set in "No. of PLC" of PLC parameter ("Multiple CPU Setting"). *2 When a module occupying two slots is mounted, the ma xi mum number of mountable I/O modules is the number obtained by "65 - (Number of CPU modules + 1)"[...]

185 APPENDICES A Appendix 2 Comparison with a Single CPU System *1 When a CPU module occupying two slots is mounted, the slot on the right of the CPU module will be 10 H . When a CPU module occupying three slots is mounted, the slot on the right of the CPU module will be 20 H . *2 When a Universal model QCPU ( except the Q00UCPU, Q01UCPU, and Q02UC[...]

186 *1 When the Q00UCPU, Q01UCPU, or Q02 UCPU is used as CPU No.1, this type of communications cannot be performed. Item Single CPU system Multiple CPU system Reference Operation Operation when a CPU module is reset. The entire system is reset by resetting the Universal model QCPU. The entire system is reset by resetting the Process CPU (CPU No.1).[...]

187 APPENDICES A Appendix 2 Comparison with a Single CPU System *1 When the Q00UCPU, Q01UCPU, or Q02U CPU is used as CPU No.1, this parameter cannot be set. *2 AnS/A series-compatible modules can be used with a Universal model QCPU with a serial number (first five digits) of "13102" or later . Item Single CPU system Multiple CPU system Re[...]

188 Appendix 3 Precautions for Using AnS/A Series Modules (1) Multiple CPU system configurat ion for using An S/A series modules AnS/A series modules can be used in a multiple CPU system co nfiguration wher e all of the following conditions are met. (a) C PU No.1 The following QC PU must be used. • Universal model QCPU with a serial number (first[...]

189 APPENDICES A Appendix 3 Precautions for Using AnS/A Series Modules Ex. When CPU No.2 is set as a control CPU Set CPU No.2 as the control CPU of all slots where AnS/A series modules are mounted. If a different CPU No. is set as a control CPU for any of the AnS/A series modules, "P ARAMET ER ERROR" (error code: 3009) will occur and the [...]

190 (3) Access ranges of controlled and non-controlled modules Access ranges of the controlled and non-controlled modules in a multiple CPU system is shown below . : Accessible ×: Inaccessible Access target Controlled module Non-controll ed module ("All CPUs Can Read All Input s") Disabled (not check ed) Enabled (check ed) Input (X) × ?[...]

191 APPENDICES A Appendix 3 Precautions for Using AnS/A Series Modules (4) Precautions (a) Accessible device ranges When the following AnS/A series modules are used, accessible device ranges are restricted. • A1SJ71J92-S3, AJ71J92-S3 type JEMANET interface module • A1SD51S, AD51-S3, AD51H-S3 type intelligent co mmunication module • A1SJ71AP23[...]

192 Appendix 4 Processing Ti me Appendix 4.1 Concept of scan time The concept of scan time in a multiple CPU system is the same as that in a single CPU system. This section describes how to calc ulate the processing time when a multiple CPU system is configured. (1) I/O refresh time For the calculating formula of I/O re fresh time, refe r to the fo[...]

193 APPENDICES A Appendix 4 Processing Time Appendix 4.1 Concept of scan time (3) Common processing time In a multiple CPU system, the comm on proc essing time increases as shown below . QCPU Common proc essing time Q00CPU, Q01CPU (0.05 to 0.13) × (Number of other CPU modu les) ms Q02CPU 0.02ms Q02HCPU, Q06HCP U, Q12HCP U, Q25HCPU 0.03ms Q02PHCPU,[...]

194 Appendix 4.2 Factors that increase scan time The processing time in a multiple CPU system increases fr om that in a single CPU system when the following functions are used. When any of the following functions is use d, add the time va lues described in this section to the values calculated on Page 192, Appendix 4.1. • Auto refresh of the CPU [...]

195 APPENDICES A Appendix 4 Processing Time Appendix 4.2 Factors that increase scan time • For the High Performance model QCPU and Process CPU The number of receive word points is the sum of the number of word poin ts sent by other CPU modules. Ex. When the number of CPU modules is 4 and the host CPU is CPU No.1 The number of receive word points [...]

196 • For the Universal model QCPU The number of receive word points is the sum of t he number of word points sent by other CPU modules. Ex. When the number of CPU modules is 4 and the host CPU is CPU No.1 The number of receive word points will be the sum of the number of word points sent by CPU No.2 to No.4. For the auto refresh using the multip[...]

197 APPENDICES A Appendix 4 Processing Time Appendix 4.2 Factors that increase scan time (c) When auto refresh is executed by another CPU module during auto refresh processing The auto refresh time increases by the time obtained by the following calculatio n. • For the Basic model QCPU Use the following valu e for N6. • For the High Performance[...]

198 (2) Refresh of CC-Link IE and MELSECNET/H (a) R efresh time of CC-Link IE and MELSECNET/H This is the time required for executing refresh between a QCPU and a CC-Link IE module or MELSECNET/H module. For each refresh time, refer to the following. Reference manual for each network module used (b) Calculating formula In a multiple CPU system, if [...]

199 APPENDICES A Appendix 4 Processing Time Appendix 4.2 Factors that increase scan time (3) Auto refresh of CC-Link (a) Auto refresh time of CC-Link This is the time required for executi ng refresh bet ween a QCPU and a CC-Link master/l ocal module. For details, refer to the following. MELSEC-Q CC-Link System Master /Local Module U ser's Manu[...]

200 Appendix 4.3 Reducing processing time (1) Multiple CPU system processing CPU modules access I/O modules an d intelligent function modul es through a bus (base unit pattern or extension cable). Note that only one CPU mo dule can use the bus at a time. If more than one CPU module attempts to use the b us simultaneously , th e CPU module attempted[...]

2 4 7 I 201 INDEX A A series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 A series power supply module . . . . . . . . . . . . . . . . 17 Access from a programming tool . . . . . . . . . . . . . . 112 Access from the programming too l connected to another station . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Access [...]

202 H High Performa nce model QCPU . . . . . . . . . . . . . . 15 High-speed Universal model QCPU . . . . . . . . . . . . 15 Host CPU operation info rmation area . . . . . . . 118,121 Host station . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 How to check the host CPU number . . . . . . . . . . . . 26 How to check the multiple CPU pa[...]

2 4 7 I 203 R Readin g data from the buffer memory . . . . . . . . . . 110 Readin g/writin g device data fro m/to Motion CPU . . 162 Reducing proce ssing time . . . . . . . . . . . . . . . . . . 200 Redundant power extension base unit . . . . . . . . . . . 16 Redundant power main base unit . . . . . . . . . . . . . . 16 Redundant power supp ly base[...]

204 REVISIONS *The manual number is given on the bottom left of the back cover . Print date Manual number Revisi on January 2004 SH(NA)-080485ENG-A First edition May 2005 SH(NA)-080485ENG-B TERMS, Chapter 1, Section 1.1, 2.1, 2.3, 2. 4, 3.1, 3.3.1, 3.3.2, 3.4.1, 3.4.2, 3.8, 3.9, 3.10, 4.1.1, 4.1.2, 4.1.3, 6.1, 6.1.1, 7.1, 8.1, 8.2.2, 8.2.3, 8. 2.4,[...]

205 December 2008 S H(NA)-080485ENG-H Addition of Universal mo del QCPU and C Controller module models Q00UCPU, Q01UCPU, Q10UDHCPU, Q20 UDHCPU, Q10UD EHCPU, Q20UDEHCPU, Q61P-D MANUALS, TERMS, Chapter 1, Section 1.1, 1.3, 2.1.1, 2.1.2, 2.1.3, 2.3, 2.4, 3.1, 3.1.2, 3.1.3, 3.2, 3.3.2, 3.7, 3.9, 4.1.1, 4.1.2, 4.1.3, 4.1.4, 4.1.5 , 4.3.1, 4.3.3, 4.5, 5.[...]

206 Japanese manual version SH-080475-R © 2004 MITSUBISHI ELECTRIC CORPORA TIO N September 2013 SH(NA)-080485ENG-P C Controller model addition Q24DHCCPU-LS MANUALS, TERMS, Chapter 1, Section 3.1.1, 3.1.2, 3.1.3, 3.2.1, 3.2.2, 3.2.3, 3.3.1, 3.3.2, 3.4, 3.5, 4.2.2, 4.4.1, 4.6, Chapter 6, Section 6.1 .1, 6.1.2, 6.1.3, 6.1.4, 6.5, Appendix 2, 3, 4.2 J[...]

207 W ARRANTY Please confirm the following pr oduct warranty det ails before using this product. 1. Gratis W arranty T e rm and Gratis W arranty Range If any faults or defect s (hereinafter "Failure") found to be the responsibility of Mitsubishi occurs during u se of the product within the gratis warranty term, the product shall be repair[...]

208 Microsoft, Windows, Windows Vist a , Windows NT , Windows XP , Wind ows Server , Visio, Excel, PowerPoint, Visual Basic, Visual C++, and Access are either registered trademarks or trademarks of Microsoft Corpor ation in the United S tates, Japan, and other countries. Intel, Pentium, and Celeron are either registered trademarks or trademarks of [...]

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SH(NA)-080485ENG-R( 1407)MEE MODEL: QCPU-U-MA-E MODEL CODE: 13JR75 Specifications subject to change without notice. When exported from Japan, this manual does not require application to the Ministry of Economy, Trade and Industry for service transaction permission. HEAD OFFICE : TOKYO BUILDING, 2-7-3 MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN NA[...]