NEC PD750004 manuel d'utilisation

µPD750008 4 BIT SINGLE-CHIP MICROCOMPUTER © 1995 USER'S MANUAL µP D750004 µP D750006 µP D750008 µP D75P0016 Document No. U10740EJ2V0UM00 (2nd edition) (Previous No. IEU-1421) Date Published April 1996 P Printed in Japan[...]

1 2 3 4 5 6 7 8 9 10 GENERAL FEATURES OF THE ARCHITECTURE AND MEMORY MAP MASK OPTION RESET FUNCTION INTERRUPT AND TEST FUNCTIONS PERIPHERAL HARDWARE FUNCTIONS INTERNAL CPU FUNCTIONS PIN FUNCTIONS A B C 11 D E F RIVISION HISTORY HARDWARE INDEX INSTRUCTION INDEX MASK ROM ORDERING PROCEDURE DEVELOPMENT TOOLS FUNCTIONS OF THE µPD75008, µPD750008, AND[...]

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NE[...]

Major Changes Page Description All The 44-pin plastic QFP package has been changed from µPD750008GB-xxx-3B4 to µPD750008GB-xxx-3BS-MTX. The µPD75P0016 under development has been changed to the already-developed µPD75P0016. The input withstand voltage at ports 4 and 5 during open drain has been changed from 12 V to 13 V. Preface English-version [...]

PREFACE Readers This manual is intended for engineers who want to learn the capabilities of the µPD750004, µPD750006, µPD750008, and µPD75P0016 to develop application systems based on them. Purpose The purpose of this manual is to help users understand the hardware capabilities (shown below) of the µPD750004, µPD750006, µPD750008, and µPD75[...]

Notation Data bit significance : Higher-order bits on the left side Lower-order bits on the right side Active low : xxx (Pin and signal names are overscored.) Memory map address : Low-order address on the upper side High-order address on the lower side Note : Explanation of an indicated part of text Caution : Information requesting the user's [...]

* Related documents Some documents are preliminary editions, but they are not so specified in the tables below. Documents related to devices Document Name Document Number Japanese English µPD750004, 750006, 750008 Data Sheet U10738J IC-3647 µPD75P0016 Data Sheet U10328J To be prepared µPD750008 User’s Manual U10740J (This manual) IEU-1421 µPD[...]

[MEMO][...]

- i - CONTENTS CHAPTER 1 GENERAL ......................................................................................................................... 1 1.1 FUNCTION OVERVIEW ......................................................................................... 2 1.2 ORDERING INFORMATION ......................................................[...]

- ii - CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP ....................................... 2 1 3.1 DATA MEMORY BANK STRUCTURE AND ADDRESSING MODES .................. 21 3.1.1 Data Memory Bank Structure .................................................................... 21 3.1.2 Data Memory Addressing Modes ...............................[...]

- iii - 5.3.5 Operation of the Watchdog Timer ............................................................. 1 02 5.3.6 Other Functions ......................................................................................... 103 5.4 CLOCK TIMER ........................................................................................................ [...]

- iv - CHAPTER 8 RESET FUNCTION ........................................................................................................... 22 5 CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) ................................... 2 29 9.1 OPERATING MODES WHEN WRITING TO AND VERIFYING THE PROGRAM MEMORY ......................................[...]

- v - APPENDIX A FUNCTIONS OF THE µPD75008, µPD750008, AND µPD75P0016 ............................ 2 99 APPENDIX B DEVELOPMENT TOOLS ................................................................................................ 3 01 APPENDIX C MASKED ROM ORDERING PROCEDURE ................................................................... 309[...]

- vi - LIST OF FIGURES (1/4) Figure No. Title Page 2-1 Pin Input/Output Circuits .................................................................................................. 1 8 3-1 Use of MBE = 0 Mode and MBE = 1 Mode ..................................................................... 22 3-2 Data Memory Organization and Addressing Range of[...]

- vii - LIST OF FIGURES (2/4) Figure No. Title Page 5-9 I/O Timing Chart of Digital I/O Ports ................................................................................ 8 2 5-10 ON Timing Chart of Built-in Pull-Up Resistor Connected by Software .......................... 8 3 5-11 Block Diagram of the Clock Generator ..........................[...]

- viii - LIST OF FIGURES (3/4) Figure No. Title Page 5-45 Operations of RELT and CMDT ....................................................................................... 1 41 5-46 Transfer Bit Switching Circuit ........................................................................................... 14 1 5-47 Example of Two-Wire Serial I/O Sy[...]

- ix - LIST OF FIGURES (4/4) Figure No. Title Page 5-81 Format of the Bit Sequential Buffer ................................................................................. 18 1 6-1 Block Diagram of Interrupt Control Circuit ....................................................................... 1 84 6-2 Interrupt Vector Table ....................[...]

- x - LIST OF TABLES (1/2) Table No. Title Page 1-1 Features of the Products .................................................................................................. 1 2-1 Digital I/O Port Pins .......................................................................................................... 9 2-2 Non-Port Pin Functions ..........[...]

- xi - LIST OF TABLES (2/2) Table No. Title Page 7-1 Operation Statuses in the Standby Mode ........................................................................ 21 6 7-2 Selection of a Wait Time with BTM .................................................................................. 2 19 8-1 Status of the Hardware after a Reset .............[...]

- xii - [MEMO][...]

1 CHAPTER 1 GENERAL CHAPTER 1 GENERAL The µPD750004, µPD750006, µPD750008, and µPD75P0016 are 75XL series 4-bit single-chip microcom- puters. The 75XL series is a successor of the 75X series consisting of many products. These µPD750004, µPD750006, µPD750008, and µPD75P0016 are collectively called the µPD750008 subseries. The 75XL series ta[...]

2 µ PD750008 USER'S MANUAL 1.1 FUNCTION OVERVIEW Item Function Instruction execution • 0.95, 1.91, 3.81, 15.3 µs (when the main system clock operates at 4.19 MHz) time • 0.67, 1.33, 2.67, 10.7 µs (when the main system clock operates at 6.0 MHz) • 122 µs (when the subsystem clock operates at 32.768 kHz) Internal memory ROM 4096 x 8 bi[...]

3 CHAPTER 1 GENERAL 1.2 ORDERING INFORMATION Part number Package On-chip ROM µPD750004CU-xxx 42-pin plastic shrink DIP (600 mil) Masked ROM µPD750004GB-xxx-3BS-MTX Note 44-pin plastic QFP (10 x 10 mm) Masked ROM µPD750006CU-xxx 42-pin plastic shrink DIP (600 mil) Masked ROM µPD750006GB-xxx-3BS-MTX Note 44-pin plastic QFP (10 x 10 mm) Masked ROM[...]

4 µ PD750008 USER'S MANUAL 1.3 DIFFERENCES AMONG SUBSERIES PRODUCTS Item µPD750004 µPD750006 µPD750008 µPD75P0016 Program counter 12 bits 13 bits 14 bits Program memory (byte) Masked ROM Masked ROM Masked ROM One-time PROM 4096 6144 8192 16384 Data memory (x 4 bits) 512 Mask Pull-up resistors at Incorporated None option ports 4 and 5 (Whe[...]

5 CHAPTER 1 GENERAL 1.4 BLOCK DIAGRAM Notes 1. The program counter for the µPD750004 consists of 12 bits, 13 bits for the µPD750006 and µPD750008, and 14 bits for the µPD75P0016. 2. The ROM capacity depends on the product. 3. ( ) : µPD75P0016 TI0 PTO0 PTO1 BUZ SI/SB1 SO/SB0 SCK INT0 INT1 INT2 Basic interval timer/ watchdog timer INTBT Timer[...]

6 µ PD750008 USER'S MANUAL 1.5 PIN CONFIGURATION (TOP VIEW) (1) 42-pin plastic shrink DIP (600 mil) µPD750004CU-XXX µPD750006CU-XXX µPD750008CU-XXX µPD75P0016CU Note Connect IC (V PP ) to V DD , keeping the wiring as short as possible. Remark ( ) : µPD75P0016. XT1 XT2 RESET X1 X2 P33 (/MD3) P32 (/MD2) P31 (/MD1) P[...]

7 CHAPTER 1 GENERAL (2) 44-pin plastic QFP (10 x 10 mm) µPD750004GB-XXX-3BS-MTX µPD750006GB-XXX-3BS-MTX µPD750008GB-XXX-3BS-MTX µPD75P0016GB-3BS-MTX Note Connect IC (V PP ) to V DD , keeping the wiring as short as possible. Remark ( ) : µPD75P0016. P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0 P53 P52 P51?[...]

8 µ PD750008 USER'S MANUAL Pin name P00-P03 : Port 0 RESET : Reset input P10-P13 : Port 1 TI0 : Timer input 0 P20-P23 : Port 2 PTO0, 1 : Programmable timer output 0, 1 P30-P33 : Port 3 BUZ : Buzzer clock P40-P43 : Port 4 PCL : Programmable clock P50-P53 : Port 5 INT0, 1, 4 : External vectored interrupt 0, 1, 4 P60-P63 : Port 6 INT2 : External[...]

9 CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 PIN FUNCTIONS OF THE µPD750008 Table 2-1. Digital I/O Port Pins (1/2) Input/ Also 8 bit Upon I/O Pin used Function circuit output as I/O reset type Note 1 P00 Input INT4 4-bit input port (PORT0). x Input B P01 I/O SCK For P01 to P03, built-in pull-up resistors F -A P02 I/O SO/SB0 can be connect[...]

10 µ PD750008 USER'S MANUAL Table 2-1. Digital I/O Port Pins (2/2) Input Also 8 bit Upon I/O Pin output used Function circuit as I/O reset type Note 1 P40- I/O — N-ch open-drain 4-bit I/O port (PORT4). O High level (when M-D P43 Note 2, 4 Withstand voltage is 13 V in open-drain a pull-up resistor (M-E) Note 3 mode. is provided) or A pull-up[...]

11 CHAPTER 2 PIN FUNCTIONS Table 2-2. Non-Port Pin Functions Input/ Also Upon I/O Pin output used Function reset circuit as type Note 1 TI0 Input P13 Inputs external event pulse to the timer/event counter — B -C PTO0 I/O P20 Timer/event counter output Input E-B PTO1 P21 Timer counter output PCL I/O P22 Clock output Input E-B BUZ I/O P23 Fixed fre[...]

12 µ PD750008 USER'S MANUAL 2.2 PIN F UNCTION S 2.2.1 P00-P03 (PORT0) : Input Pins Used Also for INT4, SCK, SO/SB0 and SI/SB1 P10-P13 (PORT1) : Input Pins Used Also for INT0-INT2, and TI0 These are the input pins of the 4-bit input ports: Ports 0 and 1. Ports 0 and 1 function as input ports, and also have the functions described below. (1) Po[...]

13 CHAPTER 2 PIN FUNCTIONS 2.2.2 P20-P23 (PORT2) : I/O Pins Used Also for PTO0, PTO1, PCL, and BUZ P30-P33 (PORT3) : I/O Pins Used Also for MD0-MD3 Note P40-P43 (PORT4), P50-P53 (PORT5) : N-ch Open-Drain Intermediate Withstand Voltage (13 V) Large-Current Output P60-P63 (PORT6), P70-P73 (PORT7) : Tristate I/O These pins are the I/O pins of the 4-bi[...]

14 µ PD750008 USER'S MANUAL 2.2.6 PCL: Output Pin Used Also for Port 2 This is the programmable clock output pin. It is used to supply the clock pulse to a peripheral LSI circuit such as a slave microcomputer or A/D converter. A RESET signal clears the clock mode register (CLOM) to 0, disabling clock output, then the pin is placed in the norm[...]

15 CHAPTER 2 PIN FUNCTIONS INT0 has a noise eliminator. Two different sampling clocks for noise elimination can be switched. The acceptable width of a signal depends on the CPU clock. INT1 is an asynchronous input, and can accept a signal with some high level width regardless of what the CPU clock is. A RESET input clears IM0 and IM1 to 0, selectin[...]

16 µ PD750008 USER'S MANUAL 2.2.14 XT1, XT2 These pins are used for connection to a crystal for subsystem clock oscillation. An external clock can also be applied. (a) Crystal oscillation (b) External clock 2.2.15 RESET This is the pin for active-low reset input. The RESET input is asynchronous. When a signal with certain low level width is a[...]

17 CHAPTER 2 PIN FUNCTIONS 2.2.18 IC (for the µPD750004, µPD750006, and µPD750008 only) The internally connected (IC) pin is used to set the µPD750008 to test mode for inspection prior to shipping. In normal operation, connect the IC pin to the V DD pin, keeping the writing as short as possible. When the wiring between the IC pin and the V DD p[...]

18 µ PD750008 USER'S MANUAL Type B-C 2.3 PIN INPUT/OUTPUT CIRCUITS Figure 2-1 shows schematic diagrams of the I/O circuitry of the µPD750008. Figure 2-1. Pin Input/Output Circuits (1/2) Type A Schmitt trigger input with hysteresis IN CMOS input buffer V DD IN P-ch N-ch Push-pull output which can be set to high-impedance output (off for bo[...]

19 CHAPTER 2 PIN FUNCTIONS P.U.R.: Pull-Up Resistor P.U.R. V DD P.U.R. enable P-ch IN/OUT Data Output disable Type D Type A Type E-B Type M-C Figure 2-1. Pin Input/Output Circuits (2/2) P.U.R.: Pull-Up Resistor N-ch P.U.R. Data Output disable P.U.R. enable V DD P-ch IN/OUT Type F-A P.U.R.: Pull-Up Resistor P.U.R. V DD P.U.R. enable P[...]

20 µ PD750008 USER'S MANUAL 2.4 CONNECTION OF UNUSED PINS Table 2-3. Connection of Unused Pins Pin name Recommended connection P00/INT4 To be connected to V SS P01/SCK To be connected to V SS or V DD P02/SO/SB0 P03/SI/SB1 P10/INT0-P12/INT2 To be connected to V SS P13/TI0 P20/PTO0 Input state: To be connected to V SS or P21/PTO1 V DD through a[...]

21 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP The 75XL series architecture of the µPD750008 has the following features: • Internal RAM of up to 4K words x 4 bits (12-bit address) • Peripheral hardware expansibility To provide these features, the following are used: (1) Data memor[...]

22 µ PD750008 USER'S MANUAL SET1 MBE CLR1 MBE SET1 MBE MBE = 1 <Main program> <Subroutine> MBE = 0 MEB = 1 CLR1 MBE MBE = 0 RET <Interrupt processing> ; MBE = 0 is to be set in the vector table. MBE = 0 RETI Internal hardware and static RAM operations are repeated. Applicable program processing Effect MBE =[...]

23 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP 3.1.2 Data Memory Addressing Modes With the architecture of the µPD750008, seven addressing modes summarized in Figures 3-2 and 3-3, and Table 3-1 are available to address data memory space efficiently for each bit length of data to be processed. These addressing modes enable more efficient [...]

24 µ PD750008 USER'S MANUAL Figure 3-2. Data Memory Organization and Addressing Range of Each Addressing Mode Remark – : Don't care Addressing mode Memory bank enable flag Area for  general register Data area Static RAM (memory bank 0) Data area Static RAM (memory bank 1) Not provided Peripheral hardware area (memory [...]

25 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Table 3-1. Addressing Modes Addressing mode Representation Specified address format 1-bit direct mem.bit Bit specified by bit at the address specified by MB and mem. addressing • When MBE = 0 and mem = 00H-7FH, MB = 0 mem = 80H-FFH, MB = 15 • When MBE = 1, MB = MBS 4-bit direct mem Addres[...]

26 µ PD750008 USER'S MANUAL (2) 4-bit direct addressing (mem) In this addressing mode, the operand of an instruction directly specifies any area in the data memory space in units of four bits. As with the 1-bit direct addressing mode, in the MBE = 0 mode, a fixed space consisting of the static RAM area ranging from 000H to 07FH and the periph[...]

27 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Example 2. Eight-bit data is latched into the serial interface shift register (SIO), and the transfer data is set at the same time. SEL MB15 ; MBS <– 15 XCH XA,SIO ; XA <—> (SIO) (4) 4-bit register indirect addressing (@rpa) In this addressing mode, the pointer (general register [...]

28 µ PD750008 USER'S MANUAL Example 2. The data memory of 00H to FFH is cleared to 0. CLR1 RBE CLR1 MBE MOV XA,#00H MOV HL,#04H LOOP: MOV @HL,A ; (HL) <– A INCS HL ; HL <– HL + 1 BR LOOP Figure 3-3. Updating Static RAM Addresses INCS D DECS D INCS L DECS L INCS D DECS D INCS E DECS E INCS H DECS H INCS L DECS L INCS H DECS H x 0H 0 [...]

29 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP (5) 8-bit register indirect addressing (@HL) In this addressing mode, the data pointer (HL register pair) indirectly specifies any area in the data memory space in units of eight bits. The 4-bit data at the address determined with bit 0 of the data pointer (bit 0 of the L register) set to 0 a[...]

30 µ PD750008 USER'S MANUAL (a) Specific address bit direct addressing (fmem.bit) In this addressing mode, peripheral equipment that frequently performs bit manipulations involving, for example, I/O ports and interrupt flags, can be processed at all times regardless of memory bank setting. Accordingly, the data memory addresses that allow thi[...]

31 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP (b) Specific address bit register indirect addressing (pmem.@L) In this addressing mode, the bits of peripheral hardware I/O ports are indirectly specified using a register to allow continuous manipulations. This addressing mode can be applied to data memory addresses FC0H to FFFH. In this ad[...]

32 µ PD750008 USER'S MANUAL (c) Specific 1-bit direct addressing (@H+mem.bit) This addressing mode enables any bit in the data memory space to be manipulated. In this addressing mode, the high-order four bits of the data memory address in the memory bank specified by MB = MBE·MBS are indirectly specified using the H register, and the low-ord[...]

33 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP (7) Stack addressing This addressing mode is used for save/restoration operation in interrupt processing or subroutine processing. In this addressing mode, the address indicated by the stack pointer (8 bits) of data memory bank 0 is specified. This addressing mode can be used for register sav[...]

34 µ PD750008 USER'S MANUAL 3.2 GENERAL REGISTER BANK CONFIGURATION The µPD750008 contains four register banks, each consisting of eight general registers: X, A, B, C, D, E, H, and L. These registers are mapped to addresses 00H to 1FH in memory bank 0 of the data memory (see Figure 3-5 ). To specify a general register bank, a register bank e[...]

35 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Figure 3-4. Example of Register Bank Selection The setting of the RBS can be modified for subroutine processing or interrupt processing by saving or restoring the RBS with the PUSH or POP instruction. The RBE is set using the SET1 or CLR1 instruction. The RBS is set using the SEL instruction.[...]

36 µ PD750008 USER'S MANUAL (2) When used as an 8-bit register When the general register area is used on an 8-bit basis, the register pairs in the register bank specified by RBE·RBS can be specified as XA, BC, DE, and HL as shown in Figure 3-6, and the register pairs in the register bank that has the inverted value of bit 0 of the register b[...]

37 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Figure 3-5. General Register Configuration (4-bit Processing) X H D B X H D B X H D B X H D B 01H 03H 05H 07H 09H 0BH 0DH 0FH 11H 13H 15H 17H 19H 1BH 1DH 1FH A L E C A L E C A [...]

38 µ PD750008 USER'S MANUAL Figure 3-6. General Register Configuration (8-bit Processing) XA HL DE BC XA’ HL’ DE’ BC’ 00H 02H 04H 06H 08H 0AH 0CH 0EH When RBE·RBS  = 0 XA’ HL’ DE’ BC’ XA HL DE BC 00H 02H 04H 06H 08H 0AH 0CH 0EH When RBE·RB[...]

39 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP 3.3 MEMORY-MAPPED I/O The µPD750008 employs memory-mapped I/O, which maps peripheral hardware such as timers and I/O ports to addresses F80H to FFFH in data memory space as shown in Figure 3-2. This means that there is no particular instruction to control peripheral hardware, but all periphe[...]

40 µ PD750008 USER'S MANUAL Figure 3-7. µPD750008 I/O Map (1/5) Notes 1. Can be manipulated separately as the RBS and MBS in 4-bit units. Can also be manipulated as the BS in 8-bit units. Use SEL MBn and SEL RBn instructions to write data to MBS and RBS respectively. 2. WDTM: Watchdog timer enable flag (W); cannot be cleared by an instructio[...]

41 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Figure 3-7. µPD750008 I/O Map (2/5) Notes 1. TOE0: Timer/event counter output enable flag (W) 2. TOE1: Timer counter output enable flag (W) FA0H FA2H FA4H FA6H FA8H FACH Address b3 b2 b1 b0 Hardware name (symbol) R/ W 1 bit 4 bits 8 bits Remarks Number of bits that can be  manipulated Bit[...]

42 µ PD750008 USER'S MANUAL Figure 3-7. µPD750008 I/O Map (3/5) Remarks 1. IExxx : Interrupt enable flag 2. IRQxxx : Interrupt request flag Notes 1. Only bit 3 can be manipulated by an EI/DI instruction. 2. Bits 3 and 2 can be manipulated bit by bit by a STOP/HALT instruction. (R/ W) FB0H FB2H FB3H FB4H FB5H FB7H FB8H FBCH FBDH FC0H FC2H Add[...]

43 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Figure 3-7. µPD750008 I/O Map (4/5) Note Whether a bit can be read or written depends on the bit. FD0H FDCH FDEH Address b3 b2 b1 b0 Hardware name (symbol) R/ W 1 bit 4 bits 8 bits Remarks Number of bits that can be  manipulated Bit  manipulation  addressing R/W – – – Pull-up [...]

44 µ PD750008 USER'S MANUAL Figure 3-7. µPD750008 I/O Map (5/5) Notes 1. Bit 1 can be read or written only in serial operation enable mode. It can be read when four-bit manipulation is performed. 2. KR0 to KR7 can be read (R) bit by bit. When inputting 4 bits at a time, specify PORT6 or PORT7. FF0H FF1H FF2H FF3H FF4H FF5H [...]

45 CHAPTER 4 INTERNAL CPU FUNCTIONS CHAPTER 4 INTERNAL CPU FUNCTIONS 4.1 Mk I MODE/Mk II MODE SWITCH FUNCTIONS 4.1.1 Differences between Mk I Mode and Mk II Mode The CPU of the µPD750008 subseries has two modes (Mk I mode and Mk II mode) and which mode is used is selectable. Bit 3 of the stack bank selection register (SBS) determines the mode. •[...]

46 µ PD750008 USER'S MANUAL 4.1.2 Setting of the Stack Bank Selection Register (SBS) The Mk I mode and Mk II mode are switched by stack bank selection register. Figure 4-1 shows the register configuration. The stack bank selection register is set with a 4-bit memory operation instruction. To use the CPU in Mk I mode, initialize the register t[...]

47 CHAPTER 4 INTERNAL CPU FUNCTIONS PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC13 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC11 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC12 4.2 PROGRAM COUNTER (PC): 12 BITS (µPD750004) 13 BITS (µPD750006 AND µPD750008) 14 BITS (µPD75P0016) The program counter is a binary counter whic[...]

48 µ PD750008 USER'S MANUAL 4.3 PROGRAM MEMORY (ROM): 4096 WORDS x 8 BITS (µPD750004: MASKED ROM) 6144 WORDS x 8 BITS (µPD750006: MASKED ROM) 8192 WORDS x 8 BITS (µPD750008: MASKED ROM) 16384 WORDS x 8 BITS (µPD75P0016: ONE-TIME PROM) The program memory is used for storing programs, an interrupt vector table, GETI instruction reference ta[...]

49 CHAPTER 4 INTERNAL CPU FUNCTIONS Figure 4-3. Program Memory Map (in µPD750004) Note Can be used only in the MkII mode. Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with only the 8 low-order bits of the PC changed. * MBE RBE 76 0000H MBE RBE 0002H MBE RBE 0004H MBE RBE 0006H MBE RBE 0008H[...]

50 µ PD750008 USER'S MANUAL Figure 4-4. Program Memory Map (in µPD750006) Note Can be used only in the MkII mode. Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with only the 8 low-order bits of the PC changed. MBE RBE 76 0000H MBE RBE 0002H MBE RBE 0004H MBE RBE 0006H MBE RBE 0008H MBE[...]

51 CHAPTER 4 INTERNAL CPU FUNCTIONS Figure 4-5. Program Memory Map (in µPD750008) Note Can be used only in the MkII mode. Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with only the 8 low-order bits of the PC changed. MBE RBE 76 0000H MBE RBE 0002H MBE RBE 0004H MBE RBE 0006H MBE RBE 0008H M[...]

52 µ PD750008 USER'S MANUAL Figure 4-6. Program Memory Map (in µPD75P0016) Note Can be used only in the MkII mode. Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with only the 8 low-order bits of the PC changed. * MBE RBE 76 0000H MBE RBE 0002H MBE RBE 0004H MBE RBE 0006H MBE RBE 0008H [...]

53 CHAPTER 4 INTERNAL CPU FUNCTIONS 4.4 DATA MEMORY (RAM): 512 WORDS x 4 BITS The data memory consists of a data area and peripheral hardware area as shown in Figure 4-7. The data memory consists of the following memory banks with each bank made of 256 words x 4 bits. • Memory banks 0 and 1 (data area) • Memory bank 15 (peripheral hardware area[...]

54 µ PD750008 USER'S MANUAL 4.4.2 Specification of a Data Memory Bank If the memory bank enable flag (MBE) enables bank specification (MBE = 1), a memory bank is specified with the 4-bit memory bank select register (MBS = 0, 1, 15). If the MBE disables bank specification (MBE = 0), memory bank 0 or 15 is automatically selected according to th[...]

55 CHAPTER 4 INTERNAL CPU FUNCTIONS Data memory is undefined when it is reset. For this reason, it is to be initialized to zero (RAM clear) usually at the start of a program. Remember to perform this initialization. Otherwise, unexpected bugs may occur. Example The following program clears data at addresses 000H to 1FFH in RAM. SET1 MBE SEL MB0 MOV[...]

56 µ PD750008 USER'S MANUAL 4.5 GENERAL REGISTER: 8 x 4 BITS x 4 BANKS The general registers are mapped to particular addresses in data memory. Four banks of registers are provided, with each bank consisting of eight 4-bit registers (B, C, D, E, H, L, X, and A). The register bank (RB) to be enabled at the time of instruction execution is dete[...]

57 CHAPTER 4 INTERNAL CPU FUNCTIONS Figure 4-9. Register Pair Format 4.6 ACCUMULATOR In the µPD750008, the A register and XA register pair function as accumulators. The A register is mainly used for 4-bit data processing instructions, and the XA register pair is mainly used for 8-bit data processing instructions. For a bit manipulation instruction[...]

58 µ PD750008 USER'S MANUAL 4.7 STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS) The µPD750008 uses static RAM as stack memory (LIFO scheme), and the 8-bit register holding the start address of the stack area is the stack pointer (SP). The stack area is located at addresses 000H to 1FFH in memory banks 0 and 1. One memory bank is sele[...]

59 CHAPTER 4 INTERNAL CPU FUNCTIONS Figure 4-11. Format of Stack Pointer and Stack Bank Select Register Note The Mk I mode and Mk II mode can be switched by bit 3 of SBS. The stack bank selection function can be used in both Mk I mode and Mk II mode. (See Section 4.1 for details.) Example SP initialization Specify memory bank 1 as a stack area to s[...]

60 µ PD750008 USER'S MANUAL PC11 - PC8 MBE SP + 2 PC3 - PC0 PC7 - PC4 SP + 4 IST1 CY SP + 6 SP + 1 SP + 3 SP + 5 Stack RBE PC12 IST0 SK2 MBE SK1 RBE SK0 RETI instruction PSW PC11 - PC8 MBE SP + 2 PC3 - PC0 PC7 - PC4 SP + 4 SP + 1 SP + 3 Stack RBE PC12 RET or RETS instruction Lower bits of pair register Upper bits of pair register SP + 2 SP + [...]

61 CHAPTER 4 INTERNAL CPU FUNCTIONS Figure 4-15. Data Restored from the Stack Memory (Mk II Mode) Notes 1. PC12 and PC13 are 0 in the µPD750004. PC13 is 0 in the µPD750006 and µPD750008. 2. PSW bits other than MBE and RBE are not saved or restored. Remark * indicates an undefined bit. Lower bits of pair register Upper bits of pair register St[...]

62 µ PD750008 USER'S MANUAL 4.8 PROGRAM STATUS WORD (PSW): 8 BITS The program status word (PSW) consists of various flags closely associated with processor operations. The PSW is mapped to addresses FB0H and FB1H in data memory space. Four bits at address FB0H can be manipulated with a memory manipulation instruction. Figure 4-16. Program Sta[...]

63 CHAPTER 4 INTERNAL CPU FUNCTIONS Table 4-4. Carry Flag Manipulation Instructions Instruction (mnemonic) Carry flag operation/processing Instruction dedicated to carry SET1 CY Sets CY to 1. flag manipulation CLR1 CY Clears CY to 0. NOT1 CY Inverts the state of CY. SKT CY Skips if CY is 1. Bit transfer instruction MOV1 mem*.bit, CY Transfers the s[...]

64 µ PD750008 USER'S MANUAL Table 4-5. Information Indicated by the Interrupt Status Flag IST1 IST0 Status of processing Processing and interrupt control being performed 0 0 Status 0 Normal program processing is being performed. Any interrupts are acceptable. 0 1 Status 1 A lower- or higher-priority interrupt is being serviced. Higher-priorit[...]

65 CHAPTER 4 INTERNAL CPU FUNCTIONS When the RBE is reset to 0, register bank 0 is always selected as general registers, regardless of the setting of the RBS. A RESET signal automatically initializes the RBE by setting the RBE to the state of bit 6 at program memory address 0. When a vectored interrupt occurs, the RBE is automatically set to the st[...]

66 µ PD750008 USER'S MANUAL Table 4-6. Register Bank to Be Selected with the RBE and RBS Bank 0 is always selected. RBE RBS 3210 000x x Bank 0 is selected. 00 Bank 1 is selected. 100 01 Bank 2 is selected. 10 Bank 3 is selected. 11 Register bank x: Don’t care Always 0[...]

67 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.1 DIGITAL I/O PORTS The µPD750008 employs the memory mapped I/O method. Thus, all input/output ports are mapped on the data memory space. Figure 5-1. Data Memory Addresses of Digital Ports Remark Some I/O parts can be used as static RAM. Input/output port manipula[...]

68 µ PD750008 USER'S MANUAL 5.1.1 Types, Features, and Configurations of Digital I/O Ports Table 5-1 lists the types of digital I/O ports. Figures 5-2 to 5-6 show the configurations of the ports. Table 5-1. Types and Features of Digital Ports Port name Function Operation and feature Remarks (symbol) PORT0 4-bit I/O Also used as INT4, SCK, SO/[...]

69 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-2. Configurations of Ports 0 and 1 Internal bus 8 CSIM Selector Selector P01  output  latch Internal  SCK SI SCK SO INT4 V DD Pull-up  resistor P-ch P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 Bit 0 of  POGA Input buffer Output buffer which can  be switched to either  push-pull out[...]

70 µ PD750008 USER'S MANUAL Figure 5-3. Configurations of Ports 2 and 7 Note For port 7 only M P X Input buffer PMm = 0 Key interrupt Note Output latch PMm Bits 2 and 7 of port mode register group B (m = 2, 7) Output buffer Internal bus Pm0 Pm1 Pm2 Pm3 Bit m of POGA Pull-up  resistor V DD P-ch Input buffer with hysteresis[...]

71 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-4. Configurations of Ports 3n and 6n (n = 0 to 3) Note For port 6n only Bit m of  POGA Pull-up  resistor P-ch V DD Pmn Input buffer M P X PMmn = 0 PMmn = 1 PMmn Output latch Corresponding bits of port mode register group A Output buffer m = 3, 6 n = 0 to 3 Internal bus Input buff[...]

72 µ PD750008 USER'S MANUAL Figure 5-5. Configurations of Ports 4 and 5 Internal bus Input buffer MPX V DD Pm0 Pm1 Pm2 Pm3 PMm = 0 PMm = 1 PMm Output  latch Pull-up resistor   N-ch open-drain  output buffer Corresponding bits of port mode  register group B (m = 4, 5)   (Mask option)[...]

73 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-6. Configuration of Port 8 Internal bus P80 P81 Bit 0 of POGB Pull-up  resistor V DD P-ch PM8 Ouput latch M P X Output buffer Corresponding bit of port mode register group C Input buffer PM8 = 1 PM8 = 0[...]

74 µ PD750008 USER'S MANUAL 5.1.2 I/O Mode Setting The I/O mode of each I/O port is set by the port mode register as shown in Figure 5-7. The I/O modes of ports 3 and 6 can be set bit by bit by port mode register group A (PMGA). The I/O modes of ports 2, 4, 5, and 7 can be set in units of four bits by port mode register group B (PMGB). The I/[...]

75 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-7. Formats of Port Mode Registers 0 1 Input mode (Output buffer off) Output mode (Output buffer on) Contents of specification PM63 PM62 PM61 PM60 PM33 PM31 PM32 PM30 76543 1 20 FE8H Address PMGA Symbol P30 I/O specification P31 I/O specification P32 I/O specification P33 I/O specification[...]

76 µ PD750008 USER'S MANUAL 5.1.3 Digital I/O Port Manipulation Instructions All I/O ports contained in the µPD750008 are mapped to data memory space, so that all data memory manipulation instructions can be used. Table 5-3 lists the instructions that are particularly useful for I/O pin manipulation and their application ranges. (1) Bit mani[...]

77 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (3) 8-bit manipulation instructions The MOV, XCH, and SKE instructions as well as the IN and OUT instructions can be used for ports 4 and 5 that allow 8-bit manipulation. As with 4-bit manipulation, memory bank 15 must be selected in advance. Example The data contained in the BC register pair is output on [...]

78 µ PD750008 USER'S MANUAL Table 5-2. I/O Pin Manipulation Instructions PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT Instruction 0 1 2 3 4 5 6 7 8 IN A, PORTn Note 1 IN XA, PORTn Note 1 —— — OUT PORTn, A Note 1 — OUT PORTn, XA Note 1 —— — SET1 PORTn.bit — SET1 PORTn.@L Note 2 — CLR1 PORTn.bit — CLR1 PORTn.@L Note 2 ?[...]

79 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.1.4 Digital I/O Port Operation When a data memory manipulation instruction is executed for a digital I/O port, the operation of the port and pins depends on the I/O mode setting (Table 5-3). This is because data taken in on the internal bus is the data input from the pins in the input mode, or the output[...]

80 µ PD750008 USER'S MANUAL Table 5-3. Operations by I/O Port Manipulation Instructions Instruction Port and pin operation Input mode Output mode SKT <1> Pin data is tested. Output latch data is tested. SKF <1> MOV1 CY, <1> Pin data is transferred to CY. Output latch data is transferred to CY. AND1 CY, <1> An operation[...]

81 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.1.5 Specification of Bilt-in Pull-Up Resistors A pull-up resistor can be contained at each port pin of the µPD750008 (except for P00). Whether to use the pull-up resistor can be specified by software (for some pins) or a mask option (for the other pins). Table 5-4 shows how a built-in pull-up resistor i[...]

82 µ PD750008 USER'S MANUAL Figure 5-8. Pull-Up Resistor Specification Register Format Pull-up resistor specification register group A Pull-up resistor specification register group B 5.1.6 I/O Timing of Digital I/O Ports Figure 5-9 shows the timing of data output to an output latch and the timing of taking in pin data or output latch data on [...]

83 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-9. I/O Timing Chart of Digital I/O Ports (2/2) (b) When data is input by a 2-machine cycle instruction (c) When data is latched by a 1-machine cycle instruction (d) When data is latched by a 2-machine cycle instruction Figure 5-10. ON Timing Chart of Built-in Pull-Up Resistor Connected by Software[...]

84 µ PD750008 USER'S MANUAL 5.2 CLOCK GENERATOR The clock generator supplies various clock signals to the CPU and peripheral hardware to control the CPU operation mode. 5.2.1 Clock Generator Configuration Figure 5-11 shows the configuration of the clock generator. Figure 5-11. Block Diagram of the Clock Generator Note Instruction execution Re[...]

85 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.2.2 Functions and Operations of the Clock Generator The clock generator generates the following clocks, and controls the CPU operation modes such as the standby mode. • Main system clock f X • Subsystem clock f XT • CPU clock F • Clock to peripheral hardware The operation of the clock generator i[...]

86 µ PD750008 USER'S MANUAL (1) Processor clock control register (PCC) The PCC is a 4-bit register for selecting a CPU clock F with the low-order two bits and for controlling the CPU operation mode with the high-order two bits (see Figure 5-12 ). When bit 3 or bit 2 is set to 1, the standby mode is set. When the standby mode is released by th[...]

87 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-12. Format of the Processor Clock Control Register Address FB3H 32 1 0 PCC3 PCC2 PCC1 PCC0 Symbol PCC CPU clock selection bit (Operation with f X = 6.0 MHz) ( ) is actual frequency at f X = 6.0 MHz CPU clock frequency Φ = f X /64 (93.7 kHz) 1 machine cycle 1 machine cycle SCC3, SCC0 = 00[...]

88 µ PD750008 USER'S MANUAL (2) System clock control register (SCC) The SCC is a 4-bit register for selecting CPU clock F with the least significant bit and for controlling the termination of main system clock generation with the most significant bit (see Figure 5-13 ). Bits 0 and 3 of the SCC are located at the same data memory address, but [...]

89 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (3) System clock oscillator The main system clock oscillator operates with a crystal resonator or ceramic resonator connected to the X1 and X2 pins. An external clock can also be input. Input the clock signal to the X1 pin and the reversed signal to the X2 pin. Figure 5-14. External Circuit for the Main Sy[...]

90 µ PD750008 USER'S MANUAL Any line carrying a high pulsating current must be kept away as far as possible. • The grounding point of the capacitor of the oscillator must have the same poten tial as that of V SS . It must not be grounded to a grounding pattern carry ing a high current. • No signal must be taken directly from the resonator[...]

91 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-16. Examples of Oscillator Connections Which Should Be Avoided (2/2) (c) A high pulsating current is too (d) The current flows through the ground close to the signal line. line of the oscillator. (The potential at points A, B, and C fluctuates.) (e) A signal is taken directly from (f) The signal l[...]

92 µ PD750008 USER'S MANUAL (4) Frequency divider The frequency divider divides the output (f X ) of the main system clock oscillator to generate various clocks. (5) Control functions of subsystem clock oscillator The subsystem clock oscillator of the µPD750008 subseries has two control functions to decrease the supply current. • The funct[...]

93 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (6) Sub-oscillator control register (SOS) The SOS register specifies whether to use the built-in feedback register and controls the drive current of the built-in inverter. (See Figure 5-18 .) Inputting a RESET signal clears all bits of the SOS register. The functions of each flag in the SOS register are de[...]

94 µ PD750008 USER'S MANUAL 5.2.3 System Clock and CPU Clock Setting (1) Time required to change the system clock and CPU clock The system clock and CPU clock can be changed by using the least significant bit of the SCC and the low-order two bits of the PCC. This switching is not performed immediately after the contents of the registers are r[...]

95 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (2) Procedure for changing the system clock and CPU clock The procedure for changing the system clock and CPU clock is explained using Figure 5-19. Figure 5-19. Changing the System Clock and CPU Clock <1> A RESET signal starts CPU operation at the lowest speed of the main system clock (10.7 µs at 6.[...]

96 µ PD750008 USER'S MANUAL 5.2.4 Clock Output Circuit (1) Configuration of the clock output circuit Figure 5-20 shows the configuration of the clock output circuit. (2) Functions of the clock output circuit The clock output circuit outputs a clock pulse signal on the P22/PCL pin to output remote control signals or to supply clock pulses to a[...]

97 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (3) Clock output mode register (CLOM) The CLOM is a 4-bit register to control clock output. The CLOM is set by a 4-bit memory manipulation instruction. No read operation is allowed on this register. Example CPU clock F is output on the PCL/P22 pin. SEL MB15 ; or CLR1 MBE MOV A,#1000B MOV CLOM,A A RESET sig[...]

98 µ PD750008 USER'S MANUAL (4) Application to remote control output The clock output function of the µPD750008 is applicable to remote control output. The frequency of the carrier for remote control output is selected by the clock frequency select bit of the clock output mode register. Pulse output is enabled or disabled by controlling the [...]

99 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.3 BASIC INTERVAL TIMER/WATCHDOG TIMER The µPD750008 contains an 8-bit basic interval timer/watchdog timer, which has the following functions: (a) Interval timer operation which generates a reference timer interrupt (b) Operation as a watchdog timer for detecting program crashes and resetting the CPU (c)[...]

100 µ PD750008 USER'S MANUAL When bit 3 is set to 1, the BT is cleared, and the basic interval ltimer/watchdog timer interrupt request flag (IRQBT) is also cleared (to start the basic interval timer/watchdog timer). A RESET signal clears the interval timer to 0, and the longest interrupt request signal generation interval time is set. Figure [...]

101 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.3.3 Watchdog Timer Enable Flag (WDTM) WDTM, when set, is a flag for enabling the generation of the reset signal when the basic interval timer overflows. WDTM is set by a bit manipulation instruction. It cannot be cleared by an instruction. Example Set the watchdog timer function. SEL MB15 ; or CLR1 MBE [...]

102 µ PD750008 USER'S MANUAL 5.3.5 Operation of the Watchdog Timer When WDTM is set to 1, the basic interval timer/watchdog timer functions as a watchdog timer. An internal reset signal is generated when the basic interval timer (BT) overflows. No reset signal, however, is generated during the oscillation wait time following the STOP instruct[...]

103 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS ······ Module 1: SET1 SEL SET1 MBE MB15 BTM.3 Processing completes  within 5.46 ms. ······ Module 2: SET1 SEL SET1 MBE MB15 BTM.3 Processing completes  within 5.46 ms. ··· 5.3.6 Other Functions The basic interval timer/watchdog has the following functions regar[...]

104 µ PD750008 USER'S MANUAL (2) Reading the count The count status of the basic interval timer (BT) can be read by using an 8-bit manipulation instruction. No data can be loaded to the timer. Caution When reading the count value of BT, execute a read instruction twice so that unstable data which has been counted will not be read. If the two [...]

105 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS MOV XA, BC MOV BUFF, XA ; Store data SET1 FLAG ; Set data presence flag RETI 5.4 CLOCK TIMER The µPD750008 contains one clock timer, which has the following functions. (a) The clock timer sets the test flag (IRQW) every 0.5 seconds. The IRQW can release the standby mode. (b) Either the main system clock [...]

106 µ PD750008 USER'S MANUAL 5.4.1 Configuration of the Clock Timer Figure 5-26 shows the configuration of the clock timer. Figure 5-26. Block Diagram of the Clock Timer The values in parentheses are for f X = 4.194304 MHz and f XT = 32.768 kHz. 5.4.2 Clock Mode Register The clock mode register (WM) is an 8-bit register which controls the clo[...]

107 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Example Time is set using the main system clock (4.19 MHz), and buzzer output is enabled: CLR1 MBE MOV XA, #84H MOV WM, XA ; Sets WM Figure 5-27. Clock Mode Register Format Remark ( ) for f W = 32.768 kHz Address F98H Symbol WM 0 WM0 1 WM1 2 WM2 3 WM3 4 WM4 5 WM5 6 0 7 WM7 WM0 0 1 Selects divided system c[...]

108 µ PD750008 USER'S MANUAL 5.5 TIMER/EVENT COUNTER The µPD750008 has one timer/event counter channel (channel 0) and one timer counter channel (channel 1). Figures 5-28 and 5-29 show the configuration of these channels. In this section, the timer/event counter and timer counters are referred to as "timer/event counters." When you[...]

109 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-28. Block Diagram of the Timer/Event Counter (Channel 0) Count register (8) TI0 MPX Timer operation start signal 8 8 8 From the  clock  generator Internal bus TM06 TM05 TM04 TM03 TM02 Port input  buffer Comparator (8) Modulo register (8) TO enable  flag P20  output  latch  si[...]

110 µ PD750008 USER'S MANUAL Figure 5-29. Block Diagram of the Timer Counter (Channel 1) Count register (8) MPX Timer operation start signal 8 8 8 From the  clock  generator Internal bus TM16 TM15 TM14 TM13 TM12 Comparator (8) Modulo register (8) TO enable  flag P21  output  latch  signal Port 2  input/ output  mode[...]

111 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (1) Timer/event counter mode register (TM0, TM1) The mode register (TMn) is an 8-bit register which controls the timer/event counter. Its format is shown in Figures 5-30 and 5-31. The timer/event counter mode register is set by an 8-bit memory manipulation instruction. Bit 3 is a timer start bit and can b[...]

112 µ PD750008 USER'S MANUAL Figure 5-30. Timer/Event Counter Mode Register (Channel 0) Format When f X = 4.19 MHz TM05 0 0 0 0 1 1 TM06 0 0 1 1 1 1 TM04 0 1 0 1 0 1  TI0 rising edge TI0 falling edge f X /2 10 (4.09 kHz) f X /2 8 (16.4 kHz) f X /2 6 (65.5 kHz) f X /2 4 (2[...]

113 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-31. Timer Counter Mode Register (Channel 1) Format Address FA8H 76  TM16 5 TM15 4 TM14 3 TM13 2 TM12 1  0  Symbol TM1 TM13 Timer start indication bit When 1 is written into the bit, the counter and IRQT1 flag are cleared. If bit 2 is set to 1, count operation i[...]

114 µ PD750008 USER'S MANUAL (2) Timer/event counter output enable flag (TOE0, TOE1) The timer/event counter output enable flag (TOE0, TOE1) controls the output enable/disable to the PTO0 and PTO1 pins in the timer out flip-flop (TOUT flip-flop ) status. The timer out flip-flop is inverted by the match signal sent from the comparator. When bi[...]

115 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-33. Timer/Event Counter Mode Register Setup (1/2) (a) In the case of timer/event counter (channel 0) Timer start indication bit When “1” is written into the bit, the counter and IRQT0 flag are cleared. If bit 2 is set to “1”, count operation is started. TM03 TM02 Operation mode Count o[...]

116 µ PD750008 USER'S MANUAL Figure 5-33. Timer/Event Counter Mode Register Setup (2/2) (b) In the case of timer counter (channel 1) (b) Timer/event counter output enable flag (TOEn) The TOEn is manipulated by a bit manipulation instruction. The TOEn is cleared to 0 by an internal reset signal. Figure 5-34. Timer/Event Counter Output Enable F[...]

117 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (2) Timer/event counter time setting [Timer setup time] (cycle) is found by dividing [modulo register contents + 1] by [count pulse (CP) frequency] selected by setting the mode register. n+1 T (sec) = = (n + 1) · (resolution) f CP T (sec) : Timer setup time (seconds) f CP (Hz) : Count pulse frequency (Hz[...]

118 µ PD750008 USER'S MANUAL (3) Timer/event counter operation The timer/event counter operates as follows. Figure 5-35 shows the configuration of the timer/event counter. <1> The count pulse (CP) is selected by setting the mode register (TMn) and is input to the count register (Tn). <2> The Tn is compared with the modulo register[...]

119 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-36. Count Operation Timing (4) Applications of the timer/event counter (a) Timer/event counter is used as an interval timer that generates interrupts at intervals of 30 ms. • The high-order four bits of the mode register are set to 0100B to select maximum set time 43.7 ms (at f X = 6.00 MHz). ?[...]

120 µ PD750008 USER'S MANUAL <Sample program> SEL MB15 MOV XA,#100 – 1 MOV TMOD0,XA ; Set the modulo register MOV XA,#00001100B MOV TM0,XA ; Set the mode register EI EI IET0 ; Enable INTT0 5.5.3 Notes on Timer/Event Counter Applications (1) Time error at the start of the timer A maximum error of one count pulse (CP) cycle from a value[...]

121 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (3) Error in reading the count register The contents of the count register can be read using an 8-bit data memory manipulation instruction at any time. During operation by such an instruction, all count pulse changes are held not to change the count register. This means that if the count pulse signal sour[...]

122 µ PD750008 USER'S MANUAL (5) Operation after the modulo register is changed The contents of the modulo register are changed when an 8-bit data memory manipulation instruction is executed. If the new value of the modulo register is less than the value of the count register, the count register continues count operation until it overflows, t[...]

123 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.6 SERIAL INTERFACE 5.6.1 Serial Interface Functions The µPD750008 contains a clock synchronous 8-bit serial interface, which has four modes. The functions of the four modes are outlined below. (1) Operation halt mode This mode is used when serial transfer is not performed. This mode reduces power consu[...]

124 µ PD750008 USER'S MANUAL Figure 5-38. Example of the SBI System Configuration 5.6.2 Configuration of Serial Interface Figure 5-39 shows the block diagram of the serial interface. SCK Master CPU SB0, SB1 SCK SB0, SB1 Slave CPU #1 Address 1 SCK SB0, SB1 Slave IC #N Address N Address Command Data Serial clock V DD[...]

125 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-39. Block Diagram of the Serial Interface Internal bus 8 8 8 8/4 P03/SI0/SB1 P02/SO0/SB0 P01/SCK (8) f x /2 3 f x /2 4 f x /2 6 TOUT0 (from timer/event counter) CSIM RELD CMDD ACKD ACKT ACKE BSYE RELT CMDT DQ SET CLR (8) (8) SBIC Bit test Slave address register (SVA) Address comparator Matc[...]

126 µ PD750008 USER'S MANUAL (1) Serial operation mode register 0 (CSIM) CSIM is an 8-bit register which specifies a serial interface operation mode, serial clock, wake-up function, and so forth. (See (1) in Section 5.6.3 for details.) (2) Serial bus interface control register (SBIC) SBIC is an 8-bit register consisting of bits for controllin[...]

127 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (9) Serial clock control circuit The serial clock control circuit controls the serial clock to be supplied to the shift register, or controls the clock to be output to the SCK pin when the internal system clock is used. (10) Busy/acknowledge output circuit and bus release/command/acknowledge detection cir[...]

128 µ PD750008 USER'S MANUAL Figure 5-40. Format of Serial Operation Mode Register (CSIM) (2/4) Serial interface operation enable/disable specification bit (W) Shift register Serial clock IRQCSI SO/SB0 and operation counter flag SI/SB1 pins CSIE 0 Shift operation Cleared Held Used only for port 0 disabled 1 Shift operation Count operation Can[...]

129 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-40. Format of Serial Operation Mode Register (CSIM) (3/4) Serial interface operation mode selection bit (W) CSIM4 CSIM3 CSIM2 Operation Bit order of SO pin SI pin mode shift register function function x 0 0 3-wire SIO 7-0 <—> XA SO/P02 SI/P03 serial (Transfer start (CMOS output) (Input) I[...]

130 µ PD750008 USER'S MANUAL Figure 5-40. Format of Serial Operation Mode Register (CSIM) (4/4) Remarks 2. The P01/SCK pin assumes any of the following states according to the state of CSIE, CSIM1, and CSIM0: CSIE CSIM1 CSIM0 P01/SCK pin state 0 0 0 Input port 1 0 0 High impedance 0 0 1 High level output 010 011 1 0 1 Serial clock output (Hig[...]

131 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (2) Serial bus interface control register (SBIC) Figure 5-41 shows the format of the serial bus interface control register (SBIC). SBIC is an 8-bit register consisting of bits for controlling the serial bus and flags for indicating the states of input data from the serial bus. SBIC is used mainly in the S[...]

132 µ PD750008 USER'S MANUAL Figure 5-41. Format of Serial Bus Interface Control Register (SBIC) (2/3) Busy enable bit (R/W) BSYE 0 <1> The busy signal is automatically disabled. <2> Busy signal output is stopped in phase with the falling edge of SCK immediately after clear instruction execution. 1 The busy signal is output after [...]

133 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-41. Format of Serial Bus Interface Control Register (SBIC) (3/3) Bus release detection flag (R) RELD Condition for being cleared (RELD = 0) Condition for being set (RELD = 1) <1> The transfer start instruction is executed. The bus release signal (REL) is detected. <2> The RESET signal[...]

134 µ PD750008 USER'S MANUAL (3) Shift register (SIO) Figure 5-42 shows the configuration of peripheral hardware of shift register. SIO is an 8-bit register which performs parallel-serial conversion and serial transfer (shift) operation in phase with the serial clock. Serial transfer is started by writing data to SIO. In transmission, data wr[...]

135 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (a) Slave address detection [In the SBI mode] SVA is used when the µPD750008 is connected as a slave device to the serial bus. SVA is an 8- bit register for a slave to set its slave address (number assigned to it). The master outputs a slave address to the connected slaves to select a particular slave. T[...]

136 µ PD750008 USER'S MANUAL Note The status of the P01/SCK pin is selectable. Remark (R): Read only (W): Write only Serial interface operation enable/disable specification bit (W) Shift register operation Serial clock counter IRQCSI flag SO/SB0 and SI/SB1 pins CSIE0 0 Shift operation disabled Cleared Held Used only for port 0 Serial clock se[...]

137 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.6.5 Three-Wire Serial I/O Mode Operations The three-wire serial I/O mode is compatible with other modes used in the 75 XL series, 75X series, µPD7500 series, and 87AD series. Communication is performed using three lines: Serial clock (SCK), serial output (SO), and serial input (SI). Figure 5-43. Exampl[...]

138 µ PD750008 USER'S MANUAL Serial interface operation enable/disable specification bit (W) Shift register operation Serial clock counter IRQCSI flag SO/SB0 and SI/SB1 pins CSIE 1 Shift operation enabled Count operation Can be set Used in each mode as well as for port 0 Signal from address comparator (R) COI Note Condition for being cleared [...]

139 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (b) Serial bus interface control register (SBIC) To use the three-wire serial I/O mode, set SBIC as shown below. (For details on SBIC format, see (2) in Section 5.6.3 .) SBIC is manipulated using a bit memory manipulation instruction. When the RESET signal is input, SBIC is set to 00H. In the figure below[...]

140 µ PD750008 USER'S MANUAL SCK SI IRQCSI 1 SO 23 4 5 6 7 8 DI0 DO0 DI1 DO1 DI2 DO2 DI3 DO3 DI4 DO4 DI5 DO5 DI6 DO6 DI7 DO7 Transfer operation is started in phase with falling edge of SCK. Execution of instruction that writes data to SIO (Transfer start request) Completion of transfer Figure 5-44. Timing of Three-Wire Serial I/O Mode The SO [...]

141 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (4) Signals Figure 5-45 shows operations of RELT and CMDT. Figure 5-45. Operations of RELT and CMDT (5) Switching between MSB and LSB as the first transfer bit The three-wire serial I/O mode has a function that can switch between the MSB and LSB as the first bit of transfer. Figure 5-46 shows the configur[...]

142 µ PD750008 USER'S MANUAL (6) Transfer start Serial transfer is started by writing transfer data into shift register (SIO), provided that the following two conditions are satisfied: • The serial interface operation enable/disable specification bit (CSIE) is set to 1. • The internal serial clock is not operating after 8-bit serial trans[...]

143 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (b) Data is transmitted and received starting with the LSB on an external clock (slave operation). (In this case, the function of inverting the MSB/LSB is used for shift register read/write operation.) <Sample program> Main routine CLR1 MBE MOV XA,#84H MOV CSIM,XA ; Serial operation halt, MSB/LSB in[...]

144 µ PD750008 USER'S MANUAL SCK Master CPU (µPD750008) SB0, SB1 Slave CPU SCK SB0, SB1 V DD 2-wire serial I/O 2-wire serial I/O <Sample program> (master side): CLR1 MBE MOV XA,#10000011B MOV CSIM,XA ; Set transfer mode MOV XA,TDATA MOV SIO,XA ; Set transfer data, and start transfer . . . . . . . . . . LOOP : SKTCLR IRQCSI ; Test IR[...]

145 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (a) Serial operation mode register (CSIM) To use the two-wire serial I/O mode, set CSIM as shown below. (For details on CSIM format, see (1) in Section 5.6.3 .) CSIM is manipulated using an 8-bit manipulation instruction. Bits 7, 6, and 5 of CSIM can be manipulated bit by bit. When the RESET signal is inp[...]

146 µ PD750008 USER'S MANUAL Serial interface operation mode selection bit (W) CSIM4 CSIM3 CSIM2 Shift register sequence SO pin function SI pin function 0 1 1 SIO 7-0 <—> XA SB0/P02 (N-ch P03 input (Transfer starting with MSB) open-drain I/O) 1 P02 input SB1/P03 (N-ch open-drain I/O) Serial clock selection bit (W) CSIM1 CSIM0 Serial c[...]

147 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Bus release trigger bit (W) RELT Control bit for bus release signal (REL) trigger output. By setting RELT = 1, the SO latch is set to 1. Then the RELT bit automatically cleared to 0. Caution Never use bits other than RELT and CMDT in the two-wire serial I/O mode. (2) Communication operation The two-wire s[...]

148 µ PD750008 USER'S MANUAL (3) Serial clock selection To select the serial clock, manipulate bits 0 and 1 of serial operation mode register (CSIM). The serial clock can be selected out of the following four clocks: Table 5-8. Serial Clock Selection and Application (In the Two-Wire Serial I/O Mode) Mode register Serial clock Timing for shift[...]

149 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (6) Error detection In the two-wire serial I/O mode, the state of serial bus SB0 or SB1 being used for communication is loaded into the shift register (SIO) of the transmitting device. So a transmission error can be detected by the methods described below. (a) Comparing SIO data before start of transmissi[...]

150 µ PD750008 USER'S MANUAL The µPD750008, which is the master microcomputer, outputs a serial clock, and all slave microcomputers operate with an external clock. 5.6.7 SBI Mode Operation The SBI (serial bus interface) is a high-speed serial interface that conforms to the NEC serial bus format. To allow communication with multiple devices o[...]

151 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Cautions 1. In the SBI mode, the serial data bus pin SB0 (or SB1) is an open-drain output. So the serial data bus line is placed in the wired OR state. A pull-up resistor is required for the serial data bus line. 2. To switch between the master and slave, a pull-up resistor is required also for the serial[...]

152 µ PD750008 USER'S MANUAL (2) SBI definition The format of serial data and signal used in the SBI mode are described below. Serial data to be transferred in the SBI mode is classified into three types: Address, command, and data. Serial data forms one frame as shown below. Figure 5-51 is a timing chart for transferring address, command, an[...]

153 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (a) Bus release signal (REL) When the SCK line is high (the serial clock is not output), the SB0 (or SB1) line changes from low to high. This signal is called the bus release signal, and is output by the master. Figure 5-52. Bus Release Signal This signal indicates that the master is to send an address to[...]

154 µ PD750008 USER'S MANUAL Figure 5-55. Slave Selection Using an Address (d) Command and data The master sends commands to the slave selected by sending an address. The master also transfers data to or from the slave. Figure 5-56. Command Figure 5-57. Data The 8-bit data following the command signal is defined as a command. The 8-bit data w[...]

155 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-58. Acknowledge Signal [When output in phase with the 11th clock of SCK] [When output in phase with the 9th clock of SCK] The acknowledge signal is a one-shot pulse output in phase with the falling edge of SCK after 8-bit data transfer. This signal may be synchronized with any clock of SCK. The t[...]

156 µ PD750008 USER'S MANUAL SB0, SB1 89 ACK BUSY READY SCK (f) Busy signal (BUSY) and ready signal (READY) The busy signal informs the master that a slave is getting ready for data transfer. The ready signal informs the master that a slave is ready for data transfer. Figure 5-59. Busy and Ready Signals In the SBI mode, a slave notifies the m[...]

157 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Serial interface operation enable/disable specification bit (W) Shift register operation Serial clock counter IRQCSI flag SO/SB0 and SI/SB1 pins CSIE 1 Shift operation enabled Count operation Can be set Used in each mode as well as for port 0 Signal from address comparator (R) COI Note Condition for being[...]

158 µ PD750008 USER'S MANUAL Serial clock selection bit (W) CSIM1 CSIM0 Serial clock SCK pin mode 0 0 External clock applied to SCK pin Input 0 1 Timer/event counter output (TOUT0) Output 10 f X /2 4 (262 kHz) 11 f X /2 3 (524 kHz) Remark The value at 4.19 MHz is indicated in parentheses. (b) Serial bus interface control register (SBIC) To us[...]

159 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Acknowledge detection flag (R) ACKD Condition for being cleared (ACKD = 0) Condition for being set (ACKD = 1) <1> The transfer operation is started. The acknowledge signal (ACK) is detected <2> The RESET signal is entered. (in phase with the rising edge of SCK). Acknowledge enable bit (R/W) AC[...]

160 µ PD750008 USER'S MANUAL Bus release trigger bit (W) RELT Control bit for bus release signal (REL) trigger output. By setting RELT = 1, the SO latch is set to 1. Then the RELT bit automatically cleared to 0. Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or after serial transfer. (4) Serial c[...]

161 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-60. Operations of RELT, CMDT, RELD, and CMDD (Master) Figure 5-61. Operations of RELT, CMDT, RELD, and CMDD (Slave) SIO SCK SO latch RELT CMDT RELD CMDD Transfer start request "H" SIO SCK 12 78 D7 D6 D1 D0 SO latch RELT (Master) CMDT (Master) RELD CMDD Transfer start request Write[...]

162 µ PD750008 USER'S MANUAL Figure 5-62. Operation of ACKT Caution Do not set the ACKT until the transfer is completed. Figure 5-63. Operation of ACKE (1/2) (a) When ACKE = 1 at time of transfer completion (b) When ACKE is set after transfer completion (c) When ACKE = 0 at time of transfer completion SCK 67 8 9 D2 D1 D0 SB0, SB1 ACK ACKT ACK[...]

163 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS SIO SCK 9 8 D2 D1 D0 SB0, SB1 ACKD 7 6 ACK Transfer start request Transfer start Figure 5-63. Operation of ACKE (2/2) (d) When ACKE = 1 period is too short Figure 5-64. Operation of ACKD (1/2) (a) When ACK signal is output during the ninth SCK clock (b) When ACK signal is output after the ninth SCK clock [...]

164 µ PD750008 USER'S MANUAL Figure 5-64. Operation of ACKD (2/2) (c) Clear timing for case where start of transfer is directed during BUSY Figure 5-65. Operation of BSYE SCK SB0, SB1 BSYE 9 BUSY 8 7 6 ACK When BSYE = 1 at this point When reset operation is executed during this period and BSYE = 0 at the falling edge of SCK SIO SCK D2 D[...]

165 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Table 5-10. Various Signals Used in the SBI Mode (1/2) SCK SB0, SB1 “H” “H” SCK SB0, SB1 Rising edge of SB0 or  SB1 when SCK = 1     Falling edge of SB0 or SB1 when SCK = 1       Low level signal output on SB0 or SB1  during one SCK clock cycle af[...]

166 µ PD750008 USER'S MANUAL Table 5-10. Various Signals Used in the SBI Mode (2/2) Synchronous clock for  outputting address / command/data, ACK  signal, synchronous  BUSY signal, and so on.  Address/command/data  is output during first 8  clock cycles.  8-bit data transferred in  phase with SCK after  REL si[...]

167 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (6) Pin configuration The configurations of serial clock pin SCK and serial data bus pin (SB0 or SB1) are as follows: (a) SCK: Pin for serial clock I/O <1> Master : CMOS, push-pull output <2> Slave : Schmitt input (b) SB0, SB1: Pin for serial data I/O Output to SB0 or SB1 is an N-ch open-drain[...]

168 µ PD750008 USER'S MANUAL (7) Address match detection method In the SBI mode, communication starts when the master selects a particular slave device by outputting an address. An address match is detected by hardware. The slave address register (SVA) is available. In the wake- up state (WUP = 1), IRQCSI is set only when the address transmit[...]

169 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-67. Address Transfer Operation from Master Device to Slave Device (WUP = 1) Program processing Hardware operation Program processing SCK pin 123456789 SB0 or SB1 pin A7 Hardware operation A6 A5 A4 A3 A2 A1 A0 ACK READY Address Master device processing (transmitter) Transfer line Slave device proc[...]

170 µ PD750008 USER'S MANUAL Figure 5-68. Command Transfer Operation from Master Device to Slave Device Program processing Hardware operation Program processing SCK pin 123456789 SB0 or SB1 pin C7 Hardware operation C6 C5 C4 C3 C2 C1 C0 ACK READY Command Master device processing (transmitter) Transfer line Slave device processing (receiver) I[...]

171 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-69. Data Transfer Operation from Master Device to Slave Device Program processing Hardware operation Program processing SCK pin 123456789 SB0 or SB1 pin D7 Hardware operation D6 D5 D4 D3 D2 D1 D0 ACK READY Data Master device processing (transmitter) Transfer line Slave device processing (receiver[...]

172 µ PD750008 USER'S MANUAL Figure 5-70. Data Transfer Operation from Slave Device to Master Device Program processing Hardware operation Program processing SCK pin 123456789 12 SB0 or SB1 pin BUSY READY D7 Hardware operation D6 D5 D4 D3 D2 D1 D0 ACK BUSY D7 D6 READY Data Master device processing (receiver) Transfer line Slave device process[...]

173 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (10) Transfer start Serial transfer is started by writing transfer data in shift register (SIO), provided that the following two conditions are satisfied: • The serial interface operation enable/disable bit (CSIE) is set to 1. • The internal serial clock is not operating after 8-bit serial transfer, o[...]

174 µ PD750008 USER'S MANUAL (12) SBI mode This section describes an example of application which performs serial data communication in the SBI mode. In the example, the µPD750008 can be used as either the master CPU or a slave CPU on the serial bus. The master can be switched to another CPU with a command. (a) Serial bus configuration In th[...]

175 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (b) Explanation of commands (i) Types of commands This example uses the following commands: <1> READ command : Transfers data from slave to master. <2> WRITE command : Transfers data from master to slave. <3> END command : Informs slave of WRITE command completion. <4> STOP command[...]

176 µ PD750008 USER'S MANUAL When the slave receives a transmission data count, if it has data enough for transmitting the specified number of bytes of data, the slave returns ACK. If the slave does not have enough data for transmission, an error occurs; ACK is not returned in this case. The master sends ACK to the slave each time it receives[...]

177 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS <3> STATUS command The STATUS command reads the status of the current slave. Figure 5-75. Transfer Format of the STATUS Command Remark M: Output by the master S: Output by the slave The slave returns the status in the format shown in Figure 5-78 . Figure 5-76. Status Format of the STATUS Command Whe[...]

178 µ PD750008 USER'S MANUAL <4> RESET command The RESET command changes the currently selected slave to a non-selected slave. When a RESET command is transmitted, any slave can be placed in the non-selected state. Figure 5-77. Transfer Format of the RESET Command Remark M: Output by the master S: Output by the slave <5> CHGMST co[...]

179 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS If ACK is not returned from the slave within a predetermined period after transmission completion, the occurrence of an error is assumed; the master outputs the ACK signal as a dummy. Figure 5-79. Master and Slave Operation in Case of Error The following errors may occur: • Error that may occur on the s[...]

180 µ PD750008 USER'S MANUAL P01/SCK P01  output  latch SCK To internal circuit Address  FF0H.1 SCK pin output mode From the serial clock  control circuit Example To output one SCK/P01 pin clock cycle by software SEL MB15 ; or CLR1 MBE MOV XA,#10000011B ; SCK (f X /2 3 ), output mode MOV CSIM,XA CLR1 0FF0H.1 ; SCK/P01 <- 0 SET1[...]

181 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.7 BIT SEQUENTIAL BUFFER: 16-BIT The bit sequential buffer (BSB) is special data memory for bit manipulations. In particular, the buffer allows bit manipulations to be performed very easily by sequentially changing address and bit specifications. So the buffer is useful in processing long data bit by bit[...]

182 µ PD750008 USER'S MANUAL Example To output 16-bit data of BUFF1 and BUFF2 serially from bit 0 of port 3: CLR1 MBE MOV XA,BUFF1 MOV BSB0,XA ; Set BSB0 and BSB1 MOV XA,BUFF2 MOV BSB2,XA ; Set BSB2 and BSB3 MOV L,#0 LOOP0: SKT BSB0, @L ; Tests the specification bit of BSB BR LOOP1 NOP ; Dummy (For timing adjustment) SET1 PORT3. 0 ; Sets bit [...]

183 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS CHAPTER 6 INTERRUPT AND TEST FUNCTIONS The µPD750008 has seven vectored interrupt sources and two test inputs, allowing a wide range of applications. In addition, the interrupt control circuitry of the µPD750008 has the following features for very high-speed interrupt processing. (1) Interrupt functions [...]

184 µ PD750008 USER'S MANUAL Figure 6-1. Block Diagram of Interrupt Control Circuit* 2 IM2 14 IRQBT IRQ4 IRQ0 IRQ1 IRQCSI IRQT0 IRQT1 IRQW IRQ2 INTBT INT4/P00 INT0/P10 INT1/P11 INTCSI INTT0 INTT1 INTW INT2/P12 Both-edge  detection  circuit IM0 Edge  detection  circuit Edge  detection  circuit Rising e[...]

185 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 6.2 TYPES OF INTERRUPT SOURCES AND VECTOR TABLES Table 6-1 lists the types of interrupt sources, and Figure 6-2 shows vector tables. Table 6-1. Interrupt Sources Interrupt source signal In/out Interrupt Vectored interrupt request priority Note (vector table address) INTBT Reference time interval signal fro[...]

186 µ PD750008 USER'S MANUAL The column of interrupt priority in Table 6-1 indicates a priority assigned when multiple interrupt requests occur concurrently or are held. A vector table contains interrupt processing start addresses and MBE and RBE setting values during interrupt processing. An assembler pseudo instruction (VENTn) is used to se[...]

187 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 6.3 VARIOUS DEVICES TO CONTROL INTERRUPT FUNCTIONS (1) Interrupt request flags and interrupt enable flags The following seven interrupt request flags (IRQxxx) corresponding to the interrupt sources are provided. INT0 interrupt request flag (IRQ0) Serial interface interrupt request flag (IRQCSI) INT1 interr[...]

188 µ PD750008 USER'S MANUAL Table 6-2. Set Signals for Interrupt Request Flags Interrupt Set signals for interrupt request flags Interrupt request flag enable flag IRQBT Set by a reference time interval signal from the basic interval timer/watchdog IEBT timer. IRQ4 Set by a detected rising or falling edge of an INT4/P00 pin input signal. IE4[...]

189 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS Figure 6-3. Interrupt Priority Specification Register IPS0 IPS1 IPS2 IPS3 0 1 2 3 IPS Symbol FB2H Address 000 001 010 011 100 101 110 111 0 1 High-order interrupt selection All low-order interrupt VRQ1  (INTBT/INT4) VRQ2  (INT0) VRQ3  (INT1) VRQ4  (INTCSI) VRQ5  (INTT0) VRQ6  (INTT1) Not [...]

190 µ PD750008 USER'S MANUAL (3) Configurations of the INT0, INT1, and INT4 circuits (a) As shown in Figure 6-4 (a), the INT0 circuit accepts an external interrupt at its rising or falling edge. The edge to be detected can be selected. The INT0 circuit has a noise elimination function (see Figure 6-5 ), called a noise eliminator, using a samp[...]

191 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS Figure 6-4. Configurations of the INT0, INT1, and INT4 Circuits (a) Configuration of the INT0 circuit (b) Configuration of the INT1 circuit (c) Configuration of the INT4 circuit INT0/P10 IM00, IM01 Internal bus IM0 4 Edge detection  circuit IRQ0 set signal INT0 Input buffer Detection edge  specifi[...]

192 µ PD750008 USER'S MANUAL Figure 6-5. I/O Timing of a Noise Eliminator Remark t SMP = t CY or 64/f X INT0 Shaped output INT0 INT0 INT0 Shaped output Shaped output Shaped output <1> Shorter than sampling cycle (t SMP ) <2> 1 to 2 times <3> Longer than 2 times (a) (b) t SMP t SMP t SMP t SMP t SMP L L H H L L H L L L H H L [...]

193 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS Figure 6-6. Format of Edge Detection Mode Registers (a) INT0 edge detection mode register (IM0) (b) INT1 edge detection mode register (IM1) Caution Changing the edge detection mode register may set an interrupt request flag. So, disable the interrupts before changing the edge detection mode register. Then [...]

194 µ PD750008 USER'S MANUAL (4) Interrupt status flags The interrupt status flags (IST0 and IST1), which are contained in the PSW, indicate the status of processing currently executed by the CPU. By using the content of these flags, the interrupt priority control circuit controls multiple interrupts as indicated in Table 6-3. A 4-bit manipul[...]

195 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 6.4 INTERRUPT SEQUENCE When an interrupt occurs, it is processed using the procedure shown in Figure 6-7 . Figure 6-7. Interrupt Sequence Notes 1. IST0 and IST1 are the interrupt status flags (bits 3 and 2 of the PSW). (See Table 6-3 .) 2. An interrupt service program start address and MBE and RBE setting [...]

196 µ PD750008 USER'S MANUAL 6.5 MULTIPLE INTERRUPT PROCESSING CONTROL The µPD750008 can handle multiple interrupts by either of the following methods. (1) Multiple interrupt processing by a high-order interrupt In this method, the µPD750008 selects an interrupt source among multiple interrupt sources, enabling double interrupt processing. [...]

197 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS (2) Multiple interrupt processing by changing the interrupt status flags Changing the interrupt status flags with the program causes multiple interrupts to be enabled. That is, when the interrupt processing program changes both IST1 and IST0 to 0 (status 0), multiple interrupt processing is enabled. This m[...]

198 µ PD750008 USER'S MANUAL 6.6 PROCESSING OF INTERRUPTS SHARING A VECTOR ADDRESS Interrupt sources INTBT and INT4 share a vector table, so an interrupt source is selected as described below. (1) Using only one interrupt The interrupt enable flag for desired one of the two interrupt sources sharing a vector table is set to 1, and the interru[...]

199 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS Examples 1. To use both INTBT and INT4 as having the higher priority and give priority to INT4 DI SKTCLR IRQ4 ; IRQ4 = 1 ? BR VSUBBT Processing routine EI of INT4 RETI VSUBBT: CLR1 IRQBT Processing routine of INTBT EI RETI 2. To use both INTBT and INT4 as having the lower priority and give priority to INT4[...]

200 µ PD750008 USER'S MANUAL 6.7 MACHINE CYCLES FOR STARTING INTERRUPT PROCESSING With the µPD750008 series, the following machine cycles are used to start the execution of the interrupt service routine after an interrupt request flag (IRQn) is set. (1) When IRQn is set during execution of an interrupt control instruction When IRQn is set du[...]

201 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS (2) When IRQn is set during an instruction other than that described in (1) (a) When IRQn is set at the last machine cycle of the instruction being executed In this case, an instruction preceded by the instruction being executed is executed, and an interrupt processing of three machine cycles is executed, [...]

202 µ PD750008 USER'S MANUAL 6.8 EFFECTIVE USE OF INTERRUPTS The interrupt function can be used more effectively in the ways described below. (1) MBE = 0 is set for the interrupt service routine By allocating addresses 00H to 7FH as data memory used by the interrupt service routine and specifying MBE = 0 in an interrupt vector table, the user[...]

203 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS (1) Interrupt enable/disable <1> A RESET signal disables all interrupts. <2> Interrupt enable flags are set by the EI IExxx instruction. At this stage, all interrupts are disabled. <3> The interrupt master enable flag is set by the EI instruction. At this stage, INT0 and INTT0 are enabled[...]

204 µ PD750008 USER'S MANUAL (2) Example of using INTBT, INT0 (falling edge active), and INTT0 without multiple interrupt processing <1> A RESET signal disables all interrupts, setting status 0. <2> INT0 is set to be falling edge active. <3> Interrupts are enabled by the EI and EI IExxx instructions. <4> On the falling[...]

205 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS (3) Nesting of interrupts with higher priority (INTBT has higher priority and INTT0 and INTCSI have lower priority) <1> INTBT is specified as having the higher priority by setting of IPS, and the interrupt is enabled at the same time. <2> INTT0 service program is started when INTT0 with the low[...]

206 µ PD750008 USER'S MANUAL (4) Execution of held interrupts (interrupt requests when interrupts are disabled) <1> If INT0 is set when interrupts are disabled, the interrupt request flag is held. <2> When the interrupt is enabled by the EI instruction, the INT0 interrupt service program starts. <3> Same as <1> <4&g[...]

207 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS (5) Execution of held interrupts – two interrupts with lower priority occur concurrently – <1> When INT0 and INTT0 with the lower priority occur concurrently (during execution of the same instruction), INT0, with a higher priority, is executed first. (INTT0 is held.) <2> When the INT0 inter[...]

208 µ PD750008 USER'S MANUAL (6) Executing pending interrupt – interrupt occurs during interrupt processing (INTBT has higher priority and INTT0 and INTCSI have lower priority) – <1> When INTBT with the higher priority and INTT0 with the lower priority occur at the same time, the processing of the interrupt with the higher priority [...]

209 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS (7) Enabling of level-two interrupts (enabling level-two INTT0 and INT0 interrupts with INTCSI and INT4 handled as level-one interrupts) <1> When an INTCSI interrupt not allowed to be a level-two interrupt occurs, the INTCSI service program starts, and status 1 is set. <2> Status 0 is set by cl[...]

210 µ PD750008 USER'S MANUAL 6.10 TEST FUNCTION 6.10.1 Test Sources The µPD750008 has two test sources. INT2 provides two types of edge-detection-test inputs. Table 6-5. Test Source Test source Internal/external INT2 (detection of the rising edge of the signal input to the INT2 pin or that of External the first falling edge of the signals in[...]

211 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS (2) INT2 and key interrupt (KR0 to KR7) hardware Figure 6-10 shows the configuration of INT2 and KR0 to KR7. The IRQ2 set signal is output in either of the following edge detection modes, which is selected with the INT2 edge detection mode register (IM2). (a) Detection of a rising edge on the INT2 input pi[...]

212 µ PD750008 USER'S MANUAL Figure 6-10. Block Diagram of the INT2 and KR0 to KR7 Circuits INT2/P12 KR7/P73 KR6/P72 KR5/P71 KR4/P70 KR3/P63 KR2/P62 KR1/P61 KR0/P60 IM2 4 Input buffer Internal bus Selector Rising edge  detection  circuit Falling edge  detection  circuit INT2 (IRQ2 set signal) IM20, IM21[...]

213 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS Figure 6-11. Format of INT2 Edge Detection Mode Register (IM2) Cautions 1. When the edge detection mode register is modified, test request flags may be set in some cases. So, disable test inputs before modifying the edge detection mode register. Then, clear the test request flags using a CLR1 instruction b[...]

214 µ PD750008 USER'S MANUAL [MEMO][...]

215 CHAPTER 7 STANDBY FUNCTION CHAPTER 7 STANDBY FUNCTION The µPD750008 provides a standby function to reduce the power consumption by the system. The standby function is available in the two modes: the STOP mode and HALT mode. Differences between these two modes are as follows: (1) STOP mode In the STOP mode, the main system clock oscillator is s[...]

216 µ PD750008 USER'S MANUAL 7.1 SETTING OF STANDBY MODES AND OPERATION STATUS Table 7-1. Operation Statuses in the Standby Mode Notes 1. Operation is possible only when the main system clock operates. 2. Operation is possible only when the noise eliminator is not selected by bit 2 of the edge detection mode register (IM0) (when IM02 = 1). A [...]

217 CHAPTER 7 STANDBY FUNCTION Caution 2. Reset all the interrupt request flags before setting the standby mode. If an interrupt source whose interrupt request flag and interrupt enable flag are both set exists, the initiated standby mode is released immediately after it is set (see Figure 6-1). When the STOP mode is set, however, the µPD750008 en[...]

218 µ PD750008 USER'S MANUAL Figure 7-1. Standby Mode Release Operation (2/2) (c) Release of the HALT mode by RESET signal (d) Release of the HALT mode by the occurrence of an interrupt Note The following two wait times can be selected by a mask option: 2 17 /f X (21.8 ms at 6.00 MHz, 31.3 ms at 4.19 MHz) 2 15 /f X (5.46 ms at 6.00 MHz, 7.81 [...]

219 CHAPTER 7 STANDBY FUNCTION Table 7-2. Selection of a Wait Time with BTM Note This time does not include the time from the release of the STOP mode to the start of oscillation. Caution The wait times used when the STOP mode is released do not include the time (a in Figure7- 2) required before clock oscillation is started following the release of[...]

220 µ PD750008 USER'S MANUAL 7.4 SELECTION OF A MASK OPTION For the standby function of the µPD750008, either of the following two values can be selected by a mask option as the wait time during which the start of oscillation deferred from the generation of a RESET signal: <1> 2 17 /f X (21.8 ms at 6.00 MHz, 31.3 ms at 4.19 MHz) <2&[...]

221 CHAPTER 7 STANDBY FUNCTION INT4 INT4 31.3 ms 31.3 ms Wait Low-speed operation STOP mode Operating mode STOP instruction V DD 0 V P00/INT4 CPU operation Voltage on V DD High-speed operation <Timing chart> <Sample program> (INT4 service program, MBE = 0) VSUB4: SKT PORT0.0 ; P00 = 1? BR PDOWN ; Power-down SET1 BTM.3 ; Power-on W[...]

222 µ PD750008 USER'S MANUAL (2) Application of the HALT mode (at f X = 4.19 MHz) <Intermittent operation under the following conditions> • The main system clock is switched to the subsystem clock on the falling edge of INT4. • The oscillation of the main system clock is stopped, and HALT mode is set. • In the standby mode, interm[...]

223 CHAPTER 7 STANDBY FUNCTION <Sample program> (Initialization) MOV A,#0011B MOV PCC,A ; High-speed mode MOV XA,#05 MOV WM,XA ; Subsystem clock EI IE4 EI IEW EI ; Enable interrupt (Main routine) SKT PORT0.0 ; Power normal? HALT ; Power-down mode NOP ; Power normal? SKTCLR IRQW ; Flag set for 0.5 second? BR MAIN ; NO CALL WATCH ; Clock subrou[...]

224 µ PD750008 USER'S MANUAL [MEMO][...]

225 CHAPTER 8 RESET FUNCTION CHAPTER 8 RESET FUNCTION The µPD750008 is reset with the external reset signal (RESET) or the reset signal received from the basic interval timer/watchdog timer. When either reset signal is input, the internal reset signal is generated. Figure 8-1 shows the configuration of the reset circuit. Figure 8-1. Configuration [...]

226 µ PD750008 USER'S MANUAL Table 8-1. Status of the Hardware after a Reset (1/2) Note Data of address 0F8H to 0FDH of the data memory becomes undefined when the RESET signal is generated. Program counter (PC) PSW Stack pointer (SP) Stack bank selection register (SBS) Data memory (RAM) General registers (X, A, H, L, D, E, B, C) Bank selectio[...]

227 CHAPTER 8 RESET FUNCTION Table 8-1. Statuses of the Hardware after a Reset (2/2) Processor clock control register (PCC) System clock control register (SCC) Clock output mode register (CLOM) Interrupt request flag (IRQxxx) Interrupt enable flag (IExxx) Priority selection register (IPS) INT0, INT1 and INT2 mode registers (IM0, IM1, IM2) Output bu[...]

228 µ PD750008 USER'S MANUAL [MEMO][...]

229 CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) The program memory in the µPD75P0016 consists of a one-time PROM (16384 x 8 bits). Writing to and verifying the contents of the one-time PROM is accomplished by using the pins shown in the table below. Note that address inputs are [...]

230 µ PD75008 USER'S MANUAL 9.1 OPERATING MODES WHEN WRITING TO AND VERIFYING THE PROGRAM MEMORY If +6 V is applied to the V DD pin and +12.5 V is applied to the V PP pin, the µPD75P0016 enters program memory write/verify mode. The specific operating mode is then selected by the setting of the MD0 through MD3 pins as listed in the table belo[...]

231 CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) The timing for steps (2) to (12) is shown below. V PP V DD V PP V DD +1 V DD V DD X1 P40-P43 P50-P53 MD0 (P30) MD1 (P31) MD2 (P32) MD3 (P33) Data input Data output Data input Write Verify Additional write Address increment Repeat x times[...]

232 µ PD75008 USER'S MANUAL 9.3 READING THE PROGRAM MEMORY The procedure for reading the contents of program memory is described below. The read is performed in the verify mode. (1) Pull low all unused pins to V SS by means of resistors. Bring X1 to low level. (2) Apply 5 V to V DD and V PP . (3) Wait 10 µs. (4) Select program memory address[...]

233 CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) 9.4 SCREENING OF ONE-TIME PROM Because of its structure, it is difficult for NEC to completely test the one-time PROM product before shipment. It is therefore recommended that screening be performed to verify the PROM contents after the necessary data has been written to the PROM and the [...]

234 µ PD75008 USER'S MANUAL [MEMO][...]

235 CHAPTER 10 MASK OPTION CHAPTER 10 MASK OPTION 10.1 PIN The pins of the µPD750008 have the following mask options: Table 10-1. Selecting Mask Option of Pin Pin Mask Option P40-P43 Pull-up resistor can be connected in 1-bit units. P50-P53 P40 through P43 (port 4) or P50 through P53 (port 5) can be connected with pull-up resistors by mask option.[...]

236 µ PD750008 USER'S MANUAL 10.3 MASK OPTION FOR FEEDBACK RESISTOR OF SUBSYSTEM CLOCK For the subsystem clock of the µPD750008, whether to enable the feedback resistor is selected by the mask option. <1> Enable the feedback resistor (switches on or off by software). <2> Disable the feedback resistor (cuts by hardware). To use th[...]

237 CHAPTER 11 INSTRUCTION SET CHAPTER 11 INSTRUCTION SET The instruction set of the µPD750008 is an improved and extended version of the 75X series instruction set. This instruction set takes over the instruction set of the 75X series, having the following features: (1) Bit manipulation instructions allowing a wide variety of applications (2) Eff[...]

238 µ PD750008 USER'S MANUAL 11.1.2 Bit Manipulation Instructions With the µPD750008, a variety of instructions are available for bit manipulation. (a) Bit setting: SET1 mem.bit SET1 mem.bit* (b) Bit clearing: CLR1 mem.bit CLR1 mem.bit* (c) Bit testing: SKT mem.bit SKT mem.bit* (d) Bit testing: SKF mem.bit SKF mem.bit* (e) Bit testing and cl[...]

239 CHAPTER 11 INSTRUCTION SET 11.1.4 Number System Conversion Instructions An application may need to convert the result of a 4-bit data addition or subtraction (performed in binary) to a decimal number. A time-related application may require sexagesimal conversion. For this reason, the instruction set of the µPD750008 contains number system conv[...]

240 µ PD750008 USER'S MANUAL 11.1.5 Skip Instructions and the Number of Machine Cycles Required for a Skip The instruction set of the µPD750008 is designed to organize a program by testing a condition with the skip function. When a skip instruction satisfies the skip condition, the immediately following instruction is skipped to execute the [...]

241 CHAPTER 11 INSTRUCTION SET 11.2 INSTRUCTION SET AND OPERATION (1) Operand identifier and description The operand field of an instruction must contain an operand coded according to the description rule for the operand identifier of the instruction. (Refer to RA75X Assembler Package User’s Manual: Language (EEU-1343 ) for detailed information.)[...]

242 µ PD750008 USER'S MANUAL (2) Legend A: A register; 4-bit accumulator B: B register C: C register D: D register E: E register H: H register L: L register X: X register XA: Register pair (XA), 8-bit accumulator BC: Register pair (BC) DE: Register pair (DE) HL: Register pair (HL) XA’: Extended register pair (XA’) BC’: Extended register[...]

243 CHAPTER 11 INSTRUCTION SET (3) Explanation of symbols used for the addressing area column Remarks 1. MB represents an accessible memory bank. 2. For * 2, MB = 0 regardless of the setting of MBE and MBS. 3. For * 4 and * 5, MB = 15 regardless of the setting of MBE and MBS. 4. Each of * 6 to * 10 indicates an addressable area. * 1 MB = MBE · MBS[...]

244 µ PD750008 USER'S MANUAL (4) Explanation of the machine cycle column S represents the number of machine cycles required when a skip instruction with the skip function performs a skip operation. S assumes one of the following values: • When no skip operation is performed: S = 0 • When a 1-byte instruction or 2-byte instruction is skipp[...]

245 CHAPTER 11 INSTRUCTION SET In Mne- Number Machine Address- struc- monic Operation of cycle Operation ing Skip condition tion bytes area MOV A,#n4 1 1 A <– n4 String-effect A reg1,#n4 2 2 reg1 <– n4 XA,#n8 2 2 XA <– n8 String-effect A HL,#n8 2 2 HL <– n8 String-effect B rp2,#n8 2 2 rp2 <– n8 A,@HL 1 1 A <– (HL) * 1 [...]

246 µ PD750008 USER'S MANUAL In- Mne- Number Machine Address- struc- monic Operand of cycle Operation ing Skip condition tion bytes area MOVT XA,@PCDE 1 3 • µPD750004 XA <– (PC 11-8 +DE) ROM • µPD750006, µPD750008 XA <– (PC 12-8 +DE) ROM • µPD75P0016 XA <– (PC 13-8 +DE) ROM XA,@PCXA 1 3 • µPD750004 XA <– (PC 1[...]

247 CHAPTER 11 INSTRUCTION SET In- Mne- Number Machine Address- struc- monic Operand of cycle Operation ing Skip condition tion bytes area AND A,#n4 2 2 A <– A n4 A,@HL 1 1 A <– A (HL) * 1 XA,rp’ 2 2 XA <– XA rp’ rp’1,XA 2 2 rp’1 <– rp’1 XA OR A,#n4 2 2 A <– A n4 A,@HL 1 1 A <– A (HL) * 1 XA,rp’ 2 2 XA <[...]

248 µ PD750008 USER'S MANUAL In Mne- Number Machine Address- struc- monic Operand of cycle Operation ing Skip condition tion bytes area SET1 mem.bit 2 2 (mem.bit) <– 1 * 3 fmem.bit 2 2 (fmem.bit) <– 1 * 4 pmem.@L 2 2 (pmem 7-2 +L 3-2 .bit(L 1-0 )) <– 1 * 5 @H+mem.bit 2 2 (H+mem 3-0 .bit) <– 1 * 1 CLR1 mem.bit 2 2 (mem.bit)[...]

249 CHAPTER 11 INSTRUCTION SET Branch In Mne- Number Machine Address- struc- monic Operand of cycle Operation ing Skip condition tion bytes area BR addr — — • µPD750004 * 6 PC 11-0 <– addr The assembler selects the most adequate instruction from instructions below. • BR !addr • BR $addr • BRCB !caddr • µPD750006 , µPD750008 PC[...]

250 µ PD750008 USER'S MANUAL Branch Note 1. Set register B to 0. 2. Only the LSB is valid in register B. 3. Only the low-order two bits are valid in register B. In Mne- Number Machine Address- struc- monic Operand o f cycle Operation ing Skip condition tion bytes area BR !addr 3 3 • µPD750004 * 6 PC 11-0 <– addr • µPD750006 , µPD7[...]

251 CHAPTER 11 INSTRUCTION SET In Mne- Number Machine Address- struc- monic Operand o f cycle Operation ing Skip condition tion bytes area BR BCXA 2 3 • µPD750004 * 11 PC 11-0 <– BCXA Note 1 • µPD750006 , µPD750008 PC 12-0 <– BCXA Note 2 • µPD75P0016 PC 13-0 <– BCXA Note 3 BRA Note 1 !addr1 3 3 • µPD750004 * 11 PC 11-0 &[...]

252 µ PD750008 USER'S MANUAL In Mne- Number Machine Address- struc- monic Operand of cycle Operation ing Skip condition tion bytes area CALL Note !addr 3 3 • µPD750004 * 6 (SP–3) <– MBE,RBE, 0, 0 (SP–4)(SP–1)(SP–2) <– PC 11-0 PC 11-0 <– addr, SP <– SP–4 • µPD750006 , µPD750008 (SP–3) <– MBE,RBE, 0, [...]

253 CHAPTER 11 INSTRUCTION SET In Mne- Number Machine Address- struc- monic Operand of cycle Operation ing Skip condition tion bytes area CALLF Note !faddr 2 3 • µPD750004 * 9 (SP–2) –> x, x, MBE,RBE (SP–6)(SP–3)(SP–4) <– PC 11-0 (SP–5) <– 0, 0, 0, 0 PC 11-0 <– 0+faddr, SP <– SP–6 • µPD750006 , µPD750008 [...]

254 µ PD750008 USER'S MANUAL Subroutine stack control In Mne- Number Machine Address- struc- monic Operand of cycle Operation ing Skip condition tion bytes area RETS Note 1 3+S • µPD750004 Unconditionally MBE, RBE, 0, 0 <– (SP+1) PC 11-0 <– (SP)(SP+3)(SP+2) SP <– SP+4 Then skip unconditionally • µPD750006 , µPD750008 MBE[...]

255 CHAPTER 11 INSTRUCTION SET In Mne- Number Machine Address- struc- monic Operand of cycle Operation ing Skip condition tion bytes area RETI Note 1 13 • µPD750004 0, 0, 0, 0 <– (SP+1) PC 11-0 <– (SP)(SP+3)(SP+2) PSW <– (SP+4)(SP+5), SP <– SP+6 • µPD750006 , µPD750008 0, 0, 0, PC 12 <– (SP+1) PC 11-0 <– (SP)(SP[...]

256 µ PD750008 USER'S MANUAL In Mne- Number Machine Address- struc- monic Operand of cycle Operation ing Skip condition tion bytes area SEL RBn 2 2 RBS <– n (n=0 - 3) MBn 2 2 MBS <– n (n=0, 1, 15) GETI Note taddr 1 3 • µPD750004 * 10 When the TBR instruction is used PC 11-0 <– (taddr) 3-0 +(taddr+1) When the TCALL instructio[...]

257 CHAPTER 11 INSTRUCTION SET Special In Mne- Number Machine Address- struc- monic Operand of cycle Operation ing Skip condition tion bytes area GETI Notes1, 2 taddr 1 3 • µPD750004 * 10 When the TBR instruction is used PC 11-0 <– (taddr) 3-0 +(taddr+1) 4 When the TCALL instruction is used (SP–6)(SP–3)(SP–4) <– PC 11-0 (SP–5) [...]

258 µ PD750008 USER'S MANUAL 11.3 INSTRUCTION CODES OF EACH INSTRUCTION (1) Explanations of the symbols for the instruction codes I n : Immediate data for n4 or n8 D n : Immediate data for mem B n : Immediate data for bit N n : Immediate data for n or IExxx T n : Immediate data for taddr x 1/2 A n : Immediate data for the address (2 to 16) re[...]

259 CHAPTER 11 INSTRUCTION SET (2) Bit manipulation addressing instruction codes * 1 in the operand field indicates that there are three types of bit manipulation addressing, fmem.bit, pmem.@L, and @H+mem.bit. The table below lists the second byte * 2 of an instruction code corresponding to the above addressing. * 1 Second byte of instruction code [...]

260 µ PD750008 USER'S MANUAL Instruction Mne- Operand Instruction code monic B 1 B 2 B 3 Transfer MOV A,#n4 0111I 3 I 2 I 1 I 0 reg1,#n4 10011010 I 3 I 2 I 1 I 0 1R 2 R 1 R 0 rp,#n8 10001P 2 P 1 1I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 A,@rpa1 11100Q 2 Q 1 Q 0 XA,@HL 10101010 00011000 @HL,A 11101000 @HL,XA 10101010 00010000 A,mem 10100011 D 7 D 6 D 5[...]

261 CHAPTER 11 INSTRUCTION SET Instruction Mne- Operand Instruction code monic B 1 B 2 B 3 Arithmetic/ ADDS A,#n4 0110I 3 I 2 I 1 I 0 logical XA,#n8 1011100 1 I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 A,@HL 1101001 0 XA,rp’ 1010101 0 11001P 2 P 1 P 0 rp’1,XA 1010101 0 11000P 2 P 1 P 0 ADDC A,@HL 1010100 1 XA,rp’ 1010101 0 11011P 2 P 1 P 0 rp’1,XA 101[...]

262 µ PD750008 USER'S MANUAL Instruction Mne- Operand Instruction code monic B 1 B 2 B 3 Increment/ INCS r e g 11000R 2 R 1 R 0 decrement r p 1 10001P 2 P 1 0 @ H L 10011001 00000010 m e m 10000010 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 DECS r e g 11001R 2 R 1 R 0 r p ’ 10101010 01101P 2 P 1 P 0 Comparison SKE reg,#n4 10011010 I 3 I 2 I 1 I 0 0R 2[...]

263 CHAPTER 11 INSTRUCTION SET Instruction Mne- Operand Instruction code monic B 1 B 2 B 3 Branch BR !addr 1010101 1 00 addr $addr1 0000A 3 A 2 A 1 A 0 (+16) to (+2) (–1) to (–15) 1111S 3 S 2 S 1 S 0 PCDE 1001100 1 00000100 PCXA 1001100 1 00000000 BCDE 0000010 1 BCXA 1001100 1 00000001 BRA !addr1 1011101 0 0 addr1 BRCB !caddr 0101 caddr Sub- CA[...]

264 µ PD750008 USER'S MANUAL 11.4 FUNCTIONS AND APPLICATIONS OF THE INSTRUCTIONS This section explains functions and applications of the instructions. For the µPD750004, µPD750006, µPD750008, and µPD75P0016, usable instructions and their functions in Mk I mode are different from those in Mk II mode. Read the following explanation. How to [...]

265 CHAPTER 11 INSTRUCTION SET MOV reg1,#n4 Function: reg1 <– n4 n4 = I 3-0 : 0-FH Transfers the 4-bit immediate data n4 to A register reg1 (X, H, L, D, E, B, C). MOV XA,#n8 Function: XA <– n8 n8 = I 7-0 : 00H-FFH Transfers the 8-bit immediate data n8 to register pair XA. The string effect can be utilized. When two or more of this instruc[...]

266 µ PD750008 USER'S MANUAL Then skips the immediately following instruction. When HL– (automatic decrement) is specified for the register pair, automatically decrements the contents of the L register by one after the data transfer, and continues the operation until the contents are set to FH. Then skips the immediately following instructi[...]

267 CHAPTER 11 INSTRUCTION SET MOV XA,mem Function: A <– (mem), X <– (mem+1) mem = D 7-0 : 00H-FEH Transfers the data at the data memory location addressed by the 8-bit immediate data mem to the A register, and transfers the data at the next address to the X register. An even address can be specified with mem. Example The data at addresse[...]

268 µ PD750008 USER'S MANUAL MOV reg1,A Function: reg1 <– A Transfers the contents of the A register to register reg1 (X, H, L, D, E, B, C). MOV rp’1,XA Function: rp’1 <– XA Transfers the contents of the XA register pair to register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, BC’). XCH A,@HL XCH A,@HL+ XCH A,@HL– XCH A,@rp[...]

269 CHAPTER 11 INSTRUCTION SET XCH XA,@HL Function: A <–> (HL), X <–> (HL+1) Exchanges the contents of the A register with the data at the data memory location addressed by the HL register pair, and exchanges the contents of the X register with the data at the next memory address. However, if the contents of the L register are odd- [...]

270 µ PD750008 USER'S MANUAL 11.4.2 Table Reference Instructions MOVT XA,@PCDE Function: For the µPD750006 and µPD750008 XA <– ROM (PC 12-8 +DE) Transfers the low-order four bits of the table data in program memory to the A register, and the high-order four bits to the X register. The table data is addressed by the program counter (PC)[...]

271 CHAPTER 11 INSTRUCTION SET For example, if MOVT XA,@PCDE is located at a as shown above, the table data in page 3 specified by the contents of the DE register pair is transferred to the XA register pair instead of that in page 2. Example The 16-byte data at addresses xxF0H-xxFFH in program memory is transferred to addresses 30H-4FH in data memo[...]

272 µ PD750008 USER'S MANUAL MOVT XA,@BCXA Function: For the µPD750006 and µPD750008 XA <– (BCXA) ROM Transfers the low-order four bits of the table data (eight bits) in program memory to the A register, and the high-order four bits to the X register. The table data is addressed by the low-order one bit of the B register and the conten[...]

273 CHAPTER 11 INSTRUCTION SET 11.4.3 Bit Transfer Instructions MOV1 CY,fmem.bit MOV1 CY,pmem.@l MOV1 CY,@H+mem.bit Function: CY <– (bit specified in operand) Transfers the data memory bit specified by bit manipulation addressing (fmem.bit, pmem.@L, @H+mem.bit) to the carry flag (CY). MOV1 fmem.bit,CY MOV1 pmem.@L,CY MOV1 @H+mem.bit,CY Functio[...]

274 µ PD750008 USER'S MANUAL ADDS XA,#n8 Function: XA <– XA+n8 ; Skip if carry. n8 = I 7-0 : 00H-FFH Adds the 8-bit immediate data n8 to the contents of the XA register pair in binary, then skips the next instruction if the addition generates a carry. The carry flag is not affected. ADDS A,@HL Function: A <– A+(HL) ; Skip if carry. [...]

275 CHAPTER 11 INSTRUCTION SET ADDC XA,rp’ Function: XA, CY <– XA+rp’+CY Adds the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, BC’) together with the carry flag to the contents of the XA register pair in binary. If the addition generates a carry, the carry flag is set. If no carry is generated, the carry flag is [...]

276 µ PD750008 USER'S MANUAL SUBS rp’1,XA Function: rp’1 <– rp’1+XA ; Skip if borrow Subtracts the contents of the XA register pair from the contents of register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, BC’), then sets the result in register pair rp’1. If the subtraction generates a borrow, the immediately following instru[...]

277 CHAPTER 11 INSTRUCTION SET AND A,@HL Function: A <– A (HL) ANDs the contents of the A register with the data at the data memory location addressed by the HL register pair, then sets the result in the A register. AND XA,rp’ Function: XA <– XA rp’ ANDs the contents of the XA register pair with the contents of register pair rp’ (XA[...]

278 µ PD750008 USER'S MANUAL OR rp’1,XA Function: rp’1 <– rp’ XA ORs the contents of register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, BC’) with the contents of the XA register pair, then sets the result in register pair rp’1. XOR A,#n4 Function: A <– A n4 n4 = I 3-0 : 0-FH Exclusive-ORs the contents of the A register[...]

279 CHAPTER 11 INSTRUCTION SET 11.4.5 Accumulator Manipulation Instructions RORC A Function: CY <- A 0 , A n-1 <- A n , A 3 <- CY (n = 1–3) Rotates the contents of the A register (4-bit accumulator) through the carry flag one bit position to the right. NOT A Function: A <– A Obtains the one’s complement of the A register (4-bit ac[...]

280 µ PD750008 USER'S MANUAL INCS mem Function: (mem) <– (mem)+1 ; Skip if (mem) = 0, mem = D 7-0 : 00H-FFH Increments the data at the data memory location addressed by the 8-bit immediate data mem. If the result of increment produces data that is 0, the immediately following instruction is skipped. DECS reg Function: reg <– reg–1[...]

281 CHAPTER 11 INSTRUCTION SET SKE XA,@HL Function: Skip if A = (HL) and X = (HL+1) Skips the immediately following instruction if the contents of the A register match the data at the data memory location addressed by the HL register pair, and the contents of the X register match the data at the next address in data memory. However, if the contents[...]

282 µ PD750008 USER'S MANUAL NOT1 CY Function: CY <– CY Inverts the carry flag. If it is 0, it is set to 1, or vice versa. 11.4.9 Memory Bit Manipulation Instructions SET1 mem.bit Function: (mem.bit) <– 1 mem = D 7-0 : 00H-FFH, bit = B 1-0 : 0–3 Sets the bit specified by the 2-bit immediate data bit at the address specified by the[...]

283 CHAPTER 11 INSTRUCTION SET Skips the immediately following instruction if the bit specified by the 2-bit immediate data bit at the address specified by the 8-bit immediate data mem is 1. SKT fmem.bit SKT pmem.@L SKT @H+mem.bit Function: Skip if (bit specified in operand) = 1 Skips the immediately following instruction if the bit in data memory [...]

284 µ PD750008 USER'S MANUAL AND1 CY, fmem.bit AND1 CY, pmem.@L AND1 CY, @H+mem.bit Function: CY <– CY ^ (bit specified in operand) ANDs the content of the carry flag with the bit in data memory specified by bit manipulation addressing (fmem.bit, pmem.@L, @H+mem.bit), then sets the result in the carry flag. OR1 CY, fmem.bit OR1 CY, pmem.[...]

285 CHAPTER 11 INSTRUCTION SET BR addr1 Function: For the µPD750008 P C 12-0 <– addr1 addr1 = 0000H-1FFFH Branches to the address specified by the immediate data addr1. This instruction is an assembler pseudo instruction, and the assembler automatically replaces this instruction with the BRA !addr1 instruction, BR !addr instruction, BRCB !cad[...]

286 µ PD750008 USER'S MANUAL Remark " Function " in this section is applicable to the µPD750008 whose program counter consists of 13 bits (addr = 0000H to 1FFFH). However, this is also applicable to the µPD750004 whose program counter consists of 12 bits (addr = 0000H to 0FFFH), the µPD750006 whose program counter consists of 13 [...]

287 CHAPTER 11 INSTRUCTION SET BR PCDE Function: For the µPD750008 PC 12-0 <– PC 12-8 + DE PC 7- 4 <– D, PC 3-0 <– E Branches to the address specified by the program counter whose low-order 8 bits (PC 7-0 ) have been replaced with the contents of the DE register pair. The high-order bits of the program counter are not affected. Caut[...]

288 µ PD750008 USER'S MANUAL B C 30 0 D 30 E 30 11 8 7 4 3 0 12 PC BR BCDE Function: For the µPD750008 P C 12-0 <– BCDE Branches to the address specified by the program counter whose bits have been replaced with the contents of the B 0 , C, D, and E registers. BR BCXA Function: For the µPD750008 PC 12-0 <– BCXA Branches to the add[...]

289 CHAPTER 11 INSTRUCTION SET 11.4.11 Subroutine Stack Control Instructions CALLA !addr1 Function: For the µPD750008 (SP–2) <– x, x, MBE, RBE, (SP–3) <– PC 7-4 (SP–4) <– PC 3-0, (SP–5) <– 0, 0, 0, PC 12 (SP–6) <– PC 11-8 PC 12-0 <– addr1, SP <– SP–6 CALL !addr Function: For the µPD750008 [Mk I mode][...]

290 µ PD750008 USER'S MANUAL CALLF !faddr Function: For the µPD750008 [Mk I mode] (SP–1) <– PC 7-4 , (SP–2) <– PC 3-0 (SP–3) <– MBE, RBE, 0, PC 12 (SP–4) <– PC 11-8 , SP <– SP – 4 PC 12-0 <– 00 + faddr faddr = 0000H – 07FFH [Mk II mode] (SP–2) <– x, x, MBE, RBE (SP–3) <– PC 7-4 , (SP–[...]

291 CHAPTER 11 INSTRUCTION SET RET Function: For the µPD750008 [Mk I mode] PC 11-8 <– (SP) MBE, RBE, 0, PC 12 <– (SP+1) PC 3-0 <– (SP+2) PC 7-4 <– (SP+3), SP <– SP+4 [Mk II mode] PC 11-8 <– (SP), x, x, x, PC 12 <– (SP+1) PC 3-0 <– (SP+2), PC 7-4 <– (SP+3) x, x, MBE, RBE <– (SP+4) SP <– SP+6 Re[...]

292 µ PD750008 USER'S MANUAL Remark " Function " in this section is applicable to the µPD750008 whose program counter consists of 13 bits (addr = 0000H to 1FFFH). However, this is also applicable to the µPD750004 whose program counter consists of 12 bits (addr = 0000H to 0FFFH),the µPD750006 whose program counter consists of 13 b[...]

293 CHAPTER 11 INSTRUCTION SET PUSH BS Function: (SP–1) <– MBS, (SP–2) <– RBS, SP <– SP–2 Saves the contents of the memory bank select register (MBS) and the register bank select register (RBS) to the data memory location (stack) addressed by the stack pointer (SP), then decrements SP. POP rp Function: r p L <– (SP), rp H [...]

294 µ PD750008 USER'S MANUAL DI IExxx Function: IExxx <– 0 xxx = N 5 , N 2-0 Resets an interrupt enable flag (IExxx) to 0 to disable an interrupt. (xxx = BT, CSI, T0, T1, W, 0, 1, 2, 4) 11.4.13 I/O Instructions IN A,PORTn Function: A <– PORTn n = N 3-0 : 0–8 Transfers the contents of the port specified by PORTn (n = 0-8) to the A [...]

295 CHAPTER 11 INSTRUCTION SET Caution Before this instruction can be executed, MBE = 0 or (MBE = 1, MBS = 15) must be set. Only 4 or 6 can be specified as n. 11.4.14 CPU Control Instructions HALT Function: PCC.2 <– 1 Sets the HALT mode. (This instruction is used to set bit 2 of the processor clock control register.) Caution The instruction im[...]

296 µ PD750008 USER'S MANUAL GETI taddr Function: taddr = T 5-0 , 0 : 20H-7FH For the µPD750008 [Mk I mode] • When a table defined by the TBR instruction is referenced PC 12-0 <– (taddr) 4-0 + (taddr+1) • When a table defined by the TCALL instruction is referenced (SP–1) <– PC 7-4 , (SP–2) <– PC 3-0 (SP–3) <– MB[...]

297 CHAPTER 11 INSTRUCTION SET Caution All 2-byte instructions (except the BRCB instruction and CALLF instruction) set in the reference table must be 2-machine-cycle instructions. Pairs of 1-byte instructions can be set as indicated in the table below. First byte instruction Second byte instruction INCS L MOV A,@HL DECS L MOV @HL,A INCS H XCH A,@HL[...]

298 µ PD750008 USER'S MANUAL Example MOV HL, #00H MOV XA, #FFH are replaced with GETI instructions. CALL SUB1 BR SUB2 ORG 20H HL00: MOV HL, #00H XAFF: MOV XA, #FFH CSUB1: TCALL SUB1 BSUB2: TBR SUB2 · · · · · · · · · · GET HL00 ; MOV HL,#00H · · · · · · · · · · GETI BSUB2 ; BR SUB2 · · · · · · · · · · GETI CSUB1 ;[...]

299 Masked ROM 0000H - 1F7FH (8064 x 8 bits) 75X standard CPU 31.3 ms 0.95, 1.91, 15.3 µs (when operating at 4.19 MHz) NC P21 Not provided 000H - 0FFH 2-byte stack Not available 3 machine cycles 2 machine cycles APPENDIX A FUNCTIONS OF THE µPD75008, µPD750008, AND µPD75P0016 Item Program memory Data memory CPU Oscillation settling time When sel[...]

300 µ PD750008 USER'S MANUAL Item (2/2) SOS register Serial interface Feedback resistor cut flag (SOS.0) Sub-oscillator current cut flag (SOS.1) Register bank selection register (RBS) Standby release with INT0 Number of vectored interrupts Processor clock control register Power supply voltage Operating ambient temperature Package Timer Clock [...]

301 APPENDIX B DEVELOPMENT TOOLS The following development tools are provided for the development of a system which employs the µPD750008. In the 75XL series, use the common relocatable assembler together with a device file of each model. Note These software products cannot use the task swap function, which is available in MS-DOS Ver. 5.00 or late[...]

302 µ PD750008 USER'S MANUAL PROM programming tools Note These software products cannot use the task swap function, which is available in MS-DOS Ver. 5.00 or later. Remark Operation of the PG-1500 controller is guaranteed only on the above host machines and OSs. Hardware Software Distribution media 3.5-inch 2HD 5.25-inch 2HD 3.5-inch 2HD 5.25[...]

303 Debugging Tools The in-circuit emulators (IE-75000-R and IE-75001-R) are provided to debug programs used for the µPD750008. The following system is shown below. Notes 1. Maintenance service only 2. To be ordered. 3. These software products cannot use the task swap function, which is available in MS DOS Ver. 5.00 or later. Remark Operation of t[...]

304 µ PD750008 USER'S MANUAL OS for IBM PC The following IBM PC OSs are supported. OS Version PC DOS Ver. 3.1 to Ver. 6.3 J6.1/V Note to J6.3/V Note MS-DOS Ver. 5.0 to Ver. 6.22 5.0/V Note to J6.2/V Note IBM DOS TM J5.02/V Note Note Only English version is supported. Caution These software products cannot use the task swap function, which is [...]

305 APPENDIX B DEVELOPMENT TOOLS Target sysytem Note 2 Emulation probe EP-75008CU-R EP-75008GB-R In-circuit emulator IE-75000-R or IE-75001-R Emulation board IE-75300-R-EM Note 1 Product containing PROM µPD75P0016CU PROM programmer PG-1500 + Programmer adapter PA-75P008CU RS-232-C Centronics interface IE control program PG-1500?[...]

306 µ PD750008 USER'S MANUAL Drawings of the Conversion Socket (EV-9200G-44) and Recommended Pattern on Boards Figure B-1. Drawings of the EV-9200G-44 (Reference) EV-9200G-44-G0[...]

307 APPENDIX B DEVELOPMENT TOOLS Figure B-2. Recommended Pattern on Boards for the EV-9200G-44 (Reference) EV-9200G-44-P0 Caution Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" [...]

308 µ PD750008 USER'S MANUAL [MEMO][...]

309 APPENDIX C MASKED ROM ORDERING PROCEDURE After program development is completed, the masked ROM is ordered by the following procedure: <1> Advance notice of an order for masked ROM Give advance notice of masked ROM ordering to a special agent or NEC’s Sales Department, otherwise the ordered products may be delivered with delay. <2>[...]

310 µ PD750008 USER'S MANUAL [MEMO][...]

311 APPENDIX D INSTRUCTION INDEX D.1 INSTRUCTION INDEX (BY FUNCTION) [Transfer instructions] MOV A,#n4 ... 245, 264 MOV reg1,#n4 ... 245, 265 MOV XA,#n8 ... 245, 265 MOV HL,#n8 ... 245, 265 MOV rp2,#n8 ... 245, 265 MOV A,@HL ... 245, 265 MOV A,@HL+ ... 245, 265 MOV A,@HL– ... 245, 265 MOV A,@rpa1 ... 245, 265 MOV XA,@HL ... 245, 266 MOV @HL,A ...[...]

312 µ PD750008 USER'S MANUAL OR A,@HL ... 247, 277 OR XA,rp’ ... 247, 277 OR rp’1,XA ... 247, 278 XOR A,#n4 ... 247, 278 XOR A,@HL ... 247, 278 XOR XA,rp’ ... 247, 278 XOR rp’1,XA ... 247, 278 [Accumulator manipulation instructions] RORC A ... 247, 279 NOT A ... 247, 279 [Increment/decrement instructions] INCS reg ... 247, 279 INCS rp[...]

313 BRA !addr1 ... 251, 285 BRCB !caddr ... 251, 286 TBR addr ... 256, 288 [Subroutine stack control instructions] CALLA !addr1 ... 251, 289 CALL !addr ... 252, 289 CALLF !faddr ... 252, 290 TCALL !addr ... 256, 290 RET ... 253, 291 RETS ... 254, 291 RETI ... 254, 292 PUSH rp ... 255, 292 PUSH BS ... 255, 293 POP rp ... 255, 293 POP BS ... 255, 293[...]

314 µ PD750008 USER'S MANUAL D.2 INSTRUCTION INDEX (ALPHABETICAL ORDER) [A] ADDC A,@HL ... 246, 274 ADDC rp’1,XA .. 246, 275 ADDC XA,rp’ ... 246, 275 ADDS A,#n4 ... 246, 273 ADDS A,@HL ... 246, 274 ADDS rp’1,XA ... 246, 274 ADDS XA,rp’ ... 246, 274 ADDS XA,#n8 ... 246, 274 AND A,#n4 ... 247, 276 AND A,@HL ... 247, 277 AND rp’1,XA ..[...]

315 MOV A,@rpa1 ... 245, 265 MOV HL,#n8 ... 245, 265 MOV mem,A ... 245, 267 MOV mem,XA ... 245, 267 MOV reg1,A ... 245, 268 MOV reg1,#n4 ... 245, 265 MOV rp’1,XA ... 245, 268 MOV rp2,#n8 ... 245, 265 MOV XA,mem ... 245, 267 MOV XA,rp’ ... 245, 267 MOV XA,#n8 ... 245, 265 MOV XA,@HL ... 245, 266 MOV @HL,A ... 245, 266 MOV @HL,XA ... 245, 266 MOV[...]

316 µ PD750008 USER'S MANUAL SKT pmem.@L ... 248, 283 SKT @H+mem.bit ... 248, 283 SKTCLR fmem.bit ... 248, 283 SKTCLR pmem.@L ... 248, 283 SKTCLR @H+mem.bit ... 248, 283 STOP ... 255, 295 SUBC A,@HL ... 246, 276 SUBC rp’1,XA ... 246, 276 SUBC XA,rp’ ... 246, 276 SUBS A,@HL ... 246, 275 SUBS rp’1,XA ... 246, 276 SUBS XA,rp’ ... 246, 27[...]

317 APPENDIX E HARDWARE INDEX E.1 HARDWARE INDEX (ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE NAME) [A] Acknowledge detection flag ... 132 Acknowledge enable bit ... 132 Acknowledge trigger bit ... 132 [B] Bank select register ... 65 Basic interval timer ... 99 Basic interval timer mode register ... 99 Bit sequential buffer ... 181 BT interrupt[...]

318 µ PD750008 USER'S MANUAL [W] Wake-up function specification bit ... 128 Watchdog timer enable flag ... 101 [R] Register bank enable flag ... 34, 64 Register bank select register ... 34, 65 [S] Serial bus interface control register ... 131 Serial interface interrupt enable flag ... 187 Serial interface interrupt request flag ... 187 Serial[...]

319 E.2 HARDWARE INDEX (ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE SYMBOL) APPENDIX E HARDWARE INDEX [A] ACKD ... 132 ACKE ... 132 ACKT ... 132 [B] BS ... 65 BSB0-BSB3 ... 181 BSYE ... 132 BT ... 99 BTM ... 99 [C] CLOM ... 97 CMDD ... 132 CMDT ... 133 COI ... 128 CSIE ... 128 CSIM .. 127 CY ... 62 [I] IE0 ... 187 IE1 ... 187 IE2 ... 210 IE4 ..[...]

320 µ PD750008 USER'S MANUAL [S] SBIC ... 131 SBS ... 46, 58 SCC ... 88 SIO ... 134 SK0, SK1, SK2 ... 63 SOS ... 93 SP ... 58 SVA ... 134 [T] T0 ... 109 T1 ... 110 TOE0 ... 114 TOE1 ... 114 TM0 ... 112 TM1 ... 113 TMOD0 ... 109 TMOD1 ... 110 [W] WDTM ... 101 WM ... 106 WUP ... 128[...]

321 APPENDIX F REVISION HISTORY Major revisions in this edition are shown below. The revised chapters refer to this edition. Edition Major revisions from previous edition Revised chapters Second The 44-pin plastic QFP package was changed from All µPD750008GB-xxx-3B4 to µPD750008GB-xxx-3BS-MTX. The µPD75P0016 under development has been changed to[...]

322 µ PD750008 USER'S MANUAL [MEMO][...]