NEC uPD78P078Y manuel d'utilisation

µ PD78076 µ PD78078 µ PD78P078 µ PD78076Y µ PD78078Y µ PD78P078Y µ PD7807 8, 78078Y Subseries 8-bit Single-chip Microcontrollers Document No. U10641EJ4V0UM00 (4th edition) Date Published December 1997 N 1994 User’s Manual Printed in Japan ©[...]

2 [MEMO][...]

3 FIP, EEPROM, IEBus, and QTOP are trademarks of NEC Corporation. MS-DOS, Windows, and WindowsNT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM DOS, IBM PC/AT, and PC DOS are trademarks of International Business Machines Corporation. HP9000 Series 700 and HP-UX are trademarks[...]

4 The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. Purchase of NEC I 2 C components conveys a license under the Philips I 2 C Patent Rights to use these components in an I 2 C system, provided that the system conforms to the I 2 C Standard Specification as defined by Philips. Li[...]

5 NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 4[...]

6 Major Revisions in This Edition Page Description Throughout The following products have been changed from “under development” to “already developed”. µ PD78078Y Subseries: µ PD78076Y, 78078Y, 78P078Y The following packages have been added to the µ PD78078Y Subseries. 100-pin plastic LQFP (Fine pitch) (14 × 14 mm, resin thickness 1.4 m[...]

7 INTRODUCTION Readers This manual has been prepared for user engineers who understand the functions of the µ PD78078 and 78078Y Subseries and design and develop its application systems and programs. The µ PD78078 and 78078Y Subseries consist of the following members. • µ PD78078 Subseries: µ PD78076, 78078, 78P078 • µ PD78078Y Subseries: [...]

8 Chapter Organization : This manual divides the descriptions for the µ PD78078 and 78078Y Subseries into different chapters as shown below. Read only the chapters related to the device you use. Chapter µ PD78078 µ PD78078Y Subseries Subseries Chapter 1 Outline ( µ PD78078 Subseries) √ — Chapter 2 Outline ( µ PD78078Y Subseries) — √ Ch[...]

9 Differences between µ PD78078 and µ PD78078Y Subseries The µ PD78078 and µ PD78078Y Subseries are different in the following functions of the serial interface channel 0. Mode of serial interface channel 0 µ PD78078 µ PD78078Y Subseries Subseries 3-wire serial I/O mode √√ 2-wire serial I/O mode √√ SBI (serial bus interface) mode √ [...]

10 • Development Tool Documents (User’s Manuals) Document Name Document No. English Japanese RA78K Series Assembler Package Operation EEU-1399 EEU-809 Language EEU-1404 EEU-815 RA78K Series Structured Assembler Preprocessor EEU-1402 U12323J RA78K0 Assembler Package Operation U11802E U11802J Language U11801E U11801J Structured Assembly U11789E U[...]

11 • Documents for Embedded Software (User’s Manuals) Document Name Document No. English Japanese 78K/0 Series Real-time OS Basics U11537E U11537J Installation U11536E U11536J 78K/0 Series OS MX78K0 Basics U12257E U12257J • Other Documents Document Name Document No. English Japanese IC Package Manual C10943X Semiconductor Device Mounting Tech[...]

12 [MEMO][...]

13 TABLE OF CONTENTS CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) ................................................................................. 33 1.1 Features .................................................................................................................................. 33 1.2 Application Fields ................................[...]

14 3.2.17 AV SS ............................................................................................................................................. 76 3.2.18 RESET ......................................................................................................................................... 76 3.2.19 X1 and X2 ..................[...]

15 5.2 Processor Registers ............................................................................................................ 110 5.2.1 Control registers ........................................................................................................................ 1 10 5.2.2 General registers ....................................[...]

16 CHAPTER 7 CLOCK GENERATOR .................................................................................................... 165 7.1 Clock Generator Functions ................................................................................................ 165 7.2 Clock Generator Configuration ...................................................[...]

17 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 ................................................................. 249 10.1 8-Bit Timer/Event Counters 5 and 6 Functions ............................................................... 2 49 10.2 8-Bit Timer/Event Counters 5 and 6 Configurations ...................................................... 25[...]

18 CHAPTER 16 D/A CONVERTER ......................................................................................................... 309 16.1 D/A Converter Functions .................................................................................................... 3 09 16.2 D/A Converter Configuration ............................................[...]

19 CHAPTER 21 REAL-TIME OUTPUT PORT ........................................................................................ 495 21.1 Real-Time Output Port Functions ..................................................................................... 4 95 21.2 Real-Time Output Port Configuration ....................................................[...]

20 CHAPTER 27 µ PD78P078, 78P078Y .................................................................................................. 569 27.1 Internal Memory Size Switching Register ........................................................................ 57 0 27.2 Internal Extension RAM Size Switching Register .....................................[...]

21 LIST OF FIGURES (1/9) Figure No. Title Page 3-1 List of Pin Input/Output Circuits ................................................................................................... 80 4-1 List of Pin Input/Output Circuits ................................................................................................... 98 5-1 Memory Map ( µ P[...]

22 LIST OF FIGURES (2/9) Figure No. Title Page 7-1 Block Diagram of Clock Generator ............................................................................................ 16 6 7-2 Subsystem Clock Feedback Resistor ........................................................................................ 1 67 7-3 Processor Clock Control Register[...]

23 LIST OF FIGURES (3/9) Figure No. Title Page 8-26 Control Register Settings in External Event Counter Mode ..................................................... 21 1 8-27 External Event Counter Configuration Diagram ........................................................................ 21 2 8-28 External Event Counter Operation Timings (with Ri[...]

24 LIST OF FIGURES (4/9) Figure No. Title Page 10-14 8-Bit Timer Control Register Settings for PWM Output Operation .......................................... 264 10-15 PWM Output Operation Timing (Active High Setting) ............................................................... 26 5 10-16 PWM Output Operation Timings (CRn0 = 00H, Active High Se[...]

25 LIST OF FIGURES (5/9) Figure No. Title Page 17-1 Serial Bus Interface (SBI) System Configuration Example ...................................................... 3 17 17-2 Serial Interface Channel 0 Block Diagram ................................................................................ 318 17-3 Timer Clock Select Register 3 Format .........[...]

26 LIST OF FIGURES (6/9) Figure No. Title Page 18-10 Serial Bus Configuration Example Using 2-Wire Serial I/O Mode ........................................... 385 18-11 2-Wire Serial I/O Mode Timings ................................................................................................. 388 18-12 RELT and CMDT Operations .................[...]

27 LIST OF FIGURES (7/9) Figure No. Title Page 19-21 Operation Timings when Using Busy & Strobe Control Option (BUSY0 = 0) ......................... 45 2 19-22 Operation Timing of the Bit Slippage Detection Function through the Busy Signal (BUSY0 = 1) ..............................................................................................[...]

28 LIST OF FIGURES (8/9) Figure No. Title Page 22-13 Interrupt Request Acknowledge Processing Algorithm ............................................................. 5 17 22-14 Interrupt Request Acknowledge Timing (Minimum Time) ......................................................... 5 18 22-15 Interrupt Request Acknowledge Timing (Maximum Time) [...]

29 LIST OF FIGURES (9/9) Figure No. Title Page 27-1 Internal Memory Size Switching Register Format ..................................................................... 5 70 27-2 Internal Extension RAM Size Switching Register Format ........................................................ 57 1 27-3 Page Program Mode Flowchart ......................[...]

30 LIST OF TABLES (1/3) Table No. Title Page 1-1 Mask Options of Mask ROM Versions ......................................................................................... 4 7 1-2 Differences between µ PD78078 Subseries and µ PD78054 Subseries ..................................... 47 2-1 Mask Options of Mask ROM Versions ........................[...]

31 LIST OF TABLES (2/3) Table No. Title Page 9-9 Interval Times when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter .................................................................................. 2 43 9-10 Square-Wave Output Ranges when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-B[...]

32 LIST OF TABLES (3/3) Table No. Title Page 20-3 Relationship between Main System Clock and Baud Rate ...................................................... 467 20-4 Relationship between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H) .................................................................................................[...]

33 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) 1.1 Features Internal high-capacity ROM and RAM Notes 1. The capacity of internal PROM can be changed by means of the internal memory size switching register (IMS). 2. The capacity of internal high-speed RAM can be changed by means of the internal expansion RAM size switching register (IXS). External Mem[...]

34 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) 1.2 Application Fields Cellular phones, cordless telephones, printers, AV equipment, air conditioners, cameras, PPCs, fuzzy home appliances, vending machines, etc. 1.3 Ordering Information Part number Package Internal ROM µ PD78076GC-xxx-7EA 100-pin plastic QFP (Fine pitch) (14 x 14 mm, resin thickness [...]

35 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) 1.4 Quality Grade Part number Package Quality grades µ PD78076GC-xxx-7EA 100-pin plastic QFP (Fine pitch) (14 x 14 mm, resin thickness 1.45 mm) Standard µ PD78076GC-xxx-8EU Note 100-pin plastic LQFP (Fine pitch) (14 x 14 mm, resin thickness 1.4 mm) Standard µ PD78076GF-xxx-3BA 100-pin plastic QFP (14 [...]

36 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) 1.5 Pin Configuration (Top View) (1) Normal operating mode 100-pin plastic QFP (Fine pitch) (14 x 14 mm, resin thickness 1.45 mm) µ PD78076GC-xxx-7EA, 78078GC-xxx-7EA µ PD78P078GC-7EA 100-pin plastic LQFP (Fine pitch) (14 x 14 mm, resin thickness 1.4 mm) µ PD78076GC-xxx-8EU Note , 78078GC-xxx-8EU Note[...]

37 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) Cautions 1. Connect IC (Internally Connected) pin to V SS directly. 2. Connect AV DD pin to V DD . 3. Connect AV SS pin to V SS . Remark Pin connection in parentheses is for the µ PD78P078. 100 P13/ANI3 P122/RTP2 P121/RTP1 P120/RTP0 P96 P95 P94 P93 P92 P91 P90 P37 P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2[...]

38 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) 100-pin plastic QFP (14 x 20 mm) µ PD78076GF-xxx-3BA, 78078GF-xxx-3BA µ PD78P078GF-3BA 100-pin ceramic WQFN (14 x 20 mm) µ PD78P078KL-T Cautions 1. Connect IC (Internally Connected) pin to V SS directly. 2. Connect AV DD pin to V DD . 3. Connect AV SS pin to V SS . Remark Pin connection in parentheses[...]

39 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) Pin Identifications A0 to A15 : Address Bus AD0 to AD7 : Address/Data Bus ANI0 to ANI7 : Analog Input ANO0, ANO1 : Analog Output ASCK : Asynchronous Serial Clock ASTB : Address Strobe AV DD : Analog Power Supply AV REF0 , AV REF1 : Analog Reference Voltage AV SS : Analog Ground BUSY : Busy BUZ : Buzzer C[...]

40 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) (2) PROM programming mode 100-pin plastic QFP (Fine pitch) (14 x 14 mm, resin thickness 1.45 mm) µ PD78P078GC-7EA 100-pin plastic LQFP (Fine pitch) (14 x 14 mm, resin thickness 1.4 mm) µ PD78P078GC-8EU Note Note Under development Cautions 1. (L) : Connect independently to V SS via a pull-down resistor.[...]

41 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) 100-pin plastic QFP (14 x 20 mm) µ PD78P078GF-3BA 100-pin ceramic WQFN µ PD78P078KL-T Cautions 1. (L) : Connect independently to V SS via a pull-down resistor. 2. V SS : Connect to the ground. 3. RESET : Set to the low level. 4. Open : Leave open. A0 to A16 : Address Bus RESET : Reset CE : Chip Enable [...]

42 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) 1.6 78K/0 Series Expansion The products in the 78K/0 Series are listed below. The names in boxes are subseries names. Note Planned µ PD78098 80-pin Added IEBus controller to µ PD78054 µ PD78044F 80-pin Basic subseries for driving FIPs, 34 display outputs µ PD78002 µ PD78083 µ PD78002Y µ PD780208 ?[...]

43 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) The following shows the major differences between subseries products. Function ROM Timer 8-bit 10-bit 8-bit Serial Interface I/O V DD Externa l Subseries Name Capacity 8-bit 16-bit Watch WDT A/D A/D D/A MIN. Value Expansion Control µ PD78075B 32 K to 40 K 4 ch 1 ch 1 ch 1 ch 8 ch – 2 ch 3 ch (UART: 1 [...]

44 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) 1.7 Block Diagram Remarks 1. The internal ROM and RAM capacities depend on the product. 2. Pin connection in parentheses is for the µ PD78P078. TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 Interrupt Control Serial Interface 1 A/D Converter Serial Interface 0 Watchdog Timer 8-bit TIMER/ Event Counter 1 16-bit T[...]

45 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) 1.8 Outline of Function Internal ROM Mask ROM PROM memory 48 Kbytes 60 Kbytes 60 Kbytes Note 1 High-speed RAM 1024 bytes Buffer RAM 32 bytes Expansion RAM 1024 bytes 1024 bytes Note 2 Memory space 64 Kbytes General register 8 bits x 8 x 4 banks With main system clock selected 0.4 µ s/0.8 µ s/1.6 µ s/3[...]

46 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) Item µ PD78076 µ PD78078 µ PD78P078 Part Number Vectored Maskable Internal: 15 interrupt External: 7 source Non-maskable Internal: 1 Software Internal: 1 Test input Internal: 1 External: 1 Power supply voltage V DD = 1.8 to 5.5 V Operating ambient temperature T A = –40 to +85 ° C Package • 100-pi[...]

47 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) 1.9 Mask Options The mask ROM versions ( µ PD78076, 78078) provide pull-up register mask options which allow users to specify whether to connect a pull-up register to a specific port pin when the user places an order for the device production. Using this mask option when pull-up resistors are required r[...]

48 [MEMO][...]

49 Data Memory Part Number Type Program Memory (ROM) µ PD78076Y µ PD78078Y µ PD78P078Y CHAPTER 2 OUTLINE ( µ PD78078Y SUBSERIES) 2.1 Features Internal high-capacity ROM and RAM Notes 1. The capacity of internal PROM can be changed using the internal memory size switching register (IMS). 2. The capacity of internal high-speed RAM can be changed [...]

50 CHAPTER 2 OUTLINE ( µ PD78078Y SUBSERIES) 2.2 Application Fields Cellular phones, cordless telephones, printers, AV equipment, air conditioners, cameras, PPCs, fuzzy home appliances, vending machines, etc. 2.3 Ordering Information Part number Package Internal ROM µ PD78076YGC-xxx-8EU Note 100-pin plastic LQFP (Fine pitch) (14 x 14 mm, resin th[...]

51 CHAPTER 2 OUTLINE ( µ PD78078Y SUBSERIES) 2.4 Quality Grade Part number Package Quality grades µ PD78076YGC-xxx-8EU Note 100-pin plastic LQFP (Fine pitch) (14 x 14 mm, resin thickness 1.4 mm) Standard µ PD78076YGF-xxx-3BA 100-pin plastic QFP (14 x 20 mm, resin thickness 2.7 mm) Standard µ PD78078YGC-xxx-8EU Note 100-pin plastic LQFP (Fine pi[...]

52 CHAPTER 2 OUTLINE ( µ PD78078Y SUBSERIES) 2.5 Pin Configuration (Top View) (1) Normal operating mode 100-pin plastic LQFP (Fine pitch) (14 x 14 mm, resin thickness 1.4 mm) µ PD78076YGC-xxx-8EU Note , 78078YGC-xxx-8EU Note µ PD78P078YGC-8EU Note Note Under development[...]

53 CHAPTER 2 OUTLINE ( µ PD78078Y SUBSERIES) 100 P13/ANI3 P122/RTP2 P121/RTP1 P120/RTP0 P96 P95 P94 P93 P92 P91 P90 P37 P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P103 P102 P101/TI6/TO6 P100/TI5/TO5 P67/ASTB P66/WAIT P65/WR 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1[...]

54 CHAPTER 2 OUTLINE ( µ PD78078Y SUBSERIES) 1 49 48 47 45 43 42 40 39 38 37 35 33 31 44 41 34 32 P16/ANI6 2 3 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 4 5 17 26 27 28 29 30 P66/WAIT P65/WR P64/RD P61 P60 P57/A15 P56/A14 V SS P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P87/A7 P6[...]

55 CHAPTER 2 OUTLINE ( µ PD78078Y SUBSERIES) Pin Identifications A0 to A15 : Address Bus AD0 to AD7 : Address/Data Bus ANI0 to ANI7 : Analog Input ANO0, ANO1 : Analog Output ASCK : Asynchronous Serial Clock ASTB : Address Strobe AV DD : Analog Power Supply AV REF0 , AV REF1 : Analog Reference Voltage AV SS : Analog Ground BUSY : Busy BUZ : Buzzer [...]

56 CHAPTER 2 OUTLINE ( µ PD78078Y SUBSERIES) (2) PROM programming mode 100-pin plastic QFP (Fine pitch) (14 x 14 mm, resin thickness 1.45 mm) µ PD78P078YGC-7EA 100-pin plastic LQFP (Fine pitch) (14 x 14 mm, resin thickness 1.4 mm) µ PD78P078YGC-8EU Note Note Under development Cautions 1. (L) : Connect independently to V SS via a pull-down resist[...]

57 CHAPTER 2 OUTLINE ( µ PD78078Y SUBSERIES) 100-pin plastic QFP (14 x 20 mm) µ PD78P078YGF-3BA 100-pin ceramic WQFN µ PD78P078YKL-T Cautions 1. (L) : Connect independently to V SS via a pull-down resistor. 2. V SS : Connect to the ground. 3. RESET : Set to the low level. 4. Open : Leave open. A0 to A16 : Address Bus RESET : Reset CE : Chip Enab[...]

58 CHAPTER 2 OUTLINE ( µ PD78078Y SUBSERIES) 2.6 78K/0 Series Expansion The products in the 78K/0 Series are listed below. The names in boxes are subseries names. Note Planned µ PD78098 80-pin Added IEBus controller to µ PD78054 µ PD78044F 80-pin Basic subseries for driving FIPs, 34 display outputs µ PD78002 µ PD78083 µ PD78002Y µ PD780208 [...]

59 CHAPTER 2 OUTLINE ( µ PD78078Y SUBSERIES) Major differences among Y subseries are tabulated below. Function ROM Configuration of Serial Interface I /O V DD Subseries Capacity MIN. Control µ PD78078Y 48K to 60K 3-wire/2-wire/I 2 C : 1 ch 88 1.8 V 3-wire with automatic transmit/receive function : 1 ch µ PD78070AY — 3-wire/UART : 1 ch 61 2.7 V[...]

60 CHAPTER 2 OUTLINE ( µ PD78078Y SUBSERIES) 2.7 Block Diagram Remarks 1. The internal ROM and RAM capacities depend on the product. 2. Pin connection in parentheses is for the µ PD78P078Y. TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 Interrupt Control Serial Interface 1 A/D Converter Serial Interface 0 Watchdog Timer 8-bit TIMER/ Event Counter 1 16-bit[...]

61 CHAPTER 2 OUTLINE ( µ PD78078Y SUBSERIES) Part Number 2.8 Outline of Function Mask ROM PROM 48 Kbytes 60 Kbytes 60 Kbytes Note 1 High-speed RAM 1024 bytes Buffer RAM 32 bytes Expansion RAM 1024 bytes 1024 bytes Memory space 64 Kbytes General register 8 bits x 8 x 4 banks With main system clock selected 0.4 µ s/0.8 µ s/1.6 µ s/3.2 µ s/6.4 µ[...]

62 CHAPTER 2 OUTLINE ( µ PD78078Y SUBSERIES) Item Part Number µ PD78076Y µ PD78078Y µ PD78P078Y Vectored Maskable Internal: 15 interrupt External: 7 source Non-maskable Internal: 1 Software Internal: 1 Test input Internal: 1 External: 1 Power supply voltage V DD = 1.8 to 5.5 V Operating ambient temperature T A = –40 to +85 ° C Package • 10[...]

63 CHAPTER 2 OUTLINE ( µ PD78078Y SUBSERIES) 2.9 Mask Options The mask ROM versions ( µ PD78076Y, 78078Y) provide pull-up register mask options which allow users to specify whether to connect a pull-up register to a specific port pin when the user places an order for the device production. Using this mask option when pull-up resistors are require[...]

64 [MEMO][...]

65 Input/ output CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) 3.1 Pin Function List 3.1.1 Normal operating mode pins (1) Port pins (1/3) Input Input Pin Name Input/Output Function After Reset Alternate Function P00 Input Input only Input INTP0/TI00 P01 Input/output mode can be specified INTP1/TI01 P02 bit-wise. INTP2 P03 Input/ Port 0. If used as[...]

66 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) (1) Port pins (2/3) Pin Name Input/Output Function After Reset Alternate Function P30 TO0 P31 TO1 P32 Port 3. TO2 P33 Input/ 8-bit input/output port. TI1 P34 output Input/output mode can be specified bit-wise. TI2 P3 5 If used as an input port, an on-chip pull-up resistor can be connected by PC L P3[...]

67 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) Input/ output N-ch open-drain input/output port. On-chip pull-up resistor can be specified by mask option. (Mask ROM version only). LEDs can be driven directly. (1) Port pins (3/3) Pin Name Input/Output Function After Reset Alternate Function P90 P91 Port 9. P92 7-bit input/output port. P93 Input/ou[...]

68 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) Input/ output Serial interface serial data input/output Input (2) Non-port pins (1/2) Pin Name Input/Output Function After Reset Alternate Function INTP0 P00/TI00 INTP1 P01/TI01 INTP2 External interrupt request inputs with specifiable valid edges (rising edge, P0 2 INTP3 Input falling edge, both ris[...]

69 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) (2) Non-port pins (2/2) Pin Name Input/Output Function After Reset Alternate Function AD0 to AD7 Input/Output Low-order address/data bus when expanding external memory Input P40 to P47 A0 to A7 Output Low-order address bus when expanding external memory Input P80 to P87 A8 to A15 Output High-order a[...]

70 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) 3.2 Description of Pin Functions 3.2.1 P00 to P07 (Port 0) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem[...]

71 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) 3.2.3 P20 to P27 (Port 2) These are 8-bit input/output ports. Besides serving as input/output ports, they function as data input/output to/ from the serial interface, clock input/output, automatic transmit/receive busy input, and strobe output functions. The following operating modes can be specifie[...]

72 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) 3.2.4 P30 to P37 (Port 3) These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock output and buzzer output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can b[...]

73 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) 3.2.6 P50 to P57 (Port 5) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address bus. Port 5 can drive LEDs directly. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be s[...]

74 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) 3.2.8 P70 to P72 (Port 7) This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions. The following operating modes can be specified bit-wise. (1) Port mode Port 7 functions as a 3-bit input/outp[...]

75 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) 3.2.10 P90 to P96 (Port 9) These are 7-bit input/output ports. P90 to P93 can drive LEDs directly. They can be specified bit-wise as input or output ports with port mode register 9 (PM9). P90 to P93 are N-ch open-drain pins. Mask ROM version product can contain pull-up resistors with the mask option[...]

76 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) 3.2.13 P130 and P131 (Port 13) These are 2-bit input/output ports. Besides serving as input/output ports, they are used for D/A converter analog output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 2-bit input/output ports. They can be specified bit-[...]

77 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) 3.2.21 V DD Positive power supply pin 3.2.22 V SS Ground potential pin 3.2.23 V PP ( µ PD78P078 only) High-voltage apply pin for PROM programming mode setting and program write/verify. Connect directly to V SS in normal operating mode. 3.2.24 IC (Mask ROM version only) The IC (Internally Connected)[...]

78 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) 3.3 Input/output Circuits and Recommended Connection of Unused Pins Table 2-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. Refer to Figure 3-1 for the configuration of the input/output circuit of each type. Table 3-1. Pin Input/Output Circuit Types (1/[...]

79 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) Table 3-1. Pin Input/Output Circuit Types (2/2) Pin Name Input/Output Input/Output Recommended Connection of Unused Pins Circuit Type P50/A8 to P57/A15 5-A Input/output Connect independently via a resistor to V DD or V SS . P60 to P63 (Mask ROM version) 13-B Input/output Connect independently via a [...]

80 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) Figure 3-1. List of Pin Input/Output Circuits (1/2) IN pullup enable V DD P-ch IN/OUT input enable output disable data V DD P-ch N-ch Type 2 Type 5-A Schmitt-Triggered Input with Hysteresis Characteristics Type 5-E Type 11 Type 10-A Type 8-A pullup enable V DD P-ch IN/OUT output disable data V DD P-[...]

81 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) Figure 3-1. List of Pin Input/Output Circuits (2/2) Type 12-A Type 13-B Type 13-D output disable V DD N-ch IN/OUT RD medium breakdown input buffer data P-ch XT2 XT1 feedback cut-off P-ch Type 16 output disable V DD V DD N-ch Mask Option IN/OUT RD medium breakdown input buffer data P-ch pullup enable[...]

82 [MEMO][...]

83 Input/ output CHAPTER 4 PIN FUNCTION ( µ PD78078Y SUBSERIES) 4.1 Pin Function List 4.1.1 Normal operating mode pins (1) Port pins (1/3) Input Input Pin Name Input/Output Function After Reset Alternate Function P00 Input Input only Input INTP0/TI00 P01 Input/output mode can be specified INTP1/TI01 P02 bit-wise. INTP2 P03 Input/ Port 0. If used a[...]

84 CHAPTER 4 PIN FUNCTION ( µ PD78078Y SUBSERIES) Input P40 to P47 Input AD0 to AD7 (1) Port pins (2/3) Pin Name Input/Output Function After Reset Alternate Function P30 TO0 P31 TO1 P32 Port 3. TO2 P33 Input/ 8-bit input/output port. TI1 P34 output Input/output mode can be specified bit-wise. TI2 P3 5 If used as an input port, an on-chip pull-up r[...]

85 CHAPTER 4 PIN FUNCTION ( µ PD78078Y SUBSERIES) Input/ output N-ch open-drain input/output port. On-chip pull-up resistor can be specified by mask option. (Mask ROM version only). LEDs can be driven directly. (1) Port pins (3/3) Pin Name Input/Output Function After Reset Alternate Function P90 P91 Port 9. P92 7-bit input/output port. P93 Input/o[...]

86 CHAPTER 4 PIN FUNCTION ( µ PD78078Y SUBSERIES) (2) Non-port pins (1/2) Pin Name Input/Output Function After Reset Alternate Function INTP0 P00/TI00 INTP1 P01/TI01 INTP2 External interrupt request inputs with specifiable valid edges (rising edge, P0 2 INTP3 Input falling edge, both rising and falling edges). Input P03 INTP4 P04 INTP5 P05 INTP6 P[...]

87 CHAPTER 4 PIN FUNCTION ( µ PD78078Y SUBSERIES) V PP — —— (2) Non-port pins (2/2) Pin Name Input/Output Function After Reset Alternate Function AD0 to AD7 Input/Output Low-order address/data bus when expanding external memory Input P40 to P47 A0 to A7 Output Low-order address bus when expanding external memory Input P80 to P87 A8 to A15 Ou[...]

88 CHAPTER 4 PIN FUNCTION ( µ PD78078Y SUBSERIES) 4.2 Description of Pin Functions 4.2.1 P00 to P07 (Port 0) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsyste[...]

89 CHAPTER 4 PIN FUNCTION ( µ PD78078Y SUBSERIES) 4.2.3 P20 to P27 (Port 2) These are 8-bit input/output ports. Besides serving as input/output ports, they function as data input/output to/ from the serial interface, clock input/output, automatic transmit/receive busy input, and strobe output functions. The following operating modes can be specifi[...]

90 CHAPTER 4 PIN FUNCTION ( µ PD78078Y SUBSERIES) 4.2.4 P30 to P37 (Port 3) These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock output and buzzer output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can [...]

91 CHAPTER 4 PIN FUNCTION ( µ PD78078Y SUBSERIES) 4.2.6 P50 to P57 (Port 5) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address bus. Port 5 can drive LEDs directly. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be [...]

92 CHAPTER 4 PIN FUNCTION ( µ PD78078Y SUBSERIES) 4.2.8 P70 to P72 (Port 7) This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions. The following operating modes can be specified bit-wise. (1) Port mode Port 7 functions as a 3-bit input/out[...]

93 CHAPTER 4 PIN FUNCTION ( µ PD78078Y SUBSERIES) 4.2.10 P90 to P96 (Port 9) These are 7-bit input/output ports. P90 to P93 can drive LEDs directly. They can be specified bit-wise as input or output ports with port mode register 9 (PM9). P90 to P93 are N-ch open-drain pins. Mask ROM version product can contain pull-up resistors with the mask optio[...]

94 CHAPTER 4 PIN FUNCTION ( µ PD78078Y SUBSERIES) 4.2.13 P130 and P131 (Port 13) These are 2-bit input/output ports. Besides serving as input/output ports, they are used for D/A converter analog output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 2-bit input/output ports. They can be specified bit[...]

95 CHAPTER 4 PIN FUNCTION ( µ PD78078Y SUBSERIES) 4.2.21 V DD Positive power supply pin 4.2.22 V SS Ground potential pin 4.2.23 V PP ( µ PD78P078Y only) High-voltage apply pin for PROM programming mode setting and program write/verify. Connect directly to V SS in normal operating mode. 4.2.24 IC (Mask ROM version only) The IC (Internally Connecte[...]

96 CHAPTER 4 PIN FUNCTION ( µ PD78078Y SUBSERIES) 4.3 Input/output Circuits and Recommended Connection of Unused Pins Table 4-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. Refer to Figure 4-1 for the configuration of the input/output circuit of each type. Table 4-1. Pin Input/Output Circuit Types (1[...]

97 CHAPTER 4 PIN FUNCTION ( µ PD78078Y SUBSERIES) Table 4-1. Pin Input/Output Circuit Types (2/2) Pin Name Input/Output Input/Output Recommended Connection of Unused Pins Circuit Type P50/A8 to P57/A15 5-A Input/output Connect independently via a resistor to V DD or V SS . P60 to P63 (Mask ROM version) 13-B Input/output Connect independently via a[...]

98 CHAPTER 4 PIN FUNCTION ( µ PD78078Y SUBSERIES) Figure 4-1. List of Pin Input/Output Circuits (1/2) IN pullup enable V DD P-ch IN/OUT input enable output disable data V DD P-ch N-ch Type 2 Type 5-A Schmitt-Triggered Input with Hysteresis Characteristics Type 5-E Type 11 Type 10-A Type 8-A pullup enable V DD P-ch IN/OUT output disable data V DD P[...]

99 CHAPTER 4 PIN FUNCTION ( µ PD78078Y SUBSERIES) Figure 4-1. List of Pin Input/Output Circuits (2/2) Type 12-A Type 13-B Type 13-D output disable V DD N-ch IN/OUT RD medium breakdown input buffer data P-ch XT2 XT1 feedback cut-off P-ch Type 16 output disable V DD V DD N-ch Mask Option IN/OUT RD medium breakdown input buffer data P-ch pullup enabl[...]

100 [MEMO][...]

101 0000H Data memory space General Registers 32 x 8 bits Internal ROM 49152 x 8 bits BFFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Internal Buffer RAM 32 x 8 bits External Memory 13312 x 8 bits Reserved Program memory space C000H BFFFH F800H F7FFH FAC0H FAB[...]

102 CHAPTER 5 CPU ARCHITECTURE 0000H Data memory space General Registers 32 x 8 bits Internal ROM 61440 x 8 bits EFFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Internal Buffer RAM 32 x 8 bits Reserved Note Program memory space F000H EFFFH F800H F7FFH FAC0H FA[...]

103 CHAPTER 5 CPU ARCHITECTURE 0000H Data memory space General Registers 32 x 8 bits Internal PROM 61440 x 8 bits EFFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Internal Buffer RAM 32 x 8 bits Reserved Program memory space F000H EFFFH F800H F7FFH FAC0H FABFH [...]

104 CHAPTER 5 CPU ARCHITECTURE 5.1.1 Internal program memory space The internal program memory space stores programs and table data. This is generally accessed by the program counter (PC). The µ PD78078 and 78078Y Subseries have various size of internal ROMs or PROM as shown below. Table 5-1. Internal ROM Capacities Part number Internal ROM Type C[...]

105 CHAPTER 5 CPU ARCHITECTURE (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. Of the 16-bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are [...]

106 CHAPTER 5 CPU ARCHITECTURE 5.1.2 Internal data memory space The µ PD78078 and 78078Y Subseries units incorporate the following RAMs. (1) Internal high-speed RAM This is a 1024 x 8-bit configuration in the area FB00H to FEFFH 4 banks of general registers, each bank consisting of eight 8-bit registers, are allocated in the 32-byte area FEE0H to [...]

107 CHAPTER 5 CPU ARCHITECTURE 0000H General Registers 32 x 8 bits Internal ROM 49152 x 8 bits Internal Buffer RAM 32 x 8 bits External Memory 13312 x 8 bits Reserved C000H BFFFH F800H F7FFH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High-speed RAM 1024 x 8 bits Reserved FB00H FAFFH F400H F3FFH FF20H FF1FH FE20H FE1FH Special Fu[...]

108 CHAPTER 5 CPU ARCHITECTURE 0000H General Registers 32 x 8 bits Internal ROM 61440 x 8 bits Internal Buffer RAM 32 x 8 bits Reserved F000H EFFFH F800H F7FFH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High-speed RAM 1024 x 8 bits Reserved FB00H FAFFH F400H F3FFH FF20H FF1FH FE20H FE1FH Special Function Registers (SFRs) 256 x 8[...]

109 CHAPTER 5 CPU ARCHITECTURE 0000H General Registers 32 x 8 bits Internal ROM 61440 x 8 bits Internal Buffer RAM 32 x 8 bits Reserved F000H EFFFH F800H F7FFH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High-speed RAM 1024 x 8 bits Reserved FB00H FAFFH F400H F3FFH FF20H FF1FH FE20H FE1FH Special Function Registers (SFRs) 256 x 8[...]

110 CHAPTER 5 CPU ARCHITECTURE 70 IE PSW Z RBS1 AC RBS0 0 ISP CY PC 15 0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 5.2 Processor Registers The µ PD78078 and 78078Y Subseries units incorporate the following processor registers. 5.2.1 Control registers The control registers control the program sequence, statuses, and stac[...]

111 CHAPTER 5 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When IE = 0, the IE is set to interrupt disabled (DI) status. All interrupts except non-maskable interrupt are disabled. When IE = 1, the IE is set to interrupt enabled (EI) status and interrupt request acknowled[...]

112 CHAPTER 5 CPU ARCHITECTURE SP 15 0 SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 5-9. Stack Pointer Configuration The SP is decremented ahead of w[...]

113 CHAPTER 5 CPU ARCHITECTURE 5.2.2 General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can also be used as an 8-bit register. Two 8-bit registers can be used in pairs as a 16-bit[...]

114 CHAPTER 5 CPU ARCHITECTURE 5.2.3 Special function register (SFR) Unlike a general register, each special function register has special functions. It is allocated in the FF00H to FFFFH area. The special function registers can be manipulated in a similar way as the general registers, by using operation, transfer, or bit-manipulate instructions. T[...]

115 CHAPTER 5 CPU ARCHITECTURE Address Special Function Register (SFR) Name Symbol R/W After Reset FF00H Port0 P0 R/W √√ — 00H FF01H Port1 P1 √√ — FF02H Port2 P2 √√ — FF03H Port3 P3 √√ — FF04H Port4 P4 √√ — Undefined FF05H Port5 P5 √√ — FF06H Port6 P6 √√ — FF07H Port7 P7 √√ — 00H FF08H Port8 P8 √√[...]

116 CHAPTER 5 CPU ARCHITECTURE Table 5-3. Special Function Register List (2/3) 8 bits 1 bit 16 bits Address Special Function Register (SFR) Name Symbol R/W After Reset FF30H Real-time output buffer register L RTBL R/W — √ — 00H FF31H Real-time output buffer register H RTBH — √ — FF34H Real-time output port mode register RTPM √√ — [...]

117 CHAPTER 5 CPU ARCHITECTURE Address Special Function Register (SFR) Name Symbol R/W After Reset FF74H Transmit shift register TXS SIO2 W — √ — FFH Receive buffer register RXB R FF80H A/D converter mode register ADM R/W √√ — 01H FF84H A/D converter input select register ADIS — √ — 00H FF8AH Correction control register CORCN √?[...]

118 CHAPTER 5 CPU ARCHITECTURE 15 0 PC + 15 0 876 S 15 0 PC α jdisp8 When S = 0, all bits of α are 0. When S = 1, all bits of α are 1. PC indicates the start address of the instruction after the BR instruction. ... 5.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The PC contents are normal[...]

119 CHAPTER 5 CPU ARCHITECTURE 5.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can branch to all the memory space. C[...]

120 CHAPTER 5 CPU ARCHITECTURE 5.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. Table indirect addressing is carried out when the CALLT [addr5] instructi[...]

121 CHAPTER 5 CPU ARCHITECTURE 5.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] 70 rp 07 AX 15 0 PC 87[...]

122 CHAPTER 5 CPU ARCHITECTURE 5.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general register is automatically (implicitly)[...]

123 CHAPTER 5 CPU ARCHITECTURE 01100010 Register specify code Operation code 5.4.2 Register addressing [Function] The general register is accessed as an operand. The general register to be accessed is specified with register bank select flags (RBS0 and RBS1) and register specify code (Rn, RPn) in the instruction code. Register addressing is carried[...]

124 CHAPTER 5 CPU ARCHITECTURE 5.4.3 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 10001110 O P code 00000000 0 0 H 11111[...]

125 CHAPTER 5 CPU ARCHITECTURE 5.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space to which this addressing is applied to is the 256-byte space, from FE20H to FF1FH. An internal high-speed RAM and a special function register (SFR) are [...]

126 CHAPTER 5 CPU ARCHITECTURE 15 0 SFR Effective Address 1 111111 87 0 7 OP code sfr-offset 1 5.4.5 Special function register (SFR) addressing [Function] The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFF[...]

127 CHAPTER 5 CPU ARCHITECTURE 5.4.6 Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register bank select flag (RBS0 and RBS1) and the register pair specify code in the instruction code. This addressing can be carri[...]

128 CHAPTER 5 CPU ARCHITECTURE 5.4.7 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. The HL register pair to be accessed is in the register bank specified with the register bank select flags (RBS0 and RBS1). Addition is performe[...]

129 CHAPTER 5 CPU ARCHITECTURE 5.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction are added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. The HL, B, and C registers to be accessed are registers in the register bank specified with the re[...]

130 [MEMO][...]

131 CHAPTER 6 PORT FUNCTIONS 6.1 Port Functions The µ PD78078 and 78078Y Subseries units incorporate two input ports and eighty-six input/output ports. Figure 6-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. Besides port functions, the ports can also [...]

132 CHAPTER 6 PORT FUNCTIONS Pin Name Function Alternate Function P00 Input only INTP0/TI00 P01 INTP1/TI01 P02 Input/output mode can be specified bit- INTP2 P03 Port 0. wise. INTP3 P04 8-bit input/output port. If used as an input port, an on-chip pull- INTP4 P05 up resistor can be connected by software. INTP5 P06 INTP6 P07 Input only XT1 Port 1. 8-[...]

133 CHAPTER 6 PORT FUNCTIONS P120 to P127 RTP0 to RTP7 P130, P131 ANO0, ANO1 P100 TI5/TO5 P101 TI6/TO6 P102, 103 — P70 SI2/RxD P71 SO2/TxD P72 SCK2/ASCK Table 6-1. Port Functions ( µ PD78078 Subseries) (2/2) Pin Name Function Alternate Function P60 N-ch open drain input/output port. P6 1 On-chip pull-up resistor can be specified by P62 Port 6. m[...]

134 CHAPTER 6 PORT FUNCTIONS Table 6-2. Port Functions ( µ PD78078Y Subseries) (1/2) Pin Name Function Alternate Function P00 Input only INTP0/TI00 P01 INTP1/TI01 P02 Input/output mode can be specified bit- INTP2 P03 Port 0. wise. INTP3 P04 8-bit input/output port. If used as an input port, an on-chip pull- INTP4 P05 up resistor can be connected b[...]

135 CHAPTER 6 PORT FUNCTIONS Table 6-2. Port Functions ( µ PD78078Y Subseries) (2/2) Pin Name Function Alternate Function P60 N-ch open drain input/output port. P6 1 On-chip pull-up resistor can be specified by P62 Port 6. mask option. (Mask ROM version only). P63 8-bit input/output port. LEDs can be driven directly. P64 Input/output mode can be s[...]

136 CHAPTER 6 PORT FUNCTIONS 6.2 Port Configuration A port consists of the following hardware: Table 6-3. Port Configuration Item Configuration Control register Port mode register (PMm: m = 0 to 3, 5 to 10, 12, 13) Pull-up resistor option register (PUOH, PUOL) Memory expansion mode register (MM) Note Key return mode register (KRM) Port Total: 88 po[...]

137 CHAPTER 6 PORT FUNCTIONS Figure 6-2. Block Diagram of P00 and P07 Figure 6-3. Block Diagram of P01 to P06 PUO : Pull-up resistor option register PM : Port mode register RD : Port 0 read signal WR : Port 0 write signal P00/INTP0/TI00, P07/XT1 RD Internal bus P-ch WR PM WR PORT RD WR PUO V DD P01/INTP1/TI01, P02/INTP2 to P06/INTP6 Selector PUO0 O[...]

138 CHAPTER 6 PORT FUNCTIONS 6.2.2 Port 1 Port 1 is an 8-bit input/output port with output latch. It can specify the input mode/output mode in 1-bit units with a port mode register 1 (PM1). When P10 to P17 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register L (PUO[...]

139 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD Selector PUO2 Output Latch (P20, P21, P23 to P26) PM20, PM21 PM23 to PM26 Internal bus Dual Function P20/SI1, P21/SO1, P23/STB, P24/BUSY, P25/SI0/SB0, P26/SO0/SB1 6.2.3 Port 2 ( µ PD78078 Subseries) Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can specify the[...]

140 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD Selector PUO2 Output Latch (P20, P21, P23 to P26) PM20, PM21 PM23 to PM26 Internal bus Dual Function P20/SI1, P21/SO1, P23/STB, P24/BUSY, P25/SI0/SB0/SDA0, P26/SO0/SB1/SDA1 Figure 6-6. Block Diagram of P22 and P27 PUO : Pull-up resistor option register PM : Port mode register RD : Port [...]

141 CHAPTER 6 PORT FUNCTIONS P20/SI1, P21/SO1, P23/STB, P24/BUSY, P25/SI0/SB0/SDA0, P26/SO0/SB1/SDA1 P-ch WR PM WR PORT RD WR PUO V DD Selector PUO2 Output Latch (P20, P21, P23 to P26) PM20, PM21 PM23 to PM26 Internal bus Dual Function 6.2.4 Port 2 ( µ PD78078Y Subseries) Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can [...]

142 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD Selector PUO2 Output Latch (P22, P27) PM22, PM27 Internal bus Dual Function P22/SCK1, P27/SCK0/SCL Figure 6-8. Block Diagram of P22 and P27 PUO : Pull-up resistor option register PM : Port mode register RD : Port 2 read signal WR : Port 2 write signal[...]

143 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD Selector PUO3 Output Latch (P30 to P37) PM30 to PM37 Internal bus Dual Function P30/TO0 to P32/TO2, P33/TI1, P34/TI2, P35/PCL, P36/BUZ, P37 6.2.5 Port 3 Port 3 is an 8-bit input/output port with output latch. P30 to P37 pins can specify the input mode/output mode in 1-bit units with the[...]

144 CHAPTER 6 PORT FUNCTIONS 6.2.6 Port 4 Port 4 is an 8-bit input/output port with output latch. P40 to P47 pins can specify the input mode/output mode in 8-bit units with the memory expansion mode register (MM). When P40 to P47 pins are used as input ports, an on- chip pull-up resistor can be connected to them in 8-bit units with a pull-up resist[...]

145 CHAPTER 6 PORT FUNCTIONS 6.2.7 Port 5 Port 5 is an 8-bit input/output port with output latch. P50 to P57 pins can specify the input mode/output mode in 1-bit units with the port mode register 5 (PM5). When P50 to P57 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option [...]

146 CHAPTER 6 PORT FUNCTIONS 6.2.8 Port 6 Port 6 is an 8-bit input/output port with output latch. P60 to P67 pins can specify the input mode/output mode in 1-bit units with the port mode register 6 (PM6). This port has pull-up resistor options as shown below. However, the option specification method differs depending on the port pin and the device [...]

147 CHAPTER 6 PORT FUNCTIONS Figure 6-13. Block Diagram of P60 to P63 PM : Port mode register RD : Port 6 read signal WR : Port 6 write signal Figure 6-14. Block Diagram of P64 to P67 PUO : Pull-up resistor option register PM : Port mode register RD : Port 6 read signal WR : Port 6 write signal WR PM WR PORT RD V DD Selector Output Latch (P60 to P6[...]

148 CHAPTER 6 PORT FUNCTIONS 6.2.9 Port 7 This is a 3-bit input/output port with output latches. Input mode/output mode can be specified in 1-bit units with a port mode register 7 (PM7). When pins P70 to P72 are used as input port pins, an on-chip pull-up resistor can be connected in 3-bit units with a pull-up resistor option register L (PUOL). Dua[...]

149 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD Selector PUO7 Output Latch (P71, P72) PM71, PM72 Internal bus Dual Function P71/SO2/TxD, P72/SCK2/ASCK Figure 6-16. Block Diagram of P71 and P72 PUO : Pull-up resistor option register PM : Port mode register RD : Port 7 read signal WR : Port 7 write signal[...]

150 CHAPTER 6 PORT FUNCTIONS 6.2.10 Port 8 Port 8 is an 8-bit input/output port with output latch. P80 to P87 pins can specify the input mode/output mode in 1-bit units with the port mode register 8 (PM8). When pins P80 to P87 are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option[...]

151 CHAPTER 6 PORT FUNCTIONS 6.2.11 Port 9 Port 9 is an 7-bit input/output port with output latch. P90 to P96 pins can specify the input mode/output mode in 1-bit units with the port mode register 9 (PM9). This port has pull-up resistor options as shown below. However, the option specification method differs depending on the port pin and the device[...]

152 CHAPTER 6 PORT FUNCTIONS Figure 6-18. Block Diagram of P90 to P93 PM : Port mode register RD : Port 9 read signal WR : Port 9 write signal Figure 6-19. Block Diagram of P94 to P96 PUO : Pull-up resistor option register PM : Port mode register RD : Port 9 read signal WR : Port 9 write signal Mask Option Resistor WR PM WR PORT RD V DD Selector Ou[...]

153 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD Selector PUO10 Output Latch (P100, P101) PM100, PM101 Internal bus Dual-functions P100/TI5/TO5, P101/TI6/TO6 6.2.12 Port 10 Port 10 is a 4-bit input/output port with output latch. P100 to P103 pins can specify the input mode/output mode in 1-bit units with the port mode register 10 (PM1[...]

154 CHAPTER 6 PORT FUNCTIONS Figure 6-21. Block Diagram of P102 and P103 PUO : Pull-up resistor option register PM : Port mode register RD : Port 6 read signal WR : Port 6 write signal P-ch WR PM WR PORT RD WR PUO V DD Selector PUO10 Output Latch (P102, P103) PM102, PM103 Internal bus P102, P103[...]

155 CHAPTER 6 PORT FUNCTIONS 6.2.13 Port 12 This is an 8-bit input/output port with output latches. Input mode/output mode can be specified in 1-bit units with the port mode register 12 (PM12). When pins P120 to P127 are used as input port pins, an on-chip pull-up resistor can be connected in 8-bit units with a pull-up resistor option register H (P[...]

156 CHAPTER 6 PORT FUNCTIONS 6.2.14 Port 13 This is a 2-bit input/output port with output latches. Input mode/output mode can be specified in 1-bit units with the port mode register 13 (PM13). When pins P130 and P131 are used as input port pins, an on-chip pull-up resistor can be connected in 2-bit units with a pull-up resistor option register H (P[...]

157 CHAPTER 6 PORT FUNCTIONS 6.3 Port Function Control Registers The following four types of registers control the ports. • Port mode registers (PM0 to PM3, PM5 to PM10, PM12, PM13) • Pull-up resistor option register (PUOH, PUOL) • Memory expansion mode register (MM) • Key return mode register (KRM) (1) Port mode registers (PM0 to PM3, PM5 [...]

158 CHAPTER 6 PORT FUNCTIONS P00 INTP0 Input 1 (Fixed) None P50 to P57 A8 to A15 Output x Note 2 TI00 Input 1 (Fixed) None P64 RD Output x Note 2 P01 INTP1 Input 1 x P65 WR Output x Note 2 TI01 Input 1 x P66 WAIT Input x Note 2 P02 to P06 INTP2 to INTP6 Input 1 x P67 ASTB Output x Note 2 P07 Note 1 XT1 Input 1 (Fixed) None P80 to P87 A0 to A7 Outpu[...]

159 CHAPTER 6 PORT FUNCTIONS Figure 6-24. Port Mode Register Format PM0 PM1 PM2 1 PM06 PM03 PM02 PM01 1 76 54 3 21 0 Symbol PM3 PM5 FF20H FF21H FF22H FF23H FF25H FFH FFH FFH FFH FFH R/W R/W R/W R/W R/W Address After Reset R/W PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM57[...]

160 CHAPTER 6 PORT FUNCTIONS (2) Pull-up resistor option register (PUOH, PUOL) This register is used to set whether to use an internal pull-up resistor at each port or not. A pull-up resistor is internally used at bits which are set to the input mode at a port where on-chip pull-up resistor use has been specified with PUOH, PUOL. No on-chip pull-up[...]

161 CHAPTER 6 PORT FUNCTIONS (3) Memory expansion mode register (MM) This register is used to set input/output of port 4. MM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 10H. Figure 6-26. Memory Expansion Mode Register Format Notes 1. These pins can be used only in the separate bus mode. They enter[...]

162 CHAPTER 6 PORT FUNCTIONS (4) Key return mode register (KRM) This register sets enabling/disabling of standby function release by a key return signal (falling edge detection of port 4). KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H. Figure 6-27. Key Return Mode Register Format Caution When falling [...]

163 CHAPTER 6 PORT FUNCTIONS 6.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 6.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the[...]

164 CHAPTER 6 PORT FUNCTIONS 6.5 Selection of Mask Option The following mask option is provided in mask ROM version. The µ PD78P078 and 78P078Y have no mask option. Table 6-7. Comparison between Mask ROM Version and the µ PD78P078 and 78P078Y Pin Name Mask ROM Version µ PD78P078 and 78P078Y Mask option for pins P60 to P63 and Bitwise-selectable [...]

165 CHAPTER 7 CLOCK GENERATOR 7.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 1 to 5.0 MHz. Oscillation can be stopped by executing the[...]

166 CHAPTER 7 CLOCK GENERATOR Subsystem Clock Oscillator Main System Clock Oscillator X2 X1 XT2 XT1/P07 FRC STOP MCC FRC CLS CSS PCC2 PCC1 Internal Bus Standby Control Circuit To INTP0 Sampling Clock 2 f XX 2 2 f XX 2 3 f XX 2 4 f XX Prescaler Clock to Peripheral Hardware Prescaler Oscillation Mode Selection Register Watch Timer, Clock Output Funct[...]

167 CHAPTER 7 CLOCK GENERATOR 7.3 Clock Generator Control Register The clock generator is controlled by the following two registers: • Processor clock control register (PCC) • Oscillation mode selection register (OSMS) (1) Processor clock control register (PCC) The PCC selects a CPU clock and the division ratio, determines whether to make the m[...]

168 CHAPTER 7 CLOCK GENERATOR MCC FRC CLS CSS PCC2 PCC1 PCC0 PCC CLS 0 1 Main system clock Subsystem clock FFFBH 04H <7> <6> <5> <4> Symbol Address After Reset R/W R/W Note 1 0 32 0 1 CSS 0 0f XX /2 PCC2 CPU CIock (f CPU ) Selection PCC1 PCC0 CPU Clock Status 0 0 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 f XX /2 2 [...]

169 CHAPTER 7 CLOCK GENERATOR The fastest instruction of the µ PD78078 and 78078Y Subseries can be executed in two clocks of the CPU clock. The relationship between the CPU clock (f CPU ) and the minimum instruction execution time is shown in Table 7-2. Table 7-2. Relationship between CPU Clock and Minimum Instruction Execution Time CPU Clock (f C[...]

170 CHAPTER 7 CLOCK GENERATOR (2) Oscillation mode selection register (OSMS) This register specifies whether the clock output from the main system clock oscillator without passing through the scaler is used as the main system clock, or the clock output via the scaler is used as the main system clock. OSMS is set with 8-bit memory manipulation instr[...]

171 CHAPTER 7 CLOCK GENERATOR 7.4 System Clock Oscillator 7.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 p[...]

172 CHAPTER 7 CLOCK GENERATOR 7.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to the subsystem clock oscillator. In this case, input a clock signal to the XT1 pin and an antiphase clock signal to the XT2 pin. Fi[...]

173 CHAPTER 7 CLOCK GENERATOR Figure 7-8. Examples of Oscillator with Bad Connection (2/2) (c) Changing high current is too near a (d) Current flows through the grounding line signal conductor of the oscillator (potential at points A, B, and C fluctuate) (e) Signals are fetched (f) Signal conductors of the main and sub- system clock are parallel an[...]

174 CHAPTER 7 CLOCK GENERATOR 7.4.3 Divider The divider generates various clocks by dividing the main system clock oscillator output (f XX ). 7.4.4 When no subsystem clocks are used If it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the XT1 and XT2 pins as follows. XT1 : Connect to V DD[...]

175 CHAPTER 7 CLOCK GENERATOR 7.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. • Main system clock f XX • Subsystem clock f XT • CPU clock f CPU • Clock to peripheral hardware The following clock generator functions and operatio[...]

176 CHAPTER 7 CLOCK GENERATOR 7.5.1 Main system clock operations When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the following operations are carried out by PCC setting. (a) Because the operation guarantee instruction execution speed depends on the power supply voltage, the minimum[...]

177 CHAPTER 7 CLOCK GENERATOR Figure 7-9. Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC with main system clock operation 7.5.2 Subsystem clock operations When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1), the following operations are carried out. [...]

178 CHAPTER 7 CLOCK GENERATOR 7.6 Changing System Clock and CPU Clock Settings 7.6.1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by means of bit 0 to bit 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC). The actual switchover operation is not perfo[...]

179 CHAPTER 7 CLOCK GENERATOR 7.6.2 System clock and CPU clock switching procedure This section describes switching procedure between system clock and CPU clock. Figure 7-10. System Clock and CPU Clock Switching (1) The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released by setting the RESET sign[...]

180 [MEMO][...]

181 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.1 Outline of Timers Incorporated into µ PD78078, 78078Y Subseries This chapter explains the 16-bit timer/event counter. First of all, the timers incorporated into the µ PD78078, 78078Y Subseries and the related circuits are outlined below. (1) 16-bit timer/event counter (TM0) The TM0 can be used for an i[...]

182 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-1. Timer/Event Counter Operations Operation Interval timer 2 channels Note 3 2 channels 2 channels 1 channel Note 1 1 channel Note 2 mode External event counter √√√ —— Function Timer output √√√ —— PWM output √ — √ —— Pulse width measurement √ ———— Square-wave o[...]

183 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.2 16-Bit Timer/Event Counter Functions The 16-bit timer/event counter (TM0) has the following functions. • Interval timer • PWM output • Pulse width measurement • External event counter • Square-wave output • One-shot pulse output TM0 can perform both PWM output and pulse width measurement at t[...]

184 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (5) Square-wave output TM0 can output a square wave with any selected frequency. Table 8-3. 16-Bit Timer/Event Counter Square-Wave Output Ranges Minimum Pulse Width Maximum Pulse Width Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 2 x TI00 input cycle 2 16 x TI00 input cycle TI00 input edge cycl[...]

185 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.3 16-Bit Timer/Event Counter Configuration The 16-bit timer/event counter consists of the following hardware. Table 8-4. 16-Bit Timer/Event Counter Configuration Item Configuration Timer register 16 bits x 1 (TM0) Register Capture/compare register: 16 bits x 2 (CR00, CR01) Timer output 1 (TO0) Timer clock [...]

186 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-1. 16-Bit Timer/Event Counter Block Diagram Notes 1. Edge detection circuit 2. The configuration of the 16-bit timer/event counter output control circuit is shown in Figure 8-2. Internal bus Capture/Compare Control Register 0 CRC02 CRC01 CRC00 Selector TI01 / P01 / INTP1 INTTM3 2f XX f XX f XX /2 f [...]

187 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-2. 16-Bit Timer/Event Counter Output Control Circuit Block Diagram Remark The circuitry enclosed by the dotted line is the output control circuit. PWM Pulse Output Control Circuit Edge Detection Circuit 2 ES11 ES10 TI00 / P00 / INTP0 External Interrupt Mode Register 0 OSPT 16-Bit Timer Output Contro[...]

188 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (1) Capture/compare register 00 (CR00) CR00 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC00) of capture/compare control register 0 (CRC0). When CR00 is used as a compare re[...]

189 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) 16-bit timer register (TM0) TM0 is a 16-bit register which counts the count pulses. TM0 is read by a 16-bit memory manipulation instruction. When TM0 is read, capture/compare register (CR01) should first be set as a capture register. RESET input sets TM0 to 0000H. Caution As the value of TM0 is read via [...]

190 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.4 16-Bit Timer/Event Counter Control Registers The following seven types of registers are used to control the 16-bit timer/event counter. • Timer clock select register 0 (TCL0) • 16-bit timer mode control register (TMC0) • Capture/compare control register 0 (CRC0) • 16-bit timer output control regi[...]

191 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-3. Timer Clock Selection Register 0 Format Cautions 1. External interrupt mode register 0 (INTM0) sets the TI00/INTP0 pin valid edge, and the sampling clock selection register (SCS) selects the sampling clock. 2. When enabling PCL output, set TCL00 to TCL03, then set 1 in CLOE with a 1-bit memory ma[...]

192 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. f XT : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6. MCS : Bit 0 of oscillation mode selection register (OSMS) 7. Figures [...]

193 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Cautions 1. Switch the clear mode and the T00 output timing after stopping the timer operation (by setting TMC01 to TMC03 to 0, 0, 0). 2. Set the valid edge of the TI00/INTP0 pin with an external interrupt mode register 0 (INTM0) and select the sampling clock frequency with a sampling clock select register ([...]

194 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) 16-bit timer output control register (TOC0) This register controls the operation of the 16-bit timer/event counter output control circuit. It sets R-S type flip-flop (LV0) setting/resetting, the active level in PWM mode, inversion enabling/disabling in modes other than PWM mode, 16-bit timer/event counte[...]

195 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (5) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P30/TO0 pin for timer output, set PM30 and output latch of P30 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 value to FFH. Figure 8-7. Port Mode Register 3 Forma[...]

196 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (6) External interrupt mode register 0 (INTM0) This register is used to set INTP0 to INTP2 valid edges. INTM0 is set with an 8-bit memory manipulation instruction. RESET input sets INTM0 value to 00H. Figure 8-8. External Interrupt Mode Register 0 Format Caution Set 0, 0, 0 to bits 1 through 3 (TMC01 through[...]

197 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (7) Sampling clock select registers (SCS) This register sets clocks which undergo clock sampling of valid edges to be input to INTP0. When remote controlled reception is carried out using INTP0, digital noise is removed with sampling clock. SCS is set with an 8-bit memory manipulation instruction. RESET inpu[...]

198 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5 16-Bit Timer/Event Counter Operations 8.5.1 Interval timer operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-10 allows operation as an interval timer. Interrupt requests are generated repeatedly using the count value set in[...]

199 CHAPTER 8 16-BIT TIMER/EVENT COUNTER t Count Clock TM0 Count Value CR00 INTTM00 TO0 Interval Time Interval Time Interval Time 0000 0001 N 0000 0001 N 0000 0001 N Count Start Clear Clear NN N N Interrupt Request Acknowledge Interrupt Request Acknowledge Figure 8-11. Interval Timer Configuration Diagram Figure 8-12. Interval Timer Operation Timin[...]

200 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-6. 16-Bit Timer/Event Counter Interval Times Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 0 0 0 2 x TI00 input cycle 2 16 x TI00 input cycle TI00 input edge cycle 0 0 1 Setting 2 x 1/f X Setting 2 16 x 1/f X Setting 1/f X prohibited (400 ns) p[...]

201 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-13. Control Register Settings for PWM Output Operation (a) 16-bit timer mode control register (TMC0) (b) Capture/compare control register 0 (CRC0) (c) 16-bit timer output control register (TOC0) Remark 0/1 : Setting 0 or 1 allows another function to be used simultaneously with PWM output. See the de[...]

202 CHAPTER 8 16-BIT TIMER/EVENT COUNTER By integrating 14-bit resolution PWM pulses with an external low-pass filter, they can be converted to an analog voltage and used for electronic tuning and D/A converter applications, etc. The analog output voltage (V AN ) used for D/A conversion with the configuration shown in Figure 8-14 is as follows. V A[...]

203 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.3 PPG output operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-16 allows operation as PPG (Programmable Pulse Generator) output. In the PPG output operation, square waves are output from the TO0/P30 pin with the pulse width[...]

204 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.4 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00/P00 pin and TI01/P01 pin using the bit timer register (TM0). There are two measurement methods: measuring with TM0 used in free-running mode, and measuring by restarting the timer in synchroniz[...]

205 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-18. Configuration Diagram for Pulse Width Measurement by Free-Running Counter Figure 8-19. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) Count Clock TM0 Count Value TI00 Pin Input CR01 Captured Value INTP0 OVF0 0000 0001 D0 D[...]

206 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) Two pulse width measurements with free-running counter When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8- 20), it is possible to simultaneously measure the pulse widths of the two signals input to the TI00/P00 pin and the TI01/P01 pin. When the edge [...]

207 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-21. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) Count Clock TM0 Count Value TI00 Pin Input CR01 Captured Value INTP0 TI01 Pin Input t CR00 Captured Value INTP1 OVF0 (D1 – D0) x t (10000H – D1 + D2) x t (10000H – D1 + (D2 + 1)) x t (D3 – D[...]

208 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) Pulse width measurement with free-running counter and two capture registers When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-22), it is possible to measure the pulse width of the signal input to the TI00/P00 pin. When the edge specified by bits 2 an[...]

209 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-23. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count Clock TM0 Count Value TI00 Pin Input CR01 Captured Value CR00 Captured Value INTP0 OVF0 (D1 – D0) x t (10000H – D1 + D2) x t (D3 – D2) x t D1 D3 D0 D2 D3 D2 0000[...]

210 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Pulse width measurement by means of restart When input of a valid edge to the TI00/P00 pin is detected, the count value of the 16-bit timer register (TM0) is taken into 16-bit capture/compare register 01 (CR01), and then the pulse width of the signal input to the TI00/P00 pin is measured by clearing TM0 [...]

211 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.5 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI00/P00 pin with the 16-bit timer register (TM0). TM0 is incremented each time the valid edge specified with the external interrupt mode register 0 (INTM0) is input. When the TM0 c[...]

212 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-27. External Event Counter Configuration Diagram Figure 8-28. External Event Counter Operation Timings (with Rising Edge Specified) Caution When reading the external event counter count value, TM0 should be read. 16-Bit Capture/Compare Register 00 (CR00) Clear INTTM00 INTP0 16-Bit Timer Register (TM[...]

213 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.6 Square-wave output operation 16-bit timer/event counter operates as a square wave output with any selected frequency at intervals of the count value preset to the 16-bit capture/compare register 00 (CR00). The TO0/P30 pin output status is reversed at intervals of the count value preset to CR00 by setti[...]

214 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-30. Square-Wave Output Operation Timing Table 8-7. 16-Bit Timer/Event Count Square-Wave Output Ranges Minimum Pulse Width Maximum Pulse Width Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 2 x TI00 input cycle 2 16 x TI00 input cycle TI00 input edge cycle — 2 x 1/f X —2 16 x 1/f X—[...]

215 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.7 One-shot pulse output operation It is possible to output one-shot pulses synchronized with a software trigger or an external trigger (TI00/P00 pin input). (1) One-shot pulse output using software trigger If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and th[...]

216 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-32. Timing of One-Shot Pulse Output Operation Using Software Trigger Caution The 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation stop mode) is set to TMC01 to TMC03, respectively. Count Clock TM0 Count Value CR01 Set Value CR00 Set Value INTTM01 OSPT INTTM0[...]

217 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) One-shot pulse output using external trigger If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16- bit timer output control register (TOC0) are set as shown in Figure 8-33, a one-shot pulse is output from the TO0/P30 pin with a TI00/P00 valid edge as an [...]

218 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-34. Timing of One-Shot Pulse Output Operation Using External Trigger (With Rising Edge Specified) Caution The 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation stop mode) is set to TMC01 to TMC03, respectively. Count Clock TM0 Count Value CR01 Set Value CR00 [...]

219 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.6 16-Bit Timer/Event Counter Operating Precautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. This is because the 16-bit timer register (TM0) is started asynchronously with the count pulse. Figure [...]

220 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Capture register data retention timings If the valid edge of the TI00/P00 pin is input during 16-bit capture/compare register 01 (CR01) read, CR01 holds data without carrying out capture operation. However, the interrupt request flag (PIF0) is set upon detection of the valid edge. Figure 8-37. Capture Re[...]

221 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (7) Operation of OVF0 flag OFV0 flag is set to 1 in the following case. The clear & start mode on match between TM0 and CR00 is selected. ↓ CR00 is set to FFFFH. ↓ When TM0 is counted up from FFFFH to 0000H. Figure 8-38. Operation Timing of OVF0 Flag Count Pulse CR00 TM0 OVF0 INTTM00 FFFFH FFFEH FFFF[...]

222 [MEMO][...]

223 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.1 8-Bit Timer/Event Counters 1 and 2 Functions For the 8-bit timer/event counters 1 and 2, two modes are available. One is a mode for two-channel 8-bit timer/ event counters to be used separately (the 8-bit timer/event counter mode) and the other is a mode for the 8-bit timer/ event counter to be u[...]

224 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (1) 8-bit interval timer Interrupt requests are generated at the preset time intervals. Table 9-1. 8-Bit Timer/Event Counters 1 and 2 Interval Times Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 2 x 1/f X 2 2 x 1/f X 2 9 x 1/f X 2 10 x 1/f X 2 [...]

225 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 9-2. 8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges Minimum Pulse Width Maximum Pulse Width Resolution MCS[...]

226 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.1.2 16-bit timer/event counter mode (1) 16-bit interval timer Interrupt requests can be generated at the preset time intervals. Table 9-3. Interval Times when 8-Bit Timer/Event Counters 1 and 2 are Used as 16-Bit Timer/Event Counters Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MC[...]

227 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 9-4. Square-Wave Output Ranges when 8-Bit Timer/Event Counters 1 and 2 are Used as 16-Bit Timer/Event Counters Minimum P[...]

228 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.2 8-Bit Timer/Event Counters 1 and 2 Configurations The 8-bit timer/event counters 1 and 2 consist of the following hardware. Table 9-5. 8-Bit Timer/Event Counters 1 and 2 Configurations Item Configuration Timer register 8 bits x 2 (TM1, TM2) Register Compare register: 8 bits x 2 (CR10, CR20) Timer[...]

229 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-2. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1 Remark The section in the broken line is an output control circuit. Figure 9-3. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2 Remarks 1. The section in the broken line is an output control circuit. 2[...]

230 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (1) Compare registers 10 and 20 (CR10, CR20) These are 8-bit registers to compare the value set to CR10 to the 8-bit timer register 1 (TM1) count value, and the value set to CR20 to the 8-bit timer register 2 (TM2) count value, and, if they match, generate an interrupt request (INTTM1 and INTTM2, res[...]

231 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.3 8-Bit Timer/Event Counters 1 and 2 Control Registers The following four types of registers are used to control the 8-bit timer/event counter. • Timer clock select register 1 (TCL1) • 8-bit timer mode control register 1 (TMC1) • 8-bit timer output control register (TOC1) • Port mode regist[...]

232 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 TCL13 TCL12 TCL11 TCL10 0 0 0 0 TI1 falling edge 0 0 0 1 TI1 rising edge 01 10 01 11 f XX /2 f X /2 (2.5 MHz) f X /2 2 (1.25 MHz) 10 00 f XX /2 2 f X /2 2 (1.25 MHz) f X /2 3 (625 kHz) 10 01 f XX /2 3 f X /2 3 (625 kHz) f X /2 4 (313 kHz) 10 10 f XX /2 4 f X /2 4 (313 kHz) f X /2 5 (156 kHz) 10 11 f [...]

233 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) 8-bit timer mode control register 1 (TMC1) This register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8-bit timer register 2. TMC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC1 to 00H. Figure 9-5. 8-Bit Timer Mode Co[...]

234 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) 8-bit timer output control register (TOC1) This register controls operation of 8-bit timer/event counter output control circuits 1 and 2. It sets/resets the R-S flip-flops (LV1 and LV2) and enables/disables inversion and 8-bit timer output of 8- bit timer registers 1 and 2. TOC1 is set with a 1-b[...]

235 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (4) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P31/TO1 and P32/TO2 pins for timer output, set PM31, PM32, and output latches of P31 and P32 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH. Figure[...]

236 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.4 8-Bit Timer/Event Counters 1 and 2 Operations 9.4.1 8-bit timer/event counter mode (1) Interval timer operations The 8-bit timer/event counters 1 and 2 operate as interval timers which generate interrupt requests repeatedly at intervals of the count value preset to 8-bit compare registers 10 and [...]

237 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Table 9-6. 8-Bit Timer/Event Counter 1 Interval Time Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 0000 TI1 input cycle 2 8 x TI1 input cycle TI1 input edge cycle 0001 TI1 input cycle 2 8 x TI1 input cycle TI1 input edge cycle 2 x 1/f X 2 2 x 1[...]

238 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Table 9-7. 8-Bit Timer/Event Counter 2 Interval Time Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 0000 TI2 input cycle 2 8 x TI2 input cycle TI2 input edge cycle 0001 TI2 input cycle 2 8 x TI2 input cycle TI2 input edge cycle 2 x 1/f X 2 2 x 1[...]

239 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter operation The external event counter counts the number of external clock pulses to be input to the TI1/P33 and TI2/ P34 pins with 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 and TM2 are incremented each time the valid edge specified with the timer clock select register[...]

240 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) Square-wave output Operation 8-bit timer/event counters 1 and 2 operate as a square wave outputs with any selected frequency at intervals of the value preset to 8-bit compare registers 10 and 20 (CR10 and CR20). The TO1/P31 or TO2/P32 pin output status is reversed at intervals of the count value [...]

241 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-10. Timing of Square Wave Output Operation Note The initial value of the TO1 output can be set by bits 2 and 3 (LVS1 and LVR1) of the 8-bit timer output control register (TOC1). Count Clock TM1 Count Value 01 02 00 N–1 N 00 01 02 N–1 N 00 Count Start CR10 N N TO1 Note[...]

242 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Count Clock TMS (TM1, TM2) Count Value CR10, CR20 INTTM2 TO2 Interval Time Interval Time Interval Time Interrupt Request Acknowledge Interrupt Request Acknowledge NN N N Count Start Clear Clear 0000 0001 N 0000 0001 N 0000 0001 N t 9.4.2 16-bit timer/event counter mode When bit 2 (TMC12) of the 8-bit[...]

243 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Table 9-9. Interval Times when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 0000 TI1 input cycle 2 8 x TI1 input cycle TI1 input edge cycle 0001 TI1 inpu[...]

244 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter operations The external event counter counts the number of external clock pulses to be input to the TI1/P33 pin with 2-channel 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 and TM2 are incremented each time the valid edge specified with the timer clock select register 1 [...]

245 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) Square-wave output operation The 8-bit timer/event counters 1 and 2 operate as square wave outputs with any selected frequency at intervals of the value preset to 8-bit compare registers (CR10 and CR20). To set the count value, set the values of the higher 8 bits to CR20 and set the values of the[...]

246 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.5 8-Bit Timer/Event Counters 1 and 2 Precautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be gener- ated after timer start. This is because 8-bit timer registers 1 and 2 (TM1 and TM2) are started asynchronously with the[...]

247 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) Operation after compare register change during timer count operation If the values after the 8-bit compare registers 10 and 20 (CR10 and CR20) are changed are smaller than those of 8-bit timer registers (TM1 and TM2), TM1 and TM2 continue counting, overflow and then restart counting from 0. Thus,[...]

248 [MEMO][...]

249 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 10.1 8-Bit Timer/Event Counters 5 and 6 Functions The 8-bit timer event counters 5 and 6 (TM5, TM6) have the following functions. • Interval timer • External event counter • Square-wave output • PWM output[...]

250 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (1) 8-bit interval timer Interrupt requests are generated at the preset time intervals. Table 10-1. 8-Bit Timer/Event Counters 5 and 6 Interval Times Minimum Interval Width Maximum Interval Width Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 — 1/f X —2 8 x 1/f X — 1/f X (200 ns) ([...]

251 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 10-2. 8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges Minimum Pulse Width Maximum Pulse Width Resolution M[...]

252 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 10.2 8-Bit Timer/Event Counters 5 and 6 Configurations The 8-bit timer/event counters 5 and 6 consist of the following hardware. Table 10-3. 8-Bit Timer/Event Counters 5 and 6 Configurations Item Configuration Timer register 8 bits x 2 (TM5, TM6) Register Compare register: 8 bits x 2 (CR50, CR60) Ti[...]

253 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Figure 10-2. Block Diagram of 8-Bit Timer/Event Counters 5 and 6 Output Control Circuit Remarks 1. The section in the broken line is an output control circuit. 2. n = 5, 6 (1) Compare register 50 and 60 (CR50, 60) These 8-bit registers compare the value set to CR50 to 8-bit timer register 5 (TM5) co[...]

254 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 10.3 8-Bit Timer/Event Counters 5 and 6 Control Registers The following three types of registers are used to control the 8-bit timer/event counters 5 and 6. • Timer clock select register 5 and 6 (TCL5, TCL6) • 8-bit timer mode control registers 5 and 6 (TMC5, TMC6) • Port mode register 10 (PM1[...]

255 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (2) Timer clock select register 6 (TCL6) This register sets count clocks of 8-bit timer register 6. TCL6 is set with an 8-bit memory manipulation instruction. RESET input sets TCL6 to 00H. Figure 10-4. Timer Clock Select Register 6 Format Note When clock is input from the external, timer output (PWM[...]

256 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (3) 8-bit timer mode control register 5 (TMC5) This register enables/stops operation of 8-bit timer register 5, sets the operating mode of 8-bit timer register 5 and controls operation of 8-bit timer/event counter 5 output control circuit. It sets R-S flip-flop (timer output F/F 1,2) setting/resetti[...]

257 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (4) 8-bit timer mode control register 6 (TMC6) This register enables/stops operation of 8-bit timer register 6, sets the operating mode of 8-bit timer register 6 and controls operation of 8-bit timer/event counter 6 output control circuit. It sets R-S flip-flop (timer output F/F 1,2) setting/resetti[...]

258 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (5) Port mode register 10 (PM10) This register sets port 10 input/output in 1-bit units. When using the P100/TI5/TO5 and P101/TI6/TO6 pins for timer output, set PM100, PM101 and output latches of P100 and P101 to 0. PM10 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets [...]

259 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 10.4 8-Bit Timer/Event Counters 5 and 6 Operations 10.4.1 Interval timer operations Setting the 8-bit timer mode control registers (TMC5 and TMC6) as shown in Figure 10-8 allows operation as an interval timer. Interrupt requests are generated repeatedly using the count value preset in 8-bit compare [...]

260 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Table 10-4. 8-Bit Timer/Event Counters 5 and 6 Interval Times Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 0000 TIn input cycle 2 8 x TIn input cycle TIn input edge input cycle 0001 TIn input cycle 2 8 x TIn input cycle TIn input edge input c[...]

261 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 10.4.2 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI5/P100/TO5 and TI6/ P101/TO6 pins with 8-bit timer registers 5 and 6 (TM5 and TM6). TM5 and TM6 are incremented each time the valid edge specified with timer clock selec[...]

262 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 10.4.3 Square-wave output A square wave with any selected frequency is output at intervals of the value preset to 8-bit compare registers (CR50 and CR60). The TO5/P100/TI5 or TO6/P101/TI6 pin output status is reversed at intervals of the count value preset to CR50 or CR60 by setting bit 1 (TMC51) an[...]

263 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Table 10-5. 8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges Minimum Pulse Time Maximum Pulse Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 — 1/f X —2 8 x 1/f X — 1/f X (200 ns) (51.2 µ s) (200 ns) 1/f X 2 x 1/f X 2 8 x 1/f X 2 9 x 1/f X 1/f X 2 x 1/f X (200 ns) [...]

264 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 10.4.4 PWM output operations Setting the 8-bit timer mode control registers (TMC5 and TMC6) as shown in Figure 10-14 allows operation as PWM output. Pulses with the duty rate determined by the values preset in 8-bit compare registers (CR50 and CR60) output from the TO5/P100/TI5 or TO6/P101/TI6 pin. [...]

265 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Figure 10-15. PWM Output Operation Timing (Active High Setting) Remark n = 5, 6 Figure 10-16. PWM Output Operation Timings (CRn0 = 00H, Active High Setting) Remark n = 5, 6 Count Clock TMn Count Value CRn0 TCEn INTTMn TOn 01 02 FF 00 01 02 N N + 1 N + 2 N + 3 00 OVFn MN N 00 Inactive Level CRn0 Chan[...]

266 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Figure 10-17. PWM Output Operation Timings (CRn0 = FFH, Active High Setting) Remark n = 5, 6 Figure 10-18. PWM Output Operation Timings (CRn0 Changing, Active High Setting) Remark n = 5, 6 Caution If CRn0 is changed during TMn operation, the value changed is not reflected until TMn overflows. Count [...]

267 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 10.5 8-Bit Timer/Event Counters 5 and 6 Precautions (1) Timer start errors An error with a maximum of one clock might occur concerning the time required for a match signal to be generated after the timer starts. This is because 8-bit timer registers 5 and 6 are started asynchronously with the count [...]

268 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Count Pulse CR50, CR60 N X X – 1 FFH 00H 01H M 02H TM5, TM6 Count Value (3) Operation after compare register change during timer count operation If the values after the 8-bit compare registers (CR50 and CR60) are changed are smaller than those of 8- bit timer registers (TM5 and TM6), TM5 and TM6 c[...]

269 CHAPTER 11 WATCH TIMER 11.1 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. (1) Watch timer When the 32.768-kHz subsystem clock is used, a flag (WTIF) is set at 0.5-second or 0.25-second intervals. When the 4.19-MHz (standard[...]

270 CHAPTER 11 WATCH TIMER 11.2 Watch Timer Configuration The watch timer consists of the following hardware. Table 11-2. Watch Timer Configuration Item Configuration Counter 5 bits x 1 Timer clock select register 2 (TCL2) Watch timer mode control register (TMC2) Control register[...]

271 CHAPTER 11 WATCH TIMER 11.3 Watch Timer Control Registers The following two types of registers are used to control the watch timer. • Timer clock select register 2 (TCL2) • Watch timer mode control register (TMC2) (1) Timer clock select register 2 (TCL2) This register sets the watch timer count clock. TCL2 is set with an 8-bit memory manipu[...]

272 CHAPTER 11 WATCH TIMER Figure 11-2. Timer Clock Select Register 2 Format Caution When rewriting TCL2 to other data, stop the timer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. f XT : Subsystem clock oscillation frequency 4. x : Don’t care 5. MCS : Bit 0[...]

273 CHAPTER 11 WATCH TIMER (2) Watch timer mode control register (TMC2) This register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/disables prescaler and 5-bit counter operations. TMC2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC2 to 00H. Figure 11-3. Watch Ti[...]

274 CHAPTER 11 WATCH TIMER 11.4 Watch Timer Operations 11.4.1 Watch timer operation When the 32.768-kHz subsystem clock or 4.19-MHz main system clock is used, the timer operates as a watch timer with a 0.5-second or 0.25-second interval. The watch timer sets the test input flag (WTIF) to 1 at the constant time interval. The standby state (STOP mode[...]

275 CHAPTER 12 WATCHDOG TIMER 12.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM) (the watchdog timer and the interval timer cannot be used simultaneously). (1) Watchdog timer[...]

276 CHAPTER 12 WATCHDOG TIMER (2) Interval timer mode Interrupt requests are generated at the preset time intervals. Table 12-2. Interval Times Interval Time MCS = 1 MCS = 0 2 11 x 1/f XX 2 11 x 1/f X (410 µ s) 2 12 x 1/f X (819 µ s) 2 12 x 1/f XX 2 12 x 1/f X (819 µ s) 2 13 x 1/f X (1.64 ms) 2 13 x 1/f XX 2 13 x 1/f X (1.64 ms) 2 14 x 1/f X (3.[...]

277 CHAPTER 12 WATCHDOG TIMER Prescaler f XX 2 4 f XX 2 5 f XX 2 6 f XX 2 7 f XX 2 8 f XX 2 9 Selector Watchdog Timer Mode Register Internal Bus Internal Bus TCL22 TCL21 TCL20 f XX /2 3 f XX 2 11 Timer Clock Select Register 2 3 WDTM4 RUN WDTM3 8-Bit Counter TMMK4 RUN TMIF4 INTWDT Maskable Interrupt Request RESET INTWDT Non-Maskable Interrupt Reques[...]

278 CHAPTER 12 WATCHDOG TIMER 12.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock. TCL2 is set with 8-bit memory ma[...]

279 CHAPTER 12 WATCHDOG TIMER Figure 12-2. Timer Clock Select Register 2 Format Caution When rewriting TCL2 to other data, stop the timer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. f XT : Subsystem clock oscillation frequency 4. x : Don’t care 5. MCS : Bi[...]

280 CHAPTER 12 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 12-3. Watchdog Timer Mode Register Format Notes 1. Once set to 1, WDTM3 and WDTM4 cannot be [...]

281 CHAPTER 12 WATCHDOG TIMER 12.4 Watchdog Timer Operations 12.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any runaway. The watchdog timer count clock (runaway detection time interval) can be selected with bits 0 to 2 (TCL20 to TCL22) of the timer [...]

282 CHAPTER 12 WATCHDOG TIMER 12.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0, respectively. The count clock (interval time) can be selected with bits 0 to [...]

283 CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT 13.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI. Clocks selected with the timer clock select register 0 (TCL0) are output from the PCL/P35 pin. Follow the procedu[...]

284 CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT 13.2 Clock Output Control Circuit Configuration The clock output control circuit consists of the following hardware. Table 13-1. Clock Output Control Circuit Configuration Item Configuration Timer clock select register 0 (TCL0) Port mode register 3 (PM3) Figure 13-2. Clock Output Control Circuit Block Dia[...]

285 CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT 13.3 Clock Output Function Control Registers The following two types of registers are used to control the clock output function. • Timer clock select register 0 (TCL0) • Port mode register 3 (PM3) (1) Timer clock select register 0 (TCL0) This register sets PCL output clock. TCL0 is set with a 1-bit or[...]

286 CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT Figure 13-3. Timer Clock Select Register 0 Format Cautions 1. The TI00/P00/INTP0 pin valid edge is set by external interrupt mode register 0 (INTM0), and the sampling clock frequency is selected by the sampling clock selection register (SCS). 2. When enabling PCL output, set TCL00 to TCL03, then set 1 in [...]

287 CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. f XT : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6. MCS : Bit 0 of oscillation mode selection register (OSMS) 7. Figur[...]

288 [MEMO][...]

289 CHAPTER 14 BUZZER OUTPUT CONTROL CIRCUIT 14.1 Buzzer Output Control Circuit Functions The buzzer output control circuit outputs 1.2-kHz, 2.4-kHz, 4.9-kHz, or 9.8-kHz frequency square waves. The buzzer frequency selected with timer clock select register 2 (TCL2) is output from the BUZ/P36 pin. Follow the procedure below to output the buzzer freq[...]

290 CHAPTER 14 BUZZER OUTPUT CONTROL CIRCUIT 14.3 Buzzer Output Function Control Registers The following two types of registers are used to control the buzzer output function. • Timer clock select register 2 (TCL2) • Port mode register 3 (PM3) (1) Timer clock select register 2 (TCL2) This register sets the buzzer output frequency. TCL2 is set w[...]

291 CHAPTER 14 BUZZER OUTPUT CONTROL CIRCUIT Figure 14-2. Timer Clock Select Register 2 Format Caution When rewriting TCL2 to other data, stop the timer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. f XT : Subsystem clock oscillation frequency 4. x : Don’t c[...]

292 CHAPTER 14 BUZZER OUTPUT CONTROL CIRCUIT (2) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P36/BUZ pin for buzzer output function, set PM36 and output latch of P36 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH. Figure 14-3. Port Mode Registe[...]

293 CHAPTER 15 A/D CONVERTER 15.1 A/D Converter Functions The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/ D conversion result register (ADCR). The following [...]

294 CHAPTER 15 A/D CONVERTER ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Selector A /D Converter Mode Register Selector Trigger Enable ES40, ES41 Note 3 Sample & Hold Circuit 3 CS Internal Bus Edge Detector Control Circuit Series Resistor String AV DD Voltage Comparator Tap Selector INTAD INTP3 Successive Approximati[...]

295 CHAPTER 15 A/D CONVERTER (1) Successive approximation register (SAR) This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (MSB). When the result of comparison is held to the least significant bit (LSB) (terminat[...]

296 CHAPTER 15 A/D CONVERTER Caution A series resistor string of approximately 10 k Ω is connected between AV REF0 pin and AV SS pin. Therefore, if the output impedance of the reference voltage source is high, AV REF0 pin is connected in parallel with the series resistor string between AV REF0 pin and AV SS pin. As a result, the reference voltage[...]

297 CHAPTER 15 A/D CONVERTER Figure 15-2. A/D Converter Mode Register Format Notes 1. Set so that the A/D conversion time is 19.1 µ s or more. 2. Setting prohibited because A/D conversion time is less than 19.1 µ s. Cautions 1. The following sequence is recommended for power consumption reduction of A/D converter when the standby function is used[...]

298 CHAPTER 15 A/D CONVERTER (2) A/D converter input select register (ADIS) This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels or ports. Pins other than those selected as analog input can be used as input/output ports. ADIS is set with an 8-bit memory manipulation instruction. RESET input sets AD[...]

299 CHAPTER 15 A/D CONVERTER (3) External interrupt mode register 1 (INTM1) This register sets the valid edge for INTP3 to INTP6. INTM1 is set with an 8-bit memory manipulation instruction. RESET input sets INTM1 to 00H. Figure 15-4. External Interrupt Mode Register 1 Format ES71 7 ES70 6 ES61 ES60 4 ES51 3210 FFEDH Address INTM1 Symbol ES50 ES41 E[...]

300 CHAPTER 15 A/D CONVERTER 15.4 A/D Converter Operations 15.4.1 Basic operations of A/D converter (1) Set the number of analog input channels with A/D converter input select register (ADIS). (2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D converter mode register (ADM). (3) Sample the voltage [...]

301 CHAPTER 15 A/D CONVERTER Figure 15-5. A/D Converter Basic Operation A/D conversion operations are performed continuously until bit 7 (CS) of ADM is reset (0) by software. If a write to ADM is performed during an A/D conversion operation, the conversion operation is initialized, and if the CS bit is set (1), conversion starts again from the begi[...]

302 CHAPTER 15 A/D CONVERTER 15.4.2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (the value stored in ADCR) is shown by the following expression. ADCR = INT ( x 256 + 0.5) or (ADCR – 0.5) x ≤ V IN < (ADCR + 0.5) x Where, INT( ) :[...]

303 CHAPTER 15 A/D CONVERTER 15.4.3 A/D converter operating mode One analog input channel is selected from among ANI0 to ANI7 with the A/D converter input select register (ADIS) and A/D converter mode register (ADM) and A/D conversion is executed. The following two ways are available to start A/D conversion. • Hardware start: Conversion is starte[...]

304 CHAPTER 15 A/D CONVERTER (2) A/D conversion operation in software start When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 0 and 1, respectively, the A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to ADM3) of ADM. Upon termination of the A/D conversion, the con[...]

305 CHAPTER 15 A/D CONVERTER 15.5 A/D Converter Cautions (1) Current consumption in standby mode The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode or in HALT mode with the subsystem clock. As a current still flows in the AV REF0 pin at this time, this current must be cut in order to minimize the overal[...]

306 CHAPTER 15 A/D CONVERTER (2) Input range of ANI0 to ANI7 The input voltages of ANI0 to ANI7 should be within the specification range. In particular, if a voltage above AV REF0 or below AV SS is input (even if within the absolute maximum rating range), the conversion value for that channel will be indeterminate. The conversion values of the othe[...]

307 CHAPTER 15 A/D CONVERTER (5) AV REF0 pin input impedance A series resistor string of approximately 10 k Ω is connected between the AV REF0 pin and the AV SS pin. Therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the series resistor string between the AV REF0 pin and the AV S[...]

308 [MEMO][...]

309 CHAPTER 16 D/A CONVERTER 16.1 D/A Converter Functions The D/A converter converts a digital input into an analog value. It consists of two 8-bit resolution channels of voltage output type D/A converter. The conversion method used is the R-2R resistor ladder method. Start the A/D conversion by setting the DACE0 and DACE1 of the D/A converter mode[...]

310 CHAPTER 16 D/A CONVERTER 16.2 D/A Converter Configuration The D/A converter consists of the following hardware. Table 16-1. D/A Converter Configuration Item Configuration D/A conversion value set register 0 (DACS0) D/A conversion value set register 1 (DACS1) Control register D/A converter mode register (DAM) Figure 16-1. D/A Converter Block Dia[...]

311 CHAPTER 16 D/A CONVERTER (1) D/A conversion value set register 0, 1 (DACS0, DACS1) DACS0 and DACS1 are registers that set the value used to determine analog voltage values output to the ANO0 and ANO1 pins, re-spectively. DACS0 and DACS1 are set with 8-bit memory manipulation instructions. RESET input sets these registers to 00H. Analog voltage [...]

312 CHAPTER 16 D/A CONVERTER 16.3 D/A Converter Control Registers The D/A converter mode register (DAM) controls the D/A converter. This register sets D/A converter operation enable/stop. The DAM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 16-2. D/A Converter Mode Register Format Cauti[...]

313 CHAPTER 16 D/A CONVERTER 16.4 D/A Converter Operations (1) Select the channel 0 operating mode and channel 1 operating mode with DAM4 and DAM5, respectively, of the D/A converter mode register (DAM). (2) Set the data corresponding to the analog voltages output to the ANO0/P130 and ANO1/P131 pins to the D/A conversion value setting registers 0 a[...]

314 CHAPTER 16 D/A CONVERTER 16.5 D/A Converter Cautions (1) Output impedance of D/A converter Because the output impedance of the D/A converter is high, use of current flowing from the ANOn pins (n = 0,1) is prohibited. If the input impedance of the load for the converter is low, insert a buffer amplifier between the load and the ANOn pins. In add[...]

315 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) The µ PD78078 Subseries incorporates three channels of serial interfaces. Differences between channels 0, 1, and 2 are as follows (Refer to CHAPTER 19 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1. Refer to CHAPTER 20 SERIAL INTERFACE CHANNEL 2 for details[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 316 17.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes. • Operation stop mode • 3-wire serial I/O mode • SBI (serial bus interface) mode • 2-wire serial I/O mode Caution Do not change the operation mode (3-wire serial I/O/2-wire [...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 317 Master CPU SCK0 SB0 SCK0 SB0 Slave CPU1 SCK0 SB0 Slave CPU2 SCK0 SB0 Slave CPUn V DD0 (4) 2-wire serial I/O mode (MSB-first) This mode is used for 8-bit data transfer using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1). This mode enables to cope with any one of th[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 318 17.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 17-2. Serial Interface Channel 0 Configuration Item Configuration Serial I/O shift register 0 (SIO0) Slave address register (SVA) Timer clock select register 3 (TCL3) Se[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 319 (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction. When bit 7 (C[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 320 (3) SO0 latch This latch holds SI0/SB0/P25 and SO0/SB1/P26 pin levels. It can be directly controlled by software. In the SBI mode, this latch is set upon termination of the 8th serial clock. (4) Serial clock counter This counter counts the serial clocks to be output and input during [...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 321 17.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) • Serial bus interface control register (SBIC) • Interrupt[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 322 Figure 17-3. Timer Clock Select Register 3 Format Caution When rewriting TCL3 to other data, stop the serial transfer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. MCS : Bit 0 of oscillation mod[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 323 (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET [...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 324 SBI mode < 6 > < 5 > 43210 <7> Symbol CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 CSIM01 0 1 Serial Interface Channel 0 Clock Selection Input Clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output 0 0 SCK0 (CMOS input/output) R/W 1 Clock spec[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 325 (3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Figure 17-5. Serial Bus Interface Control Register Format (1/2) N[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 326 Figure 17-5. Serial Bus Interface Control Register Format (2/2) Note The busy mode can be cancelled with start of serial interface transfer. However, the BSYE flag is not cleared to 0. Remark CSIE0 : Bit 7 of serial operating mode register 0 (CSIM0) ACKE Acknowledge Signal Output Con[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 327 (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/P27 pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Figure 17-6. Interrupt Tim[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 328 17.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • SBI mode • 2-wire serial I/O mode 17.4.1 Operation stop mode Serial transfer is not carried out in t[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 329 < 6 > < 5 > 43210 <7> Symbol CSIM0 CSIM01 0 1 Serial Interface Channel 0 Clock Selection Input Clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output 0 SBI mode (See 17.4.3 SBI mode operation .) R/W 1 Clock specified with bits 0 to 3 of timer clock sele[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 330 (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Remark CSIE0 : Bit 7 of serial operating mode register 0 (CSIM0) <6> <5> <4> <3> <2> <1> <0> <[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 331 (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out at th[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 332 (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start at MSB or LSB. Figure 17-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form. MS[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 333 17.4.3 SBI mode operation SBI (Serial Bus Interface) is a high-speed serial interface in compliance with the NEC serial bus format. SBI uses a single-master device and employs the clocked serial I/O format with the addition of a bus configuration function. This function enables devic[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 334 (1) SBI functions In the conventional serial I/O format, when a serial bus is configured by connecting two or more devices, many ports and wiring are necessary, to provide chip select signal to identify command and data, and to judge the busy state, because only the data transfer fun[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 335 SCK0 SB0 (SB1) SCK0 SB0 (SB1) SCK0 SB0 (SB1) 89 9 A7 A0 ACK BUSY C7 C0 ACK BUSY READY 89 D7 D0 ACK BUSY READY Address Transfer Command Transfer Data Transfer Bus Release Signal Command Signal Address Data Command (2) SBI definition The SBI serial data format and the signals to be use[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 336 SCK0 “H” SB0 (SB1) (a) Bus release signal (REL) The bus release signal is a signal with the SB0 (SB1) line which has changed from the low level to the high level when the SCK0 line is at the high level (without serial clock output). This signal is output by the master device. Fig[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 337 (c) Address An address is 8-bit data which the master device outputs to the slave device connected to the bus line in order to select a particular slave device. Figure 17-14. Addresses 8-bit data following bus release and command signals is defined as an “address”. In the slave d[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 338 (d) Command and data The master device transmits commands to, and transmits/receives data to/from the slave device selected by address transmission. Figure 17-16. Commands Figure 17-17. Data 8-bit data following a command signal is defined as “command” data. 8-bit data without co[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 339 (e) Acknowledge signal (ACK) The acknowledge signal is used to check serial data reception between transmitter and receiver. Figure 17-18. Acknowledge Signal [When output in synchronization with 11th clock SCK0] [When output in synchronization with 9th clock SCK0] Remark The brokens [...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 340 (3) Register setting The SBI mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC) and the interrupt timing specify register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipu[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 341 (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Note Bits 2, 3, and 6 (RELD, CMDD, and ACKD) are read-only bits. Remarks 1. Bits 0, 1, and 4 (RELT, CMDT, and ACKT) are 0 when read after [...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 342 R ACKD Acknowledge Detection Clear Conditions (ACKD = 0) • SCK0 fall immediately after the busy mode is released during the transfer start instruction execution. • When CSIE0 = 0 • When RESET input is applied Set Conditions (ACKD = 1) • When acknowledge signal (ACK) is detect[...]

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 343 (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Notes 1. Bit 6 (CLD) is a read-only bit. 2. When using wake-up function in the SBI mode, set SIC to 0. 3. When CSIE0 = 0, CLD becomes 0. Cauti[...]

344 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) (4) Various signals Figures 17-20 to 17-25 show various signals and flag operations in the serial bus interface control register (SBIC). Table 17-3 lists various signals in SBI. Figure 17-20. RELT, CMDT, RELD, and CMDD Operations (Master) Figure 17-21. RELD and CMDD Operations (Slave[...]

345 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) Figure 17-22. ACKT Operation Caution Do not set ACKT before termination of transfer. SCK0 6 SB0 (SB1) ACKT 7 8 9 D2 D1 D0 ACK When set during this period ACK signal is output for a period of one clock just after setting[...]

346 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) Figure 17-23. ACKE Operations (a) When ACKE = 1 upon completion of transfer (b) When set after completion of transfer (c) When ACKE = 0 upon completion of transfer (d) When “ACKE = 1” period is short SB0 (SB1) ACKE 1 2 789 D7 D6 D2 D1 D0 ACK When ACKE = 1 at this point ACK signal[...]

347 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) Figure 17-24. ACKD Operations (a) When ACK signal is output at 9th clock of SCK0 (b) When ACK signal is output after 9th clock of SCK0 (c) Clear timing when transfer start is instructed in BUSY Figure 17-25. BSYE Operation SCK0 SB0 (SB1) ACKD 789 D1 D0 ACK 6 D2 Transfer Start Instruc[...]

348 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) Table 17-3. Various Signals in SBI Mode (1/2) Timing Chart Definition Signal Name Output Device Output Condition Effects on Flag Meaning of Signal CMD signal is output to indicate that transmit data is an address. i) Transmit data is an address after REL signal output. ii) REL signal[...]

349 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) Timing Chart Definition Signal Name Output Device Output Condition Effects on Flag Meaning of Signal Synchronous clock to output address/command/data, ACK signal, synchronous BUSY signal, etc. Address/ command/data are transferred with the first eight synchronous clocks. 8-bit data t[...]

350 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) (5) Pin configuration The serial clock pin SCK0 and serial data bus pin SB0 (SB1) have the following configurations. (a) SCK0 ............ Serial clock input/output pin <1> Master .. . CMOS and push-pull output <2> Slave ..... Schmitt input (b) SB0 (SB1) .... Serial data [...]

351 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) (6) Address match detection method In the SBI mode, a particular slave device can be selected by transmitting slave address from the master device. Address match detection can be automatically executed by hardware. With slave address register, CSIIF0 is set only when the wake-up func[...]

352 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 1 2 3 4 5 6 7 8 9 SCK0 Pin A7 A6 A5 A4 A3 A2 A1 A0 ACK BUSY SB0 (SB1) Pin Program Processing Serial Transmission INTCSI0 Generation ACKD Set SCK0 Stop Hardware Operation WUP <- 0 ACKT Set Program Processing CMDD Set INTCSI0 Generation ACK Output Hardware Operation CMDT Set RELT Se[...]

353 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 1 2 3 4 5 6 7 8 9 SCK0 Pin C7 C6 C5 C4 C3 C2 C1 C0 ACK BUSY SB0 (SB1) Pin Program Processing Serial Transmission INTCSI0 Generation ACKD Set SCK0 Stop Hardware Operation ACKT Set Program Processing INTCSI0 Generation ACK Output Hardware Operation CMDT Set Write to SIO0 Interrupt Serv[...]

354 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 1 2 3 4 5 6 7 8 9 SCK0 Pin D7 D6 D5 D4 D3 D2 D1 D0 ACK BUSY SB0 (SB1) Pin Program Processing Serial Transmission INTCSI0 Generation ACKD Set SCK0 Stop Hardware Operation ACKT Set Program Processing INTCSI0 Generation ACK Output Hardware Operation Write to SIO0 Interrupt Servicing (Pr[...]

355 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 1 2 3 4 5 6 7 8 9 SCK0 Pin D7 D6 D5 D4 D3 D2 D1 D0 ACK BUSY SB0 (SB1) Pin Program Processing Serial Reception INTCSI0 Generation ACK Output Serial Reception Hardware Operation Program Processing INTCSI0 Generation ACKD Set Hardware Operation FFH Write to SIO0 Master Device Processing[...]

356 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) (9) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. • Serial interface channel 0 operation control bit (CSIE0) = 1 • Internal serial clock is stopped or SCK0 is at high l[...]

357 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) (d) For pins which are to be used for data input/output, be sure to carry out the following settings before serial transfer of the 1st byte after RESET input. <1> Set 1 to the output latch of P25 and P26 <2> Set 1 to bit 0 (RELT) of the serial bus interface control regist[...]

358 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) < 6 > < 5 > 43210 <7> Symbol CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 CSIM01 0 1 Serial Interface Channel 0 Clock Selection Input Clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output R/W 1 Clock specified with bits 0 to 3 of timer clock [...]

359 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Remark CSIE0 : Bit 7 of serial operating mode register 0 (CSIM0) <6> <5> <4> <3> <2> <1> <0> <[...]

360 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Notes 1. Bit 6 (CLD) is a read-only bit. 2. When CSIE0 = 0, CLD becomes 0. Caution Set bits 0 to 3 to 0. Remark CSIIF0 : Interrupt request fla[...]

361 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out in syn[...]

362 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. • Serial interface channel 0 operation control bit (CSIE0) = 1 • Internal serial clock is stopped or SCK0 is at high l[...]

363 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) To Internal Circuit SCK0/P27 P27 Output Latch When CSIE0 = 1 and CSIM01 and CSIM00 are 1 and 0, or 1 and 1. Set by bit manipulation instruction SCK0 (1 when transfer stops) From Serial Clock Control Circuit 17.4.5 SCK0/P27 pin output manipulation Because the SCK0/P27 pin incorporates[...]

364 [MEMO][...]

365 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) The µ PD78078Y Subseries incorporates three channels of serial interfaces. Differences between channels 0, 1, and 2 are as follows (Refer to CHAPTER 19 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1. Refer to CHAPTER 20 SERIAL INTERFACE CHANNEL 2 for detai[...]

366 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) 18.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode •I 2 C (Inter IC) bus mode Caution Do not change the operation mode (3-wire serial I/O/2-wire serial[...]

367 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (4) I 2 C (Inter IC) bus mode (MSB-first) This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCL) and serial data bus (SDA0 or SDA1). This mode is in compliance with the I 2 C bus format. In this mode, the transmitter outputs three ki[...]

368 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) 18.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 18-2. Serial Interface Channel 0 Configuration Item Configuration Serial I/O shift register 0 (SIO0) Slave address register (SVA) Timer clock select register 3 (TCL3) S[...]

369 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) Figure 18-2. Serial Interface Channel 0 Block Diagram Remark Output Control performs selection between CMOS output and N-ch open-drain output. CSIE0 COI WUP CSIM 04 CSIM 03 CSIM 02 CSIM 01 CSIM 00 Serial Operating Mode Register 0 Control Circuit Output Control Selector SI0/SB0/ SDA0[...]

370 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel-serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction. When bit 7 ([...]

371 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (6) Interrupt request signal generator This circuit controls interrupt request signal generation. It generates interrupt request signals according to the settings of interrupt timing specification register (SINT) bits 0 and 1 (WAT0, WAT1) and serial operation mode register 0 (CSIM0)[...]

372 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) 18.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) • Serial bus interface control register (SBIC) • Interrup[...]

373 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (1) Timer clock select register 3 (TCL3) This register sets the serial clock of serial interface channel 0. TCL3 is set with an 8-bit memory manipulation instruction. RESET input sets TCL3 to 88H. Figure 18-3. Timer Clock Select Register 3 Format Caution When rewriting TCL3 to other[...]

374 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET[...]

375 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) Figure 18-4. Serial Operating Mode Register 0 Format Notes 1. Bit 6 (COI) is a read-only bit. 2. I 2 C bus mode, the clock frequency becomes 1/16 of that output from TO2. 3. Can be used as P25 (CMOS input/output) when used only for transmission. 4. Can be used freely as port functio[...]

376 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) <6> <5> <4> <3> <2> <1> <0> <7> Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT Used for stop condition signal output. When RELT = 1, SO0 Iatch is set to 1. After SO0 latch setting, automatically cleared to 0. Also cleared to [...]

377 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) Figure 18-5. Serial Bus Interface Control Register Format (2/2) Notes 1. Setting should be performed before transfer. 2. If 8-clock wait mode is selected, the acknowledge signal at reception time must be output using ACKT. 3. The busy mode can be canceled by start of serial interfac[...]

378 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/SCL pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Figure 18-6. Interrupt Ti[...]

379 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) Figure 18-6. Interrupt Timing Specify Register Format (2/2) Notes 1. When using wake-up function in the I 2 C mode, set SIC to 0. 2. When CSIE0 = 0, CLD becomes 0. Remark SVA : Slave address register CSIIF0 : Interrupt request flag corresponding to INTCSI0 CSIE0 : Bit 7 of serial op[...]

380 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) 18.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode •I 2 C (Inter IC) bus mode 18.4.1 Operation stop mode Serial transfer is not[...]

381 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) < 6 > < 5 > 43210 <7> Symbol CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 CSIM01 0 1 Serial Interface Channel 0 Clock Selection Input Clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output 0 2-wire serial I/O mode (See 18.4.3 2-wire serial I/[...]

382 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) <6> <5> <4> <3> <2> <1> <0> <7> Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT When RELT = 1, SO0 Iatch is set to 1. After SO0 Iatch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0. R/W FF61H 00H R/W Add[...]

383 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out at t[...]

384 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 18-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form.[...]

385 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) 18.4.3 2-wire serial I/O mode operation The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB1). Figure 18-10. Serial Bus Configuration Exampl[...]

386 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) < 6 > < 5 > 43210 <7> Symbol CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 CSIM01 0 1 Serial Interface Channel 0 Clock Selection Input Clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output R/W 1 Clock specified with bits 0 to 3 of timer clock[...]

387 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) <6> <5> <4> <3> <2> <1> <0> <7> Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT When RELT = 1, SO0 Iatch is set to 1. After SO0 Iatch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0. R/W FF61H 00H R/W Add[...]

388 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out in sy[...]

389 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (3) Other signals Figure 18-12 shows RELT and CMDT operations. Figure 18-12. RELT and CMDT Operations (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. • Serial interfac[...]

390 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) 18.4.4 I 2 C bus mode operation The I 2 C bus mode is provided for when communication operations are performed between a single master device and multiple slave devices. This mode configures a serial bus that includes only a single master device, and is based on the clocked serial I[...]

391 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (1) I 2 C bus mode functions In the I 2 C bus mode, the following functions are available. (a) Automatic identification of serial data Slave devices automatically detect and identifies start condition, data, and stop condition signals sent in series through the serial data bus. (b) [...]

392 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (a) Start condition When the SDA0 (SDA1) pin level is changed from high to low while the SCL pin is high, this transition is recognized as the start condition signal. This start condition signal, which is created using the SCL and SDA0 (or SDA1) pins, is output from the master devic[...]

393 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) “H” SCL SDA0 (SDA1) (d) Acknowledge signal (ACK) The acknowledge signal indicates that the transferred serial data has definitely been received. This signal is used between the sending side and receiving side devices for confirmation of correct data transfer. In principle, the r[...]

394 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (f) Wait signal (WAIT) The wait signal is output by a slave device to inform the master device that the slave device is in wait state due to preparing for transmitting or receiving data. During the wait state, the slave device continues to output the wait signal by keeping the SCL p[...]

395 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (3) Register setting The I 2 C bus mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specify register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set by a 1-bit or 8-bit memory [...]

396 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) <6> <5> <4> <3> <2> <1> <0> <7> Symbol SBIC BSYE ACKD ACKE FF61H 00H R/W Note1 Address After Reset R/W ACKT CMDD RELD CMDT RELT (b) Serial bus interface control register (SBIC) SBIC is set by a 1-bit or 8-bit memory manipulation instru[...]

397 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (c) Interrupt timing specification register (SINT) SINT is set by the 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. R/W WAT1 WAT0 Interrupt control by wait Note 2 0 0 Interrupt service request is generated on rise of 8th SCK0 clock cycle (clock output[...]

398 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (4) Various signals A list of signals in the I 2 C bus mode is given in Table 18-4. Table 18-4. Signals in I 2 C Bus Mode Signal name Description Start condition Definition : SDA0 (SDA1) falling edge when SCL is high ( Note 1 ) Function : Indicates that serial communication starts a[...]

399 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) V DD V DD SCL SDA0(SDA1) Master device Clock output (Clock input) Data output Data input Slave devices (Clock output) Clock input Data output Data input SCL SDA0(SDA1) (5) Pin configurations The configurations of the serial clock pin SCL and the serial data bus pins SDA0 (SDA1) are [...]

400 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (6) Address match detection method In the I 2 C mode, the master can select a specific slave device by sending slave address data. Address match detection is performed automatically by the slave device hardware. A slave device address has a slave register (SVA), and compares its con[...]

401 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) Figure 18-22. Example of Communication from Master to Slave (with 9-Clock Wait Selected for Both Master and Slave) (1/3) (a) Start condition - address L L L 1 A5 A4 A3 A2 A1 A0 W ACK A6 2 3 4 567 8 D7 D6 D5 D4 D3 12 34 5 9 L L L L L SIO0 <- address SIO0 <- data H L L L L L L L[...]

402 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) Figure 18-22. Example of Communication from Master to Slave (with 9-Clock Wait Selected for Both Master and Slave) (2/3) (b) Data L L L L 1 D5 D4 D3 D2 D1 D0 ACK D6 D7 2 3 4 567 8 D7 D6 D5 D4 D3 12 34 5 9 L L L L L L L SIO0 <- data SIO0 <- data H L L L L L L L H H H H SIO0 <[...]

403 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) Figure 18-22. Example of Communication from Master to Slave (with 9-Clock Wait Selected for Both Master and Slave) (3/3) (c) Stop condition Transfer line L L 1 D5 D4 D3 D2 D1 D0 ACK D6 D7 2 3 4 567 8 A6 A5 A4 A3 12 34 9 L L L L SIO0 <- data SIO0 <- address H L L L L H H H SIO0[...]

404 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) Figure 18-23. Example of Communication from Slave to Master (with 9-Clock Wait Selected for Both Master and Slave) (1/3) (a) Start condition - address L L L 1 A0 A1 A2 A3 A4 A5 A6 R ACK 2 3 4 567 8 D6 D7 D5 D4 D3 2 13 4 5 9 L L L SIO0 <- address SIO0 <- FFH H L L L L L L L H H[...]

405 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) Figure 18-23. Example of Communication from Slave to Master (with 9-Clock Wait Selected for Both Master and Slave) (2/3) (b) Data L L L L H H L 1 D1 D0 D2 D3 D4 D5 D6 D7 ACK 2 3 4 567 8 D6 D7 D5 D4 D3 2 13 4 5 9 L L L SIO0 <- FFH SIO0 <- FFH H L L L L L L L L L L H H SIO0 writ[...]

406 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) Figure 18-23. Example of Communication from Slave to Master (with 9-Clock Wait Selected for Both Master and Slave) (3/3) (c) Stop condition L L 1 D1 D0 D2 D3 D4 D5 D6 D7 NAK 2 3 4 567 8 A6 A5 A4 A3 12 34 9 L L SIO0 <- FFH Processing in master device Transfer line SIO0 <- addre[...]

407 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (9) Start of transfer A serial transfer is started by setting transfer data in the serial I/O shift register 0 (SIO0) if the following two conditions have been satisfied: • The serial interface channel 0 operation control bit (CSIE0) = 1. • After an 8-bit serial transfer, the in[...]

408 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) 18.4.5 Cautions on use of I 2 C bus mode (1) Start condition output (master) The SCL pin normally outputs a low-level signal when no serial clock is output. It is necessary to change the SCL pin to high in order to output a start condition signal. Set the bit 3 (CLC) of the interrup[...]

409 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (2) Slave wait release (slave transmission) The wait status of a slave is released by setting the WREL flag, which is bit 2 of the interrupt timing specify register (SINT), or by executing a serial I/O shift register 0 (SIO0) write instruction. If the slave sends data, the wait is i[...]

410 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (3) Slave wait release (slave reception) The wait status of a slave is released by setting the WREL flag, which is bit 2 of the interrupt timing specify register (SINT), or by executing a serial I/O shift register 0 (SIO0) write instruction. When a slave receives data, if the SCL li[...]

411 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) 18.4.6 Restrictions in I 2 C bus mode The following restrictions apply to the µ PD78078Y Subseries. • Restrictions when used as slave device in I 2 C bus mode Applicable models µ PD78076Y, 78078Y, 78P078Y, and IE-78078-R-EM Description When the wake-up function is executed (by s[...]

412 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) • Example of program releasing serial transfer status SET1 P2.5 ; <1> SET1 PM2.5 ; <2> SET1 PM2.7 ; <3> CLR1 CSIE0 ; <4> SET1 CSIE0 ; <5> SET1 RELT ; <6> CLR1 PM2.7 ; <7> CLR1 P2.5 ; <8> CLR1 PM2.5 ; <9> <1> Prevents the [...]

413 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) 18.4.7 SCK0/SCL/P27 pin output manipulation The SCK0/SCL/P27 pin enables static output by manipulating software in addition to normal serial clock output. The value of serial clocks can be set by software (SI0/SB0/SDA0 and SO0/SB1/SDA1 pins are controlled with the RELT and CMDT bits[...]

414 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (2) In I 2 C bus mode The SCK0/SCL/P27 pin output level is manipulated by the CLC bit of interrupt timing specify register (SINT). <1> Set serial operating mode register 0 (CSIM0) (SCL pin is set in the output mode and serial operation is enabled). Set 1 to the P27 output latc[...]

415 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 19.1 Serial Interface Channel 1 Functions Serial interface channel 1 employs the following three modes. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function (1) Operation stop mode This mode is used when serial transfer is not carried out to [...]

416 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 19.2 Serial Interface Channel 1 Configuration Serial interface channel 1 consists of the following hardware. Table 19-1. Serial Interface Channel 1 Configuration Item Configuration Register Serial I/O shift register 1 (SIO1) Automatic data transmit/receive address pointer (ADTP) Control register Timer clock[...]

417 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (1) Serial I/O shift register 1 (SIO1) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO1 is set with an 8-bit memory manipulation instruction. When value in bit 7 (CSIE1) of serial[...]

418 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 19.3 Serial Interface Channel 1 Control Registers The following four types of registers are used to control serial interface channel 1. • Timer clock select register 3 (TCL3) • Serial operating mode register 1 (CSIM1) • Automatic data transmit/receive control register (ADTC) • Automatic data transmi[...]

419 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Notes 1. If the external clock input has been selected with CSIM11 set to 0, set bit 1 (BUSY1) and bit 2 (STRB) of the automatic data transmit/receive control register (ADTC) to 0, 0. 2. Can be used freely as port function. 3. Can be used as P20 (CMOS input/output) when only transmitter is used (set bit 7 ([...]

420 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (3) Automatic data transmit/receive control register (ADTC) This register sets automatic receive enable/disable, the operating mode, strobe output enable/disable, busy input enable/disable, and error check enable/disable, and displays automatic transmit/receive execution and error detection. ADTC is set wit[...]

421 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (4) Automatic data transmit/receive interval specify register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H. Figure 19-5. Automatic Data Transmit/Receive Interval Sp[...]

422 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-5. Automatic Data Transmit/Receive Interval Specify Register Format (2/4) Note The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum which is calculated by the f[...]

423 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-5. Automatic Data Transmit/Receive Interval Specify Register Format (3/4) Notes 1. The interval is dependent only on CPU processing. 2. The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to A[...]

424 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Note The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum which is calculated by the following expressions is smaller than 2/f SCK , the minimum interval time is 2/f SCK [...]

425 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 19.4 Serial Interface Channel 1 Operations The following three operating modes are available to the serial interface channel 1. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function 19.4.1 Operation stop mode Serial transfer is not carried out[...]

426 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 19.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous serial interface such as the 75X/XL, 78K, and 17K Series. Communication is carried out with three lines of serial clock (SCK[...]

427 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 1 (SIO1) is carried out at the falling edge of the se[...]

428 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-7. Circuit of Switching in Transfer Bit Order Start bit switching is realized by switching the bit order write to SIO1. The SIO1 shift order remains unchanged. Thus, MSB-first and LSB-first must be switched before writing data to the shift register. (4) Transfer start Serial transfer is started by[...]

429 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 19.4.3 3-wire serial I/O mode operation with automatic transmit/receive function This 3-wire serial I/O mode is used for transmission/reception of a maximum of 32-byte data without the use of software. Once transfer is started, the data prestored in the RAM can be transmitted by the set number of bytes, and[...]

430 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (b) Automatic data transmit/receive control register (ADTC) ADTC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTC to 00H. <6> <5> <4> <3> <2> <1> <0> <7> Symbol ADTC RE ARLD ERCE ERR TRF STRB BUSY1 BUSY0 FF69H 00H R/W Note 1 [...]

431 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (c) Automatic data transmit/receive interval specify register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H. Notes 1. The interval is dependent only on CPU process[...]

432 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Note The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum which is calculated by the following expressions is smaller than 2/f SCK , the minimum interval time is 2/f SCK [...]

433 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Notes 1. The interval is dependent only on CPU processing. 2. The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum which is calculated by the following expressions is sma[...]

434 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Note The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum which is calculated by the following expressions is smaller than 2/f SCK , the minimum interval time is 2/f SCK [...]

435 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (2) Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FAC0H of buffer RAM (up to FADFH at maximum). The transmit data should be in the order from high-order address to low-order address. <2> Set to the automatic data tran[...]

436 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Cautions 1. Because, in the basic transmission/reception mode, the automatic transmit/receive function writes/reads data to/from the buffer RAM after 1-byte transmission/reception, an interval is inserted till the next transmission/reception. As the buffer RAM write/ read is performed at the same time as CP[...]

437 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 ADTP : Automatic data transmit/receive address pointer ADTI : Automatic data transmit/receive interval specify register SIO1 : Serial I/O shift register 1 TRF : Bit 3 of automatic data transmit/receive control register (ADTC) Start Write transmit data in buffer RAM Set ADTP to the value (pointer value) obta[...]

438 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission/reception (ARLD = 0, RE = 1) in basic transmit/receive mode, buffer RAM operates as follows. (i) Before transmission/reception (refer to Figure 19-10 (a)) After any data has been written to the serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit [...]

439 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-10. Buffer RAM Operation in 6-byte Transmission/Reception (in Basic Transmit/Receive Mode) (2/2) (b) 4th byte transmission/reception Receive data 1 (R1) Receive data 2 (R2) Receive data 3 (R3) Transmit data 4 (T4) Transmit data 5 (T5) Transmit data 6 (T6) FADFH FAC5H FAC0H Receive data 4 (R4) SIO1[...]

440 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (b) Basic transmission mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transfer is started when any data is written to the serial I/O shift register 1 (SIO1) while bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1) is set to 1. Upon completion of transmission of[...]

441 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-12. Basic Transmission Mode Flowchart ADTP : Automatic data transmit/receive address pointer ADTI : Automatic data transmit/receive interval specify register SIO1 : Serial I/O shift register 1 TRF : Bit 3 of automatic data transmit/receive control register (ADTC) Start Write transmit data in buffe[...]

442 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD = 0, RE = 0) in basic transmit mode, buffer RAM operates as follows. (i) Before transmission (refer to Figure 19-13 (a)) After any data has been written to the serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred f[...]

443 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-13. Buffer RAM Operation in 6-byte Transmission (in Basic Transmit Mode) (2/2) (b) 4th byte transmission point (c) Completion of transmission/reception Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) Transmit data 4 (T4) Transmit data 5 (T5) Transmit data 6 (T6) FADFH FAC5H FAC0H SI[...]

444 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (c) Repeat transmission mode In this mode, data stored in the buffer RAM is transmitted repeatedly. Serial transfer is started by writing any data to serial I/O shift register 1 (SIO1) when 1 is set in bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1). Unlike the basic transmission mode, after t[...]

445 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-15. Repeat Transmission Mode Flowchart ADTP : Automatic data transmit/receive address pointer ADTI : Automatic data transmit/receive interval specify register SIO1 : Serial I/O shift register 1 Start Write transmit data in buffer RAM Set ADTP to the value (pointer value) obtained by subtracting 1 [...]

446 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD = 1, RE = 0) in repeat transmit mode, buffer RAM operates as follows. (i) Before transmission (refer to Figure 19-16 (a)) After any data has been written to the serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred [...]

447 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-16. Buffer RAM Operation in 6-byte Transmission (in Repeat Transmit Mode) (2/2) (b) Upon completion of transmission of 6 bytes (c) 7th byte transmission point Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) Transmit data 4 (T4) Transmit data 5 (T5) Transmit data 6 (T6) FADFH FAC5H F[...]

448 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (d) Automatic transmission/reception suspending and restart Automatic transmission/reception can be temporarily suspended by setting bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1) to 0. If during 8-bit data transfer, the transmission/reception is not suspended if bit 7 (CSIE1) is set to 0, it[...]

449 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (4) Synchronization control Busy control and strobe control are functions for synchronizing sending and receiving between the master device and slave device. By using these functions, it is possible to detect bit slippage during sending and receiving. (a) Busy control option Busy control is a function which[...]

450 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-19. Operation Timings when Using Busy Control Option (BUSY0 = 0) Caution When TRF is cleared, the SO1 pin becomes low level. Remark CSIIF1 : Interrupt request flag TRF : Bit 3 of the automatic data transmit/receive control register (ADTC) If the busy signal becomes inactive, the wait is canceled. [...]

451 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-20. Busy Signal and Wait Cancel (BUSY0 = 0) (b) Busy & strobe control option Strobe control is a function for synchronizing the sending and receiving of data between a master device and slave device. When sending or receiving of 8 bit data ends, the strobe signal is output by the master device[...]

452 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-21. Operation Timings when Using Busy & Strobe Control Option (BUSY0 = 0) Caution When TRF is cleared, the SO1 pin becomes low level. Remark CSIIF1 : Interrupt request flag TRF : Bit 3 of the automatic data transmit/receive control register (ADTC) SCK1 SO1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D[...]

453 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (c) Bit slippage detection function through the busy signal During an automatic transmit/receive operation, noise occur in the serial clock signal output by the master device and bit slippage may occur in the slave device side serial clock. At this time, if the strobe control option is not used, this bit sl[...]

454 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (5) Automatic transmit/receive interval time When using the automatic transmit/receive function, the read/write operations from/to the buffer RAM are performed after transmitting/receiving one byte. Therefore, an interval is inserted before the next transmit/ receive. Since the read/write operations from/to[...]

455 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (a) When the automatic transmit/receive function is used by the internal clock If bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is set at (1), the internal clock operates. If the automatic transmit/receive function is operated by the internal clock, interval timing by CPU processing is as follo[...]

456 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (b) When the automatic transmit/receive function is used by the external clock If bit 1 (CSIM11) of serial operating mode register 1 (CSIM1) is cleared to 0, external clock operation is set. When the automatic transmit/receive function is used by the external clock, it must be selected so that the interval [...]

457 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 20.1 Serial Interface Channel 2 Functions Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption. [...]

458 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 20.2 Serial Interface Channel 2 Configuration Serial interface channel 2 consists of the following hardware. Table 20-1. Serial Interface Channel 2 Configuration Item Configuration Register Transmit shift register (TXS) Receive shift register (RXS) Receive buffer register (RXB) Control register Serial opera[...]

459 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 Figure 20-2. Baud Rate Generator Block Diagram TPS3 TPS2 TPS1 TPS0 Internal Bus MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Control Register 4 TXE CSIE2 5-Bit Counter Selector Selector Decoder 1/2 Selector Terminal Clock 1/2 Selector Receive Clock Match Match MDL0 to MDL3 5-Bit Counter RXE Start Bit Detection S[...]

460 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (1) Transmit shift register (TXS) This register is used to set the transmit data. The data written in TXS is transmitted as serial data. If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS are transferred as transmit data. Writing data to TXS starts the transmit operation. TXS [...]

461 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 20.3 Serial Interface Channel 2 Control Registers Serial interface channel 2 is controlled by the following four registers. • Serial Operating Mode Register 2 (CSIM2) • Asynchronous Serial Interface Mode Register (ASIM) • Asynchronous Serial Interface Status Register (ASIS) • Baud Rate Generator Con[...]

462 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 < 6 > 543210 <7> Symbol ASIM TXE RXE PS1 PS0 CL SL ISRM SCK FF70H 00H R/W Address After Reset R/W SCK 0 1 Clock in Asynchronous Serial Interface Mode Input clock from off-chip to ASCK pin Dedicated baud rate generator output Note ISRM 0 1 Control of Reception Completion Interrupt in Case of Erro[...]

463 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 Table 20-2. Serial Interface Channel 2 Operating Mode Settings (1) Operation Stop Mode (2) 3-wire Serial I/O Mode (3) Asynchronous Serial Interface Mode Notes 1. Can be used freely as port function. 2. Can be used as P70 (CMOS input/output) when only transmitter is used. Remark x : Don’t care PMxx : Port [...]

464 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (3) Asynchronous serial interface status register (ASIS) This is a register which displays the type of error when a reception error is generated in the asynchronous serial interface mode. ASIS is read with a 1-bit or 8-bit memory manipulation instruction. In 3-wire serial I/O mode, the contents of the ASIS [...]

465 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (4) Baud rate generator control register (BRGC) This register sets the serial clock for serial interface channel 2. BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. Figure 20-6. Baud Rate Generator Control Register Format (1/2) Note Can only be used in 3-wire serial I[...]

466 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 Figure 20-6. Baud Rate Generator Control Register Format (2/2) 5-Bit Counter Source Clock Selection TPS3 TPS2 TPS1 TPS0 n MCS = 1 MCS = 0 0000 f XX /2 10 f XX /2 10 (4.9 kHz) f X /2 11 (2.4 kHz) 11 0101 f XX f X (5.0 MHz) f X /2 (2.5 MHz) 1 0110 f XX /2 f X /2 (2.5 MHz) f X /2 2 (1.25 MHz) 2 0111 f XX /2 2 [...]

467 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (a) Generation of baud rate transmit/receive clock by means of main system clock The transmit/receive clocks generated by scaling the main system cl[...]

468 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression. [Baud rate] = [Hz] f ASC[...]

469 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 20.4 Serial Interface Channel 2 Operation Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 20.4.1 Operation stop mode In the operation stop mode, serial transfer is not performed, and therefore power co[...]

470 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. SL < 6 > 543210 <7> Symbol ASIM TXE RXE PS1 PS0 CL ISRM SCK FF70H 00H R/W Address After Reset R/W RXE 0 1 Receive Operation Control Receive oper[...]

471 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 20.4.2 Asynchronous serial interface (UART) mode In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible. A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud rates. In addition, the baud rate can[...]

472 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 < 6 > 543210 <7> Symbol ASIM TXE RXE PS1 PS0 CL SL ISRM SCK FF70H 00H R/W Address After Reset R/W SCK 0 1 Clock Selection in Asynchronous Serial Interface Mode Input clock from off-chip to ASCK pin Dedicated baud rate generator output Note ISRM 0 1 Control of Reception Completion Interrupt in Ca[...]

473 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (c) Asynchronous serial interface status register (ASIS) ASIS is set with an 8-bit memory manipulation instruction. RESET input sets ASIS to 00H. PE 6543210 7 Symbol ASIS 0 0 0 0 0 FE OVE FF71H 00H R Address After Reset R/W OVE 0 1 Overrun Error Flag Overrun error not generated Overrun error generated Note [...]

474 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (d) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. Baud Rate Generator Input Clock Selection MDL3 MDL2 MDL1 MDL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1[...]

475 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 Caution When a write is performed to BRGC during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. Therefore, BRGC must not be written to during a communication operation. Remarks 1. f SCK : 5-bit counter source clock 2. k : Value set in MDL0 [...]

476 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (i) Generation of baud rate transmit/receive clock by means of main system clock The transmit/receive clock is generated by scaling the main system [...]

477 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression. [Baud rate] = [Hz] wher[...]

478 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (2) Communication operation (a) Data format The transmit/receive data format is shown in Figure 20-7. Figure 20-7. Asynchronous Serial Interface Transmit/Receive Data Format One data frame consists of the following bits. • Start bit ................... 1 bi t • Character bits ......... 7 bits/8 bits •[...]

479 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected. With 0 parity and no parity, an[...]

480 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (c) Transmission A transmit operation is started by writing transmit data to the transmit shift register (TXS). The start bit, parity bit, and stop bit(s) are added automatically. When the transmit operation starts, the data in the transmit shift register (TXS) is shifted out, and when the transmit shift re[...]

481 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (d) Reception When the RXE bit of the asynchronous serial interface mode register (ASIM) is set (1), a receive operation is enabled and sampling of the RxD pin input is performed. RxD pin input sampling is performed using the serial clock specified by ASIM. When the RxD pin input becomes low, the 5-bit coun[...]

482 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (e) Receive errors Three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error. If the data reception result error flag is set in the asynchronous serial interface status register (ASIS), a receive error interrupt request (INTSER) is generated. A receive error[...]

483 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (3) UART mode cautions (a) When transmit operation is stopped by clearing (0) bit 7 (TXE) of the asynchronous serial interface mode register (ASIM) during transmission, be sure to set the transmit shift register (TXS) to FFH, then set the TXE to 1, before executing the next transmission. (b) When receive op[...]

484 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 20.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous clocked serial interface, such as the 75X/XL Series, 78K Series, 17K Series, etc. Communication is performed using three lines: the[...]

485 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 < 6 > 543210 <7> Symbol ASIM TXE RXE PS1 PS0 CL SL ISRM SCK FF70H 00H R/W Address After Reset R/W SCK 0 1 Clock in Asynchronous Serial Interface Mode Input clock from off-chip to ASCK pin Dedicated baud rate generator output ISRM 0 1 Control of Reception Completion Interrupt in Case of Error Gen[...]

486 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (c) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. Baud Rate Generator Input Clock Selection MDL3 MDL2 MDL1 MDL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0[...]

487 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 5-Bit Counter Source Clock Selection TPS3 TPS2 TPS1 TPS0 n MCS = 1 MCS = 0 0000 f XX /2 10 f X /2 10 (4.9 kHz) f X /2 11 (2.4 kHz) 11 0101 f XX f X (5.0 MHz) f X /2 (2.5 MHz) 1 0110 f XX /2 f X /2 (2.5 MHz) f X /2 2 (1.25 MHz) 2 0111 f XX /2 2 f X /2 2 (1.25 MHz) f X /2 3 (625 kHz) 3 1000 f XX /2 3 f X /2 3[...]

488 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 When the internal clock is used as the serial clock in the 3-wire serial I/O mode, set BRGC as described below. BRGC Setting is not required if an external serial clock is used. (i) When the baud rate generator is not used: Select a serial clock frequency with TPS0 through TPS3. Be sure then to set MDL0 thr[...]

489 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 SI2 SCK2 12345678 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO2 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SRIF Transfer Start at the Falling Edge of SCK2 End of Transfer (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/ received bit by bit i[...]

490 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (3) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 20-13 shows the configuration of the transmit shift register (TXS/SIO2) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form. MSB/LSB switching as th[...]

491 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 20.4.4 Restrictions on using UART mode In the UART mode, a receive completion interrupt request (INTSR) is generated after a certain period of time following the generation and clearing of the receive error interrupt request (INTSER). Thereby, the phenomenon shown below may occur. Details If the bit 1 (ISRM[...]

492 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 Figure 20-15. Period that Reading Receive Buffer Register is Prohibited T1 : The amount of time for one unit of data sent in the baud rate selected with the baud rate generator control register (BRGC) (1/baud rate) T2 : The amount of time for 2 clocks of 5-bit counter source clock (f SCK ) selected with BRG[...]

493 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 [Example] INTSER is generated 7 clocks (MIN.) of CPU clock (time from interrupt request to servicing) Instructions for 2205 clocks (MIN.) of CPU clock are required. UART receive error interrupt request (INTSER) servicing EI RETI MOV A,RXB Main processing[...]

494 [MEMO][...]

495 CHAPTER 21 REAL-TIME OUTPUT PORT 21.1 Real-Time Output Port Functions Data set previously in the real-time output buffer register can be transferred to the output latch by hardware concurrently with timer interrupt request or external interrupt request generation, then output externally. This is called the real-time output function. The pins th[...]

496 CHAPTER 21 REAL-TIME OUTPUT PORT (1) Real-time output buffer register (RTBL, RTBH) Addresses of RTBL and RTBH are mapped individually in the special function register (SFR) area as shown in Figure 21-2. When specifying 4 bits x 2 channels as the operating mode, data are set individually in RTBL and RTBH. When specifying 8 bits x 1 channel as th[...]

497 CHAPTER 21 REAL-TIME OUTPUT PORT 21.3 Real-Time Output Port Control Registers The following three registers control the real-time output port. • Port mode register 12 (PM12) • Real-time output port mode register (RTPM) • Real-time output port control register (RTPC) (1) Port mode register 12 (PM12) This register sets the input or output m[...]

498 CHAPTER 21 REAL-TIME OUTPUT PORT 7 0 Symbol RTPC 6 0 5 0 4 0 3 0 2 0 <1> BYTE <0> EXTR Address FF36H 00H After Reset R/W R/W EXTR 0 1 Real-time Output Control by INTP2 INTP2 not specified as real-time output trigger INTP2 specified as real-time output trigger BYTE 0 1 Real-time Output Port Operating Mode 4 bits x 2 channels 8 bits x[...]

499 CHAPTER 22 INTERRUPT FUNCTIONS 22.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in a disabled state. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. It generates a sta[...]

500 CHAPTER 22 INTERRUPT FUNCTIONS 22.2 Interrupt Sources and Configuration There are total of 24 non-maskable, maskable, and software interrupts in the interrupt sources (see Table 22-1 ). Table 22-1. Interrupt Source List (1/2) Interrupt Source Name Trigger Watchdog timer overflow (with watchdog timer mode 1 selected) Watchdog timer overflow (wit[...]

501 CHAPTER 22 INTERRUPT FUNCTIONS Table 22-1. Interrupt Source List (2/2) Interrupt Source Name Trigger Reference time interval signal from watch timer Generation of 16-bit timer register, capture/compare register (CR00) match signal Generation of 16-bit timer register, capture/compare register (CR01) match signal Generation of 8-bit timer/event c[...]

502 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Internal Bus Priority Control Circuit Vector Table Address Generator Standby Release Signal Interrupt Request (B) Internal maskable interrupt Internal Bus IE PR ISP MK IF Interrupt Request Priority Control Circuit Vect[...]

503 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (except INTP0) (E) Software interrupt External Interrupt Mode Register (INTM0, INTM1) Edge Detector Interrupt Request IE PR ISP MK IF Priority Control Circuit Vector Table Address Generator Standby Release Signal Internal [...]

504 CHAPTER 22 INTERRUPT FUNCTIONS 22.3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L) • Interrupt mask flag register (MK0L, MK0H, MK1L) • Priority specify flag register (PR0L, PR0H, PR1L) • External interrupt mode re[...]

505 CHAPTER 22 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input. IF0L[...]

506 CHAPTER 22 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable. MK0L, MK0H, and MK1L are set with a 1-bit or 8-bit memory manipulation instruction. If IF0L and IF0H are used as a 16-bit regi[...]

507 CHAPTER 22 INTERRUPT FUNCTIONS (3) Priority specify flag registers (PR0L, PR0H, PR1L) The priority specify flag is used to set the corresponding maskable interrupt priority orders. PR0L, PR0H, and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If IF0L and IF0H are used as a 16-bit register PR0, use a 16-bit memory manipulat[...]

508 CHAPTER 22 INTERRUPT FUNCTIONS Address FFECH 00H After Reset R/W R/W 0 0 1 1 INTP0 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES11 7 ES31 Symbol INTM0 6 ES30 5 ES21 4 ES20 3 ES11 2 ES10 1 0 0 0 0 1 0 1 ES10 0 0 1 1 INTP1 Valid Edge Selection Falling edge Rising edge Setting prohibited Both fal[...]

509 CHAPTER 22 INTERRUPT FUNCTIONS Address FFEDH 00H After Reset R/W R/W 0 0 1 1 INTP3 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES41 7 ES71 Symbol INTM1 6 ES70 5 ES61 4 ES60 3 ES51 2 ES50 1 ES41 0 ES40 0 1 0 1 ES40 0 0 1 1 INTP4 Valid Edge Selection Falling edge Rising edge Setting prohibited Bo[...]

510 CHAPTER 22 INTERRUPT FUNCTIONS Address FF47H 00H After Reset R/W R/W 0 0 1 1 INTP0 Sampling Clock Selection f xx /2 N f xx /2 7 f xx /2 5 f xx /2 6 SCS1 7 0 Symbol SCS 6 0 5 0 4 0 3 0 2 0 1 SCS1 0 SCS0 0 1 0 1 SCS0 MCS = 1 MCS = 0 f x /2 7 (39.1 kHz) f x /2 5 (156.3 kHz) f x /2 6 (78.1 kHz) f x /2 8 (19.5 kHz) f x /2 6 (78.1 kHz) f x /2 7 (39.1[...]

511 CHAPTER 22 INTERRUPT FUNCTIONS t SMP Sampling Clock INTP0 PIF0 “L” Because INTP0 level is not active in sampling, PIF0 output remains at low level. When the setting INTP0 input level is active twice in succession, the noise eliminator sets interrupt request flag (PIF0) to 1. Figure 22-8 shows the noise eliminator input/output timing. Figure[...]

512 CHAPTER 22 INTERRUPT FUNCTIONS 7 IE PSW 6 Z 5 RBS1 4 AC 3 RBS0 2 0 1 ISP 0 CY 02H After Reset ISP 0 Used when Normal Instruction is Executed Priority of Interrupt Currently Being Received High-priority interrupt servicing (low-priority interrupt disable) 1 Interrupt request not acknowledged or low-priority interrupt servicing (all-maskable inte[...]

513 CHAPTER 22 INTERRUPT FUNCTIONS 22.4 Interrupt Servicing Operations 22.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrup[...]

514 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-10. Flowchart from Non-Maskable Interrupt Generation to Acknowledge WDTM4 = 1 (with watchdog timer mode selected)? Overflow in WDT? WDTM3 = 0 (with non-maskable interrupt selected)? Interrupt request generation WDT interrupt servicing? Interrupt control register unaccessed? Interrupt service start Interr[...]

515 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-12. Non-Maskable Interrupt Request Acknowledge Operation (a) If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution (b) If two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution NMI Request <2&[...]

516 CHAPTER 22 INTERRUPT FUNCTIONS 22.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask (MK) flag is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state (with IE flag set to 1). However, a low[...]

517 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-13. Interrupt Request Acknowledge Processing Algorithm xxIF : Interrupt request flag xxMK : Interrupt mask flag xxPR : Priority specify flag IE : Flag to control maskable interrupt request acknowledge ISP : Flag to indicate the priority of interrupt being serviced (0 = an interrupt with higher priority i[...]

518 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-14. Interrupt Request Acknowledge Timing (Minimum Time) Remark 1 clock: (f CPU : CPU clock) Figure 22-15. Interrupt Request Acknowledge Timing (Maximum Time) Remark 1 clock: (f CPU : CPU clock) 22.4.3 Software interrupt request acknowledge operation A software interrupt request is acknowledged by BRK ins[...]

519 CHAPTER 22 INTERRUPT FUNCTIONS 22.4.4 Multiple interrupt servicing A multiple interrupt consists in acknowledging another interrupt during the execution of the interrupt. A multiple interrupt is generated only in the interrupt request acknowledge enable state (IE = 1) (except non- maskable interrupt). As soon as an interrupt request is acknowle[...]

520 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-16. Multiple Interrupt Example (1/2) Example 1. Two multiple interrupts generated During interrupt INTxx servicing, two interrupt requests, INTyy and INTzz are acknowledged, and a multiple interrupt is generated. An EI instruction is issued before each interrupt request acknowledge, and the interrupt req[...]

521 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-16. Multiple Interrupt Example (2/2) Example 3. A multiple interrupt is not generated because interrupts are not enabled Because interrupts are not enabled in interrupt INTxx servicing (an EI instruction is not issued), interrupt request INTyy is not acknowledged, and a multiple interrupt is not generate[...]

522 CHAPTER 22 INTERRUPT FUNCTIONS 22.4.5 Interrupt request reserve Some instructions may reserve the acknowledge of an instruction request until the completion of the execution of the next instruction even if the interupt request is generated during the execution. The following shows such instructions (interrupt request reserve instruction). • M[...]

523 CHAPTER 22 INTERRUPT FUNCTIONS 22.5 Test Functions In this function, when the watch timer overflows and when a rising edge of port 4 is detected, the corresponding test input flag is set (1), and a standby release signal is generated. Unlike the interrupt function, vectored processing is not performed. There are two test input factors as shown [...]

524 CHAPTER 22 INTERRUPT FUNCTIONS (1) Interrupt request flag register 1L (IF1L) It indicates whether a clock timer overflow is detected or not. It is set by a 1-bit memory manipulation instruction and 8-bit memory manipulation instruction. It is set to 00H by the RESET signal input. Figure 22-19. Format of Interrupt Request Flag Register 1L Cautio[...]

525 CHAPTER 22 INTERRUPT FUNCTIONS (3) Key return mode register (KRM) This register is used to set enable/disable of standby function clear by key return signal (port 4 falling edge detection). KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H. Figure 22-21. Key Return Mode Register Format Caution When po[...]

526 [MEMO][...]

527 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION 23.1 External Device Expansion Functions The external device expansion functions connect external devices to areas other than the internal ROM, RAM, and SFR. The external device expansion function can be used in the following two modes: • Multiplexed bus mode • Separate bus mode (1) Multiplexed [...]

528 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION (2) Separate bus mode External devices are connected using independent address and data buses. This connection requires no latches externally, resulting in reduction of external parts and area on the mounting board. In this mode, ports 4 through 6 and port 8 are used for control of address/data, rea[...]

529 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Memory maps when using the external device expansion function are as follows. Figure 23-1. Memory Map when Using External Device Expansion Function (1/2) (a) Memory map of µ PD78076, 78076Y, and of µ PD78P078, 78P078Y when internal PROM capacity is 48 Kbytes FFFFH SFR Internal High-Speed RAM FF00H[...]

530 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-1. Memory Map when Using External Device Expansion Function (2/2) (b) Memory map of µ PD78078, 78078Y, 78P078, (c) Memory map of µ PD78078, 78078Y and of 78P078Y when internal ROM capacity (PROM) µ PD78P078, 78P078Y when internal PROM is 56 Kbytes capacity is 60 Kbytes Caution When the [...]

531 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION 23.2 External Device Expansion Function Control Register The external device expansion function is controlled by the memory expansion mode register (MM) and internal memory size switching register (IMS). (1) Memory expansion mode register (MM) MM sets the wait count and external expansion area, and [...]

532 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION 1 1 48 Kbytes 56 Kbytes Note 2 1 1 0 1 0 0 7 RAM2 Symbol IMS 6 RAM1 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0 Address FFF0H Note 1 After Reset R/W R/W Internal ROM size selection ROM3 60 Kbytes 1 ROM2 1 ROM1 1 ROM0 0 Setting prohibited Other than above Internal high-speed RAM size selection RAM2 RAM1 R[...]

533 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION (3) External bus type select register (EBTS) This register sets the operation mode of the external device expansion function. When the multiplexed bus mode is selected, the P80/A0 through P87/A7 pins can be used as an I/O port. It is set by an 8-bit memory manipulation instruction. RESET signal inpu[...]

534 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION 23.3 External Device Expansion Function Timing 23.3.1 Timings in multiplexed bus mode Timing control signal output pins in the multiplexed bus mode are as follows. (1) RD pin (Alternate function: P64) Read strobe signal output pin. The read strobe signal is output in data accesses and instruction fe[...]

535 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-5. Instruction Fetch from External Memory in Multiplexed Bus Mode (a) No wait (PW1, PW0 = 0, 0) setting (b) Wait (PW1, PW0 = 0, 1) setting (c) External wait (PW1, PW0 = 1, 1) setting ASTB RD AD0 to AD7 A8 to A15 Lower Address Operation Code Higher Address ASTB RD AD0 to AD7 A8 to A15 Lower[...]

536 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-6. External Memory Read Timing in Multiplexed Bus Mode (a) No wait (PW1, PW0 = 0, 0) setting (b) Wait (PW1, PW0 = 0, 1) setting (c) External wait (PW1, PW0 = 1, 1) setting Higher Address ASTB RD AD0 to AD7 A8 to A15 Lower Address Read Data ASTB RD AD0 to AD7 A8 to A15 Lower Address Read Da[...]

537 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-7. External Memory Write Timing in Multiplexed Bus Mode (a) No wait (PW1, PW0 = 0, 0) setting (b) Wait (PW1, PW0 = 0, 1) setting (c) External wait (PW1, PW0 = 1, 1) setting ASTB WR AD0 to AD7 A8 to A15 Lower Address Write Data Hi-Z Higher Address ASTB WR AD0 to AD7 A8 to A15 Lower Address [...]

538 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-8. External Memory Read Modify Write Timing in Multiplexed Bus Mode (a) No wait (PW1, PW0 = 0, 0) setting (b) Wait (PW1, PW0 = 0, 1) setting (c) External wait (PW1, PW0 = 1, 1) setting ASTB RD WR AD0 to AD7 A8 to A15 Lower Address Write Data Higher Address Hi-Z Read Data Lower Address High[...]

539 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION 23.3.2 Timings in separate bus mode Timing control signal output pins in the separate bus mode are as follows. (1) RD pin (Alternate function: P64) Read strobe signal output pin. The read strobe signal is output in data accesses and instruction fetches from external memory. During internal memory ac[...]

540 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-9. Instruction Fetch from External Memory in Separate Bus Mode (a) No wait (PW1, PW0 = 0, 0) setting (b) Wait (PW1, PW0 = 0, 1) setting (c) External wait (PW1, PW0 = 1, 1) setting Note In the separate bus mode, use of the address strobe signal is not required though it is output from the A[...]

541 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-10. External Memory Read Timing in Separate Bus Mode (a) No wait (PW1, PW0 = 0, 0) setting (b) Wait (PW1, PW0 = 0, 1) setting (c) External wait (PW1, PW0 = 1, 1) setting Note In the separate bus mode, use of the address strobe signal is not required though it is output from the ASTB/P67 pi[...]

542 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-11. External Memory Write Timing in Separate Bus Mode (a) No wait (PW1, PW0 = 0, 0) setting (b) Wait (PW1, PW0 = 0, 1) setting (c) External wait (PW1, PW0 = 1, 1) setting Note In the separate bus mode, use of the address strobe signal is not required though it is output from the ASTB/P67 p[...]

543 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-12. External Memory Read Modify Write Timing in Separate Bus Mode (a) No wait (PW1, PW0 = 0, 0) setting (b) Wait (PW1, PW0 = 0, 1) setting (c) External wait (PW1, PW0 = 1, 1) setting Note In the separate bus mode, use of the address strobe signal is not required though it is output from th[...]

544 [MEMO][...]

545 CHAPTER 24 STANDBY FUNCTION 24.1 Standby Function and Configuration 24.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. System clock osci[...]

546 CHAPTER 24 STANDBY FUNCTION 24.1.2 Standby function control register A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H. However, it [...]

547 CHAPTER 24 STANDBY FUNCTION 24.2 Standby Function Operations 24.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the subsystem clock. The operating status in the HALT mode is described below. Table 24-1. HALT Mode Operating Status HALT mode s[...]

548 CHAPTER 24 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released with the following four types of sources. (a) Release by unmasked interrupt request An unmasked interrupt request is generated to release the HALT mode. If interrupt request acknowledge is enabled, vectored interrupt service is carried out. If disabled, the next add[...]

549 CHAPTER 24 STANDBY FUNCTION HALT Instruction RESET Signal Operating Mode Clock Reset Period HALT Mode Oscillation Oscillation stop Oscillation Stabilization Wait Status Operating Mode Oscillation Wait (2 17 /f x : 26.2 ms) (d) Release by RESET input As is the case with normal reset operation, a program is executed after branch to the reset vect[...]

550 CHAPTER 24 STANDBY FUNCTION 24.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V DD via a pull-up resistor to minimize leakage current at the crystal oscillator.[...]

551 CHAPTER 24 STANDBY FUNCTION STOP Instruction Wait (Time set by OSTS) Oscillation Stabilization Wait Status Operating Mode Oscillation Operationg Mode STOP Mode Oscillation Stop Oscillation Standby Release Signal Clock Interrupt Request (2) STOP mode release The STOP mode can be released with the following three types of sources. (a) Release by [...]

552 CHAPTER 24 STANDBY FUNCTION RESET Signal Operating Mode Clock Reset Period STOP Mode Oscillation Stop Oscillation Stabilization Wait Status Operating Mode Oscillation Wait (2 17 /f x : 26.2 ms) STOP Instruction Oscillation (c) Release by RESET input The STOP mode is released and after the lapse of oscillation stabilization time, reset operation[...]

553 CHAPTER 25 RESET FUNCTION 25.1 Reset Function The following two operations are available to generate the reset signal. (1) External reset input with RESET pin (2) Internal reset by watchdog timer overrun time detection External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 000[...]

554 CHAPTER 25 RESET FUNCTION Figure 25-2. Timing of Reset by RESET Input Figure 25-3. Timing of Reset due to Watchdog Timer Overflow Figure 25-4. Timing of Reset by RESET Input in STOP Mode RESET Internal Reset Signal Port Pin Delay Delay Hi-z X1 Normal Operation Reset Period (Oscillation Stop) Oscillation Stabilization Time Wait Normal Operation [...]

555 CHAPTER 25 RESET FUNCTION Table 25-1. Hardware Status after Reset (1/3) Hardware Status after Reset Program counter (PC) Note 1 The contents of reset vector tables (0000H and 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) 02H Data memory Undefined Note 2 General register Undefined Note 2 Ports 0 to 3, Port 7, 9, 10, 12, [...]

556 CHAPTER 25 RESET FUNCTION Table 25-1. Hardware Status after Reset (2/3) Hardware Status after Reset 8-bit timer/event counters Timer register (TM5, TM6) 00H 5 and 6 Compare register (CR50, CR60) 00H Clock select register (TCL5, TCL6) 00H Mode control register (TMC5, TMC6) 00H Watch timer Mode control register (TMC2) 00H Watchdog timer Clock sel[...]

557 CHAPTER 25 RESET FUNCTION Table 25-1. Hardware Status after Reset (3/3) Hardware Status after Reset Interrupt Request flag register (IF0L, IF0H, IF1L) 00H Mask flag register (MK0L, MK0H, MK1L) FFH Priority specify flag register FFH (PR0L, PR0H, PR1L) External interrupt mode register 00H (INTM0, INTM1) Key return mode register (KRM) 02H Sampling[...]

558 [MEMO][...]

559 CHAPTER 26 ROM CORRECTION 26.1 ROM Correction Functions The µ PD78078, 78078Y Subseries can replace part of a program in the mask ROM with a program in the internal expansion RAM. Instruction bugs found in the mask ROM can be avoided, and program flow can be changed by using the ROM correction. The ROM correction can correct two places (max.) [...]

560 CHAPTER 26 ROM CORRECTION (1) Correction address registers 0 and 1 (CORAD0, CORAD1) These registers set the start address (correction address) of the instruction(s) to be corrected in the mask ROM. The ROM correction corrects two places (max.) of the program. Addresses are set to two registers, CORAD0 and CORAD1. If only one place needs to be c[...]

561 CHAPTER 26 ROM CORRECTION 7 0 6 0 5 0 4 0 COREN1 CORST1 COREN0 CORST0 Symbol CORCN Address FF8AH After reset COREN0 0 1 CORST0 0 1 COREN1 0 1 CORST1 0 1 R/W R/W Note 00H Correction address register 0 and fetch address match detection Not detected Detected Correction address register 0 and fetch address match detection control Disabled Enabled C[...]

562 CHAPTER 26 ROM CORRECTION V DD V DD V DD PD78078, 78078Y Subseries EEPROM SCK0 SB1 P32 SCL SDA CS CE µ RA78K/0 EEPROM Source program 00 10 0D 02 9B 02 10 00H 01H 02H FFH CSEG AT 1000H ADD A, #2 BR !1002H 26.4 ROM Correction Application (1) Store the correction address and instruction after correction (patch program) to nonvolatile memory (such[...]

563 CHAPTER 26 ROM CORRECTION (2) Assemble in advance the initialization routine as shown in Figure 26-6 to correct the program. Figure 26-6. Initialization Routine Note Whether the ROM correction is used or not should be judged by the port input level. For example, when the P20 input level is high, the ROM correction is used, otherwise, it is not [...]

564 CHAPTER 26 ROM CORRECTION Figure 26-7. ROM Correction Operation No Yes Start of internal ROM program Does fetch address match with correction address? Set correction status flag Correction branch (branch to address F7FDH) Execution of correction program ROM correction[...]

565 CHAPTER 26 ROM CORRECTION 26.5 ROM Correction Example The example of ROM correction when the instruction at address 1000H “ADD A, #1” is changed to “ADD A, #2” is as follows. Figure 26-8. ROM Correction Example (1) Branches to address F7FDH when the preset value 1000H in the correction address register matches the fetch address value af[...]

566 CHAPTER 26 ROM CORRECTION 26.6 Program Execution Flow Figures 26-9 and 26-10 show the program transition diagrams when the ROM correction is used. Figure 26-9. Program Transition Diagram (when One Place is Corrected) (1) Branches to address F7FDH when fetch address matches correction address (2) Branches to correction program (3) Returns to int[...]

567 CHAPTER 26 ROM CORRECTION Figure 26-10. Program Transition Diagram (when Two Places are Corrected) (1) Branches to address F7FDH when fetch address matches correction address (2) Branches to branch destination judgment program (3) Branches to correction program 1 by branch destination judgment program (BTCLR !CORST0, $xxxxH) (4) Returns to inte[...]

568 CHAPTER 26 ROM CORRECTION 26.7 Cautions on ROM Correction (1) Address values set in correction address registers 0 and 1 (CORAD0, CORAD1) must be addresses where instruction codes are stored. (2) Correction address registers 0 and 1 (CORAD0, CORAD1) should be set when the correction enable flag (COREN0, COREN1) is 0 (when the correction branch [...]

569 CHAPTER 27 µ PD78P078, 78P078Y The µ PD78P078 and 78P078Y (PROM versions) replace the internal mask ROM of the mask ROM versions ( µ PD78074, 78075, 78076, 78078, and µ PD78074Y, 78075Y, 78076Y, 78078Y) with one-time programmable ROM or EPROM, which enable program writing, erasure, and rewriting. Table 27-1 lists differences between the PRO[...]

570 CHAPTER 27 µ PD78P078, 78P078Y 7 RAM2 Symbol IMS 6 RAM1 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0 Address FFF0H CFH After Reset R/W R/W 1 1 Internal ROM Capacity Selection 48 Kbytes 56 Kbytes Note ROM3 60 Kbytes 1 1 1 ROM2 1 0 1 ROM1 1 0 0 ROM0 1 Setting prohibited Other than above Internal High-Speed RAM Capacity Selection RAM2 RAM1 RAM0 1024 by[...]

571 CHAPTER 27 µ PD78P078, 78P078Y 7 0 Symbol IXS 6 0 5 0 4 0 3 IXRAM3 2 IXRAM2 1 IXRAM1 0 IXRAM0 Address FFF4H 0AH After Reset Internal Extension RAM Capacity Selection IXRAM3 IXRAM2 IXRAM1 1024 bytes 10 1 Setting prohibited Other than above IXRAM0 0 R/W W 0 bytes 11 00 27.2 Internal Extension RAM Size Switching Register The µ PD78P078 and 78P07[...]

572 CHAPTER 27 µ PD78P078, 78P078Y 27.3 PROM Programming The µ PD78P078 and 78P078Y each incorporate a 60-Kbyte PROM as program memory. To write a program into the PROM make the device enter the PROM programming mode by setting the levels of the V PP and RESET pins as specified. For the connection of unused pins, refer to 1.5 (2) PROM programming[...]

573 CHAPTER 27 µ PD78P078, 78P078Y (3) Standby mode Setting CE to H sets the standby mode. In this mode, data output becomes high impedance irrespective of the status of OE. (4) Page data latch mode Setting CE to H, PGM to H, and OE to L at the start of the page write mode sets the page data latch mode. In this mode, 1-page 4-byte data is latched [...]

574 CHAPTER 27 µ PD78P078, 78P078Y Start Address = G V DD = 6.5 V, V PP = 12.5 V X = 0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Latch X = X + 1 0.1 ms program pulse Verify 4 bytes Pass Address = N? No Pass V DD = 4.5 to 5.5 V, V PP = V DD All bytes verified? End of write Address = Address + 1 No Yes X = 1[...]

575 CHAPTER 27 µ PD78P078, 78P078Y Page Data Latch Page Program Program Verify Data Input Data Output Hi-Z A2 to A16 A0, A1 D0 to D7 V PP V DD V PP V DD + 1.5 V DD V PP V IH CE PGM OE V IL V IH V IL V IH V IL Figure 27-4. Page Program Mode Timing[...]

576 CHAPTER 27 µ PD78P078, 78P078Y Start Address = G V DD = 6.5 V, V PP = 12.5 V X = 0 X = X + 1 0.1 ms program pulse Verify Address = N ? V DD = 4.5 to 5.5 V, V PP = V DD All bytes verified? End of write Fail Fail Pass Yes All Pass No Pass Defective product No Yes X = 10 ? Address = Address + 1 G = Start address N = Last address of program Figure[...]

577 CHAPTER 27 µ PD78P078, 78P078Y Program Program Verify A0 to A16 D0 to D7 Data Input Hi-Z Data Output V PP V DD V DD + 1.5 V DD V IH V IL V IH V IL V IH V IL V PP V DD CE PGM OE Figure 27-6. Byte Program Mode Timing Cautions 1. Apply V DD before applying V PP , and remove it after removing V PP . 2. V PP must not exceed +13.5 V including oversh[...]

578 CHAPTER 27 µ PD78P078, 78P078Y 27.3.3 PROM reading procedure PROM contents can be read onto the external data bus (D0 to D7) using the following procedure. (1) Fix the RESET pin low, and supply +5 V to the V PP pin. Unused pins are handled as shown in, 1.5 (2) PROM programming mode and 2.5 Pin Configuration (Top View) . (2) Supply +5 V to the [...]

579 CHAPTER 27 µ PD78P078, 78P078Y 27.4 Erasure Procedure ( µ PD78P078KL-T and 78P078YKL-T Only) With the µ PD78P078KL-T or 78P078YKL-T, it is possible to erase (all contents to FFH) the data contents written in the program memory, and rewrite the memory. The data can be erased by exposing the window to light with a wavelength of approximately 4[...]

580 [MEMO][...]

581 CHAPTER 28 INSTRUCTION SET This chapter describes each instruction set of the µ PD78078 and 78078Y Subseries as list table. For details of its operation and operation code, refer to the separate document “78K/0 Series USER’S MANUAL — Instructions (U12326E).”[...]

582 CHAPTER 28 INSTRUCTION SET 28.1 Legends Used in Operation List 28.1.1 Operand identifiers and description methods Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more descri[...]

583 CHAPTER 28 INSTRUCTION SET 28.1.2 Description of “operation” column A : A register; 8-bit accumulator X : X register B : B register C : C register D : D register E : E register H : H register L : L register AX : AX register pair; 16-bit accumulator BC : BC register pair DE : DE register pair HL : HL register pair PC : Program counter SP : S[...]

584 CHAPTER 28 INSTRUCTION SET 28.2 Operation List Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 ZA C C Y 8-bit data MOV r , #byte 2 4 — r ← byte transfer saddr , #byte 3 6 7 (saddr) ← byte sfr , #byte 3 — 7 sfr ← byte A, r Note 3 12 — A ← r r, A Note 3 12 — r ← A A, saddr 2 4 5 A ← (saddr) saddr , [...]

585 CHAPTER 28 INSTRUCTION SET Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 ZA C C Y 16-bit data MOVW rp, #word 3 6 — rp ← word transfer saddrp, #word 4 8 10 (saddrp) ← word sfrp, #word 4 — 10 sfrp ← word AX, saddrp 2 6 8 AX ← (saddrp) saddrp, AX 2 6 8 (saddrp) ← AX AX, sfrp 2 — 8 AX ← sfrp sfrp, AX [...]

586 CHAPTER 28 INSTRUCTION SET Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 ZA C C Y 8-bit SUB A, #byte 2 4 — A, CY ← A – byte x x x operation saddr , #byte 3 6 8 (saddr), CY ← (saddr) – byte x x x A, r Note 3 2 4 — A, CY ← A – r x x x r, A 2 4 — r, C Y ← r – A x x x A, saddr 2 4 5 A, CY ← A ?[...]

587 CHAPTER 28 INSTRUCTION SET Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 ZA C C Y 8-bit OR A, #byte 2 4 — A ← A / byte x operation saddr , #byte 3 6 8 (saddr) ← (saddr) / byte x A, r Note 3 24 — A ← A / r x r, A 2 4 — r ← r / A x A, saddr 2 4 5 A ← A / (saddr) x A, !addr16 3 8 9 + n A ← A / [...]

588 CHAPTER 28 INSTRUCTION SET Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 ZA C C Y 16-bit ADDW AX, #word 3 6 — AX, CY ← AX + word x x x operation SUBW AX, #word 3 6 — AX, CY ← AX – word x x x CMPW AX, #word 3 6 — AX – word x x x Multiply MULU X 2 16 — AX ← A x X divide DIVUW C 2 25 — AX (Quotient[...]

589 CHAPTER 28 INSTRUCTION SET Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 ZA C C Y Bit mani- AND1 CY , saddr .bit 3 6 7 CY ← CY / (saddr .bit) x pulation CY , sfr .bit 3 — 7 CY ← CY / sfr .bit x CY , A.bit 2 4 — CY ← CY / A.bit x CY , PSW .bit 3 — 7 CY ← CY / PSW .bit x CY , [HL].bit 2 6 7 + n CY ?[...]

590 CHAPTER 28 INSTRUCTION SET Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 ZA C C Y Call / CALL !addr16 3 7 — (SP – 1) ← (PC + 3) H , (SP - 2) ← (PC + 3) L , return PC ← addr16, SP ← SP – 2 CALLF !addr1 1 2 5 — (SP – 1) ← (PC + 2) H , (SP – 2) ← (PC + 2) L , PC 15 - 1 1 ← 00001, PC 10 - 0 ?[...]

591 CHAPTER 28 INSTRUCTION SET Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 ZA C C Y Conditional BT saddr.bit, $addr16 3 8 9 PC ← PC + 3 + jdisp8 if(saddr .bit) = 1 branch sfr.bit, $addr16 4 — 1 1 PC ← PC + 4 + jdisp8 if sfr .bit = 1 A.bit, $addr16 3 8 — PC ← PC + 3 + jdisp8 if A.bit = 1 PSW .bit, $addr16 3 [...]

592 CHAPTER 28 INSTRUCTION SET 28.3 Instructions Listed by Addressing T ype (1) 8-bit instructions MOV , XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP , MULU, DIVUW , INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP , DBNZ[...]

593 CHAPTER 28 INSTRUCTION SET Second Operand [HL + byte] #byte A r Note sfr saddr !addr16 PSW [DE] [HL] [HL + B] $addr16 1 None First Operand [HL + C] A ADD MOV MOV MOV MOV MOV MOV MOV MOV ROR ADDC XCH XCH XCH XCH XCH XCH XCH ROL SUB ADD ADD ADD ADD ADD RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC AND SUB SUB SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR[...]

594 CHAPTER 28 INSTRUCTION SET (2) 16-bit instructions MOVW , XCHW , ADDW , SUBW , CMPW , PUSH, POP , INCW , DECW Second Operand #word AX rp Note sfrp saddrp !addr16 SP None 1st Operand AX ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW rp MOVW MOVW Note INCW DECW PUSH POP sfrp MOVW MOVW saddrp MOVW MOVW !addr16 MOVW SP MOVW MOVW Note Only when rp = B[...]

595 CHAPTER 28 INSTRUCTION SET (4) Call/instructions/branch instructions CALL, CALLF , CALL T , BR, BC, BNC, BZ, BNZ, BT , BF , BTCLR, DBNZ Second Operand AX !addr16 !addr1 1 [addr5] $addr16 First Operand Basic instruction BR CALL CALLF CALL T BR BR BC BNC BZ BNZ Compound BT instruction BF BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET , [...]

596 [MEMO][...]

597 APPENDIX A DIFFERENCES BETWEEN µ PD78078, 78075B SUBSERIES, AND µ PD78070A The major differences between the µ PD78078, 78075B Subseries, and µ PD78070A are shown in Table A-1. Table A-1. Major Differences between µ PD78078, 78075B Subseries, and µ PD78070A Part Number µ PD78078 Subseries µ PD78075B Subseries µ PD78070A Item Anti-EMI n[...]

598 [MEMO][...]

599 APPENDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the µ PD78078 and 78078Y Subseries. Figure B-1 shows the configuration example of the tools.[...]

600 APPENDIX B DEVELOPMENT TOOLS Figure B-1. Development Tool Configuration (1/2) (1) When using in-circuit emulator IE-78K0-NS PROM programming tool • PG-1500 controller Language processing software • Assembler package • C compiler package • C library source file • Device file Debugging tool • System simulator • Integrated debugger ?[...]

601 APPENDIX B DEVELOPMENT TOOLS Figure B-1. Development Tool Configuration (2/2) (2) When using in-circuit emulator IE-78001-R-A PROM programming tool • PG-1500 controller Language processing software • Assembler package • C compiler package • C library source file • Device file Debugging tool • System simulator • Integrated debugger[...]

602 APPENDIX B DEVELOPMENT TOOLS B.1 Language Processing Software RA78K/0 A program that converts a program written in mnemonic into object Assembler Package codes that microcomputers can process. Provided with functions to automatically perform generation of symbol table, optimizing processing of branch instructions, etc. Used in combination with [...]

603 APPENDIX B DEVELOPMENT TOOLS Remark xxxx in the part number differs depending on the host machine and OS used. µ Sxxxx RA78K0 µ Sxxxx CC78K0 µ Sxxxx DF78078 µ Sxxxx CC78K0-L xxxx Host Machine OS Supply Media AA13 PC-9800 series Japanese Windows Notes 1, 2 3.5-inch 2HD FD AB13 IBM PC/AT™ and Japanese Windows Notes 1, 2 3.5-inch 2HC FD BB13[...]

604 APPENDIX B DEVELOPMENT TOOLS B.2 PROM Writing Tools B.2.1 Hardware PG-1500 PROM Programmer PA-78P078GC PA-78P078GF PA-78P078KL-T PROM Programmer Adapter A PROM programmer that, by connecting the attached board and separately available PROM programmer adapter, is capable of programming single- chip microcomputers incorporating a PROM on stand-al[...]

605 APPENDIX B DEVELOPMENT TOOLS An in-circuit emulator to debug hardware and software when developing application systems that use the 78K/0 Series. Supports integrated debugger (ID78K0-NS). Used in combination with a power supply unit, emulation probe, and interface adapter to connect to the host machine. An adapter to supply voltage from AC100 t[...]

606 APPENDIX B DEVELOPMENT TOOLS B.3.1 Hardware (2/2) (2) When using in-circuit emulator IE-78001-R-A IE-78001-R-A Note In-circuit Emulator IE-70000-98-IF-B or IE-70000-98- IF-C Note Interface Adapter IE-70000-PC-IF-B or IE-70000-PC- IF-C Note Interface adapter IE-78000-R-SV3 Interface Adapter IE-78078-NS-EM1 Note Emulation Board IE-78K0-R-EX1 Note[...]

607 APPENDIX B DEVELOPMENT TOOLS B.3.2 Software (1/2) SM78K0 Capable of debugging in C source level or assembler level while simulating System Simulator the operation of the target system on the host machine. The SM78K0 operates on Windows. The use of the SM78K0 enables the verification of logic and performance of applications independently from ha[...]

608 APPENDIX B DEVELOPMENT TOOLS B.3.2 Software (2/2) ID78K0-NS Note Integrated debugger (supporting in-circuit emulator IE-78K0-NS) ID78K0 Integrated Debugger (supporting in-circuit emulator IE-78001-R-A) Note Under development Remark xxxx in the part number differs depending on the host machine and OS used. µ Sxxxx ID78K0-NS xxxx Host Machine OS[...]

609 APPENDIX B DEVELOPMENT TOOLS B.4 OS for IBM PC The following OSs are supported for IBM PC. Table B-1. OS for IBM PC OS Version PC DOS Ver. 5.02 to Ver. 6.3 J6.1/V Note to J6.3/V Note IBM DOS™ J5.02/V Note MS-DOS Ver. 5.0 to Ver. 6.22 5.0/V Note to 6.2/V Note Note Only English mode is supported. Caution MS-DOS ver. 5.0 or later has a task swap[...]

610 APPENDIX B DEVELOPMENT TOOLS ITEM MILLIMETERS INCHES b 1.85 ± 0.25 0.073 ± 0.010 c 3.5 0.138 a 14.45 0.569 d 2.0 0.079 h 16.0 0.630 i 1.125 ± 0.3 0.044 ± 0.012 j 0~5 ° 0.000~0.197 ° e 3.9 0.154 f 0.25 g 4.5 0.177 TGC-100SDW-G1E 0.010 k 5.9 0.232 l 0.8 0.031 m 2.4 0.094 n 2.7 0.106 ITEM MILLIMETERS INCHES B 0.5x24=12 0.020x0.945=0.472 C 0.[...]

611 APPENDIX B DEVELOPMENT TOOLS EV-9200GF-100 A D E B F 1 No.1 pin index M N O L K S R Q I H G P C J EV-9200GF-100-G0 ITEM MILLIMETERS INCHES A B C D E F G H I J K L M N O P Q R S 24.6 21 15 18.6 4-C 2 0.8 12.0 22.6 25.3 6.0 16.6 19.3 8.2 8.0 2.5 2.0 0.35 2.3 1.5 0.969 0.827 0.591 0.732 4-C 0.079 0.031 0.472 0.89 0.996 0.236 0.654 076 0.323 0.315 [...]

612 APPENDIX B DEVELOPMENT TOOLS F H E D A B C I J K L 0.026 x 1.142 = 0.742 0.026 x 0.748 = 0.486 EV-9200GF-100-P1 ITEM MILLIMETERS INCHES A B C D E F G H I J K L 26.3 21.6 15.6 20.3 12 ± 0.05 6 ± 0.05 0.35 ± 0.02 2.36 ± 0.03 2.3 1.57 ± 0.03 1.035 0.85 0.614 0.799 0.472 0.236 0.014 0.093 0.091 0.062 0.65 ± 0.02 x 29 = 18.85 ± 0.05 0.65 ± 0[...]

613 APPENDIX C EMBEDDED SOFTWARE For efficient program development and maintenance of the µ PD78078, 78078Y Subseries, the following embedded software is available. Real-time OS (1/2) RX78K/0 A real-time OS conforming to µ ITRON specifications. Real-time OS Added with the tool (configurator) to create the RX78K/0 nucleus and multiple information [...]

614 APPENDIX C EMBEDDED SOFTWARE Real-time OS (2/2) MX78K0 A µ ITRON specification subset OS. Added with MX78K0 nucleus. OS Performs task management, event management, and time management. In task management, controls the execution order of tasks and performs processing to change the task to the one executed next. <Precautions for the use in PC[...]

615 APPENDIX D REGISTER INDEX D.1 Register Name Index [A] A/D conversion result register (ADCR) ... 295 A/D converter input select register (ADIS) ... 298 A/D converter mode register (ADM) ... 296 Asynchronous serial interface mode register (ASIM) ... 462 Asynchronous serial interface status register (ASIS) ... 464 Automatic data transmit/receive a[...]

616 APPENDIX D REGISTER INDEX [E] 8-bit timer mode control register 1 (TMC1) ... 233 8-bit timer mode control register 5 (TMC5) ... 256 8-bit timer mode control register 6 (TMC6) ... 257 8-bit timer output control register (TOC1) ... 234 8-bit timer register 1 (TM1) ... 230 8-bit timer register 2 (TM2) ... 230 8-bit timer register 5 (TM5) ... 253 8[...]

617 APPENDIX D REGISTER INDEX [P] Port 0 (P0) ... 136 Port 1 (P1) ... 138 Port 2 (P2) ... 139, 141 Port 3 (P3) ... 143 Port 4 (P4) ... 144 Port 5 (P5) ... 145 Port 6 (P6) ... 146 Port 7 (P7) ... 148 Port 8 (P8) ... 150 Port 9 (P9) ... 151 Port 10 (P10) ... 153 Port 12 (P12) ... 155 Port 13 (P13) ... 156 Port mode register 0 (PM0) ... 157 Port mode [...]

618 APPENDIX D REGISTER INDEX [S] Sampling clock select register (SCS) ... 197, 510 Serial bus interface control register (SBIC) ... 325, 376 Serial I/O shift register 0 (SIO0) ... 319, 370 Serial I/O shift register 1 (SIO1) ... 417 Serial operating mode register 0 (CSIM0) ... 323, 374 Serial operating mode register 1 (CSIM1) ... 419 Serial operati[...]

619 APPENDIX D REGISTER INDEX D.2 Register Symbol Index [A] ADCR: A/D conversion result register ... 295 ADIS: A/D converter input select register ... 298 ADM: A/D converter mode register ... 296 ADTC: Automatic data transmit/receive control register ... 420 ADTI: Automatic data transmit/receive interval specify register ... 421 ADTP: Automatic dat[...]

620 APPENDIX D REGISTER INDEX IMS: Internal memory size switching register ... 532, 570 INTM0: External interrupt mode register 0 ... 196, 508 INTM1: External interrupt mode register 1 ... 299, 508 IXS: Internal extension RAM size switching register ... 571 [K] KRM: Key return mode register ... 162, 525 [M] MK0H: Interrupt mask flag register 0H ...[...]

621 APPENDIX D REGISTER INDEX PM10: Port mode register 10 ... 157, 258 PM12: Port mode register 12 ... 157, 497 PM13: Port mode register 13 ... 157 PR0H: Priority specify flag register 0H ... 507 PR0L: Priority specify flag register 0L ... 507 PR1L: Priority specify flag register 1L ... 507 PUOH: Pull-up resistor option register H ... 160 PUOL: Pul[...]

622 APPENDIX D REGISTER INDEX TMC6: 8-bit timer mode control register 6 ... 257 TMS: 16-bit timer register ... 230 TOC0: 16-bit timer output control register ... 194 TOC1: 8-bit timer output control register ... 234 TXS: Transmit shift register ... 460 [W] WDTM: Watchdog timer mode register ... 280[...]

623 APPENDIX E REVISION HISTORY The revision history is shown below. The chapters appearing in the chapter column indicate those of the corresponding edition. Version Major revisions from previous version Chapter Second µ PD78076, 78078, 78P078: Under development → Developed µ PD78074, 78075, 78074Y, 78075Y, 78076Y, 78078Y, 78P078Y have been ad[...]

624 APPENDIX E REVISION HISTORY Version Major revisions from previous version Chapter Second Table 24-1. HALT Mode Operating Status has been modified. Table 24-3. STOP Mode Operating Status has been modified. CHAPTER 26 ROM CORRECTION has been added. The development statuses for the following products have been changed from “Under Development” [...]

625 APPENDIX E REVISION HISTORY Edition Major revisions from previous edition Chapter Fourth The following products have been changed from “under development” to “already developed”. µ PD78078Y Subseries: µ PD78076Y, 78078Y, 78P078Y The following package has been added to the µ PD78078Y Subseries. 100-pin plastic LQFP (Fine pitch) (14 x [...]

626 [MEMO][...]

Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation. Please complete this form whenever you'd like to report error[...]