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NXP Semiconductors PCA9665 manuel d'utilisation

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Table des matières du manuel d’utilisation

  • Page 1

    1. General description The PCA9665 ser v es as an interf ace between most standard parallel-b us microcontrollers/microprocessors and the serial I 2 C-bus and allows the par allel b us system to communicate bidirectionally with the I 2 C-b us. The PCA9665 can oper ate as a master or a slav e and can be a tr ansmitter or receiv er . Communication wi[...]

  • Page 2

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 2 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 3. Applications n Add I 2 C-bus port to controllers/processors that do not have one n Add additional I 2 C-bus ports to controllers/processors that need multiple I 2 C-bus por[...]

  • Page 3

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 3 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 5. Bloc k diagram Fig 1. Block dia gram of PCA9665 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 I2CD A T – data register – read/wr ite BUS BUFFER SD A CONTROL AA ENSIO ST A ST O SI SCL[...]

  • Page 4

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 4 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 6. Pinning inf ormation 6.1 Pinning Fig 2. Pin configuration of SO20 Fig 3. Pin configuration of TSSOP20 Fig 4. Pin configuration of DIP20 Fig 5. Pin configuration of HVQF[...]

  • Page 5

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 5 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 6.2 Pin description [1] HVQFN package die supply ground is connected to both the V SS pin and the e xposed center pad. The V SS pin must be connected to supply ground f or pro[...]

  • Page 6

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 6 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 7. Functional description 7.1 General The PCA9665 acts as an interf ace de vice between standard high-speed par allel buses and the serial I 2 C-bus. On the I 2 C-b us, it can[...]

  • Page 7

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 7 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller T able 4. Indirect register selection by setting A1 = 1 and A0 = 0 Register name Register function INDPTR Read/Write Default I2CCOUNT byte count 00h R/W 01h I2CADR own address[...]

  • Page 8

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 8 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 7.3.1 Direct registers 7.3.1.1 The Status register , I2CST A (A1 = 0, A0 = 0) I2CST A is an 8-bit read-only register . The two least significant bits are alw a ys zero . The [...]

  • Page 9

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 9 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller In Byte mode, the CPU can read or write a single byte at a time . In Buff ered mode, the CPU can read or write up to 68 bytes at a time. See Section 8.1 “Configur ation mod[...]

  • Page 10

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 10 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller T able 12. I2CCON - Control register (A1 = 1, A0 = 1) bit description Bit Symbol Description 7 AA The Asser t Acknowledge flag. AA = 1: If the AA flag is set, an acknowledg[...]

  • Page 11

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 11 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller Remark: ENSIO bit v alue must be changed only when the I 2 C-b us is idle. 7.3.1.5 The indirect data field access register , INDIRECT (A1 = 1, A0 = 0) The registers in the i[...]

  • Page 12

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 12 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 7.3.2 Indirect registers 7.3.2.1 The Byte Count register , I2CCOUNT (indirect address 00h) The I2CCOUNT register is an 8-bit read/write register . It contains the number of b[...]

  • Page 13

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 13 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 7.3.2.3 The Clock Rate register s, I2CSCLL and I2CSCLH (indirect addresses 02h and 03h) I2CSCLL and I2CSCLH are 8-bit read/write registers. They define the data r ate f or t[...]

  • Page 14

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 14 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 7.3.2.4 The Time-out register , I2CT O (indirect address 04h) I2CT O is an 8-bit read/wr ite register . It is used to deter mine the maximum time that SCL is allow ed to be i[...]

  • Page 15

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 15 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 7.3.2.6 The I 2 C-bus mode register , I2CMODE (indirect address 06h) I2CMODE is an 8-bit read/write register . It contains the control bits that select the correct timing par[...]

  • Page 16

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 16 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 8. PCA9665 modes 8.1 Configuration modes Byte mode and Buff ered mode are selected using the MODE bit in I2CCON register : MODE = 0: Byte mode MODE = 1: Buff ered mode 8.1.1[...]

  • Page 17

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 17 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller P — ST OP condition In Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 , circles are used to indicate when the serial interr up[...]

  • Page 18

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 18 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller • B0h if the PCA9665 lost the arbitration and is addressed as a sla ve transmitter (sla v e mode enabled with AA = 1) • 68h if the PCA9665 lost the arbitration and is add[...]

  • Page 19

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 19 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller (1) See T able 27 (2) Defined state when a single byte is sent and an A CK is received. (3) Defined state when a single byte is sent and a NA CK is received. (4) Master Rec[...]

  • Page 20

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 20 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller T able 27. Master T ransmitter Byte mode (MODE = 0) Status code (I2CST A) Status of the I 2 C-bus and the PCA9665 Application software response Next action taken b y the PCA9[...]

  • Page 21

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 21 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 30h Data byte in I2CD A T has been transmitted; NA CK has been received Load data byte or 0 0 0 X 0 Data byte will be transmitted; A CK/NA CK will be receiv ed no I2CD A T ac[...]

  • Page 22

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 22 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 8.3.2 Master Receiver Byte mode In the Master Receiver Byte mode , a number of data bytes are receiv ed from a sla v e transmitter one b yte at a time (see Figure 8 ). The tr[...]

  • Page 23

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 23 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller (1) See T able 28 . (2) Defined state when a single byte is receiv ed and an ACK is sent (AA = 1). (3) Defined state when a single byte is receiv ed and a NACK is sent (AA [...]

  • Page 24

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 24 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller T able 28. Master Receiver Byte mode (MODE = 0) Status code (I2CST A) Status of the I 2 C-bus and the PCA9665 Application software response Next action taken b y the PCA9665 [...]

  • Page 25

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 25 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 8.3.3 Slave Receiver Byte mode In the Slav e Receiver Byte mode , a number of data b ytes are receiv ed from a master transmitter one b yte at a time (see Figure 9 ). T o ini[...]

  • Page 26

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 26 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller (1) See T able 31 . (2) Defined state when a single byte is receiv ed and an ACK is sent (AA = 1). (3) Defined state when a single byte is receiv ed and a NACK is sent (AA [...]

  • Page 27

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 27 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller T able 31. Slave Receiver Byte mode (MODE = 0) Status code (I2CST A) Status of the I 2 C-bus and the PCA9665 Application software response Next action taken b y the PCA9665 T[...]

  • Page 28

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 28 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller E0h Pre viously addressed with General Call; Data has been received; A CK has been returned Read data byte or X X 0 0 0 Data byte will be received and NA CK will be returned.[...]

  • Page 29

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 29 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 8.3.4 Slave T ransmitter Byte mode In the Slav e T ransmitter Byte mode, a n umber of data b ytes are transmitted to a master receiv er one byte at a time (see Figure 10 ). D[...]

  • Page 30

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 30 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller T able 32. Slave T ransmitter Byte mode (MODE = 0) Status code (I2CST A) Status of the I 2 C-bus and the PCA9665 Application software response Next action taken by PCA9665 T [...]

  • Page 31

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 31 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 8.4 Buffered mode 8.4.1 Master T ransmitter Buffered mode In the Master T ransmitter Buffered mode , a number of data b ytes are transmitted to a slav e receiver se veral b y[...]

  • Page 32

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 32 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller • 30h if the slav e address with direction bit has been successfully sent and no ackno wledgement (NACK) has been receiv ed while transmitting the data b ytes (number of to[...]

  • Page 33

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 33 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller (1) See T able 35 (2) Serial interrupt that occurs when BC[6:0] = 01. No ser ial interrupt if BC[6:0] > 01. (3) Defined state when the number of bytes sent is equal to th[...]

  • Page 34

    xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxx[...]

  • Page 35

    xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxx[...]

  • Page 36

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 36 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 8.4.2 Master Receiver Buffered mode In the Master Receiver Buff ered mode, a number of data b ytes are received from a slav e transmitter se veral b ytes at a time (see Figur[...]

  • Page 37

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 37 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller (1) See T able 28 . (2) No serial interrupt. (3) Defined state when LB = 0 and the number of b ytes receiv ed is equal to the value in I2CCOUNT register . (4) Defined state[...]

  • Page 38

    xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxx[...]

  • Page 39

    xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxx[...]

  • Page 40

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 40 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 8.4.3 Slave Receiver Buffered mode In the Slav e Receiver Buff ered mode, a number of data b ytes are receiv ed from a master transmitter se veral b ytes at a time (see Figur[...]

  • Page 41

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 41 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller If the LB bit is reset (logic 0), the PCA9665 will retur n an ackno wledge for all the b ytes that will be receiv ed. The maximum number of b ytes that are received in a sing[...]

  • Page 42

    xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxx[...]

  • Page 43

    xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxx[...]

  • Page 44

    xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxx[...]

  • Page 45

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 45 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 8.4.4 Slave T ransmitter Buffered mode In the Slav e T ransmitter Buff ered mode, a number of data b ytes are transmitted to a master receiv er se v eral b ytes at a time (se[...]

  • Page 46

    xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxx[...]

  • Page 47

    xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxx[...]

  • Page 48

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 48 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 8.5 Buffered mode e xamples 8.5.1 Buffered Master T ransmitter mode of operation 1. Program the I2CCOUNT register with the n umber of b ytes that need to be sent to the I 2 C[...]

  • Page 49

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 49 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 3. Program I2CCON register to initiate the Master Receiv er Buffered sequence . In Master mode, if ST A = 1, a ST AR T command is sent. An interr upt will be asser ted and th[...]

  • Page 50

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 50 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 6. More sequences (program I2CCOUNT register , load data b ytes in I2CD A T buff er , write the I2CCON register to send the data to the I 2 C-bus, read the I2CST A register w[...]

  • Page 51

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 51 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller – the SCL line is held LO W by the PCA9665 after the 2 bytes ha ve been sent – the PCA9665 sends an Interrupt, sets SI = 1 and updates I2CST A register – I2CST A reads [...]

  • Page 52

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 52 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller In Buff ered Receiv er mode, when an interrupt is generated and SI is set to 1 (after a ST OP command or a buff er full condition), the buff er pointer is reset and points at[...]

  • Page 53

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 53 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller Remark: Request to send or receive a n umber of b ytes equal to 0 or higher than 68 (BC[6:0] = 000 0000 or BC[6:0] > 100 0100) will cause no data to be transf erred and an[...]

  • Page 54

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 54 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller T able 44. Unbuffered Mode (MODE = 0) Control bits LB = x AA = 0 Master T ransmitter mode • address/data are transmitted on a b yte basis Master Receiv er mode • address [...]

  • Page 55

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 55 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller T able 45. Buffered Mode (MODE = 1) Control bits L B=0 L B=1 AA = 0 Master T ransmitter mode • address/data are transmitted on a multiple b yte basis = BC[6:0] value Master[...]

  • Page 56

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 56 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller AA = 1 Master T ransmitter mode • address/data are transmitted on a multiple b yte basis = BC[6:0] value Master Receiver mode • address is transmitted and data are receiv[...]

  • Page 57

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 57 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 8.8 Miscellaneous states There are f our I2CST A codes that do not correspond to a defined PCA9665 state (see T able 46 ). These are discussed in Section 8.8.1 through Secti[...]

  • Page 58

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 58 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 8.8.4 I2CST A = 78h This status code indicates that the SCL line is stuck LO W . 8.9 Some special cases The PCA9665 has f acilities to handle the f ollowing special cases tha[...]

  • Page 59

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 59 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 8.9.4 I 2 C-bus obstructed b y a LO W level on SCL or SD A An I 2 C-bus hang-up occurs if SD A or SCL is pulled LO W by an uncontrolled source . If the SCL line is obstructed[...]

  • Page 60

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 60 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 8.9.5 Bus error A bus error occurs when a ST AR T or ST OP condition is present at an illegal position in the f ormat frame. Examples of illegal positions are during the ser [...]

  • Page 61

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 61 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 8.11 Reset Reset of the PCA9665 to its def ault state can be perf ormed in 2 different w a ys: • By holding the RESET pin LO W f or a minimum of t w(rst) . • By using the[...]

  • Page 62

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 62 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller Master PCA9665 reads data from slav e transmitter. Fig 20. Bus timing diagram; Unbuff ered Master Receiver mode n byte ACK SCL SD A INT ST ART condition 7-bit address R/W = 1[...]

  • Page 63

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 63 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 8.13 I 2 C-bus timing dia grams, Buffered mode The diagrams ( Figure 23 through Figure 26 ) illustr ate typical timing diagrams f or the PCA9665 in master/slav e functions. M[...]

  • Page 64

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 64 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller External master receiver reads data from PCA9665. (1) As defined in I2CADR register . (2) Number of bytes receiv ed = value programmed in I2CCOUNT register (BC[6:0] ≤ 68).[...]

  • Page 65

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 65 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 9. Characteristics of the I 2 C-b us The I 2 C-bus is f or 2-wa y , 2-line comm unication between diff erent ICs or modules. The two lines are a serial data line (SD A) and a[...]

  • Page 66

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 66 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 9.3 Ac knowledge The number of data b ytes transf erred between the ST AR T and the STOP conditions from transmitter to receiv er is not limited. Each byte of eight bits is f[...]

  • Page 67

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 67 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 10. Application design-in inf ormation 10.1 Specific applications The PCA9665 is a parallel b us to I 2 C-b us controller that is designed to allow ‘smar t’ de vices to [...]

  • Page 68

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 68 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 10.3 Add additional I 2 C-b us por ts The PCA9665 can be used to conv er t 8-bit parallel data into additional multiple master capable I 2 C-b us por t as shown in Figure 34 [...]

  • Page 69

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 69 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 11. Limiting v alues [1] 5.5 V steady state v oltage tolerance on inputs and outputs is v alid only when the supply v oltage is present. 4.6 V steady state voltage tolerance [...]

  • Page 70

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 70 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 12. Static characteristics [1] 5.5 V steady state v oltage tolerance on inputs and outputs is v alid only when the supply v oltage is present. 4.6 V steady state voltage tole[...]

  • Page 71

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 71 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 13. Dynamic characteristics [1] Parameters are v alid over specified temperature and v oltage range. [2] All voltage measurements are ref erenced to ground (GND). F or testi[...]

  • Page 72

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 72 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller [1] Parameters are v alid over specified temperature and v oltage range. [2] All voltage measurements are ref erenced to ground (GND). F or testing, all inputs s wing betwee[...]

  • Page 73

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 73 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller Fig 36. Reset timing SD A SCL 002aab272 t rst 50 % 30 % 50 % 50 % 30 % t rec(rst) t w(rst) RESET Dn Dn off ST ART t rst ACK or read cycle 30 % Dn on 30 % Fig 37. Interrupt ti[...]

  • Page 74

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 74 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller Fig 38. Bus timing (read cycle) Fig 39. Parallel b us timing (write cycle) A0 to A1 CE RD D0 to D7 (read) 002aac693 t su(A) t h(A) t su(CE_N) t h(CE_N) t w(RDL) t w(RDH) floa[...]

  • Page 75

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 75 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller V M = 1.5 V V X =V OL + 0.3 V V Y =V OH − 0.3 V V OL and V OH are typical output voltage drops that occur with the output load. Fig 40. Data timing 002aab274 t d(QLZ) t d(Q[...]

  • Page 76

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 76 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller [1] Minimum SCL clock frequency is limited by the b us time-out feature, which resets the serial bus interf ace if either SDA or SCL is held LOW f or a minimum of 25 ms. Disa[...]

  • Page 77

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 77 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller Fig 41. Definition of timing on the I 2 C-bus SD A SCL 002aab271 t f S Sr P S t HD;ST A t LOW t r t SU;DA T t f t HD;DA T t HIGH t SU;ST A t HD;ST A t SP t SU;STO t r t BUF [...]

  • Page 78

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 78 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 14. T est information T est data are given in T able 52 . R L = load resistance. C L = load capacitance includes jig and probe capacitance. R T = ter mination resistance shou[...]

  • Page 79

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 79 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 15. P acka ge outline Fig 45. Pac kage outline SOT146-1 (DIP20) UNIT A max. 1 2 b 1 cD E e M H L REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm [...]

  • Page 80

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 80 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller Fig 46. Pac kage outline SOT163-1 (SO20) UNIT A max. A 1 A 2 A 3 b p cD (1) E (1) (1) eH E LL p Q Z y w v θ REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JED[...]

  • Page 81

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 81 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller Fig 47. Pac kage outline SOT360-1 (TSSOP20) UNIT A 1 A 2 A 3 b p cD (1) E (2) (1) eH E LL p QZ y w v θ REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JE[...]

  • Page 82

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 82 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller Fig 48. Pac kage outline SOT662-1 (HVQFN20) 0.65 1 A 1 E h b UNIT y e 0.2 c REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 5.1 4.9 D h 3.25 2.95[...]

  • Page 83

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 83 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 16. Handling inf ormation Inputs and outputs are protected against electrostatic discharge in nor mal handling. Howe ver , to be completely saf e you must tak e normal precau[...]

  • Page 84

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 84 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller packages and/or boards are not damaged. The peak temper ature of the package depends on package thic kness and volume and is classified in accordance with T able 54 and 55 M[...]

  • Page 85

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 85 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 17.3.2 W ave soldering Conv entional single wav e solder ing is not recommended f or surf ace mount de vices (SMDs) or printed-circuit boards with a high component density , [...]

  • Page 86

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 86 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller [1] For more detailed inf ormation on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from y our NXP Semiconductors sales office. [2] All surf[...]

  • Page 87

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 87 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 18. Abbreviations 19. Revision history T able 57. Abbreviations Acron ym Description ASIC Application Specific Integrated Circuit CDM Charged De vice Model CPU Central Proce[...]

  • Page 88

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 88 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller Modifications: (continued) • T able 49 , sub-section “Bus timing”: – changed Min value f or t h(A) from 7 ns to 13 ns – changed Min value f or t w(RDL) from 7 ns t[...]

  • Page 89

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 89 of 91 NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 20. Legal inf ormation 20.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘shor t data sheet[...]

  • Page 90

    PCA9665_2 © NXP B.V . 2006. All rights reserved. Product data sheet Rev . 02 — 7 December 2006 90 of 91 continued >> NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1[...]

  • Page 91

    NXP Semiconductors PCA9665 Fm+ parallel bus to I 2 C-b us controller © NXP B.V . 2006. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 7 December 2006 Document identifier: PCA9665_2 Please be aware that important notices concern[...]