Samsung KFN4G16Q2A manuel d'utilisation

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 1 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) KFM2G16Q2A KFN4G16Q2A 2Gb MuxOneNAND A-die INFORMA TION IN THIS DOCUMENT IS PROVID ED IN RELA TION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 2 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Revision History Document Title MuxOneNAND Revision History Revision No. History Draft Date Remark 0.0 0.1 0.2 1.0 1.1 1.1 1 1.2 1. Initial issue. 1. Corrected errata. 2. Chapter 3.3.1 Cold Reset Mode Operation re vised. 3. Chapter 6.17 Cold Reset Timing revised. 4. Chap[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 3 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Revision No. Histo ry Draf t Dat e Remark 1.3 1. Corrected errata. 2. Chapter 2.8.18 Command Register F220h (R /W) revised. 3. Chapter 3.4.3 NAND Array Write Protection states revised. 4. Chapter 3.4.3.3 Locked-tight NAND Array Write Protection S tate revised. Dec. 16, 2[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 4 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 1.0 INTRODUCTION This specification contains information about the Samsung Electronics Company MuxOneNAND  ‚ Flash memory product family . Section 1.0 includes a general overview , revision history , and product ordering information. Section 2.0 describes the MuxOne[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 5 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 1.2 Ordering Information 1.3 Architectural Benefit s MuxOneNAND is a highly integrated non-volatile memory solution based around a NAND Flash memory arr ay . The chip integrates system features including:  A BootRAM and bootloader  T wo independen[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 6 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 1.4 Product Features Device Architecture  Design T echnology:  Supply V oltage:  Host Interface:  5KB Internal BufferRAM:  SLC NAND Array: Device Performance  Host Interface Ty pe:  Progr[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 7 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 1.5 General Overview MuxOneNAND  ‚ is a monolithic integrated circui t with a NAND Flash array using a NOR Flash inte rface. T his device in cludes control logic, a NAND Flash array , and 5KB of internal BufferRAM. The BufferRAM reserves 1KB for boot code buffering [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 8 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.0 DEVICE DESCRIPTION 2.1 Det ailed Product Description The MuxOneNAND is an advanced generation, high-performance NAND- based Flash memory . It integrates on-chip a single-level-cell (SLC) NAND Flash Ar ray memory with two independen t data buffers, boot RAM buf fer , [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 9 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.3 Pin Configuration 2.3.1 2Gb Product (KFM2 G16Q2A) (TOP VIEW , Balls Fac ing Down) 63ball FBGA MuxOneNAND Chip 63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch FBGA NC NC NC NC INT NC NC NC NC NC NC NC NC WE RP ADQ1 V SS V SS ADQ2 ADQ3 ADQ7 ADQ14 OE ADQ6 V CC ADQ8 [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 10 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.3.2 4Gb Product (KFN4G16Q2A) (TOP VIEW , Balls Fac ing Down) 63ball FBGA MuxOneNAND Chip 63ball, 10mm x 13mm x max 1.2mmt , 0.8mm ball pitch FBGA NC NC NC NC INT NC NC NC NC NC NC NC NC WE RP ADQ1 V SS V SS ADQ2 ADQ3 ADQ7 ADQ14 OE ADQ6 V CC ADQ8 ADQ1 1 ADQ4 ADQ5 ADQ12[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 11 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.4 Pin Description NOTE : Do not leave power supply(Vcc-Core/Vcc-IO, V SS ) disco nnected. Pin Name Ty p e Name and Description Host Interface ADQ15~ADQ0 I/O Multiplexed Address/Data bus - Inputs for addresses during read operation, wh ich are for addressing BufferRAM [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 12 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.5 Block Diagram 2.6 Memory Array Organization The MuxOneNAND architecture integrates several memory areas on a single chip. 2.6.1 Internal (NAND Arra y) Me mory Organization The on-chip internal memory is a single-level-cell (SLC) NAND array used for data storage and [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 13 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Internal Memory Array Information Internal Memory Array Organization Area Block Page Sector Main 128KB 2KB 512B S pare 4KB 64B 16B 2KB Page0 512B 16B 64B Page0 2KB Page63 64B Page63 Sector Main Area Spare Area Block Page Main Area Spare Area 2KB 64B Main Area Spare Area[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 14 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.6.2 External (Buff erRAM) Memory Organization The on-chip external memory is comprised o f 3 buf fers used for Boot Code storage and data buffering. The BootRAM is a 1KB buffer that receives Boot Code from the in ternal memory and makes it available to the host at sta[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 15 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) External Memory Array Organization BootRAM 0 BootRAM 1 BootRAM DataRAM 1_0 DataRAM 1_1 DataRAM 1_2 DataRAM 1_3 DataR AM1  Main area data Spare area data DataRAM 0_0 DataRAM 0_1 DataRAM 0_2 DataRAM 0_3 DataRAM0 Sector: (512 + 16) Byte  (512B) (16B)[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 16 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.7 Memory Map The following tables are the memory maps for the MuxOneNAND. 2.7.1 Internal (NAND Array) Memo ry Organization The following tables show the Internal Memory address map in word order. Block Block Address Page and Sector Address Size Block Block Address Pag[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 17 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page a nd Sector Address Size Block Block Addre ss Page and Sect or Address Size Block64 0040h 0000h~00FFh 128KB Block96 0060h 0000h~00FFh 128KB Block65 0041h 0000h~00FFh 128KB Block97 0061h 0000h~00FFh 128KB Block66 0042h 0000h~00FFh 128KB Block98 0[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 18 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block128 0080h 0000h~00F Fh 128KB Block160 00A0h 0000h~00FFh 128KB Block129 0081h 0000h~00F Fh 128KB Block161 00A1h 0000h~00FFh 128KB Block130 0082h 0000h~00F Fh 128KB Bl[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 19 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block192 00C0h 0000h~00FFh 128KB Block224 00E0h 0000h~00FFh 128KB Block193 00C1h 0000h~00FFh 128KB Block225 00E1h 0000h~00FFh 128KB Block194 00C2h 0000h~00FFh 128KB Block[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 20 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block256 0100h 0000h~00FFh 128KB Block288 0120h 0000h~00FFh 128KB Block257 0101h 0000h~00FFh 128KB Block289 0121h 0000h~00FFh 128KB Block258 0102h 0000h~00FFh 128KB Block[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 21 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block320 0140h 0000h~00FFh 128KB Block352 0160h 0000h~00FFh 128KB Block321 0141h 0000h~00FFh 128KB Block353 0161h 0000h~00FFh 128KB Block322 0142h 0000h~00FFh 128KB Block[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 22 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block384 0180h 0000h~00FFh 128KB Block416 01A0h 0000h~00FFh 128KB Block385 0181h 0000h~00FFh 128KB Block417 01A1h 0000h~00FFh 128KB Block386 0182h 0000h~00FFh 128KB Block[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 23 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block448 01C0h 0000h~00FFh 128KB Block480 01E0h 0000h~00FFh 128KB Block449 01C1h 0000h~00FFh 128KB Block481 01E1h 0000h~00FFh 128KB Block450 01C2h 0000h~00FFh 128KB Block[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 24 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block512 0200h 0000h~00FFh 128KB Block544 0220h 0000h~00FFh 128KB Block513 0201h 0000h~00FFh 128KB Block545 0221h 0000h~00FFh 128KB Block514 0202h 0000h~00FFh 128KB Block[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 25 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block576 0240h 0000h~00FFh 128KB Block608 0260h 0000h~00FFh 128KB Block577 0241h 0000h~00FFh 128KB Block609 0261h 0000h~00FFh 128KB Block578 0242h 0000h~00FFh 128KB Block[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 26 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block640 0280h 0000h~00FFh 128KB Block672 02A0h 0000h~00FFh 128KB Block641 0281h 0000h~00FFh 128KB Block673 02A1h 0000h~00FFh 128KB Block642 0282h 0000h~00FFh 128KB Block[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 27 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block704 02C0h 0000h~00FFh 128KB Block736 02E0h 0000h~00FFh 128KB Block705 02C1h 0000h~00FFh 128KB Block737 02E1h 0000h~00FFh 128KB Block706 02C2h 0000h~00FFh 128KB Block[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 28 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block768 0300h 0000h~00FFh 128KB Block800 0320h 0000h~00FFh 128KB Block769 0301h 0000h~00FFh 128KB Block801 0321h 0000h~00FFh 128KB Block770 0302h 0000h~00FFh 128KB Block[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 29 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block832 0340h 0000h~00FFh 128KB Block864 0360h 0000h~00FFh 128KB Block833 0341h 0000h~00FFh 128KB Block865 0361h 0000h~00FFh 128KB Block834 0342h 0000h~00FFh 128KB Block[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 30 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block896 0380h 0000h~00FFh 128KB Block928 03A0h 0000h~00FFh 128KB Block897 0381h 0000h~00FFh 128KB Block929 03A1h 0000h~00FFh 128KB Block898 0382h 0000h~00FFh 128KB Block[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 31 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block960 03C0h 0000h~00FFh 128KB Block992 03E0h 0000h~00FFh 128KB Block961 03C1h 0000h~00FFh 128KB Block993 03E1h 0000h~00FFh 128KB Block962 03C2h 0000h~00FFh 128KB Block[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 32 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1024 0400h 0000h~00FFh 128KB Block1056 0420h 0000h~00FFh 128KB Block1025 0401h 0000h~00FFh 128KB Block1057 0421h 0000h~00FFh 128KB Block1026 0402h 0000h~00FFh 128KB [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 33 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1088 0440h 0000h~00FFh 128KB Block1 120 0460h 0000h~00FF h 128KB Block1089 0441h 0000h~00FFh 128KB Block1 121 0461h 0000h~00FF h 128KB Block1090 0442h 0000h~00FFh 12[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 34 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1 152 0480h 0000h~00FFh 128KB Block1 184 04A0h 0000h~00FFh 128KB Block1 153 0481h 0000h~00FFh 128KB Block1 185 04A1h 0000h~00FFh 128KB Block1 154 0482h 0000h~00FFh 1[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 35 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1216 04C0h 0000h~00FFh 128KB Block1248 04E0h 0000h~00FF h 128KB Block1217 04C1h 0000h~00FFh 128KB Block1249 04E1h 0000h~00FF h 128KB Block1218 04C2h 0000h~00FFh 128K[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 36 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1280 0500h 0000h~00FFh 128KB Block1312 0520h 0000h~00FFh 128KB Block1281 0501h 0000h~00FFh 128KB Block1313 0521h 0000h~00FFh 128KB Block1282 0502h 0000h~00FFh 128KB [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 37 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1344 0540h 0000h~00FFh 128KB Block1376 0560h 0000h~00FFh 128KB Block1345 0541h 0000h~00FFh 128KB Block1377 0561h 0000h~00FFh 128KB Block1346 0542h 0000h~00FFh 128KB [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 38 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1408 0580h 0000h~00FFh 128KB Block1440 05A0h 0000h~00FF h 128KB Block1409 0581h 0000h~00FFh 128KB Block1441 05A1h 0000h~00FF h 128KB Block1410 0582h 0000h~00FFh 128K[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 39 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1472 05C0h 0000h~00FFh 128KB Block1504 05E0h 0000h~00FF h 128KB Block1473 05C1h 0000h~00FFh 128KB Block1505 05E1h 0000h~00FF h 128KB Block1474 05C2h 0000h~00FFh 128K[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 40 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1536 0600h 0000h~00FFh 128KB Block1568 0620h 0000h~00FFh 128KB Block1537 0601h 0000h~00FFh 128KB Block1569 0621h 0000h~00FFh 128KB Block1538 0602h 0000h~00FFh 128KB [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 41 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1600 0640h 0000h~00FFh 128KB Block1632 0660h 0000h~00FFh 128KB Block1601 0641h 0000h~00FFh 128KB Block1633 0661h 0000h~00FFh 128KB Block1602 0642h 0000h~00FFh 128KB [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 42 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1664 0680h 0000h~00FFh 128KB Block1696 06A0h 0000h~00FF h 128KB Block1665 0681h 0000h~00FFh 128KB Block1697 06A1h 0000h~00FF h 128KB Block1666 0682h 0000h~00FFh 128K[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 43 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1728 06C0h 0000h~00FFh 128KB Block1760 06E0h 0000h~00FF h 128KB Block1729 06C1h 0000h~00FFh 128KB Block1761 06E1h 0000h~00FF h 128KB Block1730 06C2h 0000h~00FFh 128K[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 44 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1792 0700h 0000h~00FFh 128KB Block1824 0720h 0000h~00FFh 128KB Block1793 0701h 0000h~00FFh 128KB Block1825 0721h 0000h~00FFh 128KB Block1794 0702h 0000h~00FFh 128KB [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 45 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1856 0740h 0000h~00FFh 128KB Block1888 0760h 0000h~00FFh 128KB Block1857 0741h 0000h~00FFh 128KB Block1889 0761h 0000h~00FFh 128KB Block1858 0742h 0000h~00FFh 128KB [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 46 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sec tor Address Size Block Block Address Page and Sector Address Size Block1920 0780h 0000h~00FFh 128KB Block1952 07A0h 0000h~00F Fh 128KB Block1921 0781h 0000h~00FFh 128KB Block1953 07A1h 0000h~00F Fh 128KB Block1922 0782h 0000h~00FFh 128KB[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 47 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Block Block Address Page and Sector Address Size Block Block Addre ss Page and Sect or Address Size Block1984 07C0h 0000h~00FFh 128KB Block2016 07E0h 0000h~00FF h 128KB Block1985 07C1h 0000h~00FFh 128KB Block2017 07E1h 0000h~00FF h 128KB Block1986 07C2h 0000h~00FFh 128K[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 48 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.7.2 lnternal Memor y Sp are Area Assignment The figure below shows the assignment of the sp are area in the Internal Memory NAND Arr ay . Sp are Area Assignment in the Internal Memo ry NAND Array Information NOTE 5 : In case of ECC Bypass Mode, user can pro gram in EC[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 49 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.7.3 External Memory (Buffe rRAM) Address Map The following table shows the External Me mory address map in Word and Byte Order. Note that the data output is unknown while host reads a register bit of reserved area. Division Address (word order) Address (byte order) Si[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 50 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.7.4 External Memory Map Detail Information The tables below show Word Order Address Map inform ation for the BootRAM and DataRAM main and spare areas.  BootRAM(Main area) -0000h~01FFh: 2(sector) x 512byte(NAND main area) = 1KB  DataRAM(Main area) -0200h~09FFh: 8[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 51 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.7.5 External M emory Sp are Area Assig nment Buf. Wor d Address Byte Address F E D C B A 9 8 7 6 5 4 3 2 1 0 BootS 0 8000h 10000h BI 8001h 10002h Managed by Internal ECC logic 8002h 10004h Reserved for the future use Managed by Internal ECC logic 8003h 10006h Reserved[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 52 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Buf. Word Address Byte Address F E D C B A 9 8 7 6 5 4 3 2 1 DataS 0_2 8020h 10040h BI 8021h 10042h Managed by Internal ECC logic 8022h 10044h Reserved for the future use Managed by Internal ECC logic 8023h 10046h Reserved for the current and future use 8024h 10048h ECC[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 53 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) NOTE : - BI: Bad block Information >Host can use complete spare area except BI and ECC code area. For example, Host can write data to Spare area buffer except for the area controlled by ECC logic at program operation. >In case of ‘with ECC’ mode, MuxOneNAND au[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 54 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8 Registers Section 2.8 of this specification provides information about the MuxOneNAND registers. 2.8.1 Register Addre ss Map This map describes the register addresses, register name, register description, and host accessibility . Address (word orde r) Address (byte [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 55 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.2 Manufact urer ID Register F000h (R) This Read register describes the manufacturer's identification. Samsung Electronics Company manufacturer's ID is 00ECh. F000h, default = 00ECh Address (word orde r) Address (byte order) Name Host Access Description F24[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 56 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.3 Devic e ID Regi ster F001h ( R) This Read register describes the device. F001h, see table for default. Device Identification Device ID Default 15 14 13 12 11 10 98 76543210 DeviceID Device Identification Description DeviceID [1:0] Vcc 00 = 1.8V , 01/10/1 1 = rese [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 57 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.4 V ersion ID Register F002h This Register is reserved for internal use. 2.8.5 Dat a Buffer Size Register F003h ( R) F003h, default = 0800h Data Buffer Size Information 15 14 13 12 11 10 98 76543210 DataBufSize Register Information Description DataBufSize T otal dat[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 58 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.6 Boot Buffer Size Register F004h (R) This Read register describes the size of the Boot Buffer . F004h, default = 0200h 2.8.7 Numb er of Buffers Register F005h (R) This Read register describes the number of each Buffer . F005h, default = 0201h Number of Buffers Info[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 59 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.9 S t art Address1 Register F100h (R/W) This Read/Write register describes the NAND Flash bl ock addr ess which will be loaded, programmed, or erased. F100h, default = 0000h NOTE : 1) Bit 0 should be fixed ‘low’ at 2X Program an d 2X Cache Program . St art Addre[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 60 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.1 1 St art Addres s3 Register F102h (R/W) This Read/Write register describes the NA ND Flash destination block address which will be copy back programmed. Also, this regi ster indi- cates the block address for the first page to be read in Cache Read Operation. F102h[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 61 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.13 S t art Address5 Registe r F104h (R/W) This Read/Write register describes the num ber of page in Synchronous Burst Block Read. F104h, default = 0000h Flash Page Count (FPC) Info rmation NOTE : Synchronous Burst Block Read are NOT able to be perforformed with 1 or[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 62 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.17 S t art Buffer Register F200h (R/W) This Read/Write register describes the BufferRAM Se ctor Count (BSC) and BufferRAM Sector Address (BSA). The BufferRAM Sector Count ( BSC) field specifies the number of sectors to be loaded, pro grammed, or copy back programmed[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 63 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.18 Comman d Register F220h (R/W ) Command can be issued by two following methods, and use r ma y select one way or the other to issue appropriate command; 1. Write command into Command Register when INT is at ready stat e. INT w ill automatically turn to busy state [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 64 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.18.1 T wo Methods to Clear Interrupt Register in Command Input T o clear Interrupt Register in command input, user may select one from either following me thods. First method is to turn INT low by manually wr iting 0000h to INT bit of Interrupt Register. 1) Second m[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 65 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.19 System Configu ration 1 Register F221h (R, R/W) This Read/Write register descri bes the system configuration. F221h, default = 40C0h Read Mode (RM) Read Mode Information[15] Burst Read Write Latency (BRWL) * Default value of BRWL and HF value is BRWL=4, HF=0. For[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 66 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Burst Length (BL) Hosts must follow burst length set by BL when reading data in synchronous burst read. NOTE : 1) For normal synchronous burst read, setti ng BL=000 (continuous) will read 1K words, depending on th e number of clocks. In usi ng Synchronous Burst Bl ock R[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 67 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) I/O Buffer Enable (IOBE) IOBE is the I/O Buffer Enable for the INT and RDY signals. At startup, INT and RDY outputs are High-Z. Bits 6 and 7 become vali d after IOBE is set to "1". IOBE can be reset by a Cold Reset or by writing "0" to bit 5 of Syste[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 68 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Write Mode (WM) Write Mode Information[1] MRS(Mode register Setting) Description NOTE : 1) Operation not guara nteed for cases not defined in above table. Boot Buffer Write Protect Status(BWPS) Boot Buffer Write Protect Status Information[0] WM Write Mode 0 Asynchronous[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 69 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.20 System Configuration 2 Regist er F222h This register is reserved for future use. 2.8.21 Controller S t atus Register F240h (R) This Read register shows the overall internal status o f the MuxOneNAND and the controller. F240h, default = 0000h OnGo This bit shows t[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 70 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Progra m This bit shows the Program Operation status. In 2X Cache Program Operation, ‘Prog’ bit shows the overall stat us of 2X Cache Program process. Program Information[12] Erase This bit shows the Erase Operation status. Erase Information[11] Error This bit shows[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 71 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Reset / Busy (RSTB) This bit shows the Reset Operation status. RSTB Information[7] OTP Lock Status (OTP L ) This bit shows whether the OTP block is lo cked or unlocked. Locking the OTP has the e ffect of a 'write-protect' to gua rd agains t accidental re- prog[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 72 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Plane1 Current This bit shows the current program status of Plane1 at Final 2X Cache Program, 2X Prog ram, and 2X Interleave Cache Program. During 2X Cache Program prior to ‘2X Program’ command, which wi ll be Final 2X Cache Program, this bit will be in valid (fixed[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 73 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Controller Status Register Output Modes NOTE : 1) ERm and/or ERs bits in ECC status register at Load Fail case is 10. (2bits error - uncorrectable) 2) ERm and ERs bits in ECC status register at Load Reset case are 00. (No error) 3) Multi Bl ock Erase status should be ch[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 74 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Controller Status Register Output Modes (Continued) NOTE : 1) "1" for OTP Block Lock, "0" for OTP Block Unlock. 2) "1" for 1st Block OTP Lock, "0" for 1st Block O TP Unlock. 3) This value is invalid in this case. Host can recogniz[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 75 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.22 Interrupt S t atus Register F241h (R/W) This Read/Write register shows st atus of the MuxOneNAND interrupts. In DDP, INT register will not be written if DBS, DFS is not set. F241h, defaults = 8080h after Cold R eset; 8010h after Warm/Hot Reset Interrupt (INT ) Th[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 76 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Write Interrupt (WI) This is the Write interrupt bit. WI Interrupt [6] Erase Interrupt (EI) This is the Erase interrupt bit. EI Interrupt [ 5] Reset Interrupt (RSTI) This is the Reset interrupt bit. RSTI Interrupt [4] Status Condition s Default State V alid State Interr[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 77 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.23 St art Block Address Register F24Ch (R/W) This Read/Write register shows the NAND Fl ash block address in the Write Protection m ode. Setting this register precedes a 'Loc k Block' command, 'Unlock Block' command, or ‘Lock-Tight' Comman[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 78 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.26 ECC St atus Register F F00h (R) This Read register shows the Error Correction Status. The MuxOneN AND can detect 1- or 2-bit errors and correct 1-bit errors. 3-bit or more error detection and correction is not supported. ECC can be performed on the NAND Flash mai[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 79 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.27 ECC Result of 1 st Selected Sector , Main Area Data Register FF01h (R) This Read register shows the Error Correctio n result for the 1st selected sector of the main are a data. ECCposWord0 is the erro r position address in the Main Area data of 256 words. ECCposI[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 80 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.31 ECC R esult of 3 rd Selected Sector , Main Area Data Register FF05h (R) This Read register shows the Er ror Correction result for the 3rd selected sector of the main area data. ECCposWord2 is the err o r position address in the Main Area data of 256 words. ECCpos[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 81 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) ECC Log Sector ECClogSector0~ECClogSector3 i ndicates the error position in the 2nd word and LSB of 3rd word in the spare area. Refer to note 2 in chapter 2.7.2 ECClogSect or Information [ 5:4] ECClogSector Error Position 00 2nd word 01 3rd word 10, 1 1 Reserved[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 82 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.0 DEVICE OPERA TION This section of the datasheet discusses the operati on of the MuxOneNAND device. It is followed by AC/DC Characteristics and Timing Diagrams which may be consulted for further information. The MuxOneNAND supports a limited command-based interface i[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 83 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.1.1 Reset MuxOneNAND Command The Reset command is given by writing 00F0h to the boot partiti on address. R eset will return all default values into the device . 3.1.2 Load MuxOneNAND Command Load Data into Buffer command is a two-cycle command. T wo sequent ial design[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 84 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.2 Device Bus Operation The device bus operations are shown in the table belo w. NOTE : L=VIL (Low), H=VIH (High), X=Don’t Care. Operation CE OE WE ADQ0~15 RP CL K AV D S tandby H X X High-Z H X X W arm Reset X X X High -Z L X X Asynchronous Write L H L Add. In /Data[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 85 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.3 Reset Mode Operation The One NAND has 4 reset modes: Cold/Warm/Hot Reset, and NAND Fl ash Array Reset. Section 3.3 disc usses the operation of these r eset modes. The Register Reset T able shows the which reg isters are affected by the various types or Reset operati[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 86 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.3.1 Cold Reset Mode Operation See Timing Diagram 6.17 At system power-up, the voltage detector in the device detects th e rising edge of Vcc and releases an internal pow er-up reset s ignal. This trig- gers bootcode loading. Boo tcode l oading means that the bo ot loa[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 87 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.4 Write Protecti on Operation The MuxOneNAND can be write-protected to pr ev ent re-programming or erasu re of data. The areas of write-protection are the BootRAM, and the NAND Flash Array . 3.4.1 Boo tRAM Write Protecti on Operation At system power-up, voltage detect[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 88 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.4.3.1 Un locked NA ND Array Write Protecti on St ate An Unlocked block can be programmed or erased. The status of an unlocked block can be cha nged to locked or locked-tight using t he appro- priate software command. (locked-tight state can be achi eved via lock-tight[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 89 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.4.3.3 Locked-tight NAND A rray Write Protection St ate A block that is in a locked-tight state can only be changed to lock ed state after a Cold or Warm Reset. Unlock and Lock command sequences will not affect its state. This is an added level of w rite pr otection se[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 90 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Data Protection Operation Flow Diagram * Samsung strongly recommen ds to follow the above flow chart NOTE : 1) ‘Write 0 to interru pt register’ step may be ignored when using INT auto mode. Ref er to chapter 2.8.18.1 * DFS, DBS is for DDP Start Lock/Unlock/Lock-Tigh[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 91 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) All Block Unlock Flow Di agram * Samsung strongly recommen ds to follow the above flow chart * * If any blocks are changed to locked -tight st ate, the all block unlock command will fail. In order to use all block unlock command again, a cold reset is needed. NOTE : 1) [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 92 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.5 Dat a Protection Duri ng Power Down Operation See Timing Diagram 6.21 The device is designed to offer protection from any involuntary program/erase during power-transitions. RP pin which provides hardware protection is recomm ended to be kept at VIL before Vcc drops[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 93 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.7 Read Operation See Timing Diagrams 6.1, 6.2, 6.5, and 6.6 The device has two read modes; Asynchronous Read an d Synchronous Burst Read. The initial state machine automatically set s the device into the Asynchronous Read Mode (RM=0) to prevent the spurious altering o[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 94 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.7.2.1 Continuous Linear Burst Read Opera tion See Timing Diagram 6.2 First Clock Cycle The initial word is output at tIAA after the rising edge of the first CLK cycle. The RDY output indicates the initial word is r eady to the system by pulsing high. If the device is [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 95 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.7.2.3 Programmable Burst Read Latency Operation See Timing Diagrams 6.1 and 6.2 Upon power up, the number of initial clock cycles from V alid Address (A VD ) to initial data defaults to four clocks. The number of clock cycles (n) which a re inserted after the cl ock w[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 96 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.8 Cache Read Operation (RM=X, WM=X) A Normal Load Operation(0000h) consists of sequential operation of ‘sensing from NAND Flash Array to Page Buffer’ and ‘transfer ring from Page Buffer to DataRAM’. Cache Read is a method of improving the data read throughput [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 97 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Cache Read Flow Chart NOTE : 1) In case of first cycle cache re ad, BSA must be set to 1000 or 1 100, and from second cycle cache read, BSA will aut omatical ly be switched between DataRAM0 and DataRAM1. 2) BSC, F SA and FCSA must be se t to "00". 3) These st [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 98 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Cache Read Diagram INT A/DQ0: A/DQ15 1st Address Host reads 1st data from Dat aRAM  Setting 2nd Address Setting Command Setting 3rd Address Setting 1) 4th Address Setting Command Setting Status Read Status Read  Host reads (n-2)th data from Dat aRAM  Command Se[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 99 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.9 Synchronous Burst Block Read Operation(RM=1, WM=X) See Timing Diagram 6.3 and 6.4. MuxOneNAND is internally composed of two Da taRAMs and NAND Flash Array . And for host to read data from NAND Cell Array , load operation which moves data from NAND Cell Array to Data[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 100 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.9.1 Burst Address Sequence During Synchronous Burst Block Re ad Mode In a Synchronous Burst Block Read, data is output with respect to a clock input. MuxOneNAND is capable of a continuous li near burst o peration within one block size and a fixed-length linear burst [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 101 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Synchronous Burst Block Read Boundary Read Sequence for Single Plane Device :note that only main area data is read. Main Area  S pare Area Page 0 Page 63 . . . Not supported[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 102 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.9.3 4-, 8-, 16-, 32-, 1K- W ord Linear Burst Read Operation During Synchron ous Burst Block Read Mode Same as normal linear burst read, synchr onous bur st block read enables a fixed number of words to be read from consecutive addr ess. The device supports a burst re[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 103 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.9.5 Handshaking Operation During Synchr onous Burst Block Re ad Mode The handshaking feature allows the host system to simply monitor t he RDY signal from the device to determine whe n the initial w ord of burst data is ready to be read. T o set the number of initial[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 104 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.10 Synchronous Wr ite(RM=1, WM=1) See Timing Diagram 6.8, 6.9 and 6.10. Burst mode operations enable high-speed synchronous read and write operations. Burst operations consist of a multi-clock sequen ce that must be performed in an ordered fashion. After CE goes low [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 105 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.1 1 Program Operation See Timing Diagram 6.12 The Program operation is used to program data from the on-chip BufferRAMs into the NAND FLASH memory array . The device has two 2KB data buffers, each 1 Page (2KB + 64B) in si ze. Each page has 4 sectors of 512B each main[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 106 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Program Operation Fl ow Diagram NOTE : 1) DBS must be set before data input. 2) Data input could be done anywhere between "S tart" and "Write Program Command". 3) ‘Write 0 to int errupt register’ step may be ignored when using INT auto mode. Ref[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 107 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.1 1.1 2X Program Operation See Timing Diagram 6.13 The 2X Program is an extension of Program Operation. Since the device is equipped with two DataRAMs, and two-plane NAND Flash m em- ory array , these two component ena bles simultaneous program of 4KB. Plane1 has onl[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 108 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2X Program Operation Flow Diagram NOTE : 1) DBS must be set before data input. 2) Data input could be done anywhere between "S tart" and "Write Program Command" 3) FBA must be an even block. 4) These registers must b e set as BSA=1000, BSC=00 and FS[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 109 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.1 1.2 2X Cache Program Operation See Timing Diagram 6.14 The 2X Cache Program Operation is invented to accomplish continuous 2X Program Operat ion efficiently by hi ding transferring tim e from Dat- aRAM to page buffer .. 1. 4KB Data write from host to DataRAMs. 2. 2[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 110 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2X Cache Program Operation Flow Diagram NOTE : 1) DBS must be set before data input. 2) FBA must be an even block. 3) These registers must be set as BSA=1000, BSC=00 and FSA=00. 4) ‘Write 0 to inter rupt register’ step may be ignored when using INT auto mode. Refer[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 111 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.1 1.3 2X Interleave Cache Program Operation See Timing Diagram 6.15 The 2X Interleave Cache Progr am is available only on DDP . Host can write data on a chip while programming another chip with th is operation. 2X Interleave Cache Program is executed as following: 1.[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 112 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2X Interleave Cache Program Operatio n Flow Diagram NOTE : 1) DBS must be set before data input. 2) FBA must be an even block. 3) These registers must be set as BSA=1 000, BSC=00 and FSA=00. 4) ‘Write 0 to i nterrupt register’ step may be ignored when using INT aut[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 113 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.12 Copy-Back Program Operation The Copy-Back program is configured to quickly rewrite data stor ed in one page without utilizing memory other than OneNAND. Sin ce the time-consuming cycles of serial access and re-loading cycles are removed, the syst em performance is[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 114 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) The Copy-Back steps shown in the flow chart are :  Data is read from the NAND Array using Flash Bl ock Addre ss (FBA), Flash Page Address (FP A) and Flash Sector Address (FSA). FBA, FP A, and FSA identify the source address to read data from NAND Flash arra[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 115 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.12.1 Copy-Back Program Operat ion with Random Dat a Input The Copy-Back Program Operation with Random Data Input in MuxOne NAND consists of 2 phase, Load data into Dat aRAM, Modify data a nd program into designated page. Data from the source page is sa ved in one of [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 116 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.13 Erase Operation There are multiple methods for erasing data in th e device including Block Erase and Multi- Block Erase. 3.13.1 Block Erase Op eration See Timing Diagram 6.16 The Block Erase Operation is don e on a block ba sis. T o erase a block is to write all 1[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 117 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) In order to perform the Internal Erase Rout ine, the following comm and sequence is necessary .  The Host selects Flash Core of DDP chip.  The Host sets the block address of the memory location.  The Erase Command initiates th e Inte[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 118 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.13.3 Multi-Block Erase V erify Read Operation After a Multi-Block Erase Operation, verify Erase Operation result of each block with Multi-Block Erase V erify Command combined with address of each block. If a failed address is identified, it must be managed b y firmwa[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 119 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.13.4 Erase Suspend / Erase Resume Operation The Erase Suspend/Erase Resume Commands interrupt and restart a Blo ck Erase or Multi-Block Erase ope ration so that user may per form another urgent operation on the block that is not be ing designated by Erase/Mult i-Bloc[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 120 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Erase Resume When the Erase Resume command is executed, the Block Erase will restart. The Erase Re sume operation does not actually resume th e erase, but starts it again from the beginning. When an Erase Suspend or Erase Resume command is ex ecuted, the addresse s are[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 121 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) OTP Block Area Structure 1st Block OTP Area Structure Page:2KB+64B Sector(main area) :512B Sector(spare area):16B One Block: 128KB+4KB 64pages Manufacturer Area : page 50 to page 63 14pages User Area : page 0 to page 49 50pages Page:2KB+64B Sector(main area) :512B Sect[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 122 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.14.1 OTP Block Load Operation An OTP Block Load Operation accesses the OTP area and transfers i dentified content from the OTP to the DataRAM on-chip buffer , thus making the OTP contents available to the Host. The OTP area is a separate p art of the NAND Flash Array[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 123 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.14.2 OTP Block Program Operation An OTP Block Program Operation accesses the OT P area and program s content from th e DataRAM on-chip buffer to the designated pag e(s) of the OTP . A memory location in the OTP area can be programmed only one time (no erase o peratio[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 124 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) OTP Block Program Operatio n Flow Chart NOTE : 1) FBA(NAND Flash Block Address) could be omitted or any address. 2) Data input could be done anywhere between "S tart" and "Write Program Command". 3) FBA should point the unlocked area address among N[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 125 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.14.3 OTP Block Lock Op eration Even though the OTP area can only be programmed once withou t eras e capability , it can be locked when the device starts up to pr event any changes from being made. Unlike the main area o f the NAND Flash Array memory , once the OTP bl[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 126 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) OTP Block Lock Operation Flow Chart NOTE : 1) FBA(NAND Flash Block Address) could be omitted or any address. 2) Data input could be done anywhere between "S tart" and "W rite Program Command". 3) FBA should point the unlocked area address among NAND[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 127 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.14.4 1st Block OTP Lock Operation 1st Block could be used as OTP , for secured booting operation. 1st Block OTP can be accessed ju st as any other N AND Flash Array Blocks before it is locked, however, once 1st Block is locked to be OTP , 1st Block OTP cannot be eras[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 128 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 1st Block OTP Lock Operation Flow Ch art NOTE : 1) FBA(NAND Flash Block Address) could be omitted or any address. 2) Data input could be done anywhere between "S tart" and "W rite Program Command". 3) FBA should point the unlocked area address among[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 129 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.14.5 OTP and 1st Block OTP Lock Operation OTP and 1st Block can be locked simultaneously , for lo cking bit lies in the same word of OTP area. 1st Block OTP can be accessed ju st as any other N AND Flash Array Blocks before it is locked, however, once 1st Block is lo[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 130 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) OTP and 1st Block OTP Lock Operation Flow Chart NOTE : 1) FBA(NAND Flash Block Address) could be omitted or any address. 2) Data input could be done anywhere between "S tart" and "W rite Program Command". 3) FBA should point the unlocked area addres[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 131 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.15 Dual Operations The device has independent dual data buffers on-chip (except duri ng the Boot Load period) that enables higher performance read and pro- gram operation. 3.15.1 Read-While-Load Operation This operation accelerates the read performance of the device [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 132 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Read While Load Diagram Page B ADQ WE OE INT 0~15 2) 2) Page A Int_reg : Interrupt Register Address Add_reg : Address Register Address Flash_add : Flash Address to be loaded DBn_add : DataRAM Address to be loaded CMD_reg : Command Register Address LD_CMD : Load Command[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 133 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Write While Program Diagram Page B ADQ WE OE INT 0~15 3) 2) Page A Add_reg : Address Register Address DBn_add : DataRAM Address to be programmed Data Write_DBn : W rite Data to DataRAMn Flash_add : Flash Address to be programmed Int_reg : Interrupt Register Address CMD[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 134 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.16 DQ6 T oggle Bit The MuxOneNAND device has DQ6 T oggle bit. T oggle bit is anoth er option to detect whether an interna l load operation is in progr ess or com- pleted. Once the BufferRAM(BootRAM, DataRAM0, DataRAM1) is at a busy state during internal load operatio[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 135 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.17 ECC Operation The MuxOneNAND device has on-chip ECC with t he capability of detecting 2 bit errors and correcting 1-bit errors in the NAND Fla sh Arr ay memory main and spare areas. As the device transfers data from a Buf ferRAM to the NAND Flash A rra y memory Pa[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 136 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.18 Invalid Block Operation Invalid blocks are defined as blocks in the device's N AND Flash Array memory that contai n one or more invalid bits whose re liab ility is not guaranteed by Samsung. The information regarding th e invalid block(s) is called the Inva l[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 137 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Invalid Block T ab le Creation Flow Chart 3.18.2 Invalid Block Replacement Operation Within its life time, additional invalid blo cks may develop with NAND Flash Array memo ry . Refer to the device's qualification r eport for the actual data. The following possibl[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 138 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Referring to the diagram for further illustration, when an erro r happens in the nth page of block 'A' during program operation, copy the data in the 1st ~ (n-1)th page to the same location of block 'B' via data buffer0. Then copy the nth page data [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 139 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 4.0 DC CHARACTERISTICS 4.1 Absolute Maximum Ratings NOTE : 1) Minimum DC voltage is -0.5V on In put/ Output pins. During transitions, this level should not fall to POR level(typ. 1.5V@1.8 V device). Maximum DC voltage may overshoot to Vcc+2.0V for periods <20ns. 2) [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 140 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 4.3 DC Characteristics NOTE : 1) CE should be VIH for RDY . IOBE should be ‘0’ for INT . 2) I CC active for Host access 3) I CC active for Internal operation. (without ho st access) 4) Vccq is equivalent to Vcc-I O Parameter Symbol T est Conditions RMS V alue Unit [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 141 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 5.0 AC CHARACTERISTICS 5.1 AC T est Conditions 5.2 Device Cap acit ance CAP ACIT ANCE (T A = 25  C, V CC = 1.8V , f = 1.0MHz) NOTE : Capacitance is perio dically sampled and not 100% tested. 5.3 V alid Block Characteristics NOTE : 1) The device may include invalid b[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 142 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 5.4 AC Characteristics for Sy nchronous Burst Read See Timing Diagrams 6.1, 6.2, 6.3, 6.4 and 6.24 NOTE : 1) If OE is disabled at th e same time or before CE is disabled, the output will go to hig h-z by t OEZ . If CE is disabled at the same time or bef ore OE is disab[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 143 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 5.5 AC Characteristics for Asynchronous Read See Timing Diagrams 6.5, 6.6, 6.22 and 6.23. NOTE : 1) If OE is disabled at th e same time or before CE is disabled, the output will go to hig h-z by t OEZ . If CE is disabled at the same time or bef ore OE is disabled, the [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 144 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 5.7 AC Characteristics for Asynchronous Write See Timing Diagrams 6.7 5.8 AC Characteristics fo r Burst Write Operation See Timing Diagrams 6.8, 6.9 and 6.10 NOTE : 1) T arget Clock frequency is 83Mhz. Parameter Symbol Min Max Unit WE Cycle T ime tWC 70 - ns AV D low p[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 145 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 5.9 AC Characteristics for Loa d/Program/Erase Performance See Timing Diagrams 6.1 1, 6.12, and 6.16 NOTE : 1) These parameters are tested based on INT bit of interrupt regi ster . Because the time on INT pin is related to the pull-up an d pu ll-down resistor value. 2)[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 146 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.0 TIMING DIAGRAMS 6.1 8-Word Linear Burst Read Mode with W rap Around See AC Characteristics T able 5.4 6.2 Continuous Line ar Burst Read Mode with W rap Around See AC Characteristics T able 5.4 t CES t AV D S t AV D H t ACS t ACH t IAA t RDYO t BA t BDH t CLK Hi-Z C[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 147 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.3 Synchronous Burst Bloc k Read Operation Timing See AC Characteristics table 5.4 and 5.7. WE CE CLK t DS t WPL t CS t WPH t WC AA FP A FBA AA ADQ0- OE t AA VDH t AA VDS INT t CH t CS AV D V IL t DH t RD2 CA SBBRCD FPC AA ADQ15 Hi-Z D0 D1 D2 RDY NOTE : Asynchronous w[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 148 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.4 Synchronous Burs t Block Read Timing See AC Characteristics table 5.4 and 5.1 1. Case 1 : BL=1K word synchronous burs t block read 2nd page out 3rd page out 4th page out S tart Page Address Setting Number of Pages Synchronous Burst Block Read Command ADQ0~ CE CLK R[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 149 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Case 2 : BL=8 word synchrono us burst block read 1st burst dat a Nth burst data S tart Page Address Setting Number of Pages Synchronous Burst Block Read Command ADQ0~ CE CLK RDY High-Z INT bit : Ind icator for Da taRAM’s S tatus (Ready=1, Busy=0) RDY : Indicator fo r[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 150 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.5 Asynchronous Read (V A T ransition Before A VD Low) See AC Characteristics T able 5.5 NOTE : V A=V alid Read Address, RD=Read Data. See timing diagram 6.22, 6.23 for t ASO 6.6 Asynchronous Read (V A T ransition After A VD Low) See AC Characteristics T able 5.5 NOTE[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 151 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.7 Asynchronous Write See AC Characteristics T able 5.7 NOTE : V A=V alid Read Address, WD=W rite Dat a. CE WE OE RP t CS t DS RDY t WPL t WPH t WC t CER Hi-Z Hi-Z CLK V IL t CH Valid WD VA Valid WD AVD t AAVDS t AVDP t AAVDH t WEA t DH t CEZ VA[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 152 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.8 8-Word Linear Burst W rit e Mode See AC Characteristics T able 5.8 6.9 Burst Write Operati on followed by Burst Read See AC Characteristics T able 5.8 t CES t AV D S t AV D H t ACS t ACH t RDYO t WDH t WDS t CLK Hi-Z CE CLK AV D OE RDY       t RDY[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 153 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.10 S t art Initial Burst W rite Operation See AC Characteristics T able 5.8 t CES t AV D S t AV D H t ACS t ACH t RDYO t WDH t WDS t CLK Hi-Z CE CLK AV D OE RDY t RDYS t RDY A A/DQ0: t CER D0 t CLKH t CLKL t CER WE t WES t WEH t CEH - 1 0 123 4 BRWL = 4 t CEZ t CEHP [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 154 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.1 1 Load Operation Timing See AC Characteristics T ables 5.5, 5.7 and 5.9. NOTE : 1) AA = Address of address register CA = Address of command register LCD = Load Command LMA = Address of memory to be loaded BA = Address of BufferRAM to load the dat a SA = Address of [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 155 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.12 Program Operation Timing See AC Characteristics T ab les 5.5, 5.7 and 5.9. NOTE : 1) AA = Address of address register CA = Address of command register PCD = Program Command PMA = Address of memory to be programmed BA = Address of BufferRAM to write t he data BD = [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 156 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.13 2X Program Operation Timing A1 : Address of DataRAM to be written. INT : Indicator for DataRAM’s S ta tus (Ready=High, Busy=Low) Ongoing S tatus : In dicated by OnGo bit in Controller S tatus Register [15] (F240h) 4KB data input : Asynch W rite / Synch Write ava[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 157 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.14 2X Cache Program Operation Timing 1st data input 2nd dat a input 2X cache program Command ADQ0~ A1, A2, A3 : Address of DataRAM to be written INT : Indicator for DataRAM’s S tatus (Ready=High, Busy=Low) Ongoing S tatus : Indicated by OnGo bit in Controller S tat[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 158 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.15 2X Interleave Cache Program Operation Timing 1st data input 2nd data input Address Setting 2X cache program Command ADQ0~ A1, A2, A3 : Address of Dat aRAM to be written. INT : Indicator for DataRAM’s S ta tus (Ready=High, Busy=Low) Ongoing S tatus : In dicated b[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 159 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.16 Block Erase Operation Timing See AC Characteristics T ables 5.5, 5.7 and 5.9. NOTE : 1) AA = Address of address register CA = Address of command register ECD = Erase Command EMA = Address of memory to be erased SA = Address of status regist er AA* = Address of S t[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 160 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.17 Cold Reset Timing NOTE : 1) Bootcode copy operation start s 400us later than POR activation. The system power should reach Vcc after POR triggerin g level(typ. 1.5V) within 400us for valid boot code data. 2) 1K bytes Bootcode co py takes 70us( es timated) from sec[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 161 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.18 W arm Reset Timing See AC Characteristics T ab les 5.6. NOTE : 1) The status which can accept any registe r ba sed operation(Load, Prog ram, Erase command, etc.). 2) The status wher e reset is ongoing. 3) The status all ows only BootRAM(BL1) read operat ion for Bo[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 162 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.19 Hot Reset Timing See AC Characteristics T ab les 5.6. NOTE : 1) Internal reset operation means tha t the device initializes in ternal registers and makes output signals go to default status a nd bufferRAM dat a are kept unchanged after W arm/Hot reset opera tions.[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 163 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.20 NAND Flash Core Reset Timing 6.21 Dat a Protection Timing During Power Down The device is designed to offer protection from any in vo luntary program/erase during power-transitions. RP pin provides hardware protection and is recommended to be kept at V IL before V[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 164 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.22 T oggle Bit Timing in Asynchronous Read (V A T ransition Before A VD Low) See AC Characteristics T able 5.5 NOTE : 1) V A=V alid Read Address, RD=Read Da ta. 2) Before IOBE is set to 1, RDY and INT pin are High-Z stat e. 3) Refer to chapter 5.5 for tASO descripti [...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 165 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.24 INT auto mode See AC Characteristics T ab les 5.10. NOTE : INT pin polarity is based on ‘IOBE=1 and IN T pol=1 (default)’ setting Write command into Command Register INT will automatically turn to Busy S tate INT will automatically turn back to ready state whe[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 166 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 7.0 TECHNICAL AND APPLICA TION NOTES From time-to-time supplemental technical information and application notes pertaining to the design a nd operation of the device in a system are included in this section. Contact your Samsung Repres entative to determine if ad ditio[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 167 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 7.1.1 The INT Pin to a Host General Purpose I/O INT can be tied to a Host GPIO to detect the rising edge of INT , signaling the end of a command operation. This can be configured to operate eith er synchro nously or asynchronously as shown in the diagrams below . Synch[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 168 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 7.1.2 Polling the Interrupt Register S t atus Bit An alternate method of determining the end of an operation is to c ontinuously monitor the Interrupt St atus Register Bit instead of using the INT pin. When using interrupt register instead of INT pin, INT pin is re com[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 169 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 7.1.3 Determining R p V alue (DDP , QDP only) For general operation, INT operates as normal output pin, so that tF is equivalent to tR (below 10ns). But since INT operates a s open drain with 50K ohm for Reset (Hot/Warm/NAND Flash Core) operations and ‘2X program ope[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 170 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) NOTE : 1) Refer to chapter 2.8.10 St art Address Register F101h DDP Block Diagram ~50k ohm INT 1) Vcc or Vccq Rp INT pol = ‘Low’ Busy S tate Ready VOH tf tr VOL Vss Vcc tr ,t f Ibusy [mA] Rp( oh m) Ibusy tf [ us ] KFN4G16Q2A @ Vcc = 1.8V , T a = 25  C , C L = 30[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 171 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 7.2 Boot Sequence One of the best features MuxOneNAND has is that it can be a booting device itself si nce it contains an internally built-in boot loade r despite the fact that its core architecture is based on NAND Flash. Thus, MuxOneNAND does not make any additio nal[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 172 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Partition of NAND Flash array NOTE : Step 2 and Step 3 can be copied into DRAM through two DataRAMs using dual buffering MuxOneNAND Boot Sequence Reservoir File System Os Image NBL3 NBL2 NBL1 Partition 6 Block 162 Block 2 Block 1 Block 0 Partition 5 Sector 0 Sector 1 S[...]

MuxOneNAND2G(KFM2G16Q2A-DEBx) - 173 - FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 8.0 P ACKAGE DIMENSIONS 2G product (KFM2G16Q2A) 4G product (KFN4G16Q2A) 0.10 MAX 0.45 ± 0.05 0.32 ± 0.0 5 0.9 ± 0.10 BOTTOM VIEW TOP VIEW A C E B D F 0.80x9=7.20 A 0.80x1 1=8.80 63-   0.45 ± 0.05 G 4.40 0 . 8 0 B 0.20 M A B  (Datum A) (Datum B) 2 543 1 6 3[...]