Samsung S3C2410A manuel d'utilisation

21-S3-C2410A-032004 USER'S MANUAL S3C2410A – 200MHz & 266MHz 32-Bit RISC Microprocessor Revision 1.0[...]

S3C2410A 200MHz & 266MHz 32-BIT RISC MICROPROCESSOR USER'S MANUAL Revision 1.0[...]

Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make chang[...]

S3C2410A MICROPROCESSOR iii Table of Contents Chapter 1 Product Overview Introduction ......................................................................................................................................... 1-1 Features .................................................................................................................[...]

iv S3C2410A MICROPROCESSOR Table of Contents (Continued) Chapter 3 ARM Instruction set Instruction Set Summay ....................................................................................................................... 3-1 Format Summary .....................................................................................................[...]

S3C2410A MICROPROCESSOR v Table of Contents (Continued) Chapter 3 ARM Instruction set (Continued) Single Data Transfer (LDR, STR) ........................................................................................................... 3-28 Offsets And Auto-Indexing .................................................................................[...]

vi S3C2410A MICROPROCESSOR Table of Contents (Continued) Chapter 3 ARM Instruction set (Continued) Coprocessor Data Transfers (LDC, STC) ................................................................................................ 3-53 The Coprocessor Fields ........................................................................................[...]

S3C2410A MICROPROCESSOR vii Table of Contents (Continued) Chapter 4 Thumb Instruction Set (Continued) Format 5: Hi-Register Operations/Branch Exchange ............................................................................... 4-13 Operation ........................................................................................................[...]

viii S3C2410A MICROPROCESSOR Table of Contents (Continued) Chapter 4 Thumb Instruction Set (Continued) Format 16: Conditional Branch .............................................................................................................. 4-34 Operation ...........................................................................................[...]

S3C2410A MICROPROCESSOR ix Table of Contents (Continued) Chapter 6 NAND Flash Controller Overview ............................................................................................................................................. 6-1 Features .................................................................................................[...]

x S3C2410A MICROPROCESSOR Table of Contents (Continued) Chapter 8 DMA Overview ............................................................................................................................................. 8-1 DMA Request Sources .........................................................................................................[...]

S3C2410A MICROPROCESSOR xi Table of Contents (Continued) Chapter 10 PWM Timer Overview ............................................................................................................................................. 10-1 Feature ............................................................................................................[...]

xii S3C2410A MICROPROCESSOR Table of Contents (Continued) Chapter 12 USB Host Controller Overview ............................................................................................................................................. 12-1 USB Host Controller Special Registers ...................................................................[...]

S3C2410A MICROPROCESSOR xiii Table of Contents (Continued) Chapter 14 Interrupt Controller Overview ............................................................................................................................................. 14-1 Interrupt Controller Operation ........................................................................[...]

xiv S3C2410A MICROPROCESSOR Table of Contents (Continued) Chapter 16 ADC & Touch Screen Interface Overview ............................................................................................................................................. 16-1 Features ...................................................................................[...]

S3C2410A MICROPROCESSOR xv Table of Contents (Continued) Chapter 18 WatchDog Timer Overview ............................................................................................................................................. 18-1 Features ......................................................................................................[...]

xvi S3C2410A MICROPROCESSOR Table of Contents (Continued) Chapter 21 IIS-BUS Interface Overview ............................................................................................................................................. 21-1 Block Diagram .............................................................................................[...]

S3C2410A MICROPROCESSOR xvii Table of Contents (Continued) Chapter 23 BUS Priorities Overview ............................................................................................................................................. 23-1 Bus Priority Map ............................................................................................[...]

xviii S3C2410A MICROPROCESSOR Table of Contents (Continued) Appendix 1- ARM920T Introduction Abuot the Introduction .......................................................................................................................... 1-1 Processor Functional Block Diagram ........................................................................[...]

S3C2410A MICROPROCESSOR xix Table of Contents (Concluded) Appendix 3- MMU (Continued) Level Two Descriptor ............................................................................................................................ 3-11 Translating Large Page References ...............................................................................[...]

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S3C2410A MICROPROCESSOR xxi List of Figures Figure Title Page Number Number 1-1 S3C 2410A Block Diagram .................................................................................... 1-5 1-2 S3C2410A Pin Assignments (272-FBGA) .............................................................. 1-6 2-1 Big-Endian Addresses of Bytes within Words ...[...]

xxii S3C2410A MICROPROCESSOR List of Figures (Continued) Figure Title Page Number Number 4-1 THUMB Instruction Set Formats ........................................................................... 4-2 4-2 Format 1 ............................................................................................................. 4-5 4-3 Format 2 .......[...]

S3C2410A MICROPROCESSOR xxiii List of Figures (Continued) Figure Title Page Number Number 6-1 NAND Flash Controller Block Diagram ................................................................... 6-2 6-2 NAND Flash Operation Scheme ............................................................................ 6-2 6-3 TACLS = 0, TWRPH0 = 1, TWRPH1 =[...]

xxiv S3C2410A MICROPROCESSOR List of Figures (Continued) Figure Title Page Number Number 14-1 Interrupt Process Diagram .................................................................................... 14-1 14-2 Priority Generating Block ..................................................................................... 14-4 15-1 LCD Controlle[...]

S3C2410A MICROPROCESSOR xxv List of Figures (Continued) Figure Title Page Number Number 24-8 ROM/SRAM Burst READ Timing(I) (Tacs = 0, Tcos = 0, Tacc = 2, Tcoh = 0, Tcah = 0, PMC = 0, ST = 0, DW = 16-bit) .............................................................. 24-8 24-9 ROM/SRAM Burst READ Timing(II) (Tacs = 0, Tcos = 0, Tacc = 2, Tcoh = 0, T[...]

xxvi S3C2410A MICROPROCESSOR List of Figures (Concluded) Figure Title Page Number Number 1-1 ARM920T Functional Block Diagram ..................................................................... 1-2 2-1 CP15 MRC and MCR Bit Pattern .......................................................................... 2-5 2-2 Register 7 MVA Format ............[...]

S3C2410A MICROPROCESSOR xxvii List of Tables Table Title Page Number Number 1-1 272-Pin FBGA Pin Assignments – Pin Number Order ............................................. 1-7 1-2 272-Pin FBGA Pin Assignments ........................................................................... 1-10 1-3 S3C2410A Signal Descriptions .......................[...]

xxviii S3C2410A MICROPROCESSOR List of Tables (Continued) Table Title Page Number Number 8-1 DMA Request Sources for Each Channel ............................................................... 8-2 8-2 DMA Controller Module Signal Timing Constants .................................................... 8-3 9-1 S3C2410A Port Configuration .............[...]

S3C2410A MICROPROCESSOR xxix List of Table (Concluded) Figure Title Page Number Number 2-1 ARM9TDMI Im plementation Option ........................................................................ 2-2 2-2 CP15 Register Map ............................................................................................. 2-4 2-3 CP15 Abbreviations .......[...]

S3C2410A PRODUCT OVERVIEW 1- 1 1 PRODUCT OVERVIEW INTRODUCTION This manual describes SAMSUNG's S3C2410A 16/32-bit RISC microprocessor. This product is designed to provide hand-held devices and general applications with cost-effective, low-power, and high-performance micro-controller solution in small die size. To reduce total system cost, the [...]

PRODUCT OVERVIEW S3 C2410A 1- 2 FEATURES Architecture • Integrated system for hand-held devices and general embedded applications • 16/32-Bit RISC architecture and powerful instruction set with ARM920T CPU core • Enhanced ARM architecture MMU to support WinCE, EPOC 32 and Linux • Instruction cache, data cache, write buffer and Physical addr[...]

S3C2410A PRODUCT OVERVIEW 1- 3 FEATURES ( Continued) Interrupt Controller • 55 Interrupt sources (One Watch dog timer, 5 timers, 9 UARTs, 24 external interrupts, 4 DMA, 2 RTC, 2 ADC, 1 IIC, 2 SPI, 1 SDI, 2 USB, 1 LCD, and 1 Battery Fault) • Level/Edge mode on external interrupt source • Programmable polarity of edge and level • Supports Fas[...]

PRODUCT OVERVIEW S3 C2410A 1- 4 FEATURES ( Continued) Watchdog Timer • 16-bit Watchdog Timer • Interrupt request or system reset at time-out IIC-Bus Interface • 1-ch Multi-Master IIC-Bus • Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbit/s in Standard mode or up to 400 Kbit/s in Fast mode. IIS-Bus Inter[...]

S3C2410A PRODUCT OVERVIEW 1- 5 BLOCK DIAGRAM ARM920T ARM9TDMI Processor core (Internal Embedded ICE) DD[31:0] WriteBack PA Tag RAM Data MMU C13 DVA[31:0] DV A[31:0] Instruction CACHE (16KB) Instruction MMU External Coproc Interface C13 ID[31:0] IPA[31:0] IV A[31:0] CP15 Write Buffer AMBA Bus I/F JTAG Data CACHE (16KB) WBPA[31:0] DPA[31:0] Bridge &a[...]

PRODUCT OVERVIEW S3 C2410A 1- 6 PIN ASSIGNMENTS BOTTOM VIEW U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Figure 1-2. S3C2410A Pin Assignments (272-FBGA)[...]

S3C2410A PRODUCT OVERVIEW 1- 7 Table 1-1. 272-Pin FBGA Pin Assignments – Pin Number Order Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name A1 DATA19 B14 ADDR0/GPA0 D10 ADDR19/GPA4 A2 DATA18 B15 nSRAS D11 VDDi A3 DATA16 B16 nBE1:nWBE1:DQM1 D12 ADDR10 A4 DATA15 B17 VSSi D13 ADDR5 A5 DATA11 C1 DATA24 D14 ADDR1 A6 VDDMOP C2 DATA23 D15 VSSM[...]

PRODUCT OVERVIEW S3 C2410A 1- 8 Table 1-1. 272-Pin FBGA Pin Assignments – Pin Number Order (Continued) Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name F6 VSSi H4 nXDREQ1/GPB8 K13 TXD2/nRTS1/GPH6 F7 DATA8 H5 nTRST K14 RXD1/GPH5 F8 VSSMOP H6 TCK K15 TXD0/GPH2 F9 VSSi H12 CLE/GPA17 K16 TXD1/GPH4 F10 ADDR20/GPA5 H13 VSSOP K17 RXD0/GPH3 F1[...]

S3C2410A PRODUCT OVERVIEW 1- 9 Table 1-1. 272-Pin FBGA Pin Assignments – Pin Number Order (Continued) Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name M11 EINT23/nYPON/GPG15 P8 SPICLK0/GPE13 T5 I2SLRCK/GPE0 M12 RTCVDD P9 EINT12/LCD_PWREN/GPG4 T6 SDCLK/GPE5 M13 VSSi_MPLL P10 EINT18/GPG10 T7 SPIMISO0/GPE11 M14 EINT5/GPF5 P11 EINT20/XMON/[...]

PRODUCT OVERVIEW S3 C2410A 1- 10 Table 1-2. 272-Pin FBGA Pin Assignments Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @PWR-off I/O State @nRESET I/O Type C3 DATA21 DATA21 Hi-z Hi-z I t12 B1 DATA22 DATA22 Hi-z Hi-z I t12 C2 DATA23 DATA23 Hi-z Hi-z I t12 D3 VSSMOP VSSMOP PPP s3o E5 VDDMOP VDDMOP PPP d3o C1 DATA24 DATA24 Hi-z Hi-z[...]

S3C2410A PRODUCT OVERVIEW 1- 11 Table 1-2. 272-Pin FBGA Pin Assignments (Continued) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @PWR-off I/O State @nRESET I/O Type J5 TDO TDO OOO ot J4 LEND:STH/GPC0 GPC0 –/– O(L)/– I t8 J2 VCLK:LCD_HCLK/GPC1 GPC1 –/– O(L)/– I t8 J6 VLINE:HSYNC:CPV/GPC2 GPC2 –/– O(L)/– I t8 K3[...]

PRODUCT OVERVIEW S3 C2410A 1- 12 Table 1-2. 272-Pin FBGA Pin Assignments (Continued) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @PWR-off I/O State @nRESET I/O Type T2 VD16/GPD8 GPD8 –/– O(L)/– I t8 R3 VD17/GPD9 GPD9 –/– O(L)/– I t8 R4 VD18/GPD10 GPD10 –/– O(L)/– I t8 U2 VD19/GPD11 GPD11 –/– O(L)/– I t8[...]

S3C2410A PRODUCT OVERVIEW 1- 13 Table 1-2. 272-Pin FBGA Pin Assignments (Continued) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @PWR-off I/O State @nRESET I/O Type L9 EINT11/nSS1/GPG3 GPG3 –/–/– –/–/– I t8 P9 EINT12/LCD_PWREN/GPG4 GPG4 –/–/– –/O(L)/– I t8 U9 EINT13/SPIMISO1/GPG5 GPG5 –/–/– –/Hi-z/[...]

PRODUCT OVERVIEW S3 C2410A 1- 14 Table 1-2. 272-Pin FBGA Pin Assignments (Continued) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @PWR-off I/O State @nRESET I/O Type T15 AIN1 AIN1 – – AI r10 U17 AIN2 AIN2 – – AI r10 T16 AIN3 AIN3 – – AI r10 R15 AIN4 AIN4 – – AI r10 T17 AIN5 AIN5 – – AI r10 R16 AIN6 AIN6 – [...]

S3C2410A PRODUCT OVERVIEW 1- 15 Table 1-2. 272-Pin FBGA Pin Assignments (Continued) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @PWR-off I/O State @nRESET I/O Type K13 TXD2/nRTS1/GPH6 GPH6 –/– O(H)/– I t8 K12 RXD2/nCTS1/GPH7 GPH7 –/– –/– I t8 J17 nBATT_FLT nBATT_FLT – – I is J16 nRSTOUT/GPA21 nRSTOUT –/– [...]

PRODUCT OVERVIEW S3 C2410A 1- 16 Table 1-2. 272-Pin FBGA Pin Assignments (Continued) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @PWR-off I/O State @nRESET I/O Type B17 VSSi VSSi PPP s3i E13 nWE nWE Hi-z O(H) O(H) ot C16 nOE nOE Hi-z O(H) O(H) ot A17 nBE0:nWBE0:DQM0 DQM0 Hi-z O(H) O(H) ot B16 nBE1:nWBE1:DQM1 DQM1 Hi-z O(H) O(H[...]

S3C2410A PRODUCT OVERVIEW 1- 17 Table 1-2. 272-Pin FBGA Pin Assignments (Continued) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @PWR-off I/O State @nRESET I/O Type C10 VSSMOP VSSMOP PPP s3o E10 ADDR18/GPA3 ADDR18 Hi-z/– O(L) O(L) ot D10 ADDR19/GPA4 ADDR19 Hi-z/– O(L) O(L) ot F10 ADDR20/GPA5 ADDR20 Hi-z/– O(L) O(L) ot A9 [...]

PRODUCT OVERVIEW S3 C2410A 1- 18 Table 1-2. 272-Pin FBGA Pin Assignments (Continued) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @PWR-off I/O State @nRESET I/O Type E6 VSSMOP VSSMOP PPP s3o C4 VDDi VDDi PPP d1c F6 VSSi VSSi PPP s3i A3 DATA16 DATA16 Hi-z Hi-z Hi-z t12 B3 DATA17 DATA17 Hi-z Hi-z Hi-z t12 A2 DATA18 DATA18 Hi-z Hi[...]

S3C2410A PRODUCT OVERVIEW 1- 19 7. The table below shows I/O types and the descriptions. I/O Type Descriptions d1i(vdd1ih), s3i(vss3i) 1.8V / 2.0V V DD /V SS for internal logic d1c(vdd1ih_core), s3i(vss3i) 1.8V / 2.0V V DD /V SS for internal logic without input driver d3o(vdd3op), s3o(vss3op) 3.3V V DD /V SS for external logic d3t(vdd3t_abb), s3t(v[...]

PRODUCT OVERVIEW S3 C2410A 1- 20 SIGNAL DESCRIPTIONS Table 1-3. S3C2410A Signal Descriptions Signal I/O Descriptions Bus Controller OM [1:0] I OM [1:0] sets S3C2410A in the TEST mode, which is used only at fabrication. Also, it determines the bus width of nGCS0. The pull-up/down resistor determines the logic level during the RESET cycle. 00:Nand-bo[...]

S3C2410A PRODUCT OVERVIEW 1- 21 Table 1-3. S3C2410A Signal Descriptions (Continued) Signal I/O Descriptions NAND Flash CLE O Command Latch Enable ALE O Address Latch Enable nFCE O NAND Flash Chip Enable nFRE O NAND Flash Read Enable nFWE O NAND Flash Write Enable NCON I NAND Flash Configuration. If NAND Flash Controller isn't used, it has to b[...]

PRODUCT OVERVIEW S3 C2410A 1- 22 Table 1-3. S3C2410A Signal Descriptions (Continued) Signal I/O Descriptions UART RxD [2:0] I UART receives data input TxD [2:0] O UART transmits data output nCTS [1:0] I UART clear to send input signal nRTS [1:0] O UART request to send output signal UEXTCLK I UART clock signal ADC AIN [7:0] AI ADC input [7:0]. If it[...]

S3C2410A PRODUCT OVERVIEW 1- 23 Table 1-3. S3C2410A Signal Descriptions (Continued) Signal I/O Description SD SDDAT [3:0] IO SD receive/transmit data SDCMD IO SD receive response/ transmit command SDCLK O SD clock General Port GPn [116:0] IO General input/output ports (some ports are output only) TIMMER/PWM TOUT [3:0] O Timer Output [3:0] TCLK [1:0[...]

PRODUCT OVERVIEW S3 C2410A 1- 24 Table 1-3. S3C2410A Signal Descriptions (Continued) Signal I/O Description Reset, Clock & Power (Continued) EXTCLK I External clock source. When OM [3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source. When OM [3:2] = 10b, EXTCLK is used for MPLL CLK source only. When OM [3:2] = 01b, EXTCLK is use[...]

S3C2410A PRODUCT OVERVIEW 1- 25 Table 1-3. S3C2410A Signal Descriptions (Continued) Signal I/O Description Power VDDalive P S3C2410A reset block and port status register V DD (1.8V / 2.0V). It should be always supplied whether in normal mode or in power-off mode. VDDi/VDDiarm P S3C2410A core logic V DD (1.8V / 2.0V) for CPU. VSSi/VSSiarm P S3C2410A[...]

PRODUCT OVERVIEW S3 C2410A 1- 26 S3C2410A SPECIAL REGISTERS Table 1-4. S3C2410A Special Registers Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function Memory Controller BWSCON 0x48000000 ← W R/W Bus Width & Wait Status Control BANKCON0 0x48000004 Boot ROM Control BANKCON1 0x48000008 BANK1 Control BANKCON2 0x480[...]

S3C2410A PRODUCT OVERVIEW 1- 27 Table 1-4. S3C2410A Special Registers (Continued) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function USB Host Controller HcRevision 0x49000000 ← W Control and Status Group HcControl 0x49000004 HcCommonStatus 0x49000008 HcInterruptStatus 0x4900000C HcInterruptEnable 0x49000010 HcInt[...]

PRODUCT OVERVIEW S3 C2410A 1- 28 Table 1-4. S3C2410A Special Registers (Continued) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function DMA DISRC0 0x4B000000 ← W R/W DMA 0 Initial Source DISRCC0 0x4B000004 DMA 0 Initial Source Control DIDST0 0x4B000008 DMA 0 Initial Destination DIDSTC0 0x4B00000C DMA 0 Initial Dest[...]

S3C2410A PRODUCT OVERVIEW 1- 29 Table 1-4. S3C2410A Special Registers (Continued) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function Clock & Power Management LOCKTIME 0x4C000000 ← W R/W PLL Lock Time Counter MPLLCON 0x4C000004 MPLL Control UPLLCON 0x4C000008 UPLL Control CLKCON 0x4C00000C Clock Generator Cont[...]

PRODUCT OVERVIEW S3 C2410A 1- 30 Table 1-4. S3C2410A Special Registers (Continued) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function UART ULCON0 0x50000000 ← W R/W UART 0 Line Control UCON0 0x50000004 UART 0 Control UFCON0 0x50000008 UART 0 FIFO Control UMCON0 0x5000000C UART 0 Modem Control UTRSTAT0 0x50000010 [...]

S3C2410A PRODUCT OVERVIEW 1- 31 Table 1-4. S3C2410A Special Registers (Continued) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function PWM Timer TCFG0 0x51000000 ← W R/W Timer Configuration TCFG1 0x51000004 Timer Configuration TCON 0x51000008 Timer Control TCNTB0 0x5100000C Timer Count Buffer 0 TCMPB0 0x51000010 Ti[...]

PRODUCT OVERVIEW S3 C2410A 1- 32 Table 1-4. S3C2410A Special Registers (Continued) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function USB Device FUNC_ADDR_REG 0x52000143 0x52000140 B R/W Function Address PWR_REG 0x52000147 0x52000144 Power Management EP_INT_REG 0x5200014B 0x52000148 EP Interrupt Pending and Clear U[...]

S3C2410A PRODUCT OVERVIEW 1- 33 Table 1-4. S3C2410A Special Registers (Continued) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/W rite Function USB Device (Continued) EP2_DMA_CON 0x5200021B 0x52000218 B R/W EP2 DMA Interface Control EP2_DMA_UNIT 0x5200021F 0x5200021C EP2 DMA Tx Unit Counter EP2_DMA_FIFO 0x52000223 0x52000220 [...]

PRODUCT OVERVIEW S3 C2410A 1- 34 Table 1-4. S3C2410A Special Registers (Continued) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function I/O port GPACON 0x56000000 ← W R/W Port A Control GPADAT 0x56000004 Port A Data GPBCON 0x56000010 Port B Control GPBDAT 0x56000014 Port B Data GPBUP 0x56000018 Pull-up Control B GP[...]

S3C2410A PRODUCT OVERVIEW 1- 35 Table 1-4. S3C2410A Special Registers (Continued) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function RTC RTCCON 0x57000043 0x57000040 B R/W RTC Control TICNT 0x57000047 0x57000044 Tick time count RTCALM 0x57000053 0x57000050 RTC Alarm Control ALMSEC 0x57000057 0x57000054 Alarm Second[...]

PRODUCT OVERVIEW S3 C2410A 1- 36 Table 1-4. S3C2410A Special Registers (Continued) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function SD interface SDICON 0x5A000000 ← W R/W SDI Control SDIPRE 0x5A000004 SDI Baud Rate Prescaler SDICmdArg 0x5A000008 SDI Command Argument SDICmdCon 0x5A00000C SDI Command Control SDIC[...]

S3C2410A PROGRAMMER'S MODEL 2- 1 2 PROGRAMMER'S MODEL OVERVIEW S3C2410A has been developed using the advanced ARM920T core, which has been designed by Advanced RISC Machines, Ltd. PROCESSOR OPERATING STATES From the programmer's point of view, the ARM920T can be in one of two states: • ARM state which executes 32-bit, word-aligned [...]

PROGRAMMER'S MODEL S3C2410A 2- 2 BIG-ENDIAN FORMAT In Big-Endian format, the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. Byte 0 of the memory system is therefore connected to data lines 31 through 24. 31 8 4 0 23 9 5 1 10 6 2 11 7 3 8 7 0 4 0 8 Higher Addres[...]

S3C2410A PROGRAMMER'S MODEL 2- 3 OPERATING MODES ARM920T supports seven modes of operation: • User (usr): The normal ARM program execution state • FIQ (fiq): Designed to support a data transfer or channel process • IRQ (irq): Used for general-purpose interrupt handling • Supervisor (svc): Protected mode for the operating system • Abo[...]

PROGRAMMER'S MODEL S3C2410A 2- 4 R0 R1 R2 R3 R4 R5 R6 R7 R9 R8 R10 R11 R12 R13 R14 R15 (PC) R0 R1 R2 R3 R4 R5 R6 R7 R9 R8 R10 R11 R12 R13_ svc R14_ svc R15 (PC) R0 R1 R2 R3 R4 R5 R6 R7 R9_ fiq R10_ fiq R11_ fiq R12_ fiq R13_ fiq R14_ fiq R15 (PC) R8_ fiq R0 R1 R2 R3 R4 R5 R6 R7 R9 R8 R10 R11 R12 R13_ abt R14_ abt R15 (PC) R0 R1 R2 R3 R4 R5 R6 [...]

S3C2410A PROGRAMMER'S MODEL 2- 5 The THUMB State Register Set The THUMB state register set is a subset of the ARM state set. The programmer has direct access to eight general registers, R0-R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR. There are banked Stack Pointers, Link Registers [...]

PROGRAMMER'S MODEL S3C2410A 2- 6 The relationship between ARM and THUMB state registers The THUMB state registers relate to the ARM state registers in the following way: • THUMB state R0-R7 and ARM state R0-R7 are identical • THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical • THUMB state SP maps onto ARM state R13 ?[...]

S3C2410A PROGRAMMER'S MODEL 2- 7 Accessing Hi-Registers in THUMB State In THUMB state, registers R8-R15 (the Hi registers) are not part of the standard register set. However, the assembly language programmer has limited access to them, and can use them for fast temporary storage. A value may be transferred from a register in the range R0-R7 (a[...]

PROGRAMMER'S MODEL S3C2410A 2- 8 The Condition Code Flags The N, Z, C and V bits are the condition code flags. These may be changed as a result of arithmetic and logical operations, and may be tested to determine whether an instruction should be executed. In ARM state, all instructions may be executed conditionally: see Table 3-2 for details. [...]

S3C2410A PROGRAMMER'S MODEL 2- 9 Table 2-1. PSR Mode Bit Values M[4:0] Mode Visible THUMB state registers Visible ARM state registers 10000 User R7..R0, LR, SP PC, CPSR R14..R0, PC, CPSR 10001 FIQ R7..R0, LR_fiq, SP_fiq PC, CPSR, SPSR_fiq R7..R0, R14_fiq..R8_fiq, PC, CPSR, SPSR_fiq 10010 IRQ R7..R0, LR_irq, SP_irq PC, CPSR, SPSR_irq R12..R0, R[...]

PROGRAMMER'S MODEL S3C2410A 2- 10 EXCEPTIONS Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an interrupt from a peripheral. Before an exception can be handled, the current processor state must be preserved so that the original program can resume when the handler routine has finished.[...]

S3C2410A PROGRAMMER'S MODEL 2- 11 Exception Entry/Exit Summary Table 2-2 summarizes the PC value preserved in the relevant R14 on exception entry, and the recommended instruction for exiting the exception handler. Table 2-2. Exception Entry/Exit Return Instruction Previous State Notes ARM R14_x THUMB R14_x BL MOV PC, R14 PC + 4 PC + 2 1 SWI MO[...]

PROGRAMMER'S MODEL S3C2410A 2- 12 IRQ The IRQ (Interrupt Request) exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered. It may be disabled at any time by setting the I bit in the CPSR, though this can only be done from a privileged (non-User)[...]

S3C2410A PROGRAMMER'S MODEL 2- 13 Software Interrupt The software interrupt instruction (SWI) is used for entering Supervisor mode, usually to request a particular supervisor function. A SWI handler should return by executing the following irrespective of the state (ARM or Thumb): MOV PC,R14_svc This restores the PC and CPSR, and returns to th[...]

PROGRAMMER'S MODEL S3C2410A 2- 14 Exception Priorities When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled: Highest priority: 1. Reset 2. Data abort 3. FIQ 4. IRQ 5. Prefetch abort Lowest priority: 6. Undefined Instruction, S oftware interrupt. Not All Exceptions Can Occur at [...]

S3C2410A PROGRAMMER'S MODEL 2- 15 INTERRUPT LATENCIES The worst case latency for FIQ, assuming that it is enabled, consists of the longest time the request can take to pass through the synchronizer (Tsyncmax if asynchronous), plus the time for the longest instruction to complete (Tldm, the longest instruction is an LDM which loads all the regi[...]

PROGRAMMER'S MODEL S3C2410A 2- 16 NOTES[...]

S3C2410A ARM INSTRUCTION SET 3- 1 3 ARM INSTRUCTION SET INSTRUCTION SET SUMMAY This chapter describes the ARM instruction set in the ARM920T core. FORMAT SUMMARY The ARM instruction set formats are shown below. Cond Rn Data/Processing/ PSR Transfer 0 0 I S Opcode 0 00 P U 0 W L 0 00 P U 1 W L 0 1 I P U B W L 0 1 I 1 00 P U B W L 1 1 1 1 1 1 1 1 1 0[...]

ARM INSTRUCTION SET S3C2410A 3- 2 NOTE Some instruction codes are not defined but do not cause the Undefined instruction trap to be taken, for instance a Multiply instruction with bit 6 changed to a 1. These instructions should not be used, as their action may change in future ARM implementations. INSTRUCTION SUMMARY Table 3-1. The ARM Instruction [...]

S3C2410A ARM INSTRUCTION SET 3- 3 Table 3-1. The ARM Instruction Set (Continued) Mnemonic Instruction Action MRC Move from coprocessor register to CPU register Rn: = cRn {<op>cRm} MRS Move PSR status/flags to register Rn: = PSR MSR Move register to PSR status/flags PSR: = Rm MUL Multiply Rd: = Rm × Rs MVN Move negative register Rd: = 0 × FF[...]

ARM INSTRUCTION SET S3C2410A 3- 4 THE CONDITION FIELD In ARM state, all instructions are conditionally executed according to the state of the CPSR condition codes and the instruction's condition field. This field (bits 31:28) determines the circumstances under which an instruction is to be executed. If the state of the C, N, Z and V flags fulf[...]

S3C2410A ARM INSTRUCTION SET 3- 5 BRANCH AND EXCHANGE (BX) This instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. This instruction performs a branch by copying the contents of a general register, Rn, into the program counter, PC. The branch causes a pipeline flush and refill from the address spe[...]

ARM INSTRUCTION SET S3C2410A 3- 6 Examples ADR R0, Into_THUMB + 1 ; Generate branch target address ; and set bit 0 high - hence ; arrive in THUMB state. BX R0 ; Branch and change to THUMB ; state. CODE16 ; Assemble subsequent code as Into_THUMB ; THUMB instru ctions • • • ADR R5, Back_to_ARM ; Generate branch target to word aligned address ; [...]

S3C2410A ARM INSTRUCTION SET 3- 7 BRANCH AND BRANCH WITH LINK (B, BL) The instruction is only executed if the condition is true. The various conditions are defined Table 3-2. The instruction encoding is shown in Figure 3-3, below. 31 24 27 Cond Offset 28 23 [24] Link bit 0 = Branch 1 = Branch with link [31:28] Condition Field 25 101 L 0 Figure 3-3.[...]

ARM INSTRUCTION SET S3C2410A 3- 8 ASSEMBLER SYNTAX Items in {} are optional. Items in <> must be present. B{L}{cond} <expression> { L} Used to request the Branch with Link form of the instruction. If absent, R14 will not be affected by the instruction. { cond} A two-character mnemonic as shown in Table 3-2. If absent then AL (ALways) wi[...]

S3C2410A ARM INSTRUCTION SET 3- 9 DATA PROCESSING The data processing instruction is only executed if the condition is true. The conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-4. 31 24 27 19 15 Cond Operand2 28 16 11 12 21 [15:12] Destination register 0 = Branch 1 = Branch with link [19:16] 1st operand register 0[...]

ARM INSTRUCTION SET S3C2410A 3- 10 The instruction produces a result by performing a specified arithmetic or logical operation on one or two operands. The first operand is always a register (Rn). The second operand may be a shifted register (Rm) or a rotated 8 bit immediate value (Imm) according to the value of the I bit in the instruction. The con[...]

S3C2410A ARM INSTRUCTION SET 3- 11 CPSR FLAGS The data processing operations may be classified as logical or arithmetic. The logical operations (AND, EOR, TST, TEQ, ORR, MOV, BIC, MVN) perform the logical action on all corresponding bits of the operand or operands to produce the result. If the S bit is set (and Rd is not R15, see below) the V flag [...]

ARM INSTRUCTION SET S3C2410A 3- 12 SHIFTS When the second operand is specified to be a shifted register, the operation of the barrel shifter is controlled by the Shift field in the instruction. This field indicates the type of shift to be performed (logical left or right, arithmetic right or rotate right). The amount by which the register should be[...]

S3C2410A ARM INSTRUCTION SET 3- 13 31 Contents of Rm Value of Operand 2 0 carry out 4 5 0 0 0 0 0 Figure 3-7. Logical Shift Right The form of the shift field which might be expected to correspond to LSR #0 is used to encode LSR #32, which has a zero result with bit 31 of Rm as the carry output. Logical shift right zero is redundant as it is the sam[...]

ARM INSTRUCTION SET S3C2410A 3- 14 Rotate right (ROR) operations reuse the bits which "overshoot" in a logical shift right operation by reintroducing them at the high end of the result, in place of the zeros used to fill the high end in logical right operations. For example, ROR #5 is shown in Figure 3-9. 31 Contents of Rm Value of Operan[...]

S3C2410A ARM INSTRUCTION SET 3- 15 Register Specified Shift Amount Only the least significant byte of the contents of Rs is used to determine the shift amount. Rs can be any general register other than R15. If this byte is zero, the unchanged contents of Rm will be used as the second operand, and the old value of the CPSR C flag will be passed on a[...]

ARM INSTRUCTION SET S3C2410A 3- 16 IMMEDIATE OPERAND ROTATES The immediate operand rotate field is a 4-bit unsigned integer which specifies a shift operation on the 8-bit immediate value. This value is zero extended to 32 bits, and then subject to a rotate right by twice the value in the rotate field. This enables many common constants to be genera[...]

S3C2410A ARM INSTRUCTION SET 3- 17 ASSEMBLER SYNTAX • MOV,MVN (single operand instructions). <opcode>{cond}{S} Rd,<Op2> • CMP,CMN,TEQ,TST (instructions which do not produce a result). <opcode>{cond} Rn,<Op2> • AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,ORR,BIC <opcode>{cond}{S} Rd,Rn,<Op2> where: <Op2> Rm{,<s[...]

ARM INSTRUCTION SET S3C2410A 3- 18 PSR TRANSFER (MRS, MSR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The MRS and MSR instructions are formed from a subset of the Data Processing operations and are implemented using the TEQ, TST, CMN and CMP instructions without the S flag set. The en[...]

S3C2410A ARM INSTRUCTION SET 3- 19 MSR (transfer register contents or immediate value to PSR flag bits only) Cond Source operand Pd 101001111 31 22 27 28 11 12 21 23 I 10 00 26 25 24 0 Cond 00000000 00010 Pd 101001111 31 22 27 28 11 12 21 23 Rm MSR (transfer register contents to PSR) 4 3 0 Cond 000000000000 00010 Rd Ps 001111 31 22 27 15 28 16 11 1[...]

ARM INSTRUCTION SET S3C2410A 3- 20 RESERVED BITS Only twelve bits of the PSR are defined in ARM920T (N,Z,C,V,I,F, T & M[4:0]); the remaining bits are reserved for use in future versions of the processor. Refer to Figure 2-6 for a full description of the PSR bits. To ensure the maximum compatibility between ARM920T programs and future processors[...]

S3C2410A ARM INSTRUCTION SET 3- 21 ASSEMBLY SYNTAX • MRS - transfer PSR contents to a register MRS{cond} Rd,<psr> • MSR - transfer register contents to PSR MSR{cond} <psr>,Rm • MSR - transfer register contents to PSR flag bits only MSR{cond} <psrf>,Rm The most significant four bits of the register contents are written to the[...]

ARM INSTRUCTION SET S3C2410A 3- 22 MULTIPLY AND MULTIPLY-ACCUMULATE (MUL, MLA) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-12. The multiply and multiply-accumulate instructions use an 8-bit Booth's algorithm to perform integer multipli[...]

S3C2410A ARM INSTRUCTION SET 3- 23 If the Operands Are Interpreted as Signed Operand A has the value -10, operand B has the value 20, and the result is -200 which is correctly represented as 0xFFFFFF38. If the Operands Are Interpreted as Unsigned Operand A has the value 4294967286, operand B has the value 20 and the result is 85899345720, which is [...]

ARM INSTRUCTION SET S3C2410A 3- 24 CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N (Negative) and Z (Zero) flags are set correctly on the result (N is made equal to bit 31 of the result, and Z is set if and only if the result is zero). The C (Carry) flag is set to a meaningless value and the V[...]

S3C2410A ARM INSTRUCTION SET 3- 25 MULTIPLY LONG AND MULTIPLY-ACCUMULATE LONG (MULL, MLAL) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-13. The multiply long instructions perform integer multiplication on two 32-bit operands and produce 64-b[...]

ARM INSTRUCTION SET S3C2410A 3- 26 OPERAND RESTRICTIONS • R15 must not be used as an operand or as a destination register. • RdHi, RdLo, and Rm must all specify different registers. CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N and Z flags are set correctly on the result (N is equal to b[...]

S3C2410A ARM INSTRUCTION SET 3- 27 ASSEMBLER SYNTAX Table 3-5. Assembler Syntax Descriptions Mnemonic Description Purpose UMULL{cond}{S} RdLo,RdHi,Rm,Rs Unsigned Multiply Long 32 x 32 = 64 UMLAL{cond}{S} RdLo,RdHi,Rm,Rs Unsigned Multiply & Accumulate Long 32 x 32 + 64 = 64 SMULL{cond}{S} RdLo,RdHi,Rm,Rs Signed Multiply Long 32 x 32 = 64 SMLAL{c[...]

ARM INSTRUCTION SET S3C2410A 3- 28 SINGLE DATA TRANSFER (LDR, STR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-14. The single data transfer instructions are used to load or store single bytes or words of data. The memory address used in the[...]

S3C2410A ARM INSTRUCTION SET 3- 29 OFFSETS AND AUTO-INDEXING The offset from the base may be either a 12-bit unsigned binary immediate value in the instruction, or a second register (possibly shifted in some way). The offset may be added to (U = 1) or subtracted from (U = 0) the base register Rn. The offset modification may be performed either befo[...]

ARM INSTRUCTION SET S3C2410A 3- 30 LDR from word aligned address A+3 A A+2 A+1 memory 24 16 8 0 A B C D register 24 16 8 0 A B C D LDR from address offset by 2 A+3 A A+2 A+1 memory 24 16 8 0 A B C D register 24 16 8 0 A B C D Figure 3-15. Little-Endian Offset Addressing Big-Endian Configuration A byte load (LDRB) expects the data on data bus inputs[...]

S3C2410A ARM INSTRUCTION SET 3- 31 USE OF R15 Write-back must not be specified if R15 is specified as the base register (Rn). When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction. R15 must not be specified as the register offset (Rm). When R15 is the source register (Rd)[...]

ARM INSTRUCTION SET S3C2410A 3- 32 ASSEMBLER SYNTAX <LDR|STR>{cond}{B}{T} Rd,<Address> where: LDR Load from memory into a register STR Store from a register into memory {cond} Two-character condition mnemonic. See Table 3-2. {B} If B is present then byte transfer, otherwise word transfer {T} If T is present the W bit will be set in a po[...]

S3C2410A ARM INSTRUCTION SET 3- 33 EXAMPLES STR R1,[R2,R4]! ; Store R1 at R2+R4 (both of which are regis ters) ; and write back address to R2. STR R1,[R2],R4 ; Store R1 at R2 and write back R2+R4 to R2. LDR R1,[R2,#16] ; Load R1 from contents of R2+16, but don't write back. LDR R1,[R2,R3,LSL#2] ; Load R1 from contents of R2+R3*4. LDREQB R1,[R6[...]

ARM INSTRUCTION SET S3C2410A 3- 34 HALFWO RD AND SIGNED DATA TRANSFER (LDRH/STRH/LDRSB/LDRSH) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-16. These instructions are used to load or store half-words of data and also load sign -extended bytes[...]

S3C2410A ARM INSTRUCTION SET 3- 35 31 27 19 15 Cond 28 16 11 12 21 23 1 20 L Rn Rd [3:0] Immediate Offset (Low Nibble) [6][5] S H 0 0 = SWP instruction 0 1 = Unsigned halfword 1 1 = Signed byte 1 1 = Signed halfword [11:8] Immediate Offset (High Nibble) [15:12] Source/Destination Register [19:16] Base Register [20] Load/Store 0 = Store to memory 1 [...]

ARM INSTRUCTION SET S3C2410A 3- 36 HALFWORD LOAD AND STORES Setting S=0 and H=1 may be used to transfer unsigned Half-words between an ARM920T register and memory. The action of LDRH and STRH instructions is influenced by the BIGEND control signal. The two possible configurations are described in the section below. Signed byte and halfword loads Th[...]

S3C2410A ARM INSTRUCTION SET 3- 37 Big-Endian Configuration A signed byte load (LDRSB) expects data on data bus inputs 31 through to 24 if the supplied address is on a word boundary, on data bus inputs 23 through to 16 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bit of the destination register, and [...]

ARM INSTRUCTION SET S3C2410A 3- 38 ASSEMBLER SYNTAX <LDR|STR>{cond}<H|SH|SB> Rd,<address> LDR Load from memory into a register STR Store from a register into memory {cond} Two-character condition mnemonic. See Table 3-2.. H Transfer halfword quantity SB Load sign extended byte (Only valid for LDR) SH Load sign extended halfword (O[...]

S3C2410A ARM INSTRUCTION SET 3- 39 EXAMPLES LDRH R1,[R2,-R3]! ; Load R1 from the contents of the halfword address ; contained in R2-R3 (both of which are registers) ; and write back address to R2 STRH R3,[R4,#14] ; Store the halfword in R3 at R14+14 but don't write back. LDRSB R8,[R2],#-223 ; Load R8 with the sign extended contents of the byte[...]

ARM INSTRUCTION SET S3C2410A 3- 40 BLOCK DATA TRANSFER (LDM, STM) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-18. Block data transfer instructions are used to load (LDM) or store (STM) any subset of the currently visible registers. They sup[...]

S3C2410A ARM INSTRUCTION SET 3- 41 ADDRESSING MODES The transfer addresses are determined by the contents of the base register (Rn), the pre/post bit (P) and the up/ down bit (U). The registers are transferred in the order lowest to highest, so R15 (if in the list) will always be transferred last. The lowest register also gets transferred to/from t[...]

ARM INSTRUCTION SET S3C2410A 3- 42 Rn 1 R1 R1 2 R5 3 R1 R5 4 R7 Rn 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 Figure 3-20. Pre-Increment Addressing Rn 1 R1 R1 2 R5 3 R1 R5 4 R7 Rn 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 Figure 3-21. Post-Decrement Addressing[...]

S3C2410A ARM INSTRUCTION SET 3- 43 Rn 1 R1 R1 2 R5 3 R1 R5 4 R7 Rn 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 Figure 3-22. Pre-Decrement Addressing USE OF THE S BIT When the S bit is set in a LDM/STM instruction its meaning depends on whether or not R15 is in the transfer list and on the type of instruction.[...]

ARM INSTRUCTION SET S3C2410A 3- 44 INCLUSION OF THE BASE IN THE REGISTER LIST When write-back is specified, the base is written back at the end of the second cycle of the instruction. During a STM, the first register is written out at the start of the second cycle. A STM which includes storing the base, with the base as the first register to be sto[...]

S3C2410A ARM INSTRUCTION SET 3- 45 ASSEMBLER SYNTAX <LDM|STM>{cond}<FD|ED|FA|EA|IA|IB|DA|DB> Rn{!},<Rlist>{^} where: { cond} Two character condition mnemonic. See Table 3-2. Rn An expression evaluating to a valid register number <Rlist> A list of registers and register ranges enclosed in {} (e.g. {R0,R2-R7, R10}). { !} If pr[...]

ARM INSTRUCTION SET S3C2410A 3- 46 EXAMPLES LDMFD SP!,{R0,R1,R2} ; Unstack 3 registers. STMIA R0,{R0-R15} ; Save all registers. LDMFD SP!,{R15} ; R15 ← (SP), CPSR unchanged. LDMFD SP!,{R15}^ ; R15 ← (SP), CPSR <- SPSR_mode ; (allowed only in privileged modes). STMFD R13,{R0-R14}^ ; Save user mode regs on stack ; (allowed only in privileged m[...]

S3C2410A ARM INSTRUCTION SET 3- 47 SINGLE DATA SWAP (SWP) 31 19 15 Cond 28 16 11 12 21 23 B 20 00 Rn Rd [3:0] Source Register [15:12] Destination Register [19:16] Base Register [22] Byte/Word Bit 0 = Swap word quantity 1 = Swap word quantity [31:28] Condition Field 22 00010 0000 Rm 1001 27 8 7 4 3 0 Figure 3-23. Swap Instruction The instruction is [...]

ARM INSTRUCTION SET S3C2410A 3- 48 USE OF R15 Do not use R15 as an operand (Rd, Rn or Rs) in a SWP instruction. DATA ABORTS If the address used for the swap is unacceptable to a memory management system, the memory manager can flag the problem by driving ABORT HIGH. This can happen on either the read or the write cycle (or both), and in either case[...]

S3C2410A ARM INSTRUCTION SET 3- 49 SOFTWARE INTERRUPT (SWI) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-24, below. 31 24 27 1111 Cond Comment Field (Ignored by Processor) 28 23 [31:28] Condition Field 0 Figure 3-24. Software Interrupt Instr[...]

ARM INSTRUCTION SET S3C2410A 3- 50 ASSEMBLER SYNTAX SWI{cond} <expression> { cond} Two character condition mnemonic, Table 3-2. <expression> Evaluated and placed in the comment field (which is ignored by ARM920T). Examples SWI ReadC ; Get next character from read stream. SWI WriteI+"k” ; Output a "k" to the write stream[...]

S3C2410A ARM INSTRUCTION SET 3- 51 COPROCESSOR DATA OPERATIONS (CDP) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-25. This class of instruction is used to tell a coprocessor to perform some internal operation. No result is communicated back [...]

ARM INSTRUCTION SET S3C2410A 3- 52 INSTRUCTION CYCLE TIMES Coprocessor data operations take 1S + bI incremental cycles to execute, where b is the number of cycles spent in the coprocessor busy-wait loop. S and I are defined as sequential (S-cycle) and internal (I-cycle). Assembler syntax CDP{cond} p#,<expression1>,cd,cn,cm{,<expression2>[...]

S3C2410A ARM INSTRUCTION SET 3- 53 COPROCESSOR DATA TRANSFERS (LDC, STC) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-26. This class of instruction is used to load (LDC) or store (STC) a subset of a coprocessors's registers directly to [...]

ARM INSTRUCTION SET S3C2410A 3- 54 THE COPROCESSOR FIELDS The CP# field is used to identify the coprocessor which is required to supply or accept the data, and a coprocessor will only respond if its number matches the contents of this field. The CRd field and the N bit contain information for the coprocessor which may be interpreted in different wa[...]

S3C2410A ARM INSTRUCTION SET 3- 55 ASSEMBLER SYNTAX <LDC|STC>{cond}{L} p#,cd,<Address> LDC Load from memory to coprocessor STC Store from coprocessor to memory { L} When present perform long transfer (N = 1), otherwise perform short transfer (N = 0) { cond} Two character condition mnemonic. See Table 3-2.. p# The unique number of the re[...]

ARM INSTRUCTION SET S3C2410A 3- 56 COPROCESSOR REGISTER TRANSFERS (MRC, MCR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2.. The instruction encoding is shown in Figure 3-27. This class of instruction is used to communicate information directly between ARM920T and a coprocessor. An exampl[...]

S3C2410A ARM INSTRUCTION SET 3- 57 TRANSFERS TO R15 When a coprocessor register transfer to ARM920T has R15 as the destination, bits 31, 30, 29 and 28 of the transferred word are copied into the N, Z, C and V flags respectively. The other bits of the transferred word are ignored, and the PC and other CPSR bits are unaffected by the transfer. TRANSF[...]

ARM INSTRUCTION SET S3C2410A 3- 58 UNDEFINED INSTRUCTION The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction format is shown in Figure 3-28. 31 27 Cond 28 25 24 011 xxxxxxxxxxxxxxxxxxxx 1 xxxx 5 4 3 0 Figure 3-28. Undefined Instruction If the condition is true, the undefined in[...]

S3C2410A ARM INSTRUCTION SET 3- 59 INSTRUCTION SET EXAMPLES The following examples show ways in which the basic ARM920T instructions can combine to give efficient code. None of these methods saves a great deal of execution time (although they may save some), mostly they just save code. USING THE CONDITIONAL INSTRUCTIONS Using Conditionals for Logic[...]

ARM INSTRUCTION SET S3C2410A 3- 60 Division and Remainder A number of divide routines for specific applications are provided in source form as part of the ANSI C library provided with the ARM Cross Development Toolkit, available from your supplier. A short general purpose divide routine follows. ; Enter with numbers in Ra and Rb. MOV Rcnt,#1 ; Bit [...]

S3C2410A ARM INSTRUCTION SET 3- 61 5. Overflow in unsigned multiply accumulate with a 64-bit result UMULL Rl,Rh,Rm,Rn ; 3 to 6 cycles ADDS Rl,Rl,Ra1 ; Lower accumulate ADC Rh,Rh,Ra2 ; Upper accumulate BCS overflow ; 1 cycle and 2 registers 6. Overflow in signed multiply accumulate with a 64 -bit result SMULL Rl,Rh,Rm,Rn ; 3 to 6 cycles ADDS Rl,Rl,R[...]

ARM INSTRUCTION SET S3C2410A 3- 62 Multiplication by 6 ADD Ra,Ra,Ra,LSL #1 ; Multiply by 3 MOV Ra,Ra,LSL#1 ; and then by 2 Multiply by 10 and add in extra number ADD Ra,Ra,Ra,LSL#2 ; Multiply by 5 ADD Ra,Rc,Ra,LSL#1 ; Multiply by 2 and ad d in next digit General recursive method for Rb := Ra*C, C a constant: 1. If C even, say C = 2^n*D, D odd: D=1:[...]

S3C2410A ARM INSTRUCTION SET 3- 63 LOADING A WORD FROM AN UNKNOWN ALIGNMENT ; Enter with address in Ra (32 bits) uses ; Rb, Rc result in Rd. Note d must be less than c e.g. 0,1 BIC Rb,Ra,#3 ; Get word aligned address LDMIA Rb,{Rd,Rc} ; Get 64 bits containing answer AND Rb,Ra,#3 ; Correction factor in by tes MOVS Rb,Rb,LSL#3 ; ...now in bits and tes[...]

ARM INSTRUCTION SET S3C2410A 3- 64 NOTES[...]

S3C2410A THUMB INSTRUCTION SET 4- 1 4 THUMB INSTRUCTION SET THUMB INSTRUCTION SET FORMAT The thumb instruction sets are 16-bit versions of ARM instruction sets (32-bit format). The ARM instructions are reduced to 16-bit versions, Thumb instructions, at the cost of versatile functions of the ARM instruction sets. The thumb instructions are decompres[...]

THUMB INSTRUCTION SET S3C2410A 4- 2 FORMAT SUMMARY The THUMB instruction set formats are shown in the following figure. Move Shifted register 0 0 0 0 0 0 000 000 1 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 000 1 1 1 1 1 1 1 1 0 L 0 1 1 1 1 1 1 1111 1 1 1 1 1 1 000 0 1 1 1 1 0 0 1 0 0 L 1 0 R 110 1 0 SP 1 L L S H 0 0 1 B L 0 1 H 0 1 B 001 1 1 I Op Op Op[...]

S3C2410A THUMB INSTRUCTION SET 4- 3 OPCODE SUMMARY The following table summarizes the THUMB instruction set. For further information about a particular instruction please refer to the sections listed in the right-most column. Table 4-1. THUMB Instruction Set Opcodes Mnemonic Instruction Lo-Register Operand Hi-Register Operand Condition Codes Set AD[...]

THUMB INSTRUCTION SET S3C2410A 4- 4 Table 4-1. THUMB Instruction Set Opcodes (Continued) Mnemonic Instruction Lo-Register Operand Hi-Register Operand Condition Codes Set NEG Negate Y – Y ORR OR Y – Y POP Pop register Y – – PUSH Push register Y – – ROR Rotate Right Y – Y SBC Subtract with Carry Y – Y STMIA Store Multiple Y – – ST[...]

S3C2410A THUMB INSTRUCTION SET 4- 5 FORMAT 1: MOVE SHIFTED REGISTER 15 0 0 14 10 [2:0] Destination Register [5:3] Source Register [10:6] Immediate Vale [12:11] Opcode 0 = LSL 1 = LSR 2 = ASR Offset5 6 5 3 2 Rd 0 0 13 12 11 Op Rs Figure 4-2. Format 1 OPERATION These instructions move a shifted value between Lo registers. The THUMB assembler syntax i[...]

THUMB INSTRUCTION SET S3C2410A 4- 6 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-2. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES LSR R2, R5, #27 ; Logical shift right the contents ; of R5 by 27 and store the r[...]

S3C2410A THUMB INSTRUCTION SET 4- 7 FORMAT 2: ADD/SUBTRACT 15 0 14 10 [2:0] Destination Register [5:3] Source Register [8:6] Register/Immediate Vale [9] Opcode 0 = ADD 1 = SUB [10] Immediate Flag 0 = Register operand 1 = Immediate oerand Rn/Offset3 Rd 0 0 13 12 11 Op Rs 9 8 111 6 5 3 2 0 Figure 4-3. Format 2 OPERATION These instructions allow the c[...]

THUMB INSTRUCTION SET S3C2410A 4- 8 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-3. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES ADD R0, R3, R4 ; R0 := R3 + R4 and set condition codes on the result. SUB R6, R2[...]

S3C2410A THUMB INSTRUCTION SET 4- 9 FORMAT 3: MOVE/COMPARE/ADD/SUBTRACT IMMEDIATE 15 0 0 14 10 [7:0] Immediate Vale [10:8] Source/Destination Register [12:11] Opcode 0 = MOV 1 = CMP 2 = ADD 3 = SUB Offset8 Rd 0 0 13 12 11 Op 7 8 Figure 4-4. Format 3 OPERATIONS The instructions in this group perform operations between a Lo register and an 8-bit imme[...]

THUMB INSTRUCTION SET S3C2410A 4- 10 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-4. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES MOV R0, #128 ; R0 := 128 and set condition codes CMP R2, #62 ; Set condition co[...]

S3C2410A THUMB INSTRUCTION SET 4- 11 FORMAT 4: ALU OPERATIONS 15 0 0 14 10 [2:0] Source/Destination Register [5:3] Source Register 2 [9:6] Opcode 5 6 3 Rd 0 0 13 12 11 Op Rs 0 0 0 9 2 Figure 4-5. Format 4 OPERATION The following instructions perform ALU operations on a Lo register pair. NOTE All instructions in this group set the CPSR condition cod[...]

THUMB INSTRUCTION SET S3C2410A 4- 12 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-5. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES EOR R3, R4 ; R3 := R3 EOR R4 and set condition codes ROR R1, R0 ; Rotate Right [...]

S3C2410A THUMB INSTRUCTION SET 4- 13 FORMAT 5: HI-REGISTER OPERATIONS/BRANCH EXCHANGE 15 0 0 14 10 [2:0] Destination Register [5:3] Source Register [6] Hi Operand Flag 2 [7] Hi Operand Flag 1 [9:8] Opcode 6 5 3 2 Rd/Hd 0 0 13 12 11 Op Rs/Hs 0 0 0 987 H1 H2 Figure 4-6. Format 5 OPERATION There are four sets of instructions in this group. The first t[...]

THUMB INSTRUCTION SET S3C2410A 4- 14 Table 4-6. Summary of Format 5 Instructions (Continued) Op H1 H2 THUMB assembler ARM equivalent Action 01 1 1 CMP Hd, Hs CMP Hd, Hs Compare two registers in the range 8-15. Set the condition code flags on the result. 10 0 1 MOV Rd, Hs MOV Rd, Hs Move a value from a register in the range 8-15 to a register in the[...]

S3C2410A THUMB INSTRUCTION SET 4- 15 EXAMPLES Hi-Register Operations ADD PC, R5 ; PC : = PC + R5 but don't set the condition codes. CMP R4, R12 ; Set the condition codes on the result of R4 - R12. MOV R15, R14 ; Move R14 (LR) into R15 (PC) ; but don't set the condition codes, ; eg. return from subroutine. Branch and Exchange ; Switch from[...]

THUMB INSTRUCTION SET S3C2410A 4- 16 FORMAT 6: PC-RELATIVE LOAD 15 0 0 14 10 [7:0] Immediate Value [10:8] Destination Register Word 8 0 0 13 12 11 Rd 0 0 8 7 Figure 4-7. Format 6 OPERATION This instruction loads a word from an address specified as a 10-bit immediate offset from the PC. The THUMB assembler syntax is shown below. Table 4-7. Summary o[...]

S3C2410A THUMB INSTRUCTION SET 4- 17 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES LDR R3,[PC,#844] ; Load into R3 the w ord found at the ; address formed by adding 844 to PC. ; bit[1][...]

THUMB INSTRUCTION SET S3C2410A 4- 18 FORMAT 7: LOAD/STORE WITH REGISTER OFFSET [2:0] Source/Destination Register [5:3] Base Register [8:6] Offset Register [10] Byte/Word Flag 0 = Transfer word quantity 1 = Transfer byte quantity [11] Load/Store Flag 0 = Store to memory 1 = Load from memory 15 0 0 14 10 6 5 3 2 Rd 1 0 13 12 11 Rb 1 L B 9 8 Ro 0 Figu[...]

S3C2410A THUMB INSTRUCTION SET 4- 19 OPERATION These instructions transfer byte or word values between registers and memory. Memory addresses are pre-indexed using an offset register in the range 0-7. The THUMB assembler syntax is shown in Table 4-8. Table 4-8. Summary of Format 7 Instructions L B THUMB assembler ARM equivalent Action 0 0 STR Rd, [[...]

THUMB INSTRUCTION SET S3C2410A 4- 20 FORMAT 8: LOAD/STORE SIGN-EXTENDED BYTE/HALFWORD [2:0] Destination Register [5:3] Base Register [8:6] Offset Register [10] Sign-Extended Flag 0 = Operand not sing-extended 1 = Operand sing-extended [11] H Flag 15 0 0 14 10 6 5 3 2 Rd 1 0 13 12 11 Rb 1 H S 9 8 Ro 1 Figure 4-9. Format 8 OPERATION These instruction[...]

S3C2410A THUMB INSTRUCTION SET 4- 21 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-9. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STRH R4, [R3, R0] ; Store the lower 16 bits of R4 at the ; address formed by ad[...]

THUMB INSTRUCTION SET S3C2410A 4- 22 FORMAT 9: LOAD/STORE WITH IMMEDIATE OFFSET [2:0] Source/Destination Register [5:3] Base Register [10:6] Offset Register [11] Load/Store Flag 0 = Store to memory 1 = Load from memory [12] Byte/Word Flad 0 = Transfer word quantity 1 = Transfer byte quantity 15 0 0 14 10 6 5 3 2 Rd 1 1 13 12 11 Rb B L Offset5 Figur[...]

S3C2410A THUMB INSTRUCTION SET 4- 23 OPERATION These instructions transfer byte or word values between registers and memory using an immediate 5 or 7-bit offset. The THUMB assembler syntax is shown in Table 4-10. Table 4-10. Summary of Format 9 Instructions L B THUMB assembler ARM equivalent Action 0 0 STR Rd, [Rb, #Imm] STR Rd, [Rb, #Imm] Calculat[...]

THUMB INSTRUCTION SET S3C2410A 4- 24 FORMAT 10: LOAD/STORE HALFWORD [2:0] Source/Destination Register [5:3] Base Register [10:6] Immediate Value [11] Load/Store Flag 0 = Store to memory 1 = Load from memory 15 0 0 14 10 6 5 3 2 Rd 1 0 13 12 11 Rb 0 L Offset5 Figure 4-11. Format 10 OPERATION These instructions transfer halfword values between a Lo r[...]

S3C2410A THUMB INSTRUCTION SET 4- 25 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-11. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STRH R6, [R1, #56] ; Store the lower 16 bits of R4 at the address formed by ; [...]

THUMB INSTRUCTION SET S3C2410A 4- 26 FORMAT 11: SP-RELATIVE LOAD/STORE [7:0] Immediate Value [10:8] Destination Register [11] Load/Store Bit 0 = Store to memory 1 = Load from memory 15 0 1 14 10 0 0 13 12 11 Word 8 1 L Rd 7 8 Figure 4-12. Format 11 OPERATION The instructions in this group perform an SP-relative load or store. The THUMB assembler sy[...]

S3C2410A THUMB INSTRUCTION SET 4- 27 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-12. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STR R4, [SP,#492] ; Store the contents of R4 at the address ; formed by adding[...]

THUMB INSTRUCTION SET S3C2410A 4- 28 FORMAT 12: LOAD ADDRESS [7:0] 8-bit Unsigned Constant [10:8] Destination Register [11] Source 0 = PC 1 = SP 15 0 1 14 10 0 1 13 12 11 Word 8 0 SP Rd 7 8 Figure 4-13. Format 12 OPERATION These instructions calculate an address by adding an 10-bit constant to either the PC or the SP, and load the resulting address[...]

S3C2410A THUMB INSTRUCTION SET 4- 29 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-13. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES ADD R2, PC, #572 ; R2 := PC + 572, but don't set the ; condition codes. b[...]

THUMB INSTRUCTION SET S3C2410A 4- 30 FORMAT 13: ADD OFFSET TO STACK POINTER [6:0] 7-bit Immediate Value [7] Sign Flag 0 = Offset is positive 1 = Offset is negative 15 0 1 14 10 0 1 13 12 11 SWord 7 1 0 0 7 8 9 6 0 0 S Figure 4-14. Format 13 OPERATION This instruction adds a 9-bit signed constant to the stack pointer. The following table shows the T[...]

S3C2410A THUMB INSTRUCTION SET 4- 31 FORMAT 14: PUSH/POP REGISTERS [7:0] Register List [8] PC/LR Bit 0 = Do not store LR/Load PC 1 = Store LR/Load PC [11] Load/Store Bit 0 = Store to memory 1 = Load from memory 15 0 1 14 10 0 1 13 12 11 Rlist 1 L 0 7 8 9 1 R Figure 4-15. Format 14 OPERATION The instructions in this group allow registers 0-7 and opt[...]

THUMB INSTRUCTION SET S3C2410A 4- 32 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-15. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES PUSH {R0-R4,LR} ; Store R0,R1,R2,R3,R4 and R14 (LR) at ; the stack pointed to [...]

S3C2410A THUMB INSTRUCTION SET 4- 33 FORMAT 15: MULTIPLE LOAD/STORE [7:0] Register List [10:8] Base Register [11] Load/Store Bit 0 = Store to memory 1 = Load from memory 15 0 1 14 10 1 0 13 12 11 Rlist 0 L 7 8 Rb Figure 4-16. Format 15 OPERATION These instructions allow multiple loading and storing of Lo registers. The THUMB assembler syntax is sho[...]

THUMB INSTRUCTION SET S3C2410A 4- 34 FORMAT 16: CONDITIONAL BRANCH [7:0] 8-bit Signed Immediate [11:8] Condition 15 0 1 14 1 0 13 12 11 SOffset 8 1 7 8 Cond Figure 4-17. Format 16 OPERATION The instructions in this group all perform a conditional Branch depending on the state of the CPSR condition codes. The branch offset must take account of the p[...]

S3C2410A THUMB INSTRUCTION SET 4- 35 Table 4-17. The Conditional Branch Instructions (Continued) L THUMB assembler ARM equivalent Action 1001 BLS label BLS label Branch if C clear or Z set (unsigned lower or same) 1010 BGE label BGE label Branch if N set and V set, or N clear and V clear (greater or equal) 1011 BLT label BLT label Branch if N set a[...]

THUMB INSTRUCTION SET S3C2410A 4- 36 FORMAT 17: SOFTWARE INTERRUPT [7:0] Comment Field 15 0 1 14 1 0 13 12 11 Value 8 1 7 8 10 9 1111 Figure 4-18. Format 17 OPERATION The SWI instruction performs a software interrupt. On taking the SWI, the processor switches into ARM state and enters Supervisor (SVC) mode. The THUMB assembler syntax for this instr[...]

S3C2410A THUMB INSTRUCTION SET 4- 37 FORMAT 18: UNCONDITIONAL BRANCH [10:0] Immediate Value 15 0 1 14 1 1 13 12 11 Offset11 0 10 0 Figure 4-19. Format 18 OPERATION This instruction performs a PC-relative Branch. The THUMB assembler syntax is shown below. The branch offset must take account of the prefetch operation, which causes the PC to be 1 word[...]

THUMB INSTRUCTION SET S3C2410A 4- 38 FORMAT 19: LONG BRANCH WITH LINK [10:0] Long Branch and Link Offset High/Low [11] Low/High Offset Bit 0 = Offset high 1 = Offset low 15 0 1 14 1 1 13 12 11 Offset 1 10 H Figure 4-20. Format 19 OPERATION This format specifies a long branch with link. The assembler splits the 23-bit two's complement half-word[...]

S3C2410A THUMB INSTRUCTION SET 4- 39 INSTRUCTION CYCLE TIMES This instruction format does not have an equivalent ARM instruction. Table 4-20. The BL Instruction L THUMB assembler ARM equivalent Action 0 BL label none LR := PC + OffsetHigh << 12 1 temp := next instruction address PC := LR + OffsetLow << 1 LR := temp | 1 EXAMPLES BL faraw[...]

THUMB INSTRUCTION SET S3C2410A 4- 40 INSTRUCTION SET EXAMPLES The following examples show ways in which the THUMB instructions may be used to generate small and efficient code. Each example also shows the ARM equivalent so these may be compared. MULTIPLICATION BY A CONSTANT USING SHIFTS AND ADDS The following shows code to multiply by various const[...]

S3C2410A THUMB INSTRUCTION SET 4- 41 GENERAL PURPOSE SIGNED DIVIDE This example shows a general purpose signed divide and remainder routine in both Thumb and ARM code. Thumb code ;signed_divide ; Signed divide of R1 by R0: returns quotient in R0, ; remainder in R1 ;Get abs value of R0 into R3 ASR R2, R0, #31 ; Get 0 or -1 in R2 depending on sign of[...]

THUMB INSTRUCTION SET S3C2410A 4- 42 Now fix up the signs of the quotient (R0) and remainder (R1) POP {R2, R3} ; Get dividend/divisor signs back EOR R3, R2 ; Result sign EOR R0, R3 ; Negate if result sign = - 1 SUB R0, R3 EOR R1, R2 ; Negate remainder if dividend sign = - 1 SUB R1, R2 MOV pc, lr ARM Code signed_divide ; Effectively zero a4 as top b[...]

S3C2410A THUMB INSTRUCTION SET 4- 43 DIVISION BY A CONSTANT Division by a constant can often be performed by a short fixed sequence of shifts, adds and subtracts. Here is an example of a divide by 10 routine based on the algorithm in the ARM Cookbook in both Thumb and ARM code. Thumb Code udiv10 ; Take argument in a1 returns quotient in a1, ; remai[...]

THUMB INSTRUCTION SET S3C2410A 4- 44 NOTES[...]

S3C2410A MEMORY CONTROLLER 5- 1 5 MEMORY CONTROLLER OVERVIEW The S3C2410A's memory controller provides memory control signals required for external memory access. The S3C2410A has the following features: — Little/Big endian (selectable by a software) — Address space: 128Mbytes per ban k (total 1GB/8 banks) — Programmable access size (8[...]

MEMORY CONTROLLER S 3C2410A 5- 2 [Not using NAND flash for boot ROM] SROM/SDRAM (nGCS7) 128MB 2MB/4MB/8MB/16MB /32MB/64MB/128MB 1GB HADDR[29:0] Accessible Region NOTES: 1. SROM means ROM or SRAM type memory. 2. SFR means Special Function Register. Refer to Table 5-1 0x3000_0000 0x2800_0000 0x2000_0000 0x1800_0000 0x1000_0000 0x0800_0000 0x4000_0000[...]

S3C2410A MEMORY CONTROLLER 5- 3 FUNCTION DESCRIPTION BANK0 BUS WIDTH The data bus of BANK0 (nGCS0) should be configured to either 16-bit or 32-bit accordingly. Because the BANK0 works as the booting ROM bank (map to 0x0000_0000), the bus width of BANK0 should be determined before the first ROM access, which will depe nd on the logic level of OM[1:0[...]

MEMORY CONTROLLER S 3C2410A 5- 4 SDRAM BANK ADDRESS PIN CONNECTION Table 5-2. SDRAM Bank Address Configuration Bank Size Bus Width Base Component Memory Configuration Bank Address 2MB x8 16Mb ( 1M x 8 x 2banks) x 1 ea A20 x16 (512K x 16 x 2banks) x 1 ea 4MB x8 16Mb ( 2M x 4 x 2banks) x 2 ea A21 x16 ( 1M x 8 x 2banks) x 2 ea x32 (512K x 16 x 2banks)[...]

S3C2410A MEMORY CONTROLLER 5- 5 n WAIT PIN OPERATION If the WAIT corresponding to each memory bank is enabled, the nOE duration should be prolonged by the external nWAIT pin while the memory bank is active. nWAIT is checked from tacc-1. nOE will be deasserted at the next clock after sampling nWAIT is high. The nWE signal have the same relation with[...]

MEMORY CONTROLLER S 3C2410A 5- 6 nXBREQ/nXBACK Pin Operation If nXBREQ is asserted, the S3C2410A will respond by lowering nXBACK. If nXBACK = L, the address/data bus and memory control signals are in Hi-z state as shown in Table 1-1. When nXBREQ is de-asserted, the nXBACK will also be de-asserted. HCLK SCKE, A[24:0] D[31:0],nGCS nOE,nWE nWBE nXBREQ[...]

S3C2410A MEMORY CONTROLLER 5- 7 ROM Memory Interface Examples A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 D4 D5 D6 D7 nWE nOE nGCSn A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE Figure 5-4. Memory Interface with 8-bit ROM A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16[...]

MEMORY CONTROLLER S 3C2410A 5- 8 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 D0 D1 D2 D3 D4 D5 D6 D7 nWBE0 nOE nGCSn A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 D8 D9 D10 D11 D12 D13 D14 D15 nWBE1 nOE nGCSn A0 A1 A2 A3 A4 A5 A6 [...]

S3C2410A MEMORY CONTROLLER 5- 9 SRAM Memory Interface Examples A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nWE nOE nCS nUB nLB nWE nOE nGCSn nBE1 nBE0 Figure 5-8[...]

MEMORY CONTROLLER S 3C2410A 5- 10 SDRAM Memory Interface Examples A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nSCS nSRAS nSCAS nWE nSCS0 nSRAS nSCAS nWE A21 A22 DQM0 DQM1 SCKE SCLK BA0 BA1 LDQM[...]

S3C2410A MEMORY CONTROLLER 5- 11 PROGRAMMABLE ACCESS CYCLE Tcoh Tcos Tacs HCLK A[24:0] nGCS nOE nWE nWBE D[31:0](R) D[31:0] (W) Tacc Tacp Tcah Tacs = 1 cycle Tcos = 1 cycle Tacc = 3 cycles Tacp = 2 cycles Tcoh = 1 cycle Tcah = 2 cycles Figure 5-12. S3C2410A nGCS Timing Diagram[...]

MEMORY CONTROLLER S 3C2410A 5- 12 HCLK SCKE nSCS nSCAS ADDR A10/AP RA nSRAS BA DATA (CL2) DATA (CL3) nWE DQM Trp Trcd RA Ca Da Da BA BA Cb Cc Cd Ce Db Dc Dd De Db Dc Dd De BA BA BA BA BA Bank Precharge Row Active Write Read (CL = 2, CL = 3, BL = 1) Trp = 2 cycle Tcas = 2 cycle Trcd = 2 cycle Tcp = 2 cycle Figure 5-13. S3C2410A SDRAM Timing Diagram[...]

S3C2410A MEMORY CONTROLLER 5- 13 BUS WIDTH & WAIT CONTROL REGISTER (BWSCON) Register Address R/W Description Reset Value BWSCON 0x48000000 R/W Bus width & wait status control register 0x000000 BWSCON Bit Description Initial state ST7 [31] Determine SRAM for using UB/LB for bank 7. 0 = Not using UB/LB (The pins are dedicated nWBE[3:0]) 1 = U[...]

MEMORY CONTROLLER S 3C2410A 5- 14 BUS WIDTH & WAIT CONTROL REGISTER (BWSCON) ( Continued) BWSCON Bit Description Initial state WS2 [10] Determine WAIT status for bank 2. 0 = WAIT disable 1 = WAIT enable 0 DW2 [9:8] Determine data bus width for bank 2. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved 0 ST1 [7] Determine SRAM for using UB/LB for[...]

S3C2410A MEMORY CONTROLLER 5- 15 BANK CONTROL REGISTER (BANKCONN: n GCS0- n GCS5) Register Address R/W Description Reset Value BANKCON0 0x48000004 R/W Bank 0 control register 0x0700 BANKCON1 0x48000008 R/W Bank 1 control register 0x0700 BANKCON2 0x4800000C R/W Bank 2 control register 0x0700 BANKCON3 0x48000010 R/W Bank 3 control register 0x0700 BAN[...]

MEMORY CONTROLLER S 3C2410A 5- 16 BANK CONTROL REGISTER (BANKCON n : n GCS6- n GCS7) Register Address R/W Description Reset Value BANKCON6 0x4800001C R/W Bank 6 control register 0x18008 BANKCON7 0x48000020 R/W Bank 7 control register 0x18008 BANKCONn Bit Description Initial State MT [16:15] Determine the memory type for bank6 and bank7. 00 = ROM or[...]

S3C2410A MEMORY CONTROLLER 5- 17 REFRESH CONTROL REGISTER Register Address R/W Description Reset Value REFRESH 0x48000024 R/W SDRAM refresh control register 0xac0000 REFRESH Bit Description Initial State REFEN [23] SDRAM Refresh Enable 0 = Disable 1 = Enable (self/auto refresh) 1 TREFMD [22] SDRAM Refresh Mode 0 = Auto Refresh 1 = Self Refresh In s[...]

MEMORY CONTROLLER S 3C2410A 5- 18 BANKSIZE REGISTER Register Address R/W Description Reset Value BANKSIZE 0x48000028 R/W Flexible bank size register 0x0 BANKSIZE Bit Description Initial State BURST_EN [7] ARM core burst operation enable. 0 = Disable burst operation. 1 = Enable burst operation. 0 Reserved [6] Not used 0 SCKE_EN [5] SCKE enable contr[...]

S3C2410A MEMORY CONTROLLER 5- 19 SDRAM MODE REGISTER SET REGISTER (MRSR) Register Address R/W Description Reset Value MRSRB6 0x4800002C R/W Mode register set register bank6 xxx MRSRB7 0x48000030 R/W Mode register set register bank7 xxx MRSR Bit Description Initial State Reserved [11:10] Not used – WBL [9] Write burst length 0: Burst (Fixed) 1: Re[...]

MEMORY CONTROLLER S 3C2410A 5- 20 NOTES[...]

S3C2410A NAND FLASH CONTROLLER 6- 1 6 NAND FLASH CONTROLLER OVERVIEW Recently, a NOR flash memory gets high in price while an SDRAM and a NAND flash memory get moderate, motivating some users to execute the boot code on a NAND flash and execute the main code on an SDRAM. S3C2410A boot code can be executed on an external NAND flash memory. In order [...]

NAND FLASH CONTROLLER S3C2410A 6- 2 BLOCK DIAGRAM Buffer Control System Bus CLE Internal Buffer (4KB) Register Bank Control State Machine ECC Encoder/ Decoder NAND Flash Interface nCE nRE nWE R/nB I/O0~I/O7 ALE Figure 6-1. NAND Flash Controller Block Diagram OPERATION SCHEME Steppingstone (4 KB Buffer) NAND Flash Controller NAND Flash Memory Specia[...]

S3C2410A NAND FLASH CONTROLLER 6- 3 AUTO BOOT MODE SEQUENCE 1. Reset is completed. 2. When the auto boot mode is enabled, the first 4 KBytes of NAND flash memory is copied onto Steppingstone 4- KB internal buffer. 3. The Steppingstone is mapped to nGCS0. 4. CPU starts to execute the boot code on the Steppingstone 4-KB internal buffer. NOTE In the a[...]

NAND FLASH CONTROLLER S3C2410A 6- 4 PIN CONFIGURATION D[7:0] : Data/Command/Address In/Out Port (shared with the data bus) CLE : Command Latch Enable (Output) ALE : Address Latch Enable (Output) nFCE : NAND Flash Chip Enable (Output) nFRE : NAND Flash Read Enable (Output) nFWE : NAND Flash Write Enable (Output) R/nB : NAND Flash Ready/nBusy (Input)[...]

S3C2410A NAND FLASH CONTROLLER 6- 5 NAND FLASH MEMORY MAPPING NOTE: SFR means Special Function Register. Not Used SFR Area Not Used BootSRAM (4KBytes) SFR Area Not Used SDRAM (BANK7, nGCS7) SDRAM (BANK7, nGCS7) SDRAM (BANK6, nGCS6) SDRAM (BANK6, nGCS6) SROM (BANK5, nGCS5) SROM (BANK5, nGCS5) SROM (BANK4, nGCS4) SROM (BANK3, nGCS3) SROM (BANK2, nGCS[...]

NAND FLASH CONTROLLER S3C2410A 6- 6 SPECIAL FUNCTION REGISTERS NAND FLASH CONFIGURATION ( NFCONF ) REGISTER Register Address R/W Description Reset Value NFCONF 0x4E000000 R/W NAND flash configuration – NFCONF Bit Description Initial State Enable/Disable [15] NAND flash controller enable/disable 0 = Disable NAND Flash Controller 1 = Enable NAND Fl[...]

S3C2410A NAND FLASH CONTROLLER 6- 7 NAND FLASH COMMAND SET (NFCMD) REGISTER Register Address R/W Description Reset Value NFCMD 0x4E000004 R/W NAND flash command set register – NFCMD Bit Description Initial State Reserved [15:8] Reserved – Command [7:0] NAND flash memory command value 0x00 NAND FLASH ADDRESS SET (NFADDR) REGISTER Register Addres[...]

NAND FLASH CONTROLLER S3C2410A 6- 8 NAND FLASH OPERATION STATUS (NFSTAT) REGISTER Register Address R/W Description Reset Value NFSTAT 0x4E000010 R NAND flash operation status – NFSTAT Bit Description Initial State Reserved [16:1] Reserved – RnB [0] NAND flash memory ready/busy status. (This signal is checked through R/nB pin.) 0 = NAND flash me[...]

S3C2410A CLOCK & POWER MANAGEMENT 7 - 1 7 CLOCK & POWER MANAGEMENT OVERVIEW The clock & power management block consists of three parts: clock control, USB control, and power control. The Clock control logic in S3C2410A can generate the required clock signals including FCLK for CPU, HCLK for the AHB bus peripherals, and PCLK for the APB [...]

CLOCK & POWER MANAGEMENT S3C2410A 7 - 2 FUNCTIONAL DESCRIPTION CLOCK ARCHITECTURE Figure 7-1 shows a block diagram of the clock architecture. The main clock source comes from an external crystal (XTIpll) or an external clock (EXTCLK). The clock generator includes an oscillator (Oscillation Amplifier), which is connected to an external crystal, [...]

S3C2410A CLOCK & POWER MANAGEMENT 7 - 3 Nand Flash Controller OSC MPLL UPLL CLKCNTL FCLK HDIVN PDIVN Mpll Control Signal Upll POWCNTL F H P USBCNTL Test mode OM[1:0] Bus Controller Memory Controller Arbitration DMA 4ch ExtMaster WDT I 2 S SDI ADC UART(0,1,2) PWM I 2 C GPIO RTC SPI(0,1) USB Device ARM920T Interrupt Controller LCD Controller H_LC[...]

CLOCK & POWER MANAGEMENT S3C2410A 7 - 4 PHASE LOCKED LOOP (PLL) The MPLL within the clock generator, as a circuit, synchronizes an output signal with a reference input signal in frequency and phase. In this application, it includes the following basic blocks as shown in Figure 7-2: the Voltage Controlled Oscillator (VCO) to generate the output [...]

S3C2410A CLOCK & POWER MANAGEMENT 7 - 5 Divider P Loop Filter Fin M[7:0] S[1:0] PFD Divider M P[5:0] F vco PUMP VCO Divider S F ref MPLL,UPLL R C Internal 5 pF External MPLLCAP, UPLLCAP Figure 7-2. PLL (Phase-Locked Loop) Block Diagram EXTCLK XTIpll XTOpll EXTCLK XTIpll XTOpll External OSC a) X-TAL Oscillation (OM[3:2]=00) b) External Clock Sou[...]

CLOCK & POWER MANAGEMENT S3C2410A 7 - 6 CLOCK CONTROL LOGIC The clock control logic determines the clock source to be used, i.e., the PLL clock (Mpll) or the direct external clock (XTIpll or EXTCLK). When PLL is configured to a new frequency value, the clock control logic disables the FCLK until the PLL output is stabilized using the PLL lockin[...]

S3C2410A CLOCK & POWER MANAGEMENT 7 - 7 Change PLL Settings In Normal Operation Mode During the operation of the S3C2410A in NORMAL mode, the user can change the frequency by writing the PMS value and the PLL lock time will be automatically inserted. During the lock time, the clock is not supplied to the internal blocks in the S3C2410A. Figure [...]

CLOCK & POWER MANAGEMENT S3C2410A 7 - 8 FCLK, HCLK, and PCLK FCLK is used by ARM920T. HCLK is used for AHB bus, which is used by the ARM920T, the memory controller, the interrupt controller, the LCD controller, the DMA and the USB host block. PCLK is used for APB bus, which is used by the peripherals such as WDT, IIS, I2C, PWM timer, MMC interf[...]

S3C2410A CLOCK & POWER MANAGEMENT 7 - 9 POWER MANAGEMENT The power management block controls the system clocks by software for the reduction of power consumption in the S3C2410A. These schemes are related to PLL, clock control logics (FCLK, HCLK, and PCLK) and wakeup signals. Figure 7-7 shows the clock distribution of the S3C2410A. The S3C2410A[...]

CLOCK & POWER MANAGEMENT S3C2410A 7 - 10 IDLE POWER_OFF NORMAL (SLOW_BIT=0) SLOW (SLOW_BIT=1) IDLE_BIT=1 Interrupts, EINT[0:23], RTC alarm POWER_OFF BIT=1 EINT[15:0], RTC alarm RESET Figure 7-8. Power Management State Diagram Table 7-2. Clock and Power State in Each Power Mode Mode ARM920T AHB Modules (1) /WDT Power Management GPIO 32.768k H z [...]

S3C2410A CLOCK & POWER MANAGEMENT 7 - 11 NORMAL Mode In normal mode, all peripherals and the basic blocks including power management block, the CPU core, the bus controller, the memory controller, the interrupt controller, DMA, and the external master may operate fully. But, the clock to each peripheral, except the basic blocks, can be stopped [...]

CLOCK & POWER MANAGEMENT S3C2410A 7 - 12 Users can change the frequency by enabling SLOW mode bit in CLKSLOW register in PLL on state. The SLOW clock is generated during the SLOW mode. Figure 7-9 shows the timing diagram. Mpll Slow mode disable FCLK Slow mode enable SLOW_BIT Divided external clock MPLL_OFF It changes to PLL clock after slow mod[...]

S3C2410A CLOCK & POWER MANAGEMENT 7 - 13 If the user switches from SLOW mode to Normal mode by disabling SLOW_BIT and MPLL_OF F bit simultaneously in the CLKSLOW register, the frequency is changed just after the PLL lock time. Figure 7-11 shows the timing diagram. Mpll FCLK SLOW_BIT Divided OSC clock MPLL_OFF Hardware lock time PLL off PLL on S[...]

CLOCK & POWER MANAGEMENT S3C2410A 7 - 14 Power_OFF Mode The block disconnects the internal power. So, there occurs no power consumption due to CPU and the internal logic except the wake-up logic in this mode. Activating the Power_OFF mode requires two independent power sources. One of the two power sources supplies the power for the wake-up log[...]

S3C2410A CLOCK & POWER MANAGEMENT 7 - 15 Procedure to Wake-up from Power_OFF mode 1. The internal reset signal will be asserted if one of the wake-up sources is issued. This reset duration is determined by the internal 16-bit counter logic and the reset assertion time is calculated as tRST = (65535 / XTAL_frequency). 2. Check GSTATUS2[2] in ord[...]

CLOCK & POWER MANAGEMENT S3C2410A 7 - 16 Power Control of VDDi and VDDiarm In Power_OFF mode, only VDDi and VDDiarm will be turned off, which is controlled by PWREN pin. If PWREN signal is active(H), VDDi and VDDiarm are supplied by an external voltage regulator. If PWREN pin is inactive (L), the VDDi and VDDiarm are turned off. NOTE Although V[...]

S3C2410A CLOCK & POWER MANAGEMENT 7 - 17 Signaling EINT[15:0] for Wakeup The S3C2410A can be woken up from Power_OFF mode only if the following conditions are met. a) Level signals (H or L) or edge signals (rising or falling or both) are asserted on EINTn input pin. b) The EINTn pin has to be configured as EINT in the GPIO control register. c) [...]

CLOCK & POWER MANAGEMENT S3C2410A 7 - 18 Output Port State and Power_OFF Mode The output port should have a proper logic level in power off mode, which makes the current consumption minimized. If there is no load on an output port pin, H level is preferred. If output is L, the current will be consumed through the internal parasitic resistance; [...]

S3C2410A CLOCK & POWER MANAGEMENT 7 - 19 CLOCK GENERATOR & POWER MANAGEMENT SPECIAL REGISTER LOCK TIME COUNT REGISTER (LOCKTIME) Register Address R/W Description Reset Value LOCKTIME 0x4C000000 R/W PLL lock time count register 0x00FFFFFF LOCKTIME Bit Description Initial State U_LTIME [23:12] UPLL lock time count value for UCLK. (U_LTIME >[...]

CLOCK & POWER MANAGEMENT S3C2410A 7 - 20 PLL VALUE SELECTION TABLE It is not easy to find a proper PLL value. So, We recommend referring to the following PLL value recommendation table. Input Frequency Output Frequency MDIV PDIV SDIV 12.00MHz 11.289MHz N/A N/A N/A 12.00MHz 16.934MHz N/A N/A N/A 12.00MHz 22.50MHz N/A N/A N/A 12.00MHz 33.75MHz 82[...]

S3C2410A CLOCK & POWER MANAGEMENT 7 - 21 CLOCK CONTROL REGISTER (CLKCON) Register Address R/W Description Reset Value CLKCON 0x4C00000C R/W Clock generator control register 0x7FFF0 CLKCON Bit Description Initial State SPI [18] Control PCLK into SPI block. 0 = Disable, 1 = Enable 1 IIS [17] Control PCLK into IIS block. 0 = Disable, 1 = Enable 1 [...]

CLOCK & POWER MANAGEMENT S3C2410A 7 - 22 CLOCK SLOW CONTROL (CLKSLOW) REGISTER Register Address R/W Description Reset Value CLKSLOW 0x4C000010 R/W Slow clock control register 0x00000004 CLKSLOW Bit Description Initial State UCLK_ON [7] 0: UCLK ON (UPLL is also turned on and the UPLL lock time is inserted automatically.) 1: UCLK OFF (UPLL is als[...]

S3C2410A DMA ] 8- 1 8 DMA OVERVIEW The S3C2410A supports four-channel DMA controller that is located between the system bus and the peripheral bus. Each channel of DMA controller can perform data movements between devices in the system bus and/or peripheral bus with no restrictions. In other words, each channel can handle the following four cases: [...]

DMA S3C2410A 8- 2 DMA REQUEST SOURCES Each channel of the DMA controller can select one of DMA request source among four DMA sources if H/W DMA request mode is selected by DCON register. (Note that if S/W request mode is selected, this DMA request sources have no meaning at all.) Table 8-1 shows four DMA sources for each channel. Table 8-1. DMA Req[...]

S3C2410A DMA 8- 3 EXTERNAL DMA DREQ/DACK PROTOCOL There are three types of external DMA request/acknowledge protocols (Single service Demand, Single service Handshake and Whole service Handshake mode). Each type defines how the signals like DMA request and acknowledge are related to these protocols. Basic DMA Timing The DMA service means performing[...]

DMA S3C2410A 8- 4 Demand/Handshake Mode Comparison Demand and Handshake modes are related to the protocol between XnXDREQ and XnXDACK. Figure 8-2 shows the differences between the two modes. At the end of one transfer (Single/Burst transfer), DMA checks the state of double-synched XnXDREQ. Demand M ode — If XnXDREQ remains asserted, the next tran[...]

S3C2410A DMA 8- 5 Transfer Size — There are two different transfer sizes; unit and Burst 4. — DMA holds the bus firmly during the transfer of the chunk of data. Thus, other bus masters cannot get the bus. Burst 4 Transfer Size Four sequential Reads and Writes are performed respectively in the Burst 4 Transfer. NOTE Unit Transfer size: One read [...]

DMA S3C2410A 8- 6 EXAMPLES Single service in Demand Mode with Unit Transfer Size The assertion of XnXDREQ is need for every unit transfer (Single service mode). The operation continues while the XnXDREQ is asserted (Demand mode), and one pair of Read and Write (Single transfer size) is performed. XSCLK XnXDREQ XnXDACK Double synch Read Write ~ ~ ~ [...]

S3C2410A DMA 8- 7 DMA SPECIAL REGISTERS Each DMA channel has nine control registers (36 in total since there are four channels for DMA controller). Six of the control registers control the DMA transfer, and other three ones monitor the status of DMA controller. The details of those registers are as follows. DMA INITIAL SOURCE ( DISRC ) REGISTER Reg[...]

DMA S3C2410A 8- 8 DMA INITIAL DESTINATION (DIDST) REGISTER Register Address R/W Description Reset Value DIDST0 0x4B000008 R/W DMA 0 initial destination register 0x00000000 DIDST1 0x4B000048 R/W DMA 1 initial destination register 0x00000000 DIDST2 0x4B000088 R/W DMA 2 initial destination register 0x00000000 DIDST3 0x4B0000B8 R/W DMA 3 initial destin[...]

S3C2410A DMA 8- 9 DMA CONTROL (DCON) REGISTER Register Address R/W Description Reset Value DCON0 0x4B000010 R/W DMA 0 control register 0x00000000 DCON1 0x4B000050 R/W DMA 1 control register 0x00000000 DCON2 0x4B000090 R/W DMA 2 control register 0x00000000 DCON3 0x4B0000D0 R/W DMA 3 control register 0x00000000 DCONn Bit Description Initial State DMD[...]

DMA S3C2410A 8- 10 DMA CONTROL (DCON) REGISTER ( Continued) DCONn Bit Description Initial State SERVMODE [27] Select the service mode between Single service mode and Whole service mode. 0: Single service mode is selected in which after each atomic transfer (single or burst of length four) DMA stops and waits for another DMA request. 1: Whole servic[...]

S3C2410A DMA 8- 11 DMA STATUS (DSTAT) REGISTER Register Address R/W Description Reset Value DSTAT0 0x4B000014 R DMA 0 count register 000000h DSTAT1 0x4B000054 R DMA 1 count register 000000h DSTAT2 0x4B000094 R DMA 2 count register 000000h DSTAT3 0x4B0000D4 R DMA 3 count register 000000h D STAT n Bit Description Initial State STAT [21:20] Status of [...]

DMA S3C2410A 8- 12 CURRENT DESTINATION (DCDST) REGISTER Register Address R/W Description Reset Value DCDST0 0x4B00001C R DMA 0 current destination register 0x00000000 DCDST1 0x4B00005C R DMA 1 current destination register 0x00000000 DCDST2 0x4B00009C R DMA 2 current destination register 0x00000000 DCDST3 0x4B0000DC R DMA 3 current destination regis[...]

S3C2410A DMA 8- 13 DMA MASK TRIGGER (DMASKTRIG) REGISTER Register Address R/W Description Reset Value DMASKTRIG0 0x4B000020 R/W DMA 0 mask trigger register 000 DMASKTRIG1 0x4B000060 R/W DMA 1 mask trigger register 000 DMASKTRIG2 0x4B0000A0 R/W DMA 2 mask trigger register 000 DMASKTRIG3 0x4B0000E0 R/W DMA 3 mask trigger register 000 DMASKTRIGn Bit D[...]

DMA S3C2410A 8- 14 S/W Work-Around The DMA auto-reload is occurred only when the DMA request is issued after the DMA counter reaches 0. So, the following code should be used in the DMA done interrupt handler before setting the DMA source address, destination address and counter register for the next auto-reload. This code will wait until the first [...]

S3C2410A I/O PORTS 9- 1 9 I/O PORTS OVERVIEW The S3C2410A has 117 multi-functional input/output port pins. The ports are: — Port A (GPA): 23-output port — Port B (GPB): 11-input/output port — Port C (GPC): 16-input/output port — Port D (GPD): 16-input/output port — Port E (GPE): 16-input/output port — Port F (GPF): 8-input/output port ?[...]

I/O PORTS S3C 2410A 9- 2 Table 9-1. S3C2410A Port Configuration Port A Selectable Pin Functions GPA22 Output only nFCE – – GPA21 Output only nRSTOUT – – GPA20 Output only nFRE – – GPA19 Output only nFWE – – GPA18 Output only ALE – – GPA17 Output only CLE – – GPA16 Output only nGCS5 – – GPA15 Output only nGCS4 – – GPA[...]

S3C2410A I/O PORTS 9- 3 Table 9-1. S3C2410A Port Configuration (Continued) Port B Selectable Pin Functions GPB10 Input/output nXDREQ0 – – GPB9 Input/output nXDACK0 – – GPB8 Input/output nXDREQ1 – – GPB7 Input/output nXDACK1 – – GPB6 Input/output nXBREQ – – GPB5 Input/output nXBACK – – GPB4 Input/output TCLK0 – – GPB3 Inp[...]

I/O PORTS S3C 2410A 9- 4 Table 9-1. S3C2410A Port Configuration (Continued) Port D Selectable Pin Functions GPD15 Input/output VD23 nSS0 – GPD14 Input/output VD22 nSS1 – GPD13 Input/output VD21 – – GPD12 Input/output VD20 – – GPD11 Input/output VD19 – – GPD10 Input/output VD18 – – GPD9 Input/output VD17 – – GPD8 Input/output[...]

S3C2410A I/O PORTS 9- 5 Table 9-1. S3C2410A Port Configuration (Continued) Port F Selectable Pin Functions GPF7 Input/output EINT7 – – GPF6 Input/output EINT6 – – GPF5 Input/output EINT5 – – GPF4 Input/output EINT4 – – GPF3 Input/output EINT3 – – GPF2 Input/output EINT2 GPF1 Input/output EINT1 GPF0 Input/output EINT0 Port G Sele[...]

I/O PORTS S3C 2410A 9- 6 Table 9-1. S3C2410A Port Configuration (Continued) Port H Selectable Pin Functions GPH10 Input/output CLKOUT1 – – GPH9 Input/output CLKOUT0 – – GPH8 Input/output UEXTCLK – – GPH7 Input/output RXD2 nCTS1 – GPH6 Input/output TXD2 nRTS1 – GPH5 Input/output RXD1 – – GPH4 Input/output TXD1 – – GPH3 Input/[...]

S3C2410A I/O PORTS 9- 7 PORT CONTROL DESCRIPTIONS PORT CONFIGURATION REGISTER (GPACON-GPHCON) In the S3C2410A, most pins are multiplexed. So, It is require to determine which function is selected for each pin. port control register (PnCON) determines the function of each pin. If GPF0 – GPF7 and GPG0 – GPG7 are used for wakeup signals in Power-O[...]

I/O PORTS S3C 2410A 9- 8 I/O PORT CONTROL REGISTER PORT A CONTROL REGISTERS (GPACON/GPADAT) Register Address R/W Description Reset Value GPACON 0x56000000 R/W Configure the pins of port A 0x7FFFFF GPADAT 0x56000004 R/W The data register for port A Undefined Reserved 0x56000008 – Reserved Undefined Reserved 0x5600000C – Reserved Undefined GPACON[...]

S3C2410A I/O PORTS 9- 9 PORT B CONTROL REGISTERS (GPBCON, GPBDAT, and GPBUP) Register Address R/W Description Reset Value GPBCON 0x56000010 R/W Configure the pins of port B 0x0 GPBDAT 0x56000014 R/W The data register for port B Undefined GPBUP 0x56000018 R/W Pull-up disable register for port B 0x0 Reserved 0x5600001C – Reserved Undefined GPBCON B[...]

I/O PORTS S3C 2410A 9- 10 PORT C CONTROL REGISTERS (GPCCON, GPCDAT, and GPCUP) Register Address R/W Description Reset Value GPCCON 0x56000020 R/W Configure the pins of port C 0x0 GPCDAT 0x56000024 R/W The data register for port C Undefined GPCUP 0x56000028 R/W Pull-up disable register for port C 0x0 Reserved 0x5600002C – Reserved Undefined GPCCON[...]

S3C2410A I/O PORTS 9- 11 G PCDAT Bit Description GPC[15:0] [15:0] When the port is configured as input port, data from external sources can be read to the corresponding pin. When the port is configured as output port, data written in this register can be sent to the corresponding pin. When the port is configured as functional pin, undefined value w[...]

I/O PORTS S3C 2410A 9- 12 PORT D CONTROL REGISTERS (GPDCON, GPDDAT, and GPDUP) Register Address R/W Description Reset Value GPDCON 0x56000030 R/W Configure the pins of port D 0x0 GPDDAT 0x56000034 R/W The data register for port D Undefined GPDUP 0x56000038 R/W Pull-up disable register for port D 0xF000 Reserved 0x5600003C – Reserved Undefined GPD[...]

S3C2410A I/O PORTS 9- 13 G PDDAT Bit Description GPD[15:0] [15:0] When the port is configured as input port, data from external sources can be read to the corresponding pin. When the port is configured as output port, data written in this register can be sent to the corresponding pin. When the port is configured as functional pin, undefined value w[...]

I/O PORTS S3C 2410A 9- 14 PORT E CONTROL REGISTERS (GPECON, GPEDAT, and GPEUP) Register Address R/W Description Reset Value GPECON 0x56000040 R/W Configure the pins of port E 0x0 GPEDAT 0x56000044 R/W The data register for port E Undefined GPEUP 0x56000048 R/W pull-up disable register for port E 0x0 Reserved 0x5600004C – Reserved Undefined GPECON[...]

S3C2410A I/O PORTS 9- 15 GPEDAT Bit Description GPE[15:0] [15:0] When the port is configured as input port, data from external sources can be read to the corresponding pin. When the port is configured as output port, data written in this register can be sent to the corresponding pin. When the port is configured as a functional pin, undefined value [...]

I/O PORTS S3C 2410A 9- 16 PORT F CONTROL REGISTERS (GPFCON, GPFDAT, and GPFPU) If GPF0 - GPF7 are used for wakeup signals in Power_OFF mode, the ports must be configured as external interrupt (set in Interrupt mode). Register Address R/W Description Reset Value GPFCON 0x56000050 R/W Configure the pins of port F 0x0 GPFDAT 0x56000054 R/W The data re[...]

S3C2410A I/O PORTS 9- 17 PORT G CONTROL REGISTERS (GPGCON, GPGDAT, AND GPGUP) If GPG [7:0] are used for wakeup signals in Power_OFF mode, the ports must be configured as external interrupt (set in Interrupt mode). Register Address R/W Description Reset Value GPGCON 0x56000060 R/W Configure the pins of port G 0x0 GPGDAT 0x56000064 R/W The data regis[...]

I/O PORTS S3C 2410A 9- 18 GPGDAT Bit Description GPG[15:0] [15:0] When the port is configured as input port, data from external sources can be read to the corresponding pin. When the port is configured as output port, data written in this register can be sent to the corresponding pin. When the port is configured as functional pin, undefined value w[...]

S3C2410A I/O PORTS 9- 19 PORT H CONTROL REGISTERS (GPHCON, GPHDAT, AND GPHUP) Register Address R/W Description Reset Value GPHCON 0x56000070 R/W Configure the pins of port H 0x0 GPHDAT 0x56000074 R/W The data register for port H Undefined GPHUP 0x56000078 R/W Pull-up disable register for port H 0x0 Reserved 0x5600007C – Reserved Undefined GPHCON [...]

I/O PORTS S3C 2410A 9- 20 MISCELLANEOUS CONTROL REGISTER (MISCCR) Pads related USB are controlled by this register for USB host, or for USB device. Register Address R/W Description Reset Value MISCCR 0x56000080 R/W Miscellaneous control register 0x10330 MISCCR Bit Description Reserved [21:20] Reserved to 00b nEN_SCKE [19] 0: SCKE = Normal 1: SCKE =[...]

S3C2410A I/O PORTS 9- 21 DCLK CONTROL REGISTERS (DCLKCON) This register defines DCLKn signals, which work as clocks for external sources. See the following figure for how to make the DCLKn signals. The DCLKCON can actually operate only when CLKOUT[1:0] is set to send the DCLKn signals. Register Address R/W Description Reset Value DCLKCON 0x56000084[...]

I/O PORTS S3C 2410A 9- 22 EXTERNAL INTERRUPT CONTROL REGISTER (EXTINT n ) The 24 external interrupts can be requested by various signaling methods. The EXTINTn configures the signaling method between the level trigger and edge trigger for the external interrupt request, and also configures the signal polarity. To recognize the level interrupt, the [...]

S3C2410A I/O PORTS 9- 23 EXTINT1 Bit Description Reserved [31] Reserved EINT15 [30:28] Set the signaling method of the EINT15. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Reserved [27] Reserved EINT14 [26:24] Set the signaling method of the EINT14. 000 = Low level 001 = High le[...]

I/O PORTS S3C 2410A 9- 24 EXTINT2 Bit Description FLTEN23 [31] Filter Enable for EINT23 0 = Disable 1= Enable EINT23 [30:28] Set the signaling method of the EINT23. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered FLTEN22 [27] Filter Enable for EINT22 0 = Disable 1= Enable EINT22 [2[...]

S3C2410A I/O PORTS 9- 25 EXTERNAL INTERRUPT FILTER REGISTER (EINTFLT n ) The EINTFLTn controls the length of filter for 8 external interrupts (EINT[23:16]). Register Address R/W Description Reset Value EINTFLT0 0x56000094 R/W Reserved EINTFLT1 0x56000098 R/W Reserved EINTFLT2 0x5600009C R/W External interrupt control register 2 0x0 EINTFLT3 0x4C600[...]

I/O PORTS S3C 2410A 9- 26 EXTERNAL INTERRUPT MASK REGISTER (EINTMASK) Interrupt mask register for 20 external interrupts (EINT[23:4]). Register Address R/W Description Reset Value EINTMASK 0x560000A4 R/W External interupt mask register 0x00FFFFF0 EINTMASK Bit Description EINT23 [23] 0 = Enable Interrupt 1= Masked EINT22 [22] 0 = Enable Interrupt 1=[...]

S3C2410A I/O PORTS 9- 27 EXTERNAL INTERRUPT PENDING REGISTER (EINTPEND n ) Interrupt pending register for 20 external interrupts (EINT[23:4]). You can clear a specific bit of the ENITPEND register by writing "1" on the corresponding bit of this register. Register Address R/W Description Reset Value EINTPEND 0x560000A8 R/W External interup[...]

I/O PORTS S3C 2410A 9- 28 GENERAL STATUS REGISTER (GSTATUS n ) Register Address R/W Description Reset Value GSTATUS0 0x560000AC R External pin status Undefined GSTATUS1 0x560000B0 R Chip ID 0x32410000 GSTATUS2 0x560000B4 R/W Reset status 0x1 GSTATUS3 0x560000B8 R/W Infrom register 0x0 GSTATUS4 0x560000BC R/W Infrom register 0x0 GSTATUS0 Bit Descrip[...]

S3C2410A PWM TIMER 10- 1 10 PWM TIMER OVERVIEW The S3C2410A has five 16-bit timers. Timer 0, 1, 2, and 3 have Pulse Width Modulation (PWM) function. Timer 4 has an internal timer only with no output pins. The timer 0 has a dead-zone generator, which is used with a large current device. The timer 0 and 1 share an 8-bit prescaler, while the timer 2, [...]

PWM TIMER S3C2410A 10- 2 Clock Divider 5:1 MUX Dead Zone Generator TOUT0 TOUT1 TOUT2 Control Logic0 TCMPB0 TCNTB0 Control Logic1 TCMPB1 TCNTB1 5:1 MUX Clock Divider 5:1 MUX 5:1 MUX Control Logic2 TCMPB2 TCNTB2 TOUT3 Control Logic3 TCMPB3 TCNTB3 No Pin PCLK 8-Bit Prescaler 8-Bit Prescaler Dead Zone Dead Zone TCLK0 1/8 1/4 1/16 1/2 TCLK1 1/8 1/4 1/16[...]

S3C2410A PWM TIMER 10- 3 PWM TIMER OPERATION PRESCALER & DIVIDER An 8-bit prescaler and a 4-bit divider make the following output frequencies: 4-bit divider settings Minimum resolution (prescaler = 0) Maximum resolution (prescaler = 255) Maximum interval (TCNTBn = 65535) 1/2 (PCLK = 66.5 MHz) 0.0300 us (33.2500 MHz) 7.6992 us (129.8828 KHz) 0.5[...]

PWM TIMER S3C2410A 10- 4 AUTO RELOAD & DOUBLE BUFFERING S3C2410A PWM Timers have a double buffering function, enabling the reload value changed for the next timer operation without stopping the current timer operation. So, although the new timer value is set, a current timer operation is completed successfully. The timer value can be written in[...]

S3C2410A PWM TIMER 10- 5 TIMER INITIALIZATION USING MANUAL UPDATE BIT AND INVERTER BIT An auto reload operation of the timer occurs when the down counter reaches 0. So, a starting value of the TCNTn has to be defined by the user in advance. In this case, the starting value has to be loaded by the manual update bit. The following steps describe how [...]

PWM TIMER S3C2410A 10- 6 TIMER OPERATION TOUTn 1 2 4 6 50 110 40 40 60 20 3 7 9 10 5 8 11 Figure 10-4. Example of a Timer Operation Figure 10-4 shows the result of the following procedure: 1. Enable the auto reload function. Set the TCNTBn to 160 (50+110) and the TCMPBn to 110. Set the manual update bit and configure the inverter bit (on/off). The [...]

S3C2410A PWM TIMER 10- 7 PULSE WIDTH MODULATION (PWM) Write TCMPBn = 60 Write TCMPBn = 50 Write TCMPBn = 40 Write TCMPBn = 30 Write TCMPBn = 30 Write TCMPBn = Next PWM Value 60 50 40 30 30 Figure 10-5. Example of PWM PWM function can be implemented by using the TCMPBn. PWM frequency is determined by TCNTBn. Figure 10-5 shows a PWM value determined [...]

PWM TIMER S3C2410A 10- 8 OUTPUT LEVEL CONTROL Inverter off Initial State Period 1 Period 2 Timer Stop Inverter on Figure 10-6. Inverter On/Off The following procedure describes how to maintain TOUT as high or low (assume the inverter is off): 1. Turn off the auto reload bit. And then, TOUTn goes to high level and the timer is stopped after the TCNT[...]

S3C2410A PWM TIMER 10- 9 DEAD ZONE GENERATOR The dead zone is for the PWM control in a power device. This function enables the insertion of the time gap between a turn-off of a switching device and a turn on of another switching device. This time gap prohibits the two switching devices from being turned on simultaneously, even for a very short time[...]

PWM TIMER S3C2410A 10- 10 DMA REQUEST MODE The PWM timer can generate a DMA request at every specific time. The timer keeps DMA request signals (nDMA_REQ) low until the timer receives an ACK signal. When the timer receives the ACK signal, it makes the request signal inactive. The timer, which generates the DMA request, is determined by setting DMA [...]

S3C2410A PWM TIMER 10- 11 PWM TIMER CONTROL REGISTERS TIMER CONFIGURATION REGISTER0 (TCFG0) Timer input clock Frequency = PCLK / {prescaler value+1} / {divider value} {prescaler value} = 0~255 {divider value} = 2, 4, 8, 16 Register Address R/W Description Reset Value TCFG0 0x51000000 R/W Configures the two 8-bit prescalers 0x00000000 TCFG0 Bit Desc[...]

PWM TIMER S3C2410A 10- 12 TIMER CONFIGURATION REGISTER1 (TCFG1) Register Address R/W Description Reset Value TCFG1 0x51000004 R/W 5-MUX & DMA mode selecton register 0x00000000 TCFG1 Bit Description Initial State Reserved [31:24] 00000000 DMA mode [23:20] Select DMA request channel 0000 = No select (all interrupt) 0001 = Timer0 0010 = Timer1 001[...]

S3C2410A PWM TIMER 10- 13 TIMER CONTROL (TCON) REGISTER Register Address R/W Description Reset Value TCON 0x51000008 R/W Timer control register 0x00000000 TCON Bit Description Initial state Timer 4 auto reload on/off [22] Determine auto reload on/off for Timer 4. 0 = One-shot 1 = Interval mode (auto reload) 0 Timer 4 manual update (note) [21] Deter[...]

PWM TIMER S3C2410A 10- 14 TIMER CONTROL (TCON) REGISTER ( Continued) TCON Bit Description Initial state Reserved [7:5] Reserved Dead zone enable [4] Determine the dead zone operation. 0 = Disable 1 = Enable 0 Timer 0 auto reload on/off [3] Determine auto reload on/off for Timer 0. 0 = One-shot 1 = Interval mode(auto reload) 0 Timer 0 output inverte[...]

S3C2410A PWM TIMER 10- 15 TIMER 0 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB0/TCMPB0) Register Address R/W Description Reset Value TCNTB0 0x5100000C R/W Timer 0 count buffer register 0x00000000 TCMPB0 0x51000010 R/W Timer 0 compare buffer register 0x00000000 TCMPB0 Bit Description Initial State Timer 0 compare buffer register [15:0][...]

PWM TIMER S3C2410A 10- 16 TIMER 1 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB1/TCMPB1) Register Address R/W Description Reset Value TCNTB1 0x51000018 R/W Timer 1 count buffer register 0x00000000 TCMPB1 0x5100001C R/W Timer 1 compare buffer register 0x00000000 TCMPB1 Bit Description Initial State Timer 1 compare buffer register [15:0][...]

S3C2410A PWM TIMER 10- 17 TIMER 2 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB2/TCMPB2) Register Address R/W Description Reset Value TCNTB2 0x51000024 R/W Timer 2 count buffer register 0x00000000 TCMPB2 0x51000028 R/W Timer 2 compare buffer register 0x00000000 TCMPB2 Bit Description Initial State Timer 2 compare buffer register [15:0][...]

PWM TIMER S3C2410A 10- 18 TIMER 3 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB3/TCMPB3) Register Address R/W Description Reset Value TCNTB3 0x51000030 R/W Timer 3 count buffer register 0x00000000 TCMPB3 0x51000034 R/W Timer 3 compare buffer register 0x00000000 TCMPB3 Bit Description Initial State Timer 3 compare buffer register [15:0][...]

S3C2410A PWM TIMER 10- 19 TIMER 4 COUNT BUFFER REGISTER (TCNTB4) Register Address R/W Description Reset Value TCNTB4 0x5100003C R/W Timer 4 count buffer register 0x00000000 TCNTB4 Bit Description Initial State Timer 4 count buffer register [15:0] Set count buffer value for Timer 4 0x00000000 TIMER 4 COUNT OBSERVATION REGISTER (TCNTO4) Register Addr[...]

PWM TIMER S3C2410A 10- 20 NOTES[...]

S3C2410A UART 11- 1 11 UART OVERVIEW The S3C2410A UART (Universal Asynchronous Receiver and Transmitter) provides three independent asynchronous serial I/O (SIO) ports, each of which can operate in Interrupt-based or DMA-based mode. In other words, the UART can generate an interrupt or a DMA request to transfer data between CPU and the UART. The UA[...]

UART S3C2410A 11- 2 BLOCK DIAGRAM Buad-rate Generator Control Unit Transmitter Receiver Peripheral BUS TXDn Clock Source RXDn Transmit FIFO Register (FIFO mode) Transmit Holding Register (Non-FIFO mode) Receive FIFO Register (FIFO mode) Receive Holding Register (Non-FIFO mode only) In FIFO mode, all 16 Byte of Buffer register are used as FIFO regis[...]

S3C2410A UART 11- 3 UART OPERATION The following sections describe the UART operations that include data transmission, data reception, interrupt generation, baud-rate generation, Loopback mode, Infra-red mode, and auto flow control. Data Transmission The data frame for transmission is programmable. It consists of a start bit, 5 to 8 data bits, an o[...]

UART S3C2410A 11- 4 Auto Flow Control (AFC) The S3C2410A's UART 0 and UART 1 support auto flow control with nRTS and nCTS signals. In case, it can be connected to external UARTs. If users want to connect a UART to a Modem, disable auto flow control bit in UMCONn register and control the signal of nRTS by software. In AFC, nRTS depends on the c[...]

S3C2410A UART 11- 5 RS-232C interface If users want to connect the UART to modem interface (instead of null modem), nRTS, nCTS, nDSR, nDTR, DCD and nRI signals are needed. In this case, the users can control these signals with general I/O ports by software because the AFC does not support the RS-232C interface. Interrupt/DMA Request Generation Each[...]

UART S3C2410A 11- 6 UART Error Status FIFO UART has the error statu s FIFO besides the Rx FIFO register. The error status FIFO indicates which data, among FIFO registers, is received with an error. The error interrupt will be issued only when the data, which has an error, is ready to read out. To clear the error status FIFO, the URXHn with an error[...]

S3C2410A UART 11- 7 Baud-Rate Generation Each UART's baud-rate generator provides the serial clock for the transmitter and the receiver. The source clock for the baud-rate generator can be selected with the S3C2410A's internal system clock or UEXTCLK. In other words, dividend is selectable by setting Clock Selection of UCONn. The baud-rat[...]

UART S3C2410A 11- 8 Infra-Red (IR) Mode The S3C2410A UART block supports infra-red (IR) transmission and reception, which can be selected by setting the Infra-red-mode bit in the UART line control register (ULCONn). Figure 11-4 illustrates how to implement the IR mode. In IR transmit mode, the transmit pulse comes out at a rate of 3/16, the normal [...]

S3C2410A UART 11- 9 Start Bit Stop Bit Data Bits SIO Frame 0101 00110 1 Figure 11-5. Serial I/O Frame Timing Diagram (Normal UART) 0 Start Bit Stop Bit Data Bits IR Transmit Frame Bit Time Pulse Width = 3/16 Bit Frame 0 0 0 0 1 1 1 1 1 Figure 11-6. Infra-Red Transmit Mode Frame Timing Diagram 0 Start Bit Stop Bit Data Bits IR Receive Frame 0 0 0 0 [...]

UART S3C2410A 11- 10 UART SPECIAL REGISTERS UART LINE CONTROL REGISTER There are three UART line control registers including ULCON0, ULCON1, and ULCON2 in the UART block. Register Address R/W Description Reset Value ULCON0 0x50000000 R/W UART channel 0 line control register 0x00 ULCON1 0x50004000 R/W UART channel 1 line control register 0x00 ULCON2[...]

S3C2410A UART 11- 11 UART CONTROL REGISTER There are three UART control registers including UCON0, UCON1 and UCON2 in the UART block. Register Address R/W Description Reset Value UCON0 0x50000004 R/W UART channel 0 control register 0x00 UCON1 0x50004004 R/W UART channel 1 control register 0x00 UCON2 0x50008004 R/W UART channel 2 control register 0x[...]

UART S3C2410A 11- 12 UART CONTROL REGISTER (Continued) UCONn Bit Description Initial State Transmit Mode [3:2] Determine which function is currently able to write Tx data to the UART transmit buffer register. (UART Tx Enable/Disable) 00 = Disable 01 = Interrupt request or polling mode 10 = DMA0 request (Only for UART0), DMA3 request (Only for UART2[...]

S3C2410A UART 11- 13 UART FIFO CONTROL REGISTER There are three UART FIFO control registers including UFCON0, UFCON1 and UFCON2 in the UART block. Register Address R/W Description Reset Value UFCON0 0x50000008 R/W UART channel 0 FIFO control register 0x0 UFCON1 0x50004008 R/W UART channel 1 FIFO control register 0x0 UFCON2 0x50008008 R/W UART chann[...]

UART S3C2410A 11- 14 UART MODEM CONTROL REGISTER There are two UART MODEM control registers including UMCON0 and UMCON1 in the UART block. Register Address R/W Description Reset Value UMCON0 0x5000000C R/W UART channel 0 Modem control register 0x0 UMCON1 0x5000400C R/W UART channel 1 Modem control register 0x0 Reserved 0x5000800C - Reserved Undef U[...]

S3C2410A UART 11- 15 UART TX/RX STATUS REGISTER There are three UART Tx/Rx status registers including UTRSTAT0, UTRSTAT1 and UTRSTAT2 in the UART block. Register Address R/W Description Reset Value UTRSTAT0 0x50000010 R UART channel 0 Tx/Rx status register 0x6 UTRSTAT1 0x50004010 R UART channel 1 Tx/Rx status register 0x6 UTRSTAT2 0x50008010 R UART[...]

UART S3C2410A 11- 16 UART ERROR STATUS REGISTER There are three UART Rx error status registers including UERSTAT0, UERSTAT1 and UERSTAT2 in the UART block. Register Address R/W Description Reset Value UERSTAT0 0x50000014 R UART channel 0 Rx error status register 0x0 UERSTAT1 0x50004014 R UART channel 1 Rx error status register 0x0 UERSTAT2 0x500080[...]

S3C2410A UART 11- 17 UART FIFO STATUS REGISTER There are three UART FIFO status registers including UFSTAT0, UFSTAT1 and UFSTAT2 in the UART block. Register Address R/W Description Reset Value UFSTAT0 0x50000018 R UART channel 0 FIFO status register 0x00 UFSTAT1 0x50004018 R UART channel 1 FIFO status register 0x00 UFSTAT2 0x50008018 R UART channel[...]

UART S3C2410A 11- 18 UART MODEM STATUS REGISTER There are two UART modem status registers including UMSTAT0 and UMSTAT1 in the UART block. Register Address R/W Description Reset Value UMSTAT0 0x5000001C R UART channel 0 Modem status register 0x0 UMSTAT1 0x5000401C R UART channel 1 Modem status register 0x0 Reserved 0x5000801C – Reserved Undef UMS[...]

S3C2410A UART 11- 19 UART TRANSMIT BUFFER REGISTER (HOLDING REGISTER & FIFO REGISTER) There are three UART transmit buffer registers including UTXH0, UTXH1 and UTXH2 in the UART block. UTXHn has an 8-bit data for transmission data. Register Address R/W Description Reset Value UTXH0 0x50000020(L) 0x50000023(B) W (by byte) UART channel 0 transmit[...]

UART S3C2410A 11- 20 UART BAUD RATE DIVISOR REGISTER There are three UART baud rate divisor registers including UBRDIV0, UBRDIV1 and UBRDIV2 in the UART block. The value stored in the baud rate divisor register (UBRDIVn), is used to determine the serial Tx/Rx clock rate (baud rate) as follows: UBRDIVn = (int)(PCLK / (bps x 16) ) –1 or UBRDIVn = ([...]

S3C2410A BUS HOST CON TROLLER 12 - 1 12 USB HOST CONTROLLER OVERVIEW S3C2410A supports 2-port USB host interface as follows: • OHCI Rev 1.0 compatible • USB Rev1.1 compatible • Two down stream ports • Support for both LowSpeed and FullSpeed USB devices HCI SLAVE BLOCK APP_SADR(8) APP_SDATA(32) HCI_DATA(32) CONTROL CONTROL OHCI REGS USB STAT[...]

BUS HOST CONTROLLER S3C2410A 12 - 2 USB HOST CONTROLLER SPECIAL REGISTERS The S3C2410A USB host controller complies with OHCI Rev 1.0. Refer to Open Host Controller Interface Rev 1.0 specification for detail information. Table 12-1. OHCI Registers for USB H ost C ontroller Register Base Address R/W Description Reset Value HcRevision 0x49000000 – [...]

S3C2410A USB DEVICE 13- 1 13 USB DEVICE CONTROLLER OVERVIEW Universal Serial Bus (USB) device controller is designed to provide a high performance full speed function controller solution with DMA interface. USB device controller allows bulk transfer with DMA, interrupt transfer and control transfer. USB device controller supports: — Full speed US[...]

USB DEVICE S3C2410 A 13- 2 SIE RT_VP_OUT RT_VM_IN RT_VP_IN RXD RT_UXSUSPEND RT_UX_OEN RT_VM_OUT MC_ADDR[13:0] SIU GFI FIFOs MCU & DMA I/F MC_DATA_IN[31:0] MC_DATA_OUT[31:0] USB_CLK SYS_CLK SYS_RESETN MC_WR WR_RDN MC_CSN MC_INTR DREQN[3:0] DACKN[3:0] Figure 13-1. USB Device Controller Block Diagram[...]

S3C2410A USB DEVICE 13- 3 USB DEVICE CONTROLLER SPECIAL REGISTERS This section describes detailed functionalities about register sets of USB device controller. All special function register is byte-accessible or word-accessible. If you access byte mode offset-address is different in little endian and big endian. All reserved bit is zero. Common ind[...]

USB DEVICE S3C2410 A 13- 4 USB Device Controller Special Registers (Continued) Register Name Description Offset Address EP2_DMA_TTC_M Endpoint2 DMA transfer counter middle-byte register 0x228(L) / 0x22B(B) EP2_DMA_TTC_H Endpoint2 DMA transfer counter high-byte register 0x22C(L) / 0x22F(B) EP3_DMA_CON Endpoint3 DMA control register 0x240(L) / 0x243([...]

S3C2410A USB DEVICE 13- 5 FUNCTION ADDRESS REGISTER (FUNC_ADDR_REG) This register maintains the USB device controller address assigned by the host. The Micro Controller Unit (MCU) writes the value received through a SET_ADDRESS descriptor to this register. This address is used for the next token. Register Address R/W Description Reset Value FUNC_AD[...]

USB DEVICE S3C2410 A 13- 6 POWER MANAGEMENT REGISTER (PWR_REG) This register acts as a power control register in the USB block. Register Address R/W Description Reset Value PWR_REG 0x52000144(L) 0x52000147(B) R/W (byte) Power management register 0x00 PWR_ADDR Bit MCU USB Description Initial State Reserved [7:4] – – – – USB_RESET [3] R SET S[...]

S3C2410A USB DEVICE 13- 7 INTERRUPT REGISTER (EP_INT_REG/USB_INT_REG) The USB core has two interrupt registers. These registers act as status registers for the MCU when it is interrupted. The bits are cleared by writing a "1" (not "0") to each bit that was set. Once the MCU is interrupted, MCU should read the contents of interru[...]

USB DEVICE S3C2410 A 13- 8 INTERRUPT REGISTER (EP_INT_REG/USB_INT_REG) ( Continued) Register Address R/W Description Reset Value USB_INT_REG 0x52000158(L) 0x5200015B(B) R/W (byte) USB interrupt pending/clear register 0x00 USB_INT_REG Bit MCU USB Description Initial State RESET Interrupt [2] R /CLEAR SET Set by the USB when it receives reset signali[...]

S3C2410A USB DEVICE 13- 9 INTERRUPT ENABLE REGISTER (EP_INT_EN_REG /USB_INT_EN_REG) Corresponding to each interrupt register, The USB device controller also has two interrupt enable registers (except resume interrupt enable). By default, usb reset interrupt is enabled. If bit = 0, the interrupt is disabled. If bit = 1, the interrupt is enabled. Reg[...]

USB DEVICE S3C2410 A 13- 10 FRAME NUMBER REGISTER (FPAME_NUM1_REG/FRAME_NUM2_REG) When the host transfers USB packets, each Start Of Frame (SOF) packet includes a frame number. The USB device controller catches this frame number and loads it into this register automatically. Register Address R/W Description Reset Value FRAME_NUM1_REG 0x52000170(L) [...]

S3C2410A USB DEVICE 13- 11 INDEX REGISTER (INDEX_REG) The INDEX register is used to indicate certain endpoint registers effectively. The MCU can access the endpoint registers (MAXP_REG, IN_CSR1_REG, IN_CSR2_REG, OUT_CSR1_REG, OUT_CSR2_REG, OUT_FIFO_CNT1_REG, and OUT_FIFO_CNT2_REG) for an endpoint inside the core using the INDEX register. Register A[...]

USB DEVICE S3C2410 A 13- 12 END POINT0 CONTROL STATUS REGISTER (EP0_CSR) This register has the control and status bits for Endpoint 0. Since a control transaction is involved with both IN and OUT tokens, there is only one CSR register, mapped to the IN CSR1 register. (share IN1_CSR and can access by writing index register "0" and read/wri[...]

S3C2410A USB DEVICE 13- 13 END POINT0 CONTROL STATUS REGISTER (EP0_CSR) ( Continued) EP0_CSR Bit MCU USB Description Initial State IN_PKT_RDY [1] SET CLEAR Set by the MCU after writing a packet of data into EP0 FIFO. The USB clears this bit once the packet has been successfully sent to the host. An interrupt is generated when the USB clears this bi[...]

USB DEVICE S3C2410 A 13- 14 END POINT IN CONTROL STATUS REGISTER (IN_CSR1_REG/IN_CSR2_REG) Register Address R/W Description Reset Value IN_CSR1_REG 0x52000184(L) 0x52000187(B) R/W (byte) IN END POINT control status register1 0x00 IN_CSR1_REG Bit MCU USB Description Initial State Reserved [7] – – – 0 CLR_DATA_ TOGGLE [6] R/W R/ CLEAR Used in S[...]

S3C2410A USB DEVICE 13- 15 END POINT IN CONTROL STATUS REGISTER ( IN_CSR1_REG/IN_CSR2_REG) ( Continued) IN_CSR1_REG Bit MCU USB Description Initial State IN_PKT_RDY [0] R/SET CLEAR Set by the MCU after writing a packet of data into the FIFO. The USB clears this bit once the packet has been successfully sent to the host. An interrupt is generated wh[...]

USB DEVICE S3C2410 A 13- 16 END POINT OUT CONTROL STATUS REGISTER (OUT_CSR1_REG/OUT_CSR2_REG) Register Address R/W Description Reset Value OUT_CSR1_REG 0x52000190(L) 0x52000193(B) R/W (byte) End Point out control status register1 0x00 OUT_CSR1_REG Bit MCU USB Description Initial State CLR_DATA_ TOGGLE [7] R/W CLEAR When the MCU writes a 1 to this b[...]

S3C2410A USB DEVICE 13- 17 END POINT OUT CONTROL STATUS REGISTER (OUT_CSR1_REG/OUT_CSR2_REG) ( Continued) Register Address R/W Description Reset Value OUT_CSR2_REG 0x52000194(L) 0x52000197(B) R/W (byte) End Point out control status register2 0x00 OUT_CSR2_REG Bit MCU USB Description Initial State AUTO_CLR [7] R/W R If the MCU is set, whenever the M[...]

USB DEVICE S3C2410 A 13- 18 END POINT FIFO REGISTER (EPN_FIFO_REG) The EPn_FIFO_REG enables the MCU to access to the EPn FIFO. Register Address R/W Description Reset Value EP0_FIFO 0x520001C0(L) 0x520001C3 (B) R/W (byte) End Point0 FIFO register 0xXX EP1_FIFO 0x520001C4(L) 0x520001C7(B) R/W (byte) End Point1 FIFO register 0xXX EP2_FIFO 0x520001C8(L[...]

S3C2410A USB DEVICE 13- 19 MAX PACKET REGISTER (MAXP_REG) Register Address R/W Description Reset Value MAXP_REG 0x52000180(L) 0x52000183(B) R/W (byte) End Point MAX packet register 0x01 MAXP_REG Bit MCU USB Description Initial State MAXP [3:0] R/W R 0000: Reserved 0001: MAXP = 8 Byte0010: MAXP = 16 Byte 0100: MAXP = 32 Byte1000: MAXP = 64 Byte For [...]

USB DEVICE S3C2410 A 13- 20 END POINT OUT WRITE COUNT REGISTER (OUT_FIFO_CNT1_REG/OUT_FIFO_CNT2_REG) These registers maintain the number of bytes in the packet as the number is unloaded by the MCU. Register Address R/W Description Reset Value OUT_FIFO_CNT1_ REG 0x52000198(L) 0x5200019B(B) R (byte) End Point out write count register1 0x00 OUT_FIFO_C[...]

S3C2410A USB DEVICE 13- 21 DMA INTERFACE CONTROL REGISTER (EPN_DMA_CON) Register Address R/W Description Reset Value EP1_DMA_CON 0x52000200(L) 0x52000203(B) R/W (byte) EP1 DMA interface control register 0x00 EP2_DMA_CON 0x52000218(L) 0x5200021B(B) R/W (byte) EP2 DMA interface control register 0x00 EP3_DMA_CON 0x52000240(L) 0x52000243(B) R/W (byte) [...]

USB DEVICE S3C2410 A 13- 22 DMA UNIT COUNTER REGISTER (EPN_DMA_UNIT) This register is valid in Demand mode. In other modes, this register value must be set to "0x01" Register Address R/W Description Reset Value EP1_DMA_UNIT 0x52000204(L) 0x52000207(B) R/W (byte) EP1 DMA transfer unit counter base register 0x00 EP2_DMA_UNIT 0x5200021C(L) 0[...]

S3C2410A USB DEVICE 13- 23 DMA FIFO COUNTER REGISTER (EPN_DMA_FIFO) This register has values in byte size in FIFO to be transferred by DMA. In case of OUT_DMA_RUN enabled, the value in OUT FIFO Write Count Register1 will be loaded in this register automatically. In case of IN DMA mode, the MCU should set proper value by software. Register Address R[...]

USB DEVICE S3C2410 A 13- 24 DMA TOTAL TRANSFER COUNTER REGISTER (EPN_DMA_TTC_L, M, H) This register should have total number of bytes to be transferred using DMA (total 20-bit counter). Register Address R/W Description Reset Value EP1_DMA_TTC_L 0x5200020C(L) 0x5200020F(B) R/W (byte) EP1 DMA total transfer counter(lower byte) 0x00 EP1_DMA_TTC_M 0x52[...]

S3C2410A INTERRUPT CONTROLLER 14- 1 14 INTERRUPT CONTROLLER OVERVIEW The interrupt controller in the S3C2410A receives the request from 56 interrupt sources. These interrupt sources are provided by internal peripherals such as the DMA controller, the UART, IIC, and others. In these interrupt sources, the UARTn and EINTn interrupts are 'OR&apos[...]

INTERRUPT CONTROLLER S3C2410A 14- 2 INTERRUPT CONTROLLER OPERATION F-bit and I-bit of Program Status Register (PSR) If the F-bit of PSR in ARM920T CPU is set to 1, the CPU does not accept the Fast Interrupt Request (FIQ) from the interrupt controller. Likewise, If I-bit of the PSR is set to 1, the CPU does not accept the Interrupt Request (IRQ) fro[...]

S3C2410A INTERRUPT CONTROLLER 14- 3 INTERRUPT SOURCES The interrupt controller supports 56 interrupt sources as shown in the table below. Sources Descriptions Arbiter Group INT_ADC ADC EOC and Touch interrupt (INT_ADC/INT_TC) ARB5 INT_RTC RTC alarm interrupt ARB5 INT_SPI1 SPI1 interrupt ARB5 INT_UART0 UART0 Interrupt (ERR, RXD, and TXD) ARB5 INT_II[...]

INTERRUPT CONTROLLER S3C2410A 14- 4 INTERRUPT PRIORITY GENERATING BLOCK The priority logic for 32 interrupt requests is composed of seven rotation based arbiters: six first-level arbiters and one second-level arbiter as shown in Figure 14-2 below. ARBITER6 ARBITER0 ARM IRQ REQ1/EINT0 ARBITER1 ARBITER2 ARBITER3 ARBITER4 ARBITER5 REQ4/INT_TICK REQ5/I[...]

S3C2410A INTERRUPT CONTROLLER 14- 5 INTERRUPT PRIORITY Each arbiter can handle six interrupt requests based on the one bit arbiter mode control (ARB_MODE) and two bits of selection control signals (ARB_SEL) as follows: — If ARB_SEL bits are 00b, the priority order is REQ0, REQ1, REQ2, REQ3, REQ4, and REQ5. — If ARB_SEL bits are 01b, the priorit[...]

INTERRUPT CONTROLLER S3C2410A 14- 6 INTERRUPT CONTROLLER SPECIAL REGISTERS There are five control registers in the interrupt controller: source pending register, interrupt mode register, mask register, priority register, and interrupt pending register. All the interrupt requests from the interrupt sources are first registered in the source pending [...]

S3C2410A INTERRUPT CONTROLLER 14- 7 SOURCE PENDING (SRCPND) REGISTER (Continued) SRCPND Bit Description Initial State INT_ADC [31] 0 = Not requested, 1 = Requested 0 INT_RTC [30] 0 = Not requested, 1 = Requested 0 INT_SPI1 [29] 0 = Not requested, 1 = Requested 0 INT_UART0 [28] 0 = Not requested, 1 = Requested 0 INT_IIC [27] 0 = Not requested, 1 = R[...]

INTERRUPT CONTROLLER S3C2410A 14- 8 INTERRUPT MODE (INTMOD) REGISTER This register is composed of 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the corresponding interrupt is processed in the FIQ (fast interrupt) mode. Otherwise, it is processed in the IRQ mode (normal interrupt). Note that only one interru[...]

S3C2410A INTERRUPT CONTROLLER 14- 9 INTMOD Bit Description Initial State INT_ADC [31] 0 = IRQ, 1 = FIQ 0 INT_RTC [30] 0 = IRQ, 1 = FIQ 0 INT_SPI1 [29] 0 = IRQ, 1 = FIQ 0 INT_UART0 [28] 0 = IRQ, 1 = FIQ 0 INT_IIC [27] 0 = IRQ, 1 = FIQ 0 INT_USBH [26] 0 = IRQ, 1 = FIQ 0 INT_USBD [25] 0 = IRQ, 1 = FIQ 0 Reserved [24] Not used 0 INT_URRT1 [23] 0 = IRQ,[...]

INTERRUPT CONTROLLER S3C2410A 14- 10 INTERRUPT MASK (INTMSK) REGISTER This register also has 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the CPU does not service the interrupt request from the corresponding interrupt source (note that even in such a case, the corresponding bit of SRCPND register is set to[...]

S3C2410A INTERRUPT CONTROLLER 14- 11 INTMSK Bit Description Initial State INT_ADC [31] 0 = Service available, 1 = Masked 1 INT_RTC [30] 0 = Service available, 1 = Masked 1 INT_SPI1 [29] 0 = Service available, 1 = Masked 1 INT_UART0 [28] 0 = Service available, 1 = Masked 1 INT_IIC [27] 0 = Service available, 1 = Masked 1 INT_USBH [26] 0 = Service av[...]

INTERRUPT CONTROLLER S3C2410A 14- 12 PRIORITY REGISTER (PRIORITY) Register Address R/W Description Reset Value PRIORITY 0x4A00000C R/W IRQ priority control register 0x7F PRIORITY Bit Description Initial State ARB_SEL6 [20:19] Arbiter 6 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 0 ARB[...]

S3C2410A INTERRUPT CONTROLLER 14- 13 PRIORITY REGISTER (PRIORITY) ( Continued) PRIORITY Bit Description Initial State ARB_MODE1 [1] Arbiter 1 group priority rotate enable 0 = Priority does not rotate 1 = Priority rotate enable 1 ARB_MODE0 [0] Arbiter 0 group priority rotate enable 0 = Priority does not rotate 1 = Priority rotate enable 1[...]

INTERRUPT CONTROLLER S3C2410A 14- 14 INTERRUPT PENDING (INTPND) REGISTER Each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt request, which is unmasked and waits for the interrupt to be serviced, has the highest priority . Since the INTPND register is located after the priority logic, only one bit can be [...]

S3C2410A INTERRUPT CONTROLLER 14- 15 INTPND Bit Description Initial State INT_ADC [31] 0 = Not requested, 1 = Requested 0 INT_RTC [30] 0 = Not requested, 1 = Requested 0 INT_SPI1 [29] 0 = Not requested, 1 = Requested 0 INT_UART0 [28] 0 = Not requested, 1 = Requested 0 INT_IIC [27] 0 = Not requested, 1 = Requested 0 INT_USBH [26] 0 = Not requested, [...]

INTERRUPT CONTROLLER S3C2410A 14- 16 INTERRUPT OFFSET (INTOFFSET) REGISTER The value in the interrupt offset register shows which interrupt request of IRQ mode is in the INTPND register. This bit can be cleared automatically by clearing SRCPND and INTPND. Register Address R/W Description Reset Value INTOFFSET 0X4A000014 R Indicate the IRQ interrupt[...]

S3C2410A INTERRUPT CONTROLLER 14- 17 SUB SOURCE PENDING (SUBSRCPND) REGISTER You can clear a specific bit of the SUBSRCPND register by writing a data to this register. It clears only the bit positions of the SUBSRCPND register corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data remai[...]

INTERRUPT CONTROLLER S3C2410A 14- 18 INTERRUPT SUB MASK (INTSUBMSK) REGISTER This register has 11 bits each of which is related to an interrupt source. If a specific bit is set to 1, the interrupt request from the corresponding interrupt source is not serviced by the CPU (note that even in such a case, the corresponding bit of the SUBSRCPND registe[...]

S3C2410A LCD CONTROLLER 15- 1 15 LCD CONTROLLER OVERVIEW The LCD controller in the S3C2410A consists of the logic for transferring LCD image data from a video buffer located in system memory to an external LCD driver. The LCD controller supports monochrome, 2-bit per pixel (4-level gray scale) or 4-bit per pixel (16-level gray scale) mode on a mono[...]

LCD CONTROLLER S3 C2410A 15- 2 COMMON FEATURES The LCD controller has a dedicated DMA that supports to fetch the image data from video buffer located in system memory. Its features also include: — Dedicated interrupt functions (INT_FrSyn and INT_FiCnt) — The system memory is used as the display memory. — Supports Multiple Virtual Display Scre[...]

S3C2410A LCD CONTROLLER 15- 3 BLOCK DIAGRAM System Bus LPC3600 is a timing control logic unit for LTS350Q1-PD1 or LTS350Q1-PD2. REGBANK LCDCDMA VIDPRCS LPC3600 TIMEGEN VD[23:0] VCLK /LCD_HCLK VLINE / HSYNC / CPV VFRAME / VSYNC / STV VM / VDEN / TP LCDVF0 LCDVF1 LCDVF2 . . . VIDEO MUX Figure 15-1. LCD Controller Block Diagram The S3C2410A LCD contro[...]

LCD CONTROLLER S3 C2410A 15- 4 STN LCD CONTROLLER OPERATION TIMING GENERATOR (TIMEGEN) The TIMEGEN generates the control signals for the LCD driver, such as VFRAME, VLINE, VCLK, and VM. These control signals are closely related to the configuration on the LCDCON1/2/3/4/5 registers in the REGBANK. Based on these programmable configurations on the LC[...]

S3C2410A LCD CONTROLLER 15- 5 Table 15-1. Relation Between VCLK and CLKVAL (STN, HCLK = 60 MHz) CLKVAL 60 MHz/X VCLK 2 60 MHz/4 15.0 MHz 3 60 MHz/6 10.0 MHz ::: 1023 60 MHz/2046 29.3 kHz VIDEO OPERATION The S3C2410A LCD controller supports 8-bit color mode (256 color mode), 12-bit color mode (4096 color mode), 4 level gray scale mode, 16 level gray[...]

LCD CONTROLLER S3 C2410A 15- 6 256 Level Color Mode Operation The S3C2410A LCD controller can support an 8-bit per pixel 256 color display mode. The color display mode can generate 256 levels of color using the dithering algorithm and FRC. The 8-bit per pixel are encoded into 3-bits for red, 3-bits for green, and 2-bits for blue. The color display [...]

S3C2410A LCD CONTROLLER 15- 7 DITHERING AND FRAME RATE CONTROL For STN LCD displays (except monochrome), video data must be processed by a dithering algorithm. The DITHFRC block has two functions, such as Time-based Dithering Algorithm for reducing flicker and Frame Rate Control (FRC) for displaying gray and color level on the STN panel. The main p[...]

LCD CONTROLLER S3 C2410A 15- 8 Display Types The LCD controller supports 3 types of LCD drivers: 4-bit dual scan, 4-bit single scan, and 8-bit single scan display mode. Figure 15-2 shows these 3 different display types for monochrome displays, and Figure 15-3 show these 3 different display types for color displays. 4-bit Dual Scan Display Type A 4-[...]

S3C2410A LCD CONTROLLER 15- 9 MEMORY DATA FORMAT (STN, BSWP=0) Mono 4-bit Dual Scan Display: Video Buffer Memory: Address Data 0000H A[31:0] 0004H B[31:0] • • • 1000H L[31:0] 1004H M[31:0] • • • LCD Panel A[31] A[30] ...... A[0] B[31] B[30] ...... B[0] ...... L[31] L[30] ...... L[0] M[31] M[30] ...... M[0] ...... Mono 4-bit Single Scan [...]

LCD CONTROLLER S3 C2410A 15- 10 MEMORY DATA FORMAT ( STN, BSWP = 0 ) ( Continued) In 4-level gray mode, 2 bits of video data correspond to 1 pixel. In 16-level gray mode, 4 bits of video data correspond to 1 pixel. In 256 level color mode, 8 bits (3 bits of red, 3 bits of green, and 2 bits of blue) of video data correspond to 1 pixel. The color dat[...]

S3C2410A LCD CONTROLLER 15- 11 4-bit Dual Scan Display 4-bit Single Scan Display 8-bit Single Scan Display . . . . . . . . . . . . VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 . . . . . . VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 . . . . . . Figure 15-2. Monochrome Display Types (STN)[...]

LCD CONTROLLER S3 C2410A 15- 12 VD3 R1 VD2 G1 VD1 B1 VD0 R2 VD3 G2 VD2 B2 VD1 R3 VD0 G3 . . . . . . 1 Pixel . . . . . . 4-bit Dual Scan Display VD3 R1 VD2 G1 VD1 B1 VD0 R2 VD3 G2 VD2 B2 VD1 R3 VD0 G3 . . . . . . 1 Pixel 4-bit Single Scan Display VD7 R1 VD6 G1 VD5 B1 VD4 R2 VD7 G2 VD6 B2 VD5 R3 VD4 G3 . . . . . . 1 Pixel 8-bit Single Scan Display VD[...]

S3C2410A LCD CONTROLLER 15- 13 Timing Requirements Image data should be transferred from the memory to the LCD driver using the VD[7:0] signal. VCLK signal is used to clock the data into the LCD driver's shift register. After each horizontal line of data has been shifted into the LCD driver's shift register, the VLINE signal is asserted t[...]

LCD CONTROLLER S3 C2410A 15- 14 WDLY WLH LINE1LINE2LINE3LINE4LINE5LINE6 LINE1 LINEn First Line Timing LINECNT decreases & Display the 1st line LINEBLANK First Line Check & Data Timing VFRAME VM VLINE VFRAME VM VLINE LINECNT VCLK VFRAME VM VLINE VCLK VD[7:0] WDLY WDLY Display the last line of the previous frame Full Frame Timing (MMODE = 1, [...]

S3C2410A LCD CONTROLLER 15- 15 TFT LCD CONTROLLER OPERATION The TIMEGEN generates the control signals for LCD driver, such as VSYNC, HSYNC, VCLK, VDEN, and LEND signal. These control signals are highly related with the configurations on the LCDCON1/2/3/4/5 registers in the REGBANK. Base on these programmable configurations on the LCD control regist[...]

LCD CONTROLLER S3 C2410A 15- 16 MEMORY DATA FORMAT (TFT) This section includes some examples of each display mode. 24BPP Display (BSWP = 0, HWSWP = 0, BPP24BL = 0) D[31:24] D[23:0] 000H Dummy Bit P1 004H Dummy Bit P2 008H Dummy Bit P3 ... (BSWP = 0, HWSWP = 0, BPP24BL = 1) D[31:8] D[7:0] 000H P1 Dummy Bit 004H P2 Dummy Bit 008H P3 Dummy Bit ... P1 [...]

S3C2410A LCD CONTROLLER 15- 17 16BPP Display (BSWP = 0, HWSWP = 0) D[31:16] D[15:0] 000H P1 P2 004H P3 P4 008H P5 P6 ... (BSWP = 0, HWSWP = 1) D[31:16] D[15:0] 000H P2 P1 004H P4 P3 008H P6 P5 ... P1 P2 P3 P4 P5 ...... LCD Panel VD Pin Connections at 16BPP (5:6:5) VD 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RED 43210 NC NC NC G[...]

LCD CONTROLLER S3 C2410A 15- 18 8BPP Display (BSWP = 0, HWSWP = 0) D[31:24] D[23:16] D[15:8] D[7:0] 000H P1 P2 P3 P4 004H P5 P6 P7 P8 008H P9 P10 P11 P12 ... (BSWP = 1, HWSWP = 0) D[31:24] D[23:16] D[15:8] D[7:0] 000H P4 P3 P2 P1 004H P8 P7 P6 P5 008H P12 P11 P10 P9 ... P1 P2 P3 P4 P5 ...... LCD Panel P6 P7 P8 P10 P11 P12 P9[...]

S3C2410A LCD CONTROLLER 15- 19 4BPP Display (BSWP = 0, HWSWP = 0) D[31:28] D[27:24] D[23:20] D[19:16] D[15:12] D[11:8] D[7:4] D[3:0] 000H P1 P2 P3 P4 P5 P6 P7 P8 004H P9 P10 P11 P12 P13 P14 P15 P16 008H P17 P18 P19 P20 P21 P22 P23 P24 ... (BSWP = 1, HWSWP = 0) D[31:28] D[27:24] D[23:20] D[19:16] D[15:12] D[11:8] D[7:4] D[3:0] 000H P7 P8 P5 P6 P3 P4[...]

LCD CONTROLLER S3 C2410A 15- 20 256 PALETTE USAGE (TFT) Palette Configuration and Format Control The S3C2410A provides 256 color palette for TFT LCD Control. The user can select 256 colors from the 64K colors in these two formats. The 256 color palette consists of the 256 (depth) × 16-bit SPSRAM. The palette supports 5:6:5 (R:G:B) format and 5:5:5[...]

S3C2410A LCD CONTROLLER 15- 21 12 345 LCD Panel 16BPP 5:5:5+1 Format (Non-Palette) R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 I R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 I 12 345 LCD Panel 16BPP 5:6:5 Format (Non-Palette) R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 A[15] A[14] A[13] A[12] A[1[...]

LCD CONTROLLER S3 C2410A 15- 22 INT_FrSyn VSYNC HSYNC VDEN HSYNC VCLK VD LEND VBPD+1 VSPW+1 VFPD+1 HBPD+1 HFPD+1 HSPW+1 VDEN 1 Frame 1 Line LINEVAL +1 HOZVAL+1 Figure 15-6. TFT LCD Timing Example[...]

S3C2410A LCD CONTROLLER 15- 23 SAMSUNG TFT LCD PANEL (3.5 ″ PORTRAIT / 256K COLOR /REFLECTIVE A-SI TFT LCD) The S3C2410A supports SEC TFT LCD panel (SAMSUNG 3.5 ″ Portrait / 256K Color /Reflective a-Si TFT LCD). LTS350Q1-PD1: TFT LCD panel with touch panel and front light unit LTS350Q1-PD2: TFT LCD panel only The S3C2410A provides timing signal[...]

LCD CONTROLLER S3 C2410A 15- 24 VIRTUAL DISPLAY (TFT/STN) The S3C2410A supports hardware horizontal or vertical scrolling. If the screen is scrolled, the fields of LCDBASEU and LCDBASEL in LCDSADDR1/2 registers need to be changed (see Figure 15-7), except the values of PAGEWIDTH and OFFSIZE. The video buffer in which the image is stored should be l[...]

S3C2410A LCD CONTROLLER 15- 25 LCD POWER ENABLE (STN/TFT) The S3C2410A provides Power enable (PWREN) function. When PWREN is set to make PWREN signal enabled, the output value of LCD_PWREN pin is controlled by ENVID. In other words, If LCD_PWREN pin is connected to the power on/off control pin of the LCD panel, the power of LCD panel is controlled [...]

LCD CONTROLLER S3 C2410A 15- 26 LCD CONTROLLER SPECIAL REGISTERS LCD Control 1 Register Register Address R/W Description Reset Value LCDCON1 0X4D000000 R/W LCD control 1 register 0x00000000 LCDCON1 Bit Description Initial State LINECNT (read only) [27:18] Provide the status of the line counter. Down count from LINEVAL to 0 0000000000 CLKVAL [17:8] [...]

S3C2410A LCD CONTROLLER 15- 27 LCD Control 2 Register Register Address R/W Description Reset Value LCDCON2 0X4D000004 R/W LCD control 2 register 0x00000000 LCDCON2 Bit Description Initial State VBPD [31:24] TFT : Vertical back porch is the number of inactive lines at the start of a frame, after vertical synchronization period. STN : These bits shou[...]

LCD CONTROLLER S3 C2410A 15- 28 LCD Control 3 Register Register Address R/W Description Reset Value LCDCON3 0X4D000008 R/W LCD control 3 register 0x00000000 LCDCON3 Bit Description Initial state HBPD (TFT) [25:19] TFT : Horizontal back porch is the number of VCLK periods between the falling edge of HSYNC and the start of active data. 0000000 WDLY ([...]

S3C2410A LCD CONTROLLER 15- 29 LCD Control 4 Register Register Address R/W Description Reset Value LCDCON4 0X4D00000C R/W LCD control 4 register 0x00000000 LCDCON4 Bit Description Initial state MVAL [15:8] STN : These bit define the rate at which the VM signal will toggle if the MMODE bit is set to logic '1'. 0X00 HSPW(TFT) [7:0] TFT : Ho[...]

LCD CONTROLLER S3 C2410A 15- 30 LCD Control 5 Register Register Address R/W Description Reset Value LCDCON5 0X4D000010 R/W LCD control 5 register 0x00000000 LCDCON5 Bit Description Initial state Reserved [31:17] This bit is reserved and the value should be '0'. 0 VSTATUS [16:15] TFT : Vertical Status (read only). 00 = VSYNC 01 = BACK Porc[...]

S3C2410A LCD CONTROLLER 15- 31 LCD Control 5 Register (Continued) LCDCON5 Bit Description Initial state INVVDEN [6] TFT : This bit indicates the VDEN signal polarity. 0 = Normal 1 = Inverted 0 INVPWREN [5] STN/TFT : This bit indicates the PWREN signal polarity. 0 = Normal 1 = Inverted 0 INVLEND [4] TFT : This bit indicates the LEND signal polarity.[...]

LCD CONTROLLER S3 C2410A 15- 32 FRAME BUFFER START ADDRESS 1 REGISTER Register Address R/W Description Reset Value LCDSADDR1 0X4D000014 R/W STN/TFT : Frame buffer start address 1 register 0x00000000 LCDSADDR1 Bit Description Initial State LCDBANK [29:21] These bits indicate A[30:22] of the bank location for the video buffer in the system memory. LC[...]

S3C2410A LCD CONTROLLER 15- 33 FRAME Buffer Start Address 3 Register Register Address R/W Description Reset Value LCDSADDR3 0X4D00001C R/W STN/TFT : Virtual screen address set 0x00000000 LCDSADDR3 Bit Description Initial State OFFSIZE [21:11] Virtual screen offset size (the number of half words). This value defines the difference between the addres[...]

LCD CONTROLLER S3 C2410A 15- 34 RED Lookup Table Register Register Address R/W Description Reset Value REDLUT 0X4D000020 R/W STN : Red lookup table register 0x00000000 REDLUT Bit Description Initial State REDVAL [31:0] These bits define which of the 16 shades will be chosen by each of the 8 possible red combinations. 000 = REDVAL[3:0], 001 = REDVAL[...]

S3C2410A LCD CONTROLLER 15- 35 Dithering Mode Register Register Address R/W Description Reset Value DITHMODE 0X4D00004C R/W STN : Dithering mode register. This register reset value is 0x00000 But, user can change this value to 0x12210. (Refer to a sample program source for the latest value of this register.) 0x00000 DITHMODE Bit Description Initial[...]

LCD CONTROLLER S3 C2410A 15- 36 Temp Palette Register Register Address R/W Description Reset Value TPAL 0X4D000050 R/W TFT : Temporary palette register. This register value will be video data at next frame. 0x00000000 TPAL Bit Description Initial state TPALEN [24] Temporary palette register enable bit. 0 = Disable 1 = Enable 0 TPALVAL [23:0] Tempor[...]

S3C2410A LCD CONTROLLER 15- 37 LCD I nterrupt Pending Register Register Address R/W Description Reset Value LCDINTPND 0X4D000054 R/W Indicate the LCD interrupt pending register 0x0 LCDINTPND Bit Description Initial state INT_FrSyn [1] LCD frame synchronized interrupt pending bit. 0 = The interrupt has not been requested. 1 = The frame has asserted [...]

LCD CONTROLLER S3 C2410A 15- 38 LCD I nterrupt Mask Register Register Address R/W Description Reset Value LCDINTMSK 0X4D00005C R/W Determine which interrupt source is masked. The masked interrupt source will not be serviced. 0x3 LCDINTMSK Bit Description Initial state FIWSEL [2] Determine the trigger level of LCD FIFO. 0 = 4 words 1 = 8 words INT_F[...]

S3C2410A LCD CONTROLLER 15- 39 Register Setting Guide (STN) The LCD controller supports multiple screen sizes by special register setting. The CLKVAL value determines the frequency of VCLK. This value has to be determined such that the VCLK value is greater than data transmission rate. The data transmission rate for the VD port of the LCD controlle[...]

LCD CONTROLLER S3 C2410A 15- 40 Example 1: 160 x 160, 4-level gray, 80 frame/sec, 4-bit single scan display, HCLK frequency is 60 MHz WLH = 1, WDLY = 1. Data transmission rate = 160 × 160 × 80 × 1/4 = 512 kHz CLKVAL = 58, VCLK = 517 kHz HOZVAL = 39, LINEVAL = 159 LINEBLANK =10 LCDBASEL = LCDBASEU + 3200 NOTE: The higher the system load is, the l[...]

S3C2410A LCD CONTROLLER 15- 41 Gray Level Selection Guide The S3C2410A LCD controller can generate 16 gray level using Frame Rate Control (FRC). The FRC characteristics may cause unexpected patterns in gray level. These unwanted erroneous patterns may be shown in fast response LCD or at lower frame rates. Because the quality of LCD gray levels depe[...]

LCD CONTROLLER S3 C2410A 15- 42 Register Setting Guide (TFT LCD) The CLKVAL register value determines the frequency of VCLK and frame rate. Frame Rate = 1/ [ { (VSPW+1) + (VBPD+1) + (LIINEVAL + 1) + (VFPD+1) } × {(HSPW+1) + (HBPD +1) + (HFPD+1) + (HOZVAL + 1) } × { 2 × ( CLKVAL+1 ) / ( HCLK ) } ] For applications, the system timing must be consi[...]

S3C2410A ADC AND TOUCH SCREEN INTERFACE 16 - 1 16 ADC & TOUCH SCREEN INTERFACE OVERVIEW The 10-bit CMOS analog to digital converter (ADC) of the S3C2410A is a recycling typed device with 8-channel analog inputs. It converts the analog input signal into 10-bit binary digital codes at a maximum conversion rate of 500KSPS with 2.5 MHz A/D converte[...]

ADC AND TOUCH SCREEN INTERFACE S3C2410A 16- 2 ADC & TOUCH SCREEN INTERFACE OPERATION BLOCK DIAGRAM Figure 16-1 shows the functional block diagram of the S3C2410A A/D converter and Touch Screen Interface. Note that the A/D converter is a recycling type. A pull-up resister is attached to AIN[7] on VDDA_ADC. So, XP pad of the touch screen panel sh[...]

S3C2410A ADC AND TOUCH SCREEN INTERFACE 16- 3 EXAMPLE FOR TOUCH SCREEN In this example, AIN[7] is connected with XP and AIN[5]is connected with YP pad of the touch screen panel. To control pads of the touch screen panel (XP, XM, YP and YM), four external transistors are applied and control signals including nYPON, YMON, nXPON and XMON are connected[...]

ADC AND TOUCH SCREEN INTERFACE S3C2410A 16- 4 FUNCTION DESCRIPTIONS A/D Conversion Time When the PCLK frequency is 50 MHz and the prescaler value is 49, total 10-bit conversion time is given: A/D converter freq. = 50 MHz/(49+1) = 1 MHz Conversion time = 1/(1 MHz / 5cycles) = 1/200 kHz = 5 us NOTE This A/D converter is designed to operate at maximum[...]

S3C2410A ADC AND TOUCH SCREEN INTERFACE 16- 5 3. Auto (Sequential) X/Y Position Conversion Mode. Auto (Sequential) X/Y Position Conversion Mode (AUTO_PST = 1 and XY_PST = 0) is operated in the following way: The Touch Screen Controller automatically converts X-position and Y-position. The Touch Screen Controller writes X-measurement data to XPDATA [...]

ADC AND TOUCH SCREEN INTERFACE S3C2410A 16- 6 Programming Notes 1. The A/D converted data can be accessed by means of interrupt or polling method. With interrupt method, the overall conversion time - from A/D converter start to converted data read - may be delayed because of the return time of interrupt service routine and data access time. With po[...]

S3C2410A ADC AND TOUCH SCREEN INTERFACE 16- 7 ADC AND TOUCH SCREEN INTERFACE SPECIAL REGISTERS ADC CONTROL (ADCCON) REGISTER Register Address R/W Description Reset Value ADCCON 0x58000000 R/W ADC control register 0x3FC4 ADCCON Bit Description Initial State ECFLG [15] End of conversion flag (read only). 0 = A/D conversion in process 1 = End of A/D c[...]

ADC AND TOUCH SCREEN INTERFACE S3C2410A 16- 8 ADC TOUCH SCREEN CONTROL (ADCTSC) REGISTER Register Address R/W Description Reset Value ADCTSC 0x58000004 R/W ADC touch screen control register 0x058 ADCTSC Bit Description Initial State Reserved [8] This bit should be zero. 0 YM_SEN [7] Select output value of YMON. 0 = YMON output is 0 (YM = Hi-Z). 1 =[...]

S3C2410A ADC AND TOUCH SCREEN INTERFACE 16- 9 ADC START DELAY (ADCDLY) REGISTER Register Address R/W Description Reset Value ADCDLY 0x58000008 R/W ADC start or interval delay register 0x00ff ADCDLY Bit Description Initial State DELAY [15:0] 1) Normal Conversion Mode, Separate X/Y Position Conversion Mode, and Auto (Sequential) X/Y Position Conversi[...]

ADC AND TOUCH SCREEN INTERFACE S3C2410A 16- 10 ADC CONVERSION DATA (ADCDAT0) REGISTER Register Address R/W Description Reset Value ADCDAT0 0x5800000C R ADC conversion data register - ADCDAT0 Bit Description Initial State UPDOWN [15] Up or down state of Stylus at Waiting for Interrupt Mode. 0 = Stylus down state 1 = Stylus up state - AUTO_PST [14] A[...]

S3C2410A ADC AND TOUCH SCREEN INTERFACE 16- 11 ADC CONVERSION DATA (ADCDAT1) REGISTER Register Address R/W Description Reset Value ADCDAT1 0x58000010 R ADC conversion data register - ADCDAT1 Bit Description Initial State UPDOWN [15] Up or down state of Stylus at Waiting for Interrupt Mode. 0 = Stylus down state 1 = Stylus up state - AUTO_PST [14] A[...]

ADC AND TOUCH SCREEN INTERFACE S3C2410A 16- 12 NOTES[...]

S3C2410A REAL TIME CLOCK (RTC) 17- 1 17 REAL TIME CLOCK (RTC) OVERVIEW The Real Time Clock (RTC) unit can be operated by the backup battery while the system power is off. The RTC can transmit 8-bit data to CPU as Binary Coded Decimal (BCD) values using the STRB/LDRB ARM operation. The data include the time by second, minute, hour, date, day, month,[...]

REAL TIME CLOCK (RTC) S3C2410A 17- 2 REAL TIME CLOCK OPERATION 2 15 Clock Divider XTOrtc XTIrtc Control Register SEC Leap Year Generator Alarm Generator Reset Register 1 Hz ALMINT RTCCON RTCALM RTCRST Time Tick Generator TIME TICK TICNT 128 Hz PMWKUP PWDN MIN HOUR DATE DAY MON YEAR Figure 17-1. Real Time Clock Block Diagram LEAP YEAR GENERATOR The [...]

S3C2410A REAL TIME CLOCK (RTC) 17- 3 READ/WRITE REGISTERS Bit 0 of the RTCCON register must be set high in order to write the BCD register in RTC block. To display the second, minute, hour, date, month, and year, the CPU should read the data in BCDSEC, BCDMIN, BCDHOUR, BCDDAY, BCDDATE, BCDMON, and BCDYEAR registers, respectively, in the RTC block. [...]

REAL TIME CLOCK (RTC) S3C2410A 17- 4 32.768KHZ X-TAL CONNECTION EXAMPLE The Figure 17-2 shows a circuit of the RTC unit oscillation at 32.768 kHz. XTIrtc XTOrtc 32768Hz 15~ 22pF Figure 17-2. Main Oscillator Circuit Example[...]

S3C2410A REAL TIME CLOCK (RTC) 17- 5 REAL TIME CLOCK SPECIAL REGISTERS REAL TIME CLOCK CONTROL (RTCCON) REGISTER The RTCCON register consists of 4 bits such as the RTCEN, which controls the read/write enable of the BCD registers, CLKSEL, CNTSEL, and CLKRST for testing. RTCEN bit can control all interfaces between the CPU and the RTC, so it should b[...]

REAL TIME CLOCK (RTC) S3C2410A 17- 6 RTC ALARM CONTROL (RTCALM) REGISTER The RTCALM register determines the alarm enable and the alarm time. Note that the RTCALM register generates the alarm signal through both ALMINT and PMWKUP in power down mode, but only through ALMINT in the normal operation mode. Register Address R/W Description Reset Value RT[...]

S3C2410A REAL TIME CLOCK (RTC) 17- 7 ALARM SECOND DATA (ALMSEC) REGISTER Register Address R/W Description Reset Value ALMSEC 0x57000054(L) 0x57000057(B) R/W (by byte) Alarm second data register 0x0 ALMSEC Bit Description Initial State Reserved [7] 0 SECDATA [6:4] BCD value for alarm second. 0 ~ 5 000 [3:0] 0 ~ 9 0000 ALARM MIN DATA (ALMMIN) REGISTE[...]

REAL TIME CLOCK (RTC) S3C2410A 17- 8 ALARM DATE DATA (ALMDATE) REGISTER Register Address R/W Description Reset Value ALMDATE 0x57000060(L) 0x57000063(B) R/W (by byte) Alarm date data register 0x01 ALMDAY Bit Description Initial State Reserved [7:6] 00 DATEDATA [5:4] BCD value for alarm date, from 0 to 28, 29, 30, 31. 0 ~ 3 00 [3:0] 0 ~ 9 0001 ALARM[...]

S3C2410A REAL TIME CLOCK (RTC) 17- 9 RTC ROUND RESET (RTCRST) REGISTER Register Address R/W Description Reset Value RTCRST 0x5700006C(L) 0x5700006F(B) R/W (by byte) RTC round reset register 0x0 RTCRST Bit Description Initial State SRSTEN [3] Round second reset enable. 0 = Disable, 1 = Enable 0 SECCR [2:0] Round boundary for second carry generation.[...]

REAL TIME CLOCK (RTC) S3C2410A 17- 10 BCD HOUR (BCDHOUR) REGISTER Register Address R/W Description Reset Value BCDHOUR 0x57000078(L) 0x5700007B(B) R/W (by byte) BCD hour register Undefined BCDHOUR Bit Description Initial State Reserved [7:6] - HOURDATA [5:4] BCD value for hour. 0 ~ 2 - [3:0] 0 ~ 9 - BCD DATE (BCDDATE) REGISTER Register Address R/W [...]

S3C2410A REAL TIME CLOCK (RTC) 17- 11 BCD MONTH (BCDMON) REGISTER Register Address R/W Description Reset Value BCDMON 0x57000084(L) 0x57000087(B) R/W (by byte) BCD month register Undefined BCDMON Bit Description Initial State Reserved [7:5] - MONDATA [4] BCD value for month. 0 ~ 1 - [3:0] 0 ~ 9 - BCD YEAR (BCDYEAR) REGISTER Register Address R/W Des[...]

REAL TIME CLOCK (RTC) S3C2410A 17- 12 NOTES[...]

S3C2410A WATCHDOG TIMER 18- 1 18 WATCHDOG TIMER OVERVIEW The S3C2410A watchdog timer is used to resume the controller operation whenever it is disturbed by malfunctions such as noise and system errors. It can be used as a normal 16-bit interval timer to request interrupt service. The watchdog timer generates the reset signal for 128 PCLK cycles. FE[...]

WATCHDOG TIMER S3C 2410A 18- 2 WATCHDOG TIMER OPERATION Figure 18-1 shows the functional block diagram of the watchdog timer. The watchdog timer uses only PCLK as its source clock. The PCLK frequency is prescaled to generate the corresponding watchdog timer clock, and the resulting frequency is divided again. Reset Signal Generator WTCNT (Down Coun[...]

S3C2410A WATCHDOG TIMER 18- 3 WATCHDOG TIMER SPECIAL REGISTERS WATCHDOG TIMER CONTROL (WTCON) REGISTER The WTCON register allows the user to enable/disable the watchdog timer, select the clock signal from 4 different sources, enable/disable interrupts, and enable/disable the watchdog timer output. The Watchdog timer is used to resume the S3C2410A r[...]

WATCHDOG TIMER S3C 2410A 18- 4 WATCHDOG TIMER DATA (WTDAT) REGISTER The WTDAT register is used to specify the time-out duration. The content of WTDAT cannot be automatically loaded into the timer counter at initial watchdog timer operation. However, using 0x8000 (initial value) will drive the first time- out. In this case, the value of WTDAT will b[...]

S3C2410A MMC/SD/SD IO HOST CONTROLLER 19- 1 19 MMC/SD/SDIO HOST CONTROLLER OVERVIEW The S3C2410A SD Host controller can support MMC/SD card and SDIO devices. FEATURES — SD Memory Card Spec. (ver. 1.0) / MMC Spec. (2.11) compatible — SDIO Card Spec (ver. 1.0) compatible — 16 words (64 bytes) FIFO (d epth 16) for data Tx/Rx — 40-bit Command R[...]

MMC/SD/SDIO HOST CONTROLLER S3C2410A 19- 2 BLOCK DIAGRAM CMD Reg (5byte) Resp Reg (17byte) CMD Control 8bit Shift Reg CRC7 Prescaler FIFO (64byte) DAT Control 32bit Shift Reg CRC16*4 DMA INT APB I/F 32 32 8 8 32 32 32 32 32 32 PADDR PSEL PCLK PWDATA [31:0] PRDATA [31:0] DREQ DACK INT TxCMD RxCMD SDCLK TxDAT[3:0] RxDAT[3:0] Figure 19-1. Block Diagra[...]

S3C2410A MMC/SD/SDIO HOST CONTROLLER 19- 3 SDI OPERATION A serial clock line is synchronized with the five data lines for shifting and sampling of the information. Making the appropriate bit settings to the SDIPRE register depends on the transmission frequency. You can modify its frequency to adjust the baud rate data register value. Programming Pr[...]

MMC/SD/SDIO HOST CONTROLLER S3C2410A 19- 4 SDIO OPERATION There are two functions of the SDIO operation: SDIO Interrupt receiving and Read Wait Request generation. These two functions can operate when RcvIOInt bit and RwaitEn bit of SDICON register is activated respectively. Detailed steps and conditions for the two functions are described below. S[...]

S3C2410A MMC/SD/SDIO HOST CONTROLLER 19- 5 SDI SPECIAL REGISTERS SDI Control (SDICON) Register Register Address R/W Description Reset Value SDICON 0x5A000000 R/W SDI control register 0x0 SDICON Bit Description Initial Value Byte Order Type (ByteOrder) [4] Determine byte order type when you read (write) data from (to) SD host FIFO with word boundary[...]

MMC/SD/SDIO HOST CONTROLLER S3C2410A 19- 6 SDI Command Argument Register (SDICARG) Register Address R/W Description Reset Value SDICARG 0x5A000008 R/W SDI command argument register 0x0 SDICARG Bit Description Initial Value CmdArg [31:0] Command Argument 0x00000000 SDI Command Control (SDICCON) Register Register Address R/W Description Reset Value S[...]

S3C2410A MMC/SD/SDIO HOST CONTROLLER 19- 7 SDI Command Status (SDICSTA) Register Register Address R/W Description Reset Value SDICSTA 0x5A000010 R/(W) SDI command status register 0x0 SDICSTA Bit Description Initial Value Response CRC Fail(RspCrc) [12] R/W CRC check failed when command response received. This flag is cleared by setting one to this b[...]

MMC/SD/SDIO HOST CONTROLLER S3C2410A 19- 8 SDI Response Register 0 (SDIRSP0) Register Address R/W Description Reset Value SDIRSP0 0x5A000014 R SDI response register 0 0x0 SDIRSP0 Bit Description Initial Value Response0 [31:0] Card status[31:0](short), card status[127:96](long) 0x00000000 SDI Response Register 1 (SDIRSP1) Register Address R/W Descri[...]

S3C2410A MMC/SD/SDIO HOST CONTROLLER 19- 9 SDI Data / Busy Timer (SDIDTIMER) Register Register Address R/W Description Reset Value SDIDTIMER 0x5A000024 R/W SDI data / busy timer register 0x2000 SDIDTIMER Bit Description Initial Value DataTimer [15:0] Data / busy timeout period (0~65535 cycle) 0x2000 SDI Block Size (SDIBSIZE) Register Register Addre[...]

MMC/SD/SDIO HOST CONTROLLER S3C2410A 19- 10 SDI Data Control (SDIDCON) Register Register Address R/W Description Reset Value SDIDCON 0x5A00002C R/W SDI data control register 0x0 SDIDCON Bit Description Initial Value SDIO Interrupt Period Type (PrdType) [21] Determine whether SDIO Interrupt period is 2 cycle or extend more cycle when last data block[...]

S3C2410A MMC/SD/SDIO HOST CONTROLLER 19- 11 SDI Data Remain Counter (SDIDCNT) Register Register Address R/W Description Reset Value SDIDCNT 0x5A000030 R SDI data remain counter register 0x0 SDIDCNT Bit Description Initial Value BlkNumCnt [23:12] Remaining block number 0x000 BlkCnt [11:0] Remaining data byte of 1 block 0x000[...]

MMC/SD/SDIO HOST CONTROLLER S3C2410A 19- 12 SDI Data Status (SDIDSTA) Register Register Address R/W Description Reset Value SDIDSTA 0x5A000034 R/(W) SDI data status register 0x0 SDIDSTA Bit Description Initial Value Read Wait Request Occur (RWaitReq) [10] R/W Read wait request signal transmits to SD card. The request signal is stopped and this flag[...]

S3C2410A MMC/SD/SDIO HOST CONTROLLER 19- 13 SDI FIFO Status (SDIFSTA) Register Register Address R/W Description Reset Value SDIFSTA 0x5A000038 R SDI FIFO status register 0x0 SDIFSTA Bit Description Initial State FIFO available Detect for Tx (TFDET) [13] Indicate that FIFO data is available for transmission when DatMode (SDIDCON[12]) is data transmi[...]

MMC/SD/SDIO HOST CONTROLLER S3C2410A 19- 14 SDI Data (SDIDAT) Register Register Address R/W Description Reset Value SDIDAT 0x5A00003C(Li/W, Li/B, Bi/W) 0x5A00003F(Bi/B) R/W SDI data register 0x0 SDIDAT Bit Description Initial State Data Register [31:0] This field contains the data to be transmitted or received over the SDI channel. 0x00000000 NOTES[...]

S3C2410A MMC/SD/SDIO HOST CONTROLLER 19- 15 SDI Interrupt Mask (SDIIMSK) Register Register Address R/W Description Reset Value SDIIMSK 0x5A000040 R/W SDI interrupt mask register 0x0 SDIIMSK Bit Description Initial Value RspCrc Interrupt Enable [17] Response CRC error interrupt. 0 = disable, 1 = interrupt enable 0 CmdSent Interrupt Enable [16] Comma[...]

MMC/SD/SDIO HOST CONTROLLER S3C2410A 19- 16 SDI D ata/ B usy T imer R egister SDI data/ busy timer register has 16-bit counter. In case of 25MHz operation, the countable maximum time is 2.6ms (40ns * 0x10000). But, some cards have very long access time (TAAC), their TAAC are up to 100ms. In this case the SDI generates data timeout error state. To s[...]

S3C2410A IIC-BUS INTERFACE 20- 1 20 IIC-BUS INTERFACE OVERVIEW The S3C2410A RISC microprocessor can support a multi-master IIC-bus serial interface. A dedicated serial data line (SDA) and a serial clock line (SCL) carry information between bus masters and peripheral devices which are connected to the IIC-bus. The SDA and SCL lines are bi-directiona[...]

IIC-BUS INTERFACE S3C2410A 20- 2 PCLK Address Register SDA 4-bit Prescaler IIC-Bus Control Logic IICSTAT IICCON Comparator Shift Register Shift Register (IICDS) Data Bus SCL Figure 20-1. IIC-Bus Block Diagram NOTE: IIC DATA HOLD TIME The IIC data hold time(tSDAH) is minimum 0ns. (IIC data hold time is minimum 0ns for standard/fast bus mode in IIC s[...]

S3C2410A IIC-BUS INTERFACE 20- 3 IIC-BUS INTERFACE The S3C2410A IIC-bus interface has four operation modes: — Master transmitter mode — Master receive mode — Slave trans mitter mode — Slave receive mode Functional relationships among these operating modes are described below. START AND STOP CONDITIONS When the IIC-bus interface is inactive,[...]

IIC-BUS INTERFACE S3C2410A 20- 4 DATA TRANSFER FORMAT Every byte placed on the SDA line should be eight bits in length. The bytes can be unlimitedly transmitted per transfer. The first byte following a Start condition should have the address field. The address field can be transmitted by the master when the IIC-bus is operating in Master mode. Each[...]

S3C2410A IIC-BUS INTERFACE 20- 5 SDA Acknowledgement Signal from Receiver SCL S 1 2 7 8 9 1 2 9 Acknowledgement Signal from Receiver MSB ACK Byte Complete, Interrupt within Receiver Clock Line Held Low by receiver and/or transmitter Figure 20-4. Data Transfer on the IIC-Bus ACK SIGNAL TRANSMISSION To complete a one-byte transfer operation, the rece[...]

IIC-BUS INTERFACE S3C2410A 20- 6 READ-WRITE OPERATION In Transmitter mode, when the data is transferred, the IIC-bus interface will wait until IIC-bus Data Shift (IICDS) register receives a new data. Before the new data is written into the register, the SCL line will be held low, and then released after it is written. The S3C2410A should hold the i[...]

S3C2410A IIC-BUS INTERFACE 20- 7 FLOWCHARTS OF OPERATIONS IN EACH MODE The following steps must be executed before any IIC Tx/Rx operations. 1) Write own slave address on IICADD register, if needed. 2) Set IICCON register. a) Enable interrupt b) Define SCL period 3) Set IICSTAT to enable Serial Output Write slave address to IICDS. Write 0xF0 (M/T S[...]

IIC-BUS INTERFACE S3C2410A 20- 8 Write slave address to IICDS. Write 0xB0 (M/R Start) to IICSTAT. The data of the IICDS (slave address) is transmitted. ACK period and then interrupt is pending. Write 0x90 (M/R Stop) to IICSTAT. Read a new data from IICDS. Stop? Clear pending bit to resume. SDA is shifted to IICDS. START Master Rx mode has been conf[...]

S3C2410A IIC-BUS INTERFACE 20- 9 IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS (the received slave address). Write data to IICDS. The IIC address match interrupt is generated. Clear pending bit to resume. The data of the IICDS is shifted to SDA. START Slave Tx mode has been configured. END Matched? N Y Stop? Inte[...]

IIC-BUS INTERFACE S3C2410A 20- 10 IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS (the received slave address). Read data from IICDS. The IIC address match interrupt is generated. Clear pending bit to resume. SDA is shifted to IICDS. START Slave Rx mode has been configured. END Matched? N Y Stop? Interrupt is pendi[...]

S3C2410A IIC-BUS INTERFACE 20- 11 IIC-BUS INTERFACE SPECIAL REGISTERS MULTI-MASTER IIC-BUS CONTROL (IICCON) REGISTER Register Address R/W Description Reset Value IICCON 0x54000000 R/W IIC-Bus control register 0x0X IICCON Bit Description Initial State Acknowledge generation (note 1) [7] IIC-bus acknowledge enable bit. 0 = Disable, 1 = Enable In Tx m[...]

IIC-BUS INTERFACE S3C2410A 20- 12 MULTI-MASTER IIC-BUS CONTROL/STATUS (IICSTAT) REGISTER Register Address R/W Description Reset Value IICSTAT 0x54000004 R/W IIC-Bus control/status register 0x0 IICSTAT Bit Description Initial State Mode selection [7:6] IIC-bus master/slave Tx/Rx mode select bits. 00: Slave receive mode 01: Slave transmit mode 10: Ma[...]

S3C2410A IIC-BUS INTERFACE 20- 13 MULTI-MASTER IIC-BUS ADDRESS (IICADD) REGISTER Register Address R/W Description Reset Value IICADD 0x54000008 R/W IIC-Bus address register 0xXX IICADD Bit Description Initial State Slave address [7:0] 7-bit slave address, latched from the IIC-bus. When serial output enable = 0 in the IICSTAT, IICADD is write- enabl[...]

IIC-BUS INTERFACE S3C2410A 20- 14 NOTES[...]

S3C2410A IIS-BUS INTERFACE 21- 1 21 IIS-BUS INTERFACE OVERVIEW Currently, many digital audio systems are attracting the consumers on the market, in the form of compact discs, digital audio tapes, digital sound processors, and digital TV sound. The S3C2410A Inter-IC Sound (IIS) bus interface can be used to implement a CODEC interface to an external [...]

IIS-BUS INTERFACE S3C2410A 21- 2 BLOCK DIAGRAM ADDR DATA CNTL PCLK BRFC IPSR_A IPSR_B TxFIFO RxFIFO SCLKG CHNC SFTR LRCK SCLK SD CDCLK Figure 21-1. IIS-Bus Block Diagram FUNCTIONAL DESCRIPTIONS Bus interface, register bank, and state machine (BRFC): Bus interface logic and FIFO access are controlled by the state machine. 5-bit dual prescaler (IPSR)[...]

S3C2410A IIS-BUS INTERFACE 21- 3 DMA Transfer In this mode, transmit or receive FIFO is accessible by the DMA controller. DMA service request in transmit or receive mode is made by the FIFO ready flag automatically. Transmit and Receive Mode In this mode, IIS bus interface can transmit and receive data simultaneously. AUDIO SERIAL INTERFACE FORMAT [...]

IIS-BUS INTERFACE S3C2410A 21- 4 IIS-bus Format (N=8 or 16) MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) LRCK SCLK SD LEFT RIGHT LEFT MSB-justified Format (N=8 or 16) 2nd Bit N-1th Bit LSB (last) MSB (1st) 2nd Bit N-1th Bit LSB (last) LRCK SCLK SD LEFT RIGHT MSB (1st) Figure 21-2. IIS-Bus and MSB (Left)-ju[...]

S3C2410A IIS-BUS INTERFACE 21- 5 Table 21-2 Usable Serial Bit Clock Frequency (IISCLK = 16 or 32 or 48fs) Serial bit per channel 8-bit 16-bit Serial clock frequency (IISCLK) @CODECLK = 256fs 16fs, 32fs 32fs @CODECLK = 384fs 16fs, 32fs, 48fs 32fs, 48fs IIS-BUS INTERFACE SPECIAL REGISTERS IIS CONTROL (IISCON) REGISTER Register Address R/W Description[...]

IIS-BUS INTERFACE S3C2410A 21- 6 IIS MODE REGISTER (IISMOD) REGISTER Register Address R/W Description Reset Value IISMOD 0x55000004 (Li/W, Li/HW, Bi/W) 0x55000006 (Bi/HW) R/W IIS mode register 0x0 IISMOD Bit Description Initial State Master/slave mode select [8] 0 = Master mode (IISLRCK and IISCLK are output mode). 1 = Slave mode (IISLRCK and IISCL[...]

S3C2410A IIS-BUS INTERFACE 21- 7 IIS PRESCALER (IISPSR) REGISTER Register Address R/W Description Reset Value IISPSR 0x55000008 (Li/HW, Li/W, Bi/W) 0x5500000A (Bi/HW) R/W IIS prescaler register 0x0 IISPSR Bit Description Initial State Prescaler control A [9:5] Data value: 0 ~ 31 Note: Prescaler A makes the master clock that is used the internal blo[...]

IIS-BUS INTERFACE S3C2410A 21- 8 IIS FIFO CONTROL (IISFCON) REGISTER Register Address R/W Description Reset Value IISFCON 0x5500000C (Li/HW, Li/W, Bi/W) 0x5500000E (Bi/HW) R/W IIS FIFO interface register 0x0 IISFCON Bit Description Initial State Transmit FIFO access mode select [15] 0 = Normal 1 = DMA 0 Receive FIFO access mode select [14] 0 = Norm[...]

S3C2410A SPI INTERFACE 22- 1 22 SPI INTERFACE OVERVIEW The S3C2410A Serial Peripheral Interface (SPI) can interface the serial data transfer. The S3C2410A includes two SPI, each of which has two 8-bit shift registers for transmission and receiving, respectively. During an SPI transfer, data is simultaneously transmitted (shifted out serially) and r[...]

SPI INTERFACE S3C2 410A 22- 2 BLOCK DIAGRAM 8bit Prescaler 1 PCLK Status Register 1 Prescaler Register 1 /SS nSS 0 SCK SPICLK 0 MOSI SPIMOSI 0 MISO SPIMISO 0 Pin Control Logic 0 MSTR Tx 8bit Shift Reg 0 Rx 8bit Shift Reg 0 LSB MSB LSB MSB 8 8 Clock SPI Clock (Master) CPOL CPHA CLOCK Logic 0 MULF DCOL REDY APB I/F 0 (INT DMA 0) Slave Data Bus INT 0 [...]

S3C2410A SPI INTERFACE 22- 3 SPI OPERATION Using the SPI interface, the S3C2410A can send/receive 8 –bit data simultaneously with an external device. A serial clock line is synchronized with the two data lines for shifting and sampling of the information. When the SPI is the master, transmission frequency can be controlled by setting the appropri[...]

SPI INTERFACE S3C2 410A 22- 4 SPI Transfer Format The S3C2410A supports 4 different format to transfer the data. Figure 22-2 shows four waveforms for SPICLK.. * L SB of previously transmitted character Cycle MOSI 12 345678 MSB 6 54321 LSB 6 54321 LSB SPICLK MISO MSB CPOL = 1, CPHA = 1 (Format B) * M SB of character just received Cycle MOSI 12 34567[...]

S3C2410A SPI INTERFACE 22- 5 Transmitting Procedure by DMA 1. The SPI is configured as DMA mode. 2. DMA is configured properly. 3. The SPI requests DMA service. 4. DMA transmits 1byte data to the SPI. 5. The SPI transmits the data to card. 6. Return to Step 3 until DMA count becomes 0. 7. The SPI is configured as interrupt or polling mode with SMOD[...]

SPI INTERFACE S3C2 410A 22- 6 Guide 1) DMA mode: This mode cannot be used at SPI slave Rx mode with f ormat B. 2) Polling mode: DATA_READ signal should be delayed by 1phase of SPICLK at SPI slave Rx mode with format B. 3) Interrupt mode: DATA_READ signal should be delayed 1phase of SPICLK at SPI slave Rx mode with format B. SPICLK READY (Internal) [...]

S3C2410A SPI INTERFACE 22- 7 SPI SPECIAL REGISTERS SPI CONTROL REGISTER Register Address R/W Description Reset Value SPCON0 0x59000000 R/W SPI channel 0 control register 0x00 SPCON1 0x59000020 R/W SPI channel 1 control register 0x00 SPCONn Bit Description Initial State SPI Mode Select (SMOD) [6:5] Determine how and by what SPTDAT is read/written. 0[...]

SPI INTERFACE S3C2 410A 22- 8 SPI STATUS REGISTER Register Address R/W Description Reset Value SPSTA0 0x59000004 R SPI channel 0 status register 0x01 SPSTA1 0x59000024 R SPI channel 1 status register 0x01 SPSTAn Bit Description Initial State Reserved [7:3] Data Collision Error Flag (DCOL) [2] This flag is set if the SPTDATn is written or the SPRDAT[...]

S3C2410A SPI INTERFACE 22- 9 SPI PIN CONTROL REGISTER When the SPI system is enabled, the direction of pins, except nSS pin, is controlled by MSTR bit of SPCONn register. The direction of nSS pin is always input. When the SPI is a master, nSS pin is used to check multi-master error, provided the SPPIN's ENMUL bit is active, and another GPIO sh[...]

SPI INTERFACE S3C2 410A 22- 10 SPI Baud Rate Prescaler Register Register Address R/W Description Reset Value SPPRE0 0x5900000C R/W SPI cannel 0 baud rate prescaler register 0x00 SPPRE1 0x5900002C R/W SPI cannel 1 baud rate prescaler register 0x00 SPPREn Bit Description Initial State Prescaler Value [7:0] Determine SPI clock rate as above equation. [...]

S3C2410A BUS PRIORITIES 23- 1 23 BUS PRIORITIES OVERVIEW The bus arbitration logic determines the priorities of bus masters. It supports a combination of rotation priority mode and fixed priority mode. BUS PRIORITY MAP The S3C2410A holds eleven bus masters including SDRAM refresh controller, LCD_DMA, DMA0, DMA1, DMA2, DMA3, USB_HOST_DMA, EXT_BUS_MA[...]

BUS PRIORITIES S3C 2410A 23- 2 NOTES[...]

S3C2410A ELECTRICAL DATA 24- 1 24 ELECTRICAL DATA ABSOLUTE MAXIMUM RATINGS Table 24-1. Absolute Maximum Rating Parameter Symbol Rating (200MHz / 266MHz) Unit DC Supply Voltage V DDi 1.8V / 2.0V V DD 2.7 V DDRTC 1.8V V DD 2.7 V DDIO 3.3V V DD 3.8 DC Input Voltage V IN 3.3V Input buffer 3.8 V 3.3V Interface / 5V Tolerant input buffer 6.5 DC Output Vo[...]

ELECTRICAL DATA S3C 2410A 24- 2 D.C. ELECTRICAL CHARACTERISTICS Table 24-3 and 24-4 define the DC electrical characteristics for the standard LVCMOS I/O buffers. Table 24-3. Normal I/O PAD DC Electrical Characteristics (V DD = 3.3V ± 0.3V, T A = -40 to 85 ° C) Symbol Parameters Condition Min Type Max Unit V IH High level input voltage LVCMOS inte[...]

S3C2410A ELECTRICAL DATA 24- 3 Table 24-4. USB DC Electrical Characteristics Symbol Parameter Condition Min Max Unit V IH High level input voltage 2.5 V V IL Low level input voltage 0.8 V I IH High level input current Vin = 3.3V -10 10 µ A I IL Low level input current Vin = 0.0V -10 10 µ A V OH Static Output High 15K Ω to GND 2.8 3.6 V V OL Sta[...]

ELECTRICAL DATA S3C 2410A 24- 4 A.C. ELECTRICAL CHARACTERISTICS 1/2 V DD 1/2 V DD t XTALCYC NOTE: The clock input from the X TIpll pin. Figure 24-1. XTIpll Clock Timing t EXTHIGH V IH 1/2 V DD V IL V IL V IH V IH 1/2 V DD t EXTLOW t EXTCYC NOTE: The clock input from the EXTCLK pin. Figure 24-2. EXTCLK Clock Input Timing HCLK (internal) EXTCLK t EX2[...]

S3C2410A ELECTRICAL DATA 24- 5 HCLK (internal) SCLK CLKOUT (HCLK) t HC2CK t HC2SCLK Figure 24-4. HCLK/CLKOUT/SCLK in case that EXTCLK is used EXTCLK t RESW nRESET Figure 24-5. Manual Reset Input Timing[...]

ELECTRICAL DATA S3C 2410A 24- 6 nRESET XTIpll or EXTCLK VCO output MCU operates by XTIpll or EXTCLK clcok. Clock Disable t PLL FCLK is new frequency. Power PLL can operate after OM[3:2] is latched. PLL is configured by S/W first time. VCO is adapted to new clock frequency. FCLK ... ... ... t RST2RUN Figure 24-6. Power-On Oscillation Setting Timing[...]

S3C2410A ELECTRICAL DATA 24- 7 XTIpll VCO Output Clock Disable FCLK Several slow clocks (XTIpll or EXTCLK) Power_OFF mode is initiated. t OSC2 EXTCLK Figure 24-7. Power_OFF Mode Return Oscillation Setting Timing[...]

ELECTRICAL DATA S3C 2410A 24- 8 HCLK nGCSx tRAD nOE DATA ADDR nBEx tRCD tROD tROD tRCD Tacc tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH '1' Figure 24-8. ROM/SRAM Burst READ Timing(I) (Tacs = 0, Tcos = 0, Tacc = 2, Tcoh = 0, Tcah = 0, PMC = 0, ST = 0, DW = 16-bit)[...]

S3C2410A ELECTRICAL DATA 24- 9 HCLK nGCSx tRAD nOE DATA ADDR nBEx tRCD tROD tROD tRCD tRBED tRBED Tacc tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH Figure 24-9. ROM/SRAM Burst READ Timing(II) (Tacs = 0, Tcos = 0, Tacc = 2, Tcoh = 0, Tcah = 0, PMC = 0, ST = 1, DW = 16-bit)[...]

ELECTRICAL DATA S3C 2410A 24- 10 HCLK nGS nOE ADDR tXnBRQS XnBREQ tXnBRQH XnBACK 'HZ' 'HZ' 'HZ' tXnBACKD tXnBACKD tHZD tHZD tHZD Figure 24-10. External Bus Request in ROM/SRAM Cycle (Tacs = 0, Tcos = 0, Tacc = 8, Tcoh = 0, Tcah = 0, PMC = 0, ST = 0)[...]

S3C2410A ELECTRICAL DATA 24- 11 HCLK nGCSx tRAD Tacs nOE Tcos DATA ADDR nWBEx '1' Tcoh Tcah tRCD tROD tRDS tRDH tROD tRCD tRAD Tacc Figure 24-11. ROM/SRAM READ Timing (I) (Tacs = 2,Tcos = 2, Tacc = 4, Tcoh = 2, Tcah = 2, PMC = 0, ST = 0)[...]

ELECTRICAL DATA S3C 2410A 24- 12 HCLK nGCSx tRAD Tacs nOE Tcos DATA ADDR nBEx Tcoh Tcah tRCD tROD tRDS tRDH tROD tRCD tRAD tRBED tRBED Tacc Figure 24-12. ROM/SRAM READ Timing (II) (Tacs = 2, Tcos = 2, Tacc = 4, Tcoh = 2, Tcah = 2, PMC = 0, ST = 1)[...]

S3C2410A ELECTRICAL DATA 24- 13 HCLK nGCSx tRAD Tacs nWE Tcos DATA ADDR nWBEx Tcoh Tcah tRCD tRWD tRDD tRWD tRCD tRAD Tcos Tcoh tRWBED tRWBED Tacc tRDD Figure 24-13. ROM/SRAM WRITE Timing (I) (Tacs = 2,Tcos = 2,Tacc = 4,Tcoh = 2, Tcah = 2, PMC = 0, ST = 0[...]

ELECTRICAL DATA S3C 2410A 24- 14 HCLK nGCSx tRAD Tacs nWE Tcos DATA ADDR nBEx Tcoh Tcah tRCD tRWD tRDD tRWD tRCD tRAD tRBED tRBED Tacc tRDD Figure 24-14. ROM/SRAM WRITE Timing (II) (Tacs = 2, Tcos = 2, Tacc = 4, Tcoh = 2, Tcah = 2, PMC = 0, ST = 1)[...]

S3C2410A ELECTRICAL DATA 24- 15 HCLK nGCSx nOE Tacc = 6cycle nWait DATA ADDR Tacs Tcos delayed NOTE : T he status of nWait is checked at (Tacc-1) cycle. sampling nWait 3nS Figure 24-15. External nWAIT READ Timing (Tacs = 1, Tcos = 1, Tacc = 4, Tcoh = 0, Tcah = 1, PMC = 0, ST = 0) HCLK nGCSx nWE DATA ADDR tRDD tRDD Tacc >= 4 cycles nWait tWS tWH [...]

ELECTRICAL DATA S3C 2410A 24- 16 HCLK nGCSx tRAD Tacs nOE Tcos DATA ADDR tRCD tROD tRDS tRDH tRAD Tacc Figure 24-17. Masked-ROM Single READ Timing (Tacs = 2, Tcos = 2, Tacc = 8, PMC = 01/10/11) HCLK nGCSx tRAD nOE DATA ADDR tRCD tROD tRDS tRDH tRAD Tacc Tpac Tpac Tpac Tpac tRAD tRAD tRAD tRAD tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH Figure 24-18. Ma[...]

S3C2410A ELECTRICAL DATA 24- 17 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD tSDS tSDH SCKE A10/AP nGCSx tSCSD nWE tSAD tSCD tSWD '1' Trcd tSBED Tcl Figure 24-19. SDRAM Single Burst READ Timing (Trp = 2, Trcd = 2, Tcl = 2, DW = 16-bit)[...]

ELECTRICAL DATA S3C 2410A 24- 18 SCLK nSRAS nSCAS ADDR/BA nBEx tXnBRQH tXnBRQS SCKE A10/AP nGCSx nWE '1' XnBREQ XnBACK EXTCLK tXnBACKD tXnBACKD 'HZ' 'HZ' 'HZ' 'HZ' 'HZ' 'HZ' 'HZ' 'HZ' 'HZ' tHZD tHZD tHZD tHZD tHZD tHZD tHZD tHZD tHZD tXnBRQL Figure 2[...]

S3C2410A ELECTRICAL DATA 24- 19 SCLK nSRAS tSAD nSCAS DATA ADDR/BA nBEx tSRD SCKE A10/AP nGCSx tSCSD nWE tSAD tSCD tSWD '1' tSAD tSCSD tSRD 'HZ' '1' tSWD Figure 24-21. SDRAM MRS Timing[...]

ELECTRICAL DATA S3C 2410A 24- 20 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD tSDS tSDH SCKE A10/AP nGCSx tSCSD nWE tSAD tSCD tSWD '1' tSAD tSAD Trcd tSCSD tSRD tSCSD tSAD tSAD tSBED Tcl Figure 24-22. SDRAM Single READ Timing(I) (Trp = 2, Trcd = 2, Tcl = 2)[...]

S3C2410A ELECTRICAL DATA 24- 21 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD tSDS tSDH SCKE A10/AP nGCSx tSCSD nWE tSAD tSCD tSWD '1' tSAD tSAD Trcd tSCSD tSRD tSCSD tSAD tSAD tSBED Tcl Figure 24-23 SDRAM Single READ Timing(II) (Trp = 2, Trcd = 2, Tcl = 3)[...]

ELECTRICAL DATA S3C 2410A 24- 22 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD SCKE A10/AP nGCSx tSCSD nWE tSAD tSCD tSWD '1' tSAD tSCSD tSRD '1' '1' 'HZ' Trc NOTE: Before executing auto/self refresh command, all banks must be in idle state. Figure 24-24. SDRAM Auto Refresh Timing (Trp = 2, Trc = 4)[...]

S3C2410A ELECTRICAL DATA 24- 23 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD tSDS tSDH SCKE A10/AP nGCSx tSCSD nWE tSAD tSCD tSWD '1' Trcd tSBED Tcl Tcl Tcl Figure 24-25. SDRAM Page Hit-Miss READ Timing (Trp = 2, Trcd = 2, Tcl = 2)[...]

ELECTRICAL DATA S3C 2410A 24- 24 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD SCKE A10/AP nGCSx tSCSD nWE tSAD tSCD tSWD tSAD tSCSD tSRD '1' '1' 'HZ' Trc tCKED 'HZ' '1' '1' '1' '1' '1' tCKED NOTE: Before executing auto/self refresh command, all banks must [...]

S3C2410A ELECTRICAL DATA 24- 25 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD tSDD tSDD SCKE A10/AP nGCSx tSCSD nWE tSAD tSCD tSWD '1' tSAD tSAD Trcd tSCSD tSRD tSCSD tSAD tSAD tSBED tSWD Figure 24-27. SDRAM Single Write Timing (Trp = 2, Trcd = 2)[...]

ELECTRICAL DATA S3C 2410A 24- 26 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD tSDD tSDD SCKE A10/AP nGCSx tSCSD nWE tSAD tSCD tSWD '1' Trcd tSBED Figure 24-28. SDRAM Page Hit-Miss Write Timing (Trp = 2, Trcd = 2, Tcl = 2)[...]

S3C2410A ELECTRICAL DATA 24- 27 XSCLK tXRS tXRS tCADL tCADH tXAD XnXDREQ XnXDACK Read Write Min. 3SCLK Figure 24-29. External DMA Timing (Handshake, Single transfer) VSYNC HSYNC VDEN Tf2hsetup Tf2hhold Tvspw Tvbpd Tvfpd HSYNC VCLK VD VDEN LEND Tl2csetup Tvclkh Tvclk Tvclkl Tvdhold Tvdsetup Tve2hold Tle2chold Tlewidth Figure 24-30. TFT LCD Controlle[...]

ELECTRICAL DATA S3C 2410A 24- 28 tSDIS IISCLK IISLRCK IISDO CODECLK IISDI tSDIH tSDO tLRCK Figure 24-31. IIS Interface Timing tSTOPH tSTARTS tSDAS tSDAH tBUF tSCLHIGH tSCLLOW fSCL IICSCL IICSDA Figure 24-32. IIC Interface Timing[...]

S3C2410A ELECTRICAL DATA 24- 29 SDCLK tSDCD SDCMD (out) tSDCH tSDCS tSDDD SDCMD (in) tSDDH tSDDS SDDATA[3:0] (in) SDDATA[3:0] (out) Figure 24-33. SD/MMC Interface Timing SPICLK tSPIMOD tSPISIH tSPISIS tSPISOD tSPIMIH tSPIMIS SPIMOSI (MO) SPIMOSI (SI) SPIMISO (SO) SPIMISO (MI) Figure 24-34. SPI Interface Timing (CPHA = 1, CPOL = 1)[...]

ELECTRICAL DATA S3C 2410A 24- 30 TACLS TWRPH0 TWRPH1 COMMAND TWRPH0 TWRPH1 ADDRESS HCLK ALE nFWE DATA[7:0] DATA[7:0] HCLK CLE nFWE tCLED tCLED tWED tWED tWDS tWDH tALED tWED tWDS tALED tWED tWDH TACLS Figure 24-35. NAND Flash Address/Command Timing HCLK nFWE TWRPH0 TWRPH1 DATA[7:0] HCLK nFRE TWRPH0 TWRPH1 DATA[7:0] tWED tWED tWDH tWED tWED tRDS tRD[...]

S3C2410A ELECTRICAL DATA 24- 31 Table 24-6. Clock Timing Constants (V DDi =V DDalive =V DDiarm = 1.8V ± 0.15 / 2.0 V ± 0.1 V , T A = -40 to 85 ° C, V DDMOP = 3.3V ± 0.3V) Parameter Symbol Min Typ Max Unit Crystal clock input frequency f XTAL 10 – 20 MHz Crystal clock input cycle time t XTALCYC 50 – 100 ns External clock input frequency f EX[...]

ELECTRICAL DATA S3C 2410A 24- 32 Table 24-7. ROM/SRAM Bus Timing Constants (V DDi =V DDalive =V DDiarm = 1.8V ± 0.15 / 2.0 V ± 0.1 V, T A = -40 to 85 ° C, V DDMOP = 3.3V ± 0.3V) Parameter Symbol Min Typ Max Unit ROM/SRAM Address Delay t RAD 3 – 11 / 10.5 ns ROM/SRAM Chip select Delay t RCD 2 – 9 / 8.5 ns ROM/SRAM Output enable Delay t ROD 2[...]

S3C2410A ELECTRICAL DATA 24- 33 Table 24-9. External Bus Request Timing Constants (V DD = 1.8V ± 0.15 / 2.0 V ± 0.1 V , T A = -40 to 85 ° C, V EXT = 3.3V ± 0.3V) Parameter Symbol Min Typ. Max Unit eXternal Bus Request Setup time t XnBRQS 2 – 5 / 4 ns eXternal Bus Request Hold time t XnBRQH – – 1 / 0.5 ns eXternal Bus Ack Delay t XnBACKD 9[...]

ELECTRICAL DATA S3C 2410A 24- 34 Table 24-11. TFT LCD Controller Module Signal Timing Constants (V DD = 1.8V ± 0.15 / 2.0 V ± 0.1 V , T A = -40 to 85 ° C, V EXT = 3.3V ± 0.3V) Parameter Symbol Min Typ Max Units Vertical sync pulse width Tvspw VSPW + 1 – – Phclk (note1) Vertical back porch delay Tvbpd VBPD+1 – – Phclk Vertical front porc[...]

S3C2410A ELECTRICAL DATA 24- 35 Table 24-13. IIC BUS Controller Module Signal Timing (V DD = 1.8V ± 0.15 / 2.0 V ± 0.1 V , T A = -40 to 85 ° C, V EXT = 3.3V ± 0.3V) Parameter Symbol Min Typ. Max Unit SCL clock frequency f SCL – – std. 100 fast 400 kHz SCL high level pulse width t SCLHIGH std. 4.0 fast 0.6 – – µ s SCL low level pulse wi[...]

ELECTRICAL DATA S3C 2410A 24- 36 Table 24-15. SPI Interface Transmit/Receive Timing Constants (V DD = 1.8V ± 0.15 / 2.0 V ± 0.1 V , T A = -40 to 85 ° C, V EXT = 3.3V ± 0.3V) Parameter Symbol Min Typ. Max Unit SPI MOSI Master Output Delay time t SPIMOD 1.0 – 4.2 ns SPI MOSI Slave Input Setup time t SPISIS 0.1 – 0.1 ns SPI MOSI Slave Input Ho[...]

S3C2410A ELECTRICAL DATA 24- 37 Table 24-17. USB Full Speed Output Buffer Electrical Characteristics (V DD = 1.8V ± 0.15 / 2.0 V ± 0.1 V , T A = -40 to 85 ° C, V EXT = 3.3V ± 0.3V) Parameter Symbol Condition Min Max Unit Driver Characteristics Transition Time Rise Time Fall Time TR TF CL = 50pF CL = 50pF 4.0 4.0 2.0 2.0 ns Rise/Fall Time Matchi[...]

ELECTRICAL DATA S3C 2410A 24- 38 Table 24-19. NAND Flash Interface Timing Constants (V DDi =V DDalive =V DDiarm = 1.8V ± 0.15 / 2.0 V ± 0.1 V , T A = -40 to 85 ° C, V DDIO = 3.3V ± 0.3V) Parameter Symbol Min Typ Max Unit NFCON Chip Enable delay t CED – – 6.2 / 5.2 ns NFCON CLE delay t CLED – – 7.1 / 6.1 ns NFCON ALE delay t ALED – –[...]

S3C2410A MECHANICAL DATA 25- 1 25 MECHANICAL DATA PACKAGE DIMENSIONS 14.00 14.00 0.35 ± 0.05 1.16 0.45 ± 0.05 C 0.12 MAX 0.10 C A B 0.15 TOLERANCE ± 0.10 x 2 0.15 x 2 C C SAMSUNG Figure 25-1. 272-FBGA-1414 Package Dimension 1 (Top View)[...]

MECHANICAL DATA S3C2410A 25- 2 A1 INDEX MARK 0.80 x 16 = 12.80 ± 0.05 14.00 0.80 0.80 A B C D E F G H J K L M N P R T U 8 9 10 11 12 13 14 15 16 17 5 6 7 1 2 3 4 14.00 0.15 0.08 M M C C A B 272 - 0.45 ± 0.05 TOLERANCE ± 0.10 Figure 25-2. 272-FBGA-1414 Package Dimension 2 (Bottom View) The recommended land open size is 390 – 410 µ m (0.39 – [...]

ARM920T PROCESSOR I NTRODUCTION 1- 1 Appendix 1 ARM920T INTRODUCTION ABUOT THE INTRODUCTION The ARM920T is a member of the ARM9TDMI family of general-purpose microprocessors, which includes: — ARM9TDMI (ARM9TDMI core) — ARM940T (ARM9TDMI core plus cache and protection unit) — ARM920T (ARM9TD MI core plus cache and MMU). The ARM9TDMI processor[...]

INTRODUCTION ARM920 T PROCESSOR 1- 2 PROCESSOR FUNCTIONAL BLOCK DIAGRAM Shows the functional block diagram of the ARM920T External Coprocessor Interface Instruction Cache Instruction MMU R13 ARM9TDMI Processor Core (Integral EmbeddedICE) R13 Data Cache Data MMU CP15 Write Back PA TAG RAM Trace Interface Port Write Buffer AMBA Bus Interface IMVA[31:[...]

ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 1 Appendix 2 PROGRAMMER'S MODEL ABOUT THE PROGRAMMER'S MODEL ARM920T incorporates the ARM9TDMI integer core, which implements the ARMv4T architecture. It executes the ARM and Thumb instruction sets, and includes Embedded ICE JTAG software debug features. The programmer's model of the ARM9[...]

PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 2 ABOUT THE ARM9TDMI PROGRAMMER'S MODEL The ARM9TDMI processor core implements ARM v4T architecture, and so executes the ARM 32-bit instruction set and the compressed Thumb 16-bit instruction set. The programmer's model is fully described in the ARM Architecture Reference Manual. The ARM9TDMI T[...]

ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 3 INSTRUCTION SET EXTENSION SPACES All ARM processors implement the undefined instruction space as one of the entry mechanisms for the undefined instruction exception. That is, ARM instructions with opcode[27:25] = 0b011 and opcode[4] = 1 are undefined on all ARM processors including the ARM9TDMI and AR[...]

PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 4 CP15 REGISTER MAP SUMMARY CP15 defines 16 registers. The register map for CP15 is shown in Table 2 -2 Table 2-2. CP15 Register Map Register Read Write 0 ID code (1) Unpredictable 0 Cache type (1) Unpredictable 1 Control Control 2 Translation table base Translation table base 3 Domain access control Dom[...]

ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 5 ACCESSING CP15 REGISTERS Throughout this section the following terms and abbreviations are used. Table 2-3. CP15 Abbreviations Term Abbreviation Description Unpredictable UNP For reads, the data returned when reading from this location is unpredictable; it could have any value. For writes, writing to [...]

PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 6 Addresses in ARM920T Three distinct types of address exist in an ARM920T system: • virtual address (VA) • modified virtual address (MVA) • physical address (PA). Below is an example of the address manipulation when the ARM9TDMI requests an instruction. 1) The VA of the instruction (IVA) is issued[...]

ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 7 REGISTER 0: ID CODE REGISTER This is a read-only register which returns a 32-bit device ID code. The ID code register is accessed by reading CP15 register 0 with the opcode_2 field set to any value other than 1 (the CRm field should be zero when reading). For example: MRC p15,0,Rd,c0,c0,0; returns ID [...]

PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 8 REGISTER 0: CACHE TYPE REGISTER This is a read-only register which contains information about the size and architecture of the caches, allowing operating systems to establish how to perform such operations as cache cleaning and lockdown. Future ARM cached processors will contain this register, allowing[...]

ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 9 Bits [20:18] give the data cache size. Bits [8:6] give the instruction cache size. Table 2 -7 on page 2 -9 shows the meaning of values used for cache size encoding. Table 2-7. Cache Size Encoding Bits [20:18]/Bits [8:6] Cache Size 000 512B 001 1KB 010 2KB 011 4KB 100 8KB 101 16KB 110 32KB 111 64KB Bit[...]

PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 10 Table 2 -9 shows the meaning of values us ed for line length encoding Table 2-9. Line Length Encoding Bits [13:12]/Bits [1:0] Words Per Line 00 2 01 4 10 8 11 16 REGISTER 1: CONTROL REGISTER This register contains the control bits of the ARM920T. All reserved bits should either be written with zero or[...]

ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 11 Table 2-10. Control Register 1-bit Functions Register Bits Name Function Value 31 iA bit Asynchronous clock select See Table 2 -11 on page 2 -11. 30 nF bit notFastBus select See Table 2 -11 on page 2 -11. 29:15 – Reserved Read = Unpredictable Write = Should be zero 14 RR bit Round robin replacement[...]

PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 12 Enabling the MMU Care must be taken with the address mapping of the code sequence used to enable the MMU, see Enabling the MMU on page 3 -25. See Instruction cache enable/disable on page 4 -3 and Data cache and write buffer enable/disable on page 4 -6 for restrictions and effects of having caches enab[...]

ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 13 REGISTER 3: DOMAIN ACCESS CONTROL REGISTER Register 3 is the read/write domain access control register consisting of sixteen 2-bit fields. Each of these 2-bit fields defines the access permissions for the domains shown in Table 2 -13. Table 2-13. Register 3: Domain Access Control Register Bits Domain[...]

PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 14 REGISTER 4: RESERVED Accessing (reading or writing) this register will cause unpredictable behavior. REGISTER 5: FAULT STATUS REGISTERS Register 5 is the fault status register (FSR). The FSR contains the source of the last data fault, indicating the domain and type of access being attempted when the d[...]

ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 15 REGISTER 6: FAULT ADDRESS REGISTER Register 6 is the fault address register (FAR) which contains the modified virtual address of the access being attempted when the last fault occurred. The FAR is only updated for data faults, not for prefetch faults. (The address for a prefetch fault can be found in[...]

PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 16 The function of each cache operation is selected by the opcode_2 and CRm fields in the MCR instruction used to write CP15 register 7. Writing other opcode_2 or CRm values is unpredictable. Reading from CP15 register 7 is unpredictable. Table 2-16 on page 2 -16 shows instructions that can be used to pe[...]

ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 17 The operations which can be carried out upon a single cache line identify the line using the data passed in the MCR instruction. The data is interpreted using one of the following formats: 31 0 4 3 0 Modified virtual address 5 0 0 0 0 2 1 SBZ Figure 2-2. Register 7 MVA Format 31 19 15 16 11 12 21 20 [...]

PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 18 REGISTER 8: TLB OPERATIONS Register 8 is a write-only register used to manage the translation lookaside buffers (TLBs), the instruction TLB and the data TLB. Five TLB operations are defined and the function to be performed is selected by the opcode_2 and CRm fields in the MCR instruction used to write[...]

ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 19 REGISTER 9: CACHE LOCK DOWN REGISTER Register 9 is the cache lock down register. The cache lock down register is 0x0 on reset. The cache lock down register allows software to control which cache line in the ICache or DCache respectively is loaded for a linefill and to prevent lines in the ICache or D[...]

PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 20 Figure 2-5 shows the format of bits in register 9 31 19 15 16 11 12 21 20 0 0 8 7 4 3 0 0000 0 Index 0 26 25 24 23 10 9 5 0000 2 1 0 0 0 0 0 0 0 0 13 14 17 18 000 22 UNP/SBZ 6 000 Figure 2-5. Register 9 Table 2-18 shows the instructions needed to access the cache lock down register: Table 2-18. Access[...]

ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 21 REGISTER 10: TLB LOCK DOWN REGISTER Register 10 is the TLB lock down register. The TLB lock down register is 0x0 on reset. There is a TLB lock down register for each of the TLBs, the value of opcode_2 determines which TLB register to access: opcode_2 = 0x0 causes the D TLB register to be accessed opc[...]

PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 22 Load a single entry into I TLB location 0, make it immune to Invalidate All and lock it down: MCR to CP15 register 10, opcode_2 = 0x1, Base Value = 0, Current Victim = 0, P = 1 MCR I prefetch. Assuming an I TLB miss occurs, then entry 0 will be loaded. MCR to CP15 register 10, opcode_2 = 0x1, Base Val[...]

ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 23 Using the process Identifier (ProcID) Addresses issued by the ARM9TDMI core in the range 0 to 32MB are translated by CP15 register 13, the ProcID register. Address A becomes A + (ProcID x 32MB). It is this translated address that is seen by both the Caches and MMU. Addresses above 32MB undergo no tra[...]

PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 24 Changing the ProcID - performing a fast context switch A fast context switch is done by writing to CP15 register 13. The contents of the caches and TLBs do not have to be flushed after a fast context switch because they still hold valid address tags. It should be noted that the two instructions after [...]

ARM920T PROCESSOR M MU 3- 1 Appendix 3 MMU ABOUT THE MMU ARM920T implements an enhanced ARM Architecture V4 MMU to provide translation and access permission checks for the instruction and data address ports of the ARM9TDMI. The MMU is controlled from a single set of two- level page tables stored in main memory, and are enabled by M-Bit in CP15 regi[...]

MMU ARM920T PROCESS OR 3- 2 TRANSLATED ENTRIES Each TLB caches 64 translated entries. During CPU memory accesses, the TLB provides the protection information to the access control logic. If the TLB contains a translated entry for the modified virtual address, the access control logic determines whether access is permitted: • If access is permitte[...]

ARM920T PROCESSOR M MU 3- 3 MMU PROGRAM ACCESSIBLE REGISTERS Table 3-1 shows system control coprocessor (CP15) registers which are used, in conjunction with page table descriptors stored in memory, to determine the operation of the MMU Table 3-1. CP15 Register Functions Register Number Bits Register description Control register 1 M, A, S, R Contain[...]

MMU ARM920T PROCESS OR 3- 4 All the CP15 MMU registers, except register 8, contain state and can be read using MRC instructions and written using MCR instructions. Registers 5 and 6 are also written by the MMU during a data abort. Writing to Register 8 causes the MMU to perform a TLB operation, to manipulate TLB entries. This register cannot be rea[...]

ARM920T PROCESSOR M MU 3- 5 Translation table 4096 entries TTB base Indexed by modified virtual address bits [31:20] 1MB Section base Indexed by modified virtual address bits [19:0] Coarse page table 256 entries Coarse page table base Indexed by modified virtual address bits [19:12] Fine page table 1024 entries Tiny page table base Indexed by modif[...]

MMU ARM920T PROCESS OR 3- 6 HARDWARE TRANSLATION PROCESS TRANSLATION TABLE BASE The hardware translation process is initiated when the TLB does not contain a translation for the requested modified virtual address. The translation table base (TTB) register points to the base address of a table in physical memory which contains section and/or Page de[...]

ARM920T PROCESSOR M MU 3- 7 LEVEL ONE FETCH Bits 31:14 of the translation table base register are concatenated with bits 31:20 of the modified virtual address to produce a 30-bit address as illustrated in Figure 3-3 on page 3 -7. This address selects a 4-byte translation table entry which is a level one descriptor for either a section or a page tab[...]

MMU ARM920T PROCESS OR 3- 8 LEVEL ONE DESCRIPTOR The level one descriptor returned is either a section descriptor a coarse page table descriptor, or a fine page table descriptor. A section descriptor provides the base address of a 1MB block of memory. The page table descriptors provide the base address of a page table that contains level two descri[...]

ARM920T PROCESSOR M MU 3- 9 SECTION DESCRIPTOR Bits 3:2 (C & B) indicate whether the area of memory mapped by this section is treated as write-back cacheable, write-through cacheable, non-cached buffered or non-cached non-buffered. Bit 4 should be written to 1 for backward compatibility. Bits 8:5 specify one of the 16 possible domains (held in [...]

MMU ARM920T PROCESS OR 3- 10 TRANSLATING SECTION REFERENCES Figure 3-5 illustrates the complete section translation sequence. Note that access permissions contained in the level one descriptor must be checked before the physical address is generated. 31 0 Table index 19 20 Section index 0 31 0 Translation base Translation table base 13 14 31 0 Tran[...]

ARM920T PROCESSOR M MU 3- 11 LEVEL TWO DESCRIPTOR If the level one fetch returns either a coarse page table descriptor or a fine page table descriptor, this provides the base address of the page table to be used. The page table is then accessed and a level two descriptor is returned. This defines either a tiny, a small or a large page descriptor: ?[...]

MMU ARM920T PROCESS OR 3- 12 Bit 3:2 (C & B) indicate whether the area of memory mapped by this page is treated as write-back cacheable, write- through cacheable, non cached buffered or non-cached non-buffered. Domain access control on page 3 -19 and Fault checking sequence on page 3 -21 show how to interpret the access permission (ap) bits. NO[...]

ARM920T PROCESSOR M MU 3- 13 31 0 Table index 19 20 Page index 0 31 0 Translation base Translation table base 13 14 31 0 Translation base 13 14 1 2 0 Table index 18 Level one descriptor 1 31 0 Coarse page table base address 1 2 0 Domain 3 4 5 1 10 9 8 31 0 Page base address Physical address Page index 16 15 12 11 L2 table index Modified virtual add[...]

MMU ARM920T PROCESS OR 3- 14 TRANSLATING SMALL PAGE REFERENCES Figure 3-8 illustrates the complete translation sequence for a 4KB small page. If a small page descriptor is included in a fine page table, the upper two bits of the page index and low-order two bits of the fine page table index overlap. Each fine page table entry for a small page must [...]

ARM920T PROCESSOR M MU 3- 15 TRANSLATING TINY PAGE REFERENCES Figure 3-9 on page 3 -16 illustrates the complete translation sequence for a 1KB tiny page. Page translation involves one additional step beyond that of a section translation: the level one descriptor is the fine page table descriptor and this is used to point to the level one descriptor[...]

MMU ARM920T PROCESS OR 3- 16 31 0 Table index 19 20 Page index 0 31 0 Translation base Translation table base 13 14 31 0 Translation base 13 14 1 2 0 Table index 18 Level one descriptor 1 31 0 Fine page table base address 1 2 1 Domain 3 4 5 1 9 8 31 0 Page base address Physical address Page index L2 table index Modified virtual address 10 12 10 0 3[...]

ARM920T PROCESSOR M MU 3- 17 SUB-PAGES Access permissions can be defined for sub pages of small and large pages. If, during a page walk, a small or large page has a non-identical sub page permission, only the sub page being accessed is written into the TLB. For example, a 16KB (large page) sub page entry will be written into the TLB if the sub page[...]

MMU ARM920T PROCESS OR 3- 18 FAULT ADDRESS AND FAULT STATUS REGISTERS On a data abort, the MMU places an encoded 4 bit value, FS[3:0], along with the 4 -bit encoded domain number, in the Data fault status register (FSR). Similarly, on a prefetch abort, in the Prefetch fault status register, intended for debug purposes only. In addition, the modifie[...]

ARM920T PROCESSOR M MU 3- 19 DOMAIN ACCESS CONTROL MMU accesses are primarily controlled via domains. There are 16 domains and each has a 2-bit field to define access to it. Two types of user are supported, clients and managers. See Table 3-5. The domains are defined in the domain access control register. Figure 3-10 illustrates how the 32 bits of [...]

MMU ARM920T PROCESS OR 3- 20 Table 3-6 shows how to interpret the access permission (AP) bits and how their interpretation is dependent upon the S and R bits (control register bits 8 and 9). Table 3-6. Interpreting Access Permission (AP) Bits AP S R Supervisor Permissions User Permissions Notes 00 0 0 No access No access Any access generates a perm[...]

ARM920T PROCESSOR M MU 3- 21 FAULT CHECKING SEQUENCE The sequence by which the MMU checks for access faults is different for sections and pages. The sequence for both types of access is shown below. The conditions that generate each of the faults are described on the following pages. Modified virtual address Check address alignment Get level one de[...]

MMU ARM920T PROCESS OR 3- 22 ALIGNMENT FAULT If alignment fault is enabled (A-Bit in CP15 register 1 set), the MMU will generate an alignment fault on any data word access the address of which is not word aligned, or on any halfword access the address of which is not halfword aligned, irrespective of whether the MMU is enabled or not. An alignment [...]

ARM920T PROCESSOR M MU 3- 23 PERMISSION FAULT If the 2-bit domain field returns 01 (client) then access permissions are checked as follows: Section If the level one descriptor defines a section-mapped access, the AP bits of the descriptor define whether or not the access is allowed according to Table 3-6 on page 3 -20. Their interpretation is depen[...]

MMU ARM920T PROCESS OR 3- 24 EXTERNAL ABORTS In addition to the MMU-generated aborts the ARM920T can be externally aborted by the AMBA bus, which may be used to flag an error on an external memory access. However, not all accesses can be aborted in this way and the Bus Interface Unit (BIU) ignores external aborts that can not be handled. The follow[...]

ARM920T PROCESSOR M MU 3- 25 INTERACTION OF THE MMU AND CACHES The MMU is enabled and disabled using bit 0 of the CP15 control register. ENABLING THE MMU To enable the MMU: 1) Program the translation table base and doma in access control registers. 2) Program level 1 and level 2 page tables as required. 3) Enable the MMU by setting bit 0 in the con[...]

MMU ARM920T PROCESS OR 3- 26 NOTES[...]

ARM920T PROCESSOR C ACHES, WRITE BUFFER 4- 1 Appendix 4 CACHES, WRITE BUFFER ABOUT THE CACHES AND WRITE BUFFER The ARM920T includes an instruction cache, a data cache, a write buffer and a Physical Address TAG RAM to reduce the effect of main memory bandwidth and latency on performance. • The ARM920 T implements separate 16KB instruction and 16KB[...]

CACHES, WRITE BUFFER ARM920T PROCESSOR 4- 2 INSTRUCTION CACHE The ARM920T includes a 16KB instruction cache. The ICache has 512 lines of 32 bytes (8 words), arranged as a 64- way set-associative cache and uses modified virtual addresses, translated by CP15 register 13 (see Address translation on page 3 -4), from the ARM9TDMI core. The ICache implem[...]

ARM920T PROCESSOR C ACHES, WRITE BUFFER 4- 3 INSTRUCTION CACHE ENABLE/DISABLE On reset, the ICache entries are all invalidated and the ICache is disabled. The ICache is enabled by writing 1 to the Icr bit, and disabled by writing 0 to the Icr bit. The ICache is usually used with the MMU enabled, in which case the C bit in the relevant MMU translati[...]

CACHES, WRITE BUFFER ARM920T PROCESSOR 4- 4 INSTRUCTION CACHE REPLACEMENT ALGORITHM The ICache and DCache replacement algorithm is selected by the RR bit in the CP15 control register (CP15 register 1, bit 14). Random replacement is selected at reset. Setting the RR bit to 1 selects round-robin replacement. INSTRUCTION CACHE LOCKDOWN Instructions ca[...]

ARM920T PROCESSOR C ACHES, WRITE BUFFER 4- 5 DATA CACHE AND WRITE BUFFER The ARM920T includes a 16KB data cache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance. The DCache has 512 lines of 32 bytes (8-words), arranged as a 64-way set- associative cache and uses virtual addresses from the ARM9T[...]

CACHES, WRITE BUFFER ARM920T PROCESSOR 4- 6 DATA CACHE AND WRITE BUFFER ENABLE/DISABLE On reset, all DCache entries are invalidated, the DCache is disabled, and the write buffer contents are discarded. There is no explicit write buffer enable bit implemented in ARM920T. Situations in which the write buffer is used are described below. The DCache is[...]

ARM920T PROCESSOR C ACHES, WRITE BUFFER 4- 7 Table 4-1. Data Cache and Write Buffer Configuration Ctt and Ccr Btt Data cache, write buffer and memory access behavior 0 (1) 0 Non-cached, non-buffered (NCNB) Reads and writes are not cached and always perform accesses on the ASB and may be externally aborted. Writes are not buffered. The CPU halts unt[...]

CACHES, WRITE BUFFER ARM920T PROCESSOR 4- 8 A linefill performs an 8-word burst read from the ASB and places it as a new entry in the cache, possible replacing another line at the same location within the cache. The location which is replaced (called the victim) is chosen from the entries which are not locked using either a random or round-robin re[...]

ARM920T PROCESSOR C ACHES, WRITE BUFFER 4- 9 DATA CACHE ORGANIZATION The DCache is organized as 8 segments, each containing 64 lines, and each line containing 8-words. The line's position within its segment is a number from 0 to 63 which is called the index. A line in the cache can be uniquely identified by its segment and index. The index is [...]

CACHES, WRITE BUFFER ARM920T PROCESSOR 4- 10 CACHE COHERENCE The ICache and DCache contain copies of information normally held in main memory. If these copies of memory information get out of step with each other because one is updated and the others are not updated, they are said to have become incoherent. If the DCache contains a line which has b[...]

ARM920T PROCESSOR C ACHES, WRITE BUFFER 4- 11 Situations which necessitate cache cleaning and invalidating include: • writing instructions to a cacheable area of memory using STR or STM instructions, for example: — self -modifying code — JIT compilation — copying code from another location — downloading code via the EmbeddedICE JTAG debug[...]

CACHES, WRITE BUFFER ARM920T PROCESSOR 4- 12 CACHE CLEANING WHEN LOCKDOWN IS IN USE The clean D single entry (using index) and clean and invalidate D entry (using index) operations can leave the victim pointer set to the index value used by the operation. In some circumstances, if DCache locking is in use, this could leave the victim pointer in the[...]

ARM920T PROCESSOR C LOCK MODES 5- 1 Appendix 5 CLOCK MODES OVERVIEW The ARM920T has two functional clock inputs, BCLK and FCLK. Internally, the ARM920T is clocked by GCLK, which can be seen on the CPCLK output as shown in Figure 5-1. GCLK can be sourced from either BCLK or FCLK depending on the clocking mode, selected using nF bit and iA bit in CP1[...]

CLOCK MODES ARM920T PROCESSOR 5- 2 F ASTBUS MODE In this mode of operation the BCLK input is the source for GCLK. The FCLK input is ignored. This mode is typically used in systems with high speed memory. SYNCHRONOUS MODE This mode is typically used in systems with low speed memory. In this mode GCLK can be sourced from BCLK and FCLK. BCLK is used t[...]

ARM920T PROCESSOR C LOCK MODES 5- 3 A SYNCHRONOUS MODE This mode is typically used in systems with low speed memory. In this mode of operation GCLK can be sourced from BCLK and FCLK. BCLK is used to control the AMBA memory interface. FCLK is used to control the internal ARM9TDMI processor core and any cache operations. The one restriction is that F[...]

CLOCK MODES ARM920T PROCESSOR 5- 4 NOTES[...]

(For duplicate copies of this form, and for additional ordering information, please contact your local Sa m sung sales representative. Samsung sales offices are listed on the back cover of this book.) S3C SERIES MASK ROM ORDER FORM Product description: Device Number: S3C__________- ___________(write down the ROM code number) Product Order Form: Pac[...]

[...]

(For duplicate copies of this form, and for additional ordering information, please contact your local Sa m sung sales representative. Samsung sales offices are listed on the back cover of this book.) S3C SERIES REQUEST FOR PRODUCTION AT CUSTOMER RISK Customer Information: Company Name: ______________________________________________________________[...]

[...]

(For duplicate copies of this form, and for additional ordering information, please contact your local Sa m sung sales representative. Samsung sales offices are listed on the back cover of this book.) S3C2410A MASK OPTION SELECTION FORM Device Number: S3C2410 A -__________(write down the ROM code number) Attachment (Check one): Diskette PROM Custom[...]