Samsung S3C8245 manuel d'utilisation

24 - S3 - C8245/P8245/C8249/P8249-032004 USER'S MANUAL S3C8245/P8245/C8249/P8249 8-Bit CMOS Microcontroller s Revision 4[...]

NOTIFICATION OF REVISIONS ORIGINATOR: Samsung Electronics, LSI Development Group, Ki-Heung, South Korea PRODUCT NAME: S3C8245/P8245/C8249/P8249 8-bit CMOS Microcontroller DOCUMENT NAME: S3C8245/P8245/C8249/P8249 User's Manual, Revision 4 DOCUMENT NUMBER: 24-S3-C8245/P8245/C8249/P8249-032004 EFFECTIVE DATE: March, 2004 SUMMARY: As a result of a[...]

REVISION DESCRIPTIONS 1. DEVICE TYPE The S3C8247/C8248 device type should be moved. Product name and document name should be changed into 'S3C8245/P8245/C8249/P8249'. 2. FEATURES The Operating Temperature Range should be changed '-40 ° C to 85 ° C' into '-25 ° C to 85 ° C' in the page 1-2, from 19-2 to 19-12, and f[...]

S3C8245/P8245 /C8249/P8249 8-BIT CMOS MICROCONTROLLER S USER'S MANUAL Revision 4[...]

Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make chang[...]

S3C8245/P8245/C8249/P8249 MICROCONTROLLER iii Preface The S3C8245/P8245/C8249/P8249 Microcontroller User's Manual is designed for application designers and progr ammers who are using the S3C8245/P8245/C8249/P8249 microcontroller for application development. It is organized in two main parts: Part I Programming Model Part II Hardware Descriptio[...]

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S3C8245/P8245/C8249/P8249 MICROCONTROLLER v Table of Contents Part I — Programming Model Chapter 1 Product Overview S3C8-Series Microcontrollers ............................................................................................................... 1-1 S3C8245/P8245/C8249/P8249 Microcontroller .............................................[...]

vi S3C8245/P8245/C8249 /P8249 MICROCONTROLLER Table of Contents (Cont inued ) Chapter 4 Control Registers Overview ............................................................................................................................................. 4-1 Chapter 5 Interrupt Structure Overview ..................................................[...]

S3C8245/P8245/C8249/P8249 MICROCONTROLLER vii Table of Contents (Continued) Part II Hardware Descriptions Chapter 7 Clock Circuit Overview ............................................................................................................................................. 7-1 System Clock Circuit ............................................[...]

viii S3C8245/P8245/C8249 /P8249 MICROCONTROLLER Table of Contents (Continued) Chapter 11 8-bit Timer A/B 8-Bit Timer A ....................................................................................................................................... 11-1 Overview .................................................................................[...]

S3C8245/P8245/C8249/P8249 MICROCONTROLLER ix Table of Contents (Continued) Chapter 15 10-bit Analog-to-Digital Converter Overview ............................................................................................................................................. 15-1 Function Description ....................................................[...]

x S3C8245/P8245/C8249 /P8249 MICROCONTROLLER Table of Contents (Concluded ) Chapter 1 9 Electrical Data Overview ............................................................................................................................................. 19-1 Chapter 20 Mechanic al Data Overview .....................................................[...]

S3C8245/P8245/C8249/P8249 MICROCONTROLLER xi List of Figures Figure Title Page Number Number 1-1 S3C8245/C8249 Block Diagram ............................................................................ 1-3 1-2 S3C8245/C8249 Pin Assignment (80-QFP-1420C) .................................................. 1-4 1-3 S3C8245/C8249 Pin Assignment (80-TQFP[...]

xii S3C8245/P8245/C8249 /P8249 MICROCONTROLLER List of Figures (Continued) Figure Title Page Number Number 5-1 S3C8-Series Interrupt Types ................................................................................. 5-2 5-2 S3C8245/C8249 Interrupt Structure ....................................................................... 5-3 5-3 ROM Vec[...]

S3C8245/P8245/C8249/P8249 MICROCONTROLLER xiii List of Figures (Continued) Page Title Page Number Number 10-1 Basic Timer Control Register (BTCON) .................................................................. 10-2 10-2 Basic Timer Block Diagram .................................................................................. 10-4 11-1 Timer A[...]

xiv S3C8245/P8245/C8249 /P8249 MICROCONTROLLER List of Figures (Concluded) Page Title Page Number Number 17-1 Voltage Booster Block Diagram ............................................................................ 17-2 17-2 Pin Connection Example ...................................................................................... 17-2 18-1 Blo[...]

S3C8245/P8245/C8249/P8249 MICROCONTROLLER xv List of Tables Table Title Page Number Number 1-1 S3C8245/C8249 Pin Descriptions ......................................................................... 1-5 2-1 S3C8249/P8249 Register Type Summary .............................................................. 2-3 2-2 S3C8245/P8245 Register Type Summary[...]

xvi S3C8245/P8245/C8249 /P8249 MICROCONTROLLER List of Tables (Continued) Table Title Page Number Number 18-1 VLDCON Value and Detection Level ...................................................................... 18-2 19-1 Absolute Maximum Ratings .................................................................................. 19-2 19-2 D.C. Ele[...]

S3C8245/P8245/C8249/P8249 MICROCONTROLLER xvii List of Programming Tips Description Page Number Chapter 2: Address Spaces Using the Page Pointer for RAM clear (Page 0, Page1) ....................................................................... 2-5 Setting the Register Pointers .....................................................................[...]

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S3C8245/P8245/C8249/P8249 MICROCONTROLLER xix List of Register Descriptions Register Full Register Name Page Identifier Number ADCON A/D Converter Control Register ............................................................................. 4-5 BTCON Basic Timer Control Register .....................................................................[...]

xx S3C8245/P8245/C8249 /P8249 MICROCONTROLLER List of Register Descriptions (Continued) Register Full Register Name Page Identifier Number PP Register Page Pointer .......................................................................................... 4-33 RP0 Register Pointer 0 ...................................................................[...]

S3C8245/P8245/C8249/P8249 MICROCONTROLLER xxi List of Instruction Descriptions Instruction Full Register Name Page Mnemonic Number ADC Add with Carry .................................................................................................... 6-14 ADD Add ......................................................................................[...]

xxii S3C8245/P8245/C8249 /P8249 MICROCONTROLLER[...]

S3C8245/P8245/C8249/P8249 MICROCONTROLLER xxiii List of Instruction Descriptions (Continued) Instruction Full Register Name Page Mnemonic Number LDC/LDE Load Memory ...................................................................................................... 6-52 LDCD/LDED Load Memory and Decrement .........................................[...]

S3C8245/P8245/C8249/P8249 PRODUCT OVER VIEW 1- 1 1 PRODUCT OVERVIEW S3C8-SERIES MICROCONTROLLERS Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are: — Efficient register-oriented arc[...]

PRODUCT OVERVIEW S3 C8245/P8245/C8249/P8249 1- 2 FEATURES Memory • ROM: 32K-byte (S3C8249/P8249) • ROM: 16K-byte (S3C8245/P8245) • RAM: 1056-Byte (S3C8249/P8249) • RAM: 544-Byte (S3C8245/P8245) • Data memory mapped I/O Oscillation Sources • Crystal, ceramic, RC (main) • Crystal for subsystem clock • Main system clock frequency 1-10 [...]

S3C8245/P8245/C8249/P8249 PRODUCT OVERV IEW 1- 3 BLOCK DIAGRAM 544/1056 Byte Register File OSC/ nRESET Basic Timer Watch Timer I/O Port and Interrupt Control 16/32-Kbyte ROM SAM88 RC CPU 8-Bit Timer/ Counter B 16-Bit Timer/ Counter 0 16-Bit Timer/ Counter 1 I/O Port 0 I/O Port 1 A/D Converter I/O Port 2 8-Bit Timer/ Counter A I/O Port 3 TAOUT/TAPWM[...]

PRODUCT OVERVIEW S3 C8245/P8245/C8249/P8249 1- 4 PIN ASSIGNMENT SEG25/P5.1 SEG24/P5.0 SEG23/P4.7 SEG22/P4.6 SEG21/P4.5 SEG20/P4.4 SEG19/P4.3 SEG18/P4.2 SEG17/P4.1 SEG16/P4.0 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG26/P5.2 SEG27/P5.3 SEG28/P5.4 SEG29/P5.5 SEG30/P5.6 SEG31/P5.7 P3.0/TBPWM P3.1/TAOUT/TAPWM P3.2/TACLK P3.3/TACAP/SDAT P3.4/SCLK V DD V SS[...]

S3C8245/P8245/C8249/P8249 PRODUCT OVERV IEW 1- 5 SEG25/P5.1 SEG24/P5.0 SEG23/P4.7 SEG22/P4.6 SEG21/P4.5 SEG20/P4.4 SEG19/P4.3 SEG18/P4.2 SEG17/P4.1 SEG16/P4.0 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG26/P5.2 SEG27/P5.3 SEG28/P5.4 SEG29/P5.5 SEG30/P5.6 SEG31/P5.7 P3.0/TBPWM P3.1/TAOUT/TAPWM P3.2/TACLK P3.3/TACAP/SDAT P3.4/SCLK V DD[...]

PRODUCT OVERVIEW S3 C8245/P8245/C8249/P8249 1- 6 PIN DESCRIPTIONS Table 1-1. S3C8245/C8249 Pin Descriptions Pin Names Pin Type Pin Description Circuit Type Pin Numbers (note) Share Pins P0.0–P0.7 I/O I/O port with bit programmable pins; Schmitt trigger input or output mode selected by software; software assignable pull-up. P0.0–P0.7 can be used[...]

S3C8245/P8245/C8249/P8249 PRODUCT OVERV IEW 1- 7 Table 1-1. S3C8245/C8249 Pin Descriptions (Continued) Pin Names Pin Type Pin Description Circuit Type Pin Numbers (note) Share Pins ADC0–ADC6 ADC7 I A/D converter analog input channels F–10 F–18 36–42 43 P2.0–P2.6 P2.7 AV REF – A/D converter reference voltage – 44 – AV SS – A/D conv[...]

PRODUCT OVERVIEW S3 C8245/P8245/C8249/P8249 1- 8 PIN CIRCUITS In V DD Figure 1-4. Pin Circuit Type B (nRESET) P-Channel N-Channel V DD Out Output Disable Data Figure 1-5. Pin Circuit Type C P-Channel I/O Output Disable Data Circuit Type C Pull-up Enable V DD Figure 1-6. Pin Circuit Type D-2 (P3) I/O Output Disable Data Pin Circuit Type C Pull-up En[...]

S3C8245/P8245/C8249/P8249 PRODUCT OVERV IEW 1- 9 V DD Output Disable Data Pull-up Resistor V DD I/O P-CH N-CH Schmitt Trigger Open drain Enable Figure 1-8. Pin Circuit Type E-2 (P1) Pull-up Enable Circuit Type C Data Output Disable ADCEN To ADC Data V DD I/O Figure 1-9. Pin Circuit Type F-10 (P2.0–P2.6) Pull-up Enable Circuit Type C Data Output D[...]

PRODUCT OVERVIEW S3 C8245/P8245/C8249/P8249 1- 10 SEG V LC2 V LC1 V LC0 Output Disable Figure 1-12. Pin Circuit Type H-4 V DD Open Drain EN Data LCD Out EN SEG Output Disable Pull-up Enable V DD Circuit Type H-4 Figure 1-13. Pin Circuit Type H-14 (P4, P5)[...]

S3C8245/P8245/C8249/P8249 ADDRESS SPACES 2- 1 2 ADDRESS SPACES OVERVIEW The S3C8245/C8249 microcontroller has two types of address space: — Internal program memory (ROM) — Internal register file A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file[...]

ADDRESS SPACES S3C8245/P8245/C8249/P8249 2- 2 PROGRAM MEMORY (ROM) Program memory (ROM) stores program codes or table data. The S3C8249 has 32K bytes internal mask- programmable program memory, the S3C8245 has 16K bytes. The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations in this address range ca[...]

S3C8245/P8245/C8249/P8249 ADDRESS SPACES 2- 3 REGISTER ARCHITECTURE In the S3C8245/C8249 implementation, the upper 64-byte area of register files is expanded two 64 -byte areas, called set 1 and set 2 . The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1), and the lower 32-byte area is a single 32-byte [...]

ADDRESS SPACES S3C8245/P8245/C8249/P8249 2- 4 System Registers (Register Addressing Mode) General Purpose Register (Register Addressing Mode) Bank 1 System and Peripheral Control Registers Bank 0 System and Peripheral Control Registers (Register Addressing Mode) Set1 FFH E0H 32 Bytes E0H DFH D0H CFH C0H Prime Data Registers (All addressing modes) L[...]

S3C8245/P8245/C8249/P8249 ADDRESS SPACES 2- 5 REGISTER PAGE POINTER (PP) The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the register page pointer (PP, DFH). In the S3C8245/[...]

ADDRESS SPACES S3C8245/P8245/C8249/P8249 2- 6 REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH. The upper 32-byte area of this 64-byte space (E0H–FFH) is expanded two 32-byte register banks, bank 0 and bank 1 . The set register bank instructions, SB0 or SB1, are used to address one bank or the o[...]

S3C8245/P8245/C8249/P8249 ADDRESS SPACES 2- 7 PRIME REGISTER SPACE The lower 192 bytes (00H–BFH) of the S3C8245/C8249's four or two 256 -byte register pages is called prime register area. Prime registers can be accessed using any of the seven addressing modes (see Chapter 3, "Addressing Modes.") The prime register area on page 0 is[...]

ADDRESS SPACES S3C8245/P8245/C8249/P8249 2- 8 WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one that consists of 32 8-byte register groups or "slic[...]

S3C8245/P8245/C8249/P8249 ADDRESS SPACES 2- 9 USING THE REGISTER POINTS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8 -byte working register slices in the register file. After a reset, they point to the working register common area: RP0 points to addresses C0H–C7H, and RP1 points to addr[...]

ADDRESS SPACES S3C8245/P8245/C8249/P8249 2- 10 16-Byte Contiguous working Register block Register File Contains 32 8-Byte Slices 0 0 0 0 0 X X X RP1 1 1 1 1 0 X X X RP0 0H (R0) 7H (R15) F0H (R0) F7H (R7) 8-Byte Slice 8-Byte Slice Figure 2-7. Non-Contiguous 16-Byte Working Register Block + PROGRAMMING TIP — Using the RPs to Calculate the Sum of a [...]

S3C8245/P8245/C8249/P8249 ADDRESS SPACES 2- 11 REGISTER ADDRESSING The S3C8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. With Register (R) addressing mode, in which the operand value is the content of a specific register or[...]

ADDRESS SPACES S3C8245/P8245/C8249/P8249 2- 12 RP1 RP0 Register Pointers 00H All Addressing Modes Page 0 Indirect Register, Indexed Addressing Modes Page 0 Register Addressing Only Can be Pointed by Register Pointer FFH E0H BFH Control Registers System Registers Special-Purpose Registers D0H C0H Bank 1 Bank 1 NOTE: In the S3C8245/C8249 microcontrol[...]

S3C8245/P8245/C8249/P8249 ADDRESS SPACES 2- 13 COMMON WORKING REGISTER AREA (C0H–CFH) After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H– CFH, as the active 16-byte working register block: RP0 → C0H–C7H RP1 → C8H–CFH This 16-byte address range is called common area . That[...]

ADDRESS SPACES S3C8245/P8245/C8249/P8249 2- 14 + PROGRAMMING TIP — Addressing the Common Working Register Area As the following examples show, you should access working registers in the common area, locations C0H–CFH, using working register addressing mode only. Examples 1. LD 0C2H,40H ; Invalid addressing mode! Use working register addressing [...]

S3C8245/P8245/C8249/P8249 ADDRESS SPACES 2- 15 Together they create an 8-bit register address Register pointer provides five high-order bits Address OPCODE Selects RP0 or RP1 RP1 RP0 4-bit address provides three low-order bits Figure 2-11. 4-Bit Working Register Addressing Register address (76H) RP0 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 0 R6 0 1 1 0 1 1 1 [...]

ADDRESS SPACES S3C8245/P8245/C8249/P8249 2- 16 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value "1100B." This 4-bit value (1100B) [...]

S3C8245/P8245/C8249/P8249 ADDRESS SPACES 2- 17 8-bit address form instruction 'LD R11, R2' RP0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 Selects RP1 R11 Register address (0ABH) RP1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 Specifies working register addressing Figure 2-14. 8-Bit Working Register Addressing Example[...]

ADDRESS SPACES S3C8245/P8245/C8249/P8249 2- 18 SYSTEM AND USER STACK The S3C8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH and POP instructions are used to control system stack operations. The S3C8245/C8249 architecture supports stack operations in the internal register file. Stack Operations[...]

S3C8245/P8245/C8249/P8249 ADDRESS SPACES 2- 19 + PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: LD SPL,#0FFH ; SPL ← FFH ; (Normally, the SPL is set to 0FFH by the initialization ; routine) • • • P[...]

ADDRESS SPACES S3C8245/P8245/C8249/P8249 2- 20 NOTES[...]

S3C8245/P8245/C8249/P8249 ADDRESSING MO DES 3- 1 3 ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The ope[...]

ADDRESSING MODES S3 C8245/P8245/C8249/P8249 3- 2 REGISTER ADDRESSING MODE (R) In Register addressing mode (R), the operand value is the content of a specified register or register pair (see Figure 3-1). Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8 -byte working register space in the[...]

S3C8245/P8245/C8249/P8249 ADDRESSING MO DES 3- 3 INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an[...]

ADDRESSING MODES S3 C8245/P8245/C8249/P8249 3- 4 INDIRECT REGISTER ADDRESSING MODE (C ontinued ) dst OPCODE PAIR Points to Register Pair Example Instruction References Program Memory Sample Instructions: CALL @RR2 JP @RR2 Program Memory Register File Value used in Instruction OPERAND REGISTER Program Memory 16-Bit Address Points to Program Memory F[...]

S3C8245/P8245/C8249/P8249 ADDRESSING MO DES 3- 5 INDIRECT REGISTER ADDRESSING MODE (C ontinued ) dst OPCODE ADDRESS 4-bit Working Register Address Point to the Working Register (1 of 8) Sample Instruction: OR R3, @R6 Program Memory Register File src 3 LSBs Value used in Instruction OPERAND Selected RP points to start fo working register block RP0 o[...]

ADDRESSING MODES S3 C8245/P8245/C8249/P8249 3- 6 INDIRECT REGISTER ADDRESSING MODE (C oncluded ) dst OPCODE 4-bit Working Register Address Sample Instructions: LCD R5,@RR6 ; Program memory access LDE R3,@RR14 ; External data memory access LDE @RR4, R8 ; External data memory access Program Memory Register File src Value used in Instruction OPERAND E[...]

S3C8245/P8245/C8249/P8249 ADDRESSING MO DES 3- 7 INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory[...]

ADDRESSING MODES S3 C8245/P8245/C8249/P8249 3- 8 INDEXED ADDRESSING MODE (C ontinued ) Register File OPERAND Program Memory or Data Memory Point to Working Register Pair (1 of 4) LSB Selects 16-Bit address added to offset RP0 or RP1 MSB Points to RP0 or RP1 Selected RP points to start of working register block dst/src OPCODE Program Memory x OFFSET[...]

S3C8245/P8245/C8249/P8249 ADDRESSING MO DES 3- 9 INDEXED ADDRESSING MODE (C oncluded ) Register File OPERAND Program Memory or Data Memory Point to Working Register Pair LSB Selects 16-Bit address added to offset RP0 or RP1 MSB Points to RP0 or RP1 Selected RP points to start of working register block Sample Instructions: LDC R4, #1000H[RR2] ; The [...]

ADDRESSING MODES S3 C8245/P8245/C8249/P8249 3- 10 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.[...]

S3C8245/P8245/C8249/P8249 ADDRESSING MO DES 3- 11 DIRECT ADDRESS MODE (C ontinued ) OPCODE Program Memory Lower Address Byte Memory Address Used Upper Address Byte Sample Instructions: JP C,JOB1 ; Where JOB1 is a 16-bit immediate address CALL DISPLAY ; Where DISPLAY is a 16-bit immediate address Next OPCODE Figure 3-11. Direct Addressing for Call a[...]

ADDRESSING MODES S3 C8245/P8245/C8249/P8249 3- 12 INDIRECT ADDRESS MODE (IA) In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed. Only the CALL instruction can use the Indire[...]

S3C8245/P8245/C8249/P8249 ADDRESSING MO DES 3- 13 RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a twos-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addit[...]

ADDRESSING MODES S3 C8245/P8245/C8249/P8249 3- 14 IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values in[...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 1 4 CONTROL REGISTERS OVERVIEW In this chapter , deta iled descriptions of the S3C8245/C8249 control registers are presented in an easy-to-read format. You can use this chapter as a quick-reference source when writing application programs. Figure 4-1 illustrates the important features of the standard r[...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 2 T able 4- 2 . Set 1, Bank 0 Registers Register Name Mnemonic Decimal Hex R/W Port 0 control High register P0 CONH 224 E0H R/W Port 0 control Low register P0CONL 225 E1H R/W Port 0 interrupt control register P0INT 226 E2H R/W Port 0 interrupt pending register P0PND 227 E3H R/W Port 1 control High reg[...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 3 Table 4- 3 . Set 1, Bank 1 Registers Register Name Mnemonic Decimal Hex R/W Locations E0H–EBH is not mapped. Port 4 control High register P4CONH 236 ECH R/W Port 4 control Low register P4CONL 237 EDH R/W Port 5 control High register P5CONH 238 EEH R/W Port 5 control Low register P5CONL 239 EFH R/W [...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 4 FLAGS - System Flags Register .7 Carry Flag (C) .6 Zero Flag (Z) .5 Bit Identifier nRESET Value Read/Write Bit Addressing Mode R = Read-only W = Write-only R/W = Read/write '-' = Not used Type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit) nRESET value notation[...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 5 AD CON — A/D Converter Control Register F7 H Set 1 , Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value –0000000 Read/Write – R/W R/W R/W R R/W R/W R/W Addressing Mode Register addressing mode only .7 Not used for the S3C8245/C8249 . 6– . 4 A/D Input Pin Selection Bits 000 ADC0 001 AD[...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 6 BTCON — Basic Timer Control Register D3H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.4 Watchdog Timer Function Disable Code (for System Reset) 1010 Disable watchdog timer function [...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 7 CLKCON — System Clock Control Register D4H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write ––– R/W R/W ––– Addressing Mode Register addressing mode only .7– .5 Not used for the S3C8245/C8249 .4– .3 CPU Clock (System Clock) Selection Bits (note) 0 0 fxx/[...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 8 EMT — External Memory Timing Register FE H Set 1 , Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0––––––– Read/Write –––––––– Addressing Mode Register addressing mode only .7–.0 Not used for the S3C8245/C8249[...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 9 FLAGS — System Flags Register D5H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value xxxxxx 0 0 Read/Write R/W R/W R/W R/W R/W R/W R R/W Addressing Mode Register addressing mode only .7 Carry Flag (C) 0 Operation does not generate a carry or borrow condition 1 Operation generates a carry-out[...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 10 IMR — Interrupt Mask Register DDH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value xxxxxxxx Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only . 7 Interrupt Level 7 (IRQ 7 ) Enable Bit; External Interrupts P0.4–0.7 0 Disable (mask) 1 Enable (unmask[...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 11 I NTPND — Interrupt Pending Register D 2 H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value –––––000 Read/Write ––––– R/W R/W R/W Addressing Mode Register addressing mode only . 7–.3 Not used for the S3C8245/C8249 .2 Timer 1 Overflow Interrupt Pending Bit 0 Interrupt[...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 12 IPH — Instruction Pointer (High Byte ) DAH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value xxxxxxxx Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.0 Instruction Pointer Address (High Byte) The high-byte instruction pointer value is the upp[...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 13 IPR — Interrupt Priority Register FFH Set 1 , Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value xxxxxxxx Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7, .4, and .1 Priority Control Bits for Interrupt Groups A, B, and C 000 Group priority undefi[...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 14 IRQ — Interrupt Request Register DCH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write RRRRRRRR Addressing Mode Register addressing mode only . 7 Level 7 (IRQ 7 ) Request Pending Bit; External Interrupts P0.4–0.7 0 Not pending 1 Pending .6 Level 6 (IRQ6) Request Pend[...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 15 LCON — LCD Control Register D0 H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write R/W R/W R/W R/W – R/W R/W R/W Addressing Mode Register addressing mode only . 7 LCD Output Segment and Pin Configuration Bits 0 P5.4–P5.7 I/O is selected 1 SEG28–SEG31 is selected, [...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 16 1 COM and SEG output is in display mode; turn display on[...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 17 LMOD — LCD Mode Control Register D1H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write – – R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – . 6 Not used for the S3C8245/C8249 . 5– . 4 LCD Clock (LCDCK) Frequency Selection Bits 0 0 32.76[...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 18 OSCCON — Oscillator Control Register F3H Set 1 ,Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write ––– R/W R/W R/W – R/W Addressing Mode Register addressing mode only . 7–.5 Not used for the S3C8245/C8249 . 4 Sub-system Oscillator Driving Ability Control Bit [...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 19 P0CON H — Port 0 Control Register (High Byte) E0H Set 1,Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – . 6 P0.7/INT7 0 0 Schmitt trigger input mode; pull-up ; interrupt on falling e[...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 20 P0CON L — Port 0 Control Register (Low Byte) E1H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – . 6 P0.3/INT3 0 0 Schmitt trigger input mode; pull-up ; interrupt on falling [...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 21 P0 INT — Port 0 Interrupt Control Register E2H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P0.7 External Interrupt (INT7) Enable Bit 0 Disable interrupt 1 Enable interrupt .6 [...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 22 P0 PND — Port 0 Interrupt Pending Register E3H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P0.7/INT7 Interrupt Pending Bit 0 Interrupt request is not pending, pending bit cle[...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 23 0 Interrupt request is not pending, pending bit clear when write 0 1 Interrupt request is pending[...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 24 P 1 CON H — Port 1 Control Register (High Byte) E 4 H Set 1 , Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – . 6 P1.7/SI 0 0 Input mode (SI) 0 1 Output mode, open-drain 1 0 Alterna[...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 25 P 1 CON L — Port 1 Control Register (Low Byte) E 5 H Set 1 , Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – . 6 P1.3 0 0 Input mode 0 1 Output mode, open-drain 1 0 Alternative funct[...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 26 P 1PUP — Port 1 Pull-up Control Register F5H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P1.7 Pull-up Resistor Enable Bit 0 Pull-up disable 1 Pull-up enable .6 P1.6 Pull-up R[...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 27[...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 28 P 2 CONH — Port 2 Control Register (High Byte ) E 6 H Set 1 , Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P2.7/VLDREF/ADC7 0 0 Input mode 0 1 Input mode, pull-up 1 0 Alternativ[...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 29 P 2 CONL — Port 2 Control Register (Low Byte ) E7 H Set 1 , Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7– .6 P 2 .3 /ADC3 0 0 Input mode 0 1 Input mode, pull-up 1 0 Alternative func[...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 30 P 3 CONH — Port 3 Control Register (High Byte ) E 8 H Set 1 , Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write –––––– R/W R/W Addressing Mode Register addressing mode only .7–.2 Not used for the S3C8245/C8249 .1–.0 P3.4 Mode Selection Bits 0 0 Input m[...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 31 P3 CONL — Port 3 Control Register (Low Byte ) E9 H Set 1 , Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7– .6 P3. 3 /TACAP Mode Selection Bits 0 0 Input mode (TACAP) 0 1 Input mode, p[...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 32 P4 CONH — Port 4 Control Register (High Byte ) E CH Set 1 , Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P4.7/SEG23 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1 [...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 33 P4 CONL — Port 4 Control Register (Low Byte ) ED H Set 1 , Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7– .6 P4. 3 /SEG19 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1[...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 34 P5CONH — Port 5 Control Register (High Byte ) EE H Set 1 , Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P5.7/SEG31 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0[...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 35 P5 CONL — Port 5 Control Register (Low Byte ) EF H Set 1 , Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7– .6 P5. 3 /SEG27 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1[...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 36 PP — Register Page Pointer DFH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .4 Destination Register Page Selection Bits 0000 Destination: page 0 0001 Destination: page 1 0010 Dest[...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 37 RP0 — Register Pointer 0 D6H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 11000––– Read/Write R/W R/W R/W R/W R/W ––– Addressing Mode Register addressing only .7 – .3 Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 256 -byte work[...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 38 SIOCON — SIO Control Register FO H Set 1 , Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 10000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 SIO Shift Clock Selection Bit 0 Internal clock (P.S clock) 1 External clock (SCK) .6 Data Dire[...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 39 SPH — Stack Pointer (High Byte ) D8H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value xxxxxxxx Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .0 Stack Pointer Address (High Byte) The high-byte stack pointer value is the upper eight bits of [...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 40 STPCON — Stop Control Register F 4 H Set 1 , Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 –.0 STOP Control Bits 1 0 1 0 0 1 0 1 Enable stop instruction Other values Disable stop in[...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 41 SYM — System Mode Register DE H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 0–– xxx 0 0 Read/Write R/W – – R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Not used, But you must keep "0" .6– .5 Not used for the S3C8245/C8249 .4 – .2 Fast Int[...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 42 T0CON — Timer 0 Control Register F1 H Set 1 , Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 000–0000 Read/Write R/W R/W R/W – R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.5 Timer 0 Input Clock Selection Bits 000 TBOF (T-FF) 010 fxx/256 100 fxx/64 110 fxx/8 [...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 43 T1CON — Timer 1 Control Register FB H Set 1 , Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.5 Timer 1 Input Clock Selection Bits 000 fxx/1024 010 fxx/256 100 fxx/64 110 fxx/8 001 fx[...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 44 T A CON — Timer A Control Register ED H Set 1 , Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 Timer A Input Clock Selection Bits 0 0 fxx/1024 0 1 fxx/256 1 0 fxx/64 1 1 External [...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 45 T B CON — Timer B Control Register EC H Set 1 , Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00 000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 Timer B Input Clock Selection Bits 0 0 fxx 0 1 fxx/2 1 0 fxx/4 1 1 fxx/8 .5–.4 Tim[...]

CONTROL REGISTERS S 3C8245/P8245/C8249/P8249 4- 46 VLDCON — Voltage Level Detector Control Register F6 H Set 1 , Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write ––– R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 –.5 Not used for the S3C8245/C8249 . 4 V IN Source Bit 0 Internal source 1 [...]

S3C8245/P8245/C8249/P8249 CONTROL REGIS TER 4- 47 WT CON — Watch Timer Control Register FA H Set 1 , Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 nRESET Value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only . 7 Watch Timer Clock Selection Bit 0 Main system clock divided by 2 7 (fxx/128) 1 Sub sys[...]

S3C8245/P8245/C8249/P8249 INTERRUPT STRUCTURE 5 - 1 5 INTERRUPT STRUCTURE OVERVIEW The S3C8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM8 CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has more than one vec t or address, the vector[...]

INTERRUPT STRUCTURE S3C8245/P8245/C8249 /P8249 5- 2 INTERRUPT TYPES The three components of the S3C8 interrupt structure described before — levels, vectors, and sources — are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. There are three possible combinations of inter[...]

S3C8245/P8245/C8249/P8249 INTERRUPT STRUCTURE 5 - 3 S3C8245/C8249 INTERRUPT STRUCTURE The S3C8245/C8249 microcontroller supports sixteen interrupt sources. All sixteen of the interrupt source s ha ve a corresponding interrupt vector address. Eight interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in Fi[...]

INTERRUPT STRUCTURE S3C8245/P8245/C8249 /P8249 5- 4 INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3C8245/C8249 interrupt structure are stored in the vector address area of the internal 32- Kbyte ROM, 0H– 7 FFF H , or 8, 16, 24-Kbyte (see Figure 5-3). You can allocate unused locations in the vector address area as normal progr[...]

S3C8245/P8245/C8249/P8249 INTERRUPT STRUCTURE 5 - 5 Table 5-1. I nterrupt Vectors Vector Address Interrupt Source Request Reset/Clear Decimal Value Hex Value Interrupt Level Priority in Level H/W S/W 256 100H Basic timer overflow Reset – √ 226 E2 H Timer A overflow IRQ0 0 √ √ 224 E0 H Timer A match/capture 1 √ √ 228 E4 H Timer B match I[...]

INTERRUPT STRUCTURE S3C8245/P8245/C8249 /P8249 5- 6 ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI ) Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then serviced as they occur according to the established priorities. NOTE The system initialization routine executed after a reset must alwa[...]

S3C8245/P8245/C8249/P8249 INTERRUPT STRUCTURE 5 - 7 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. T he system-level control points in the interr upt structure are : — Global interrupt enable and disable (by EI and DI instructions or by direct m[...]

INTERRUPT STRUCTURE S3C8245/P8245/C8249 /P8249 5- 8 PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral (see Table 5-3). Table 5-3. Interrupt Source Control and Data Registers Interrupt Source Interrupt[...]

S3C8245/P8245/C8249/P8249 INTERRUPT STRUCTURE 5 - 9 SYSTEM MODE REGISTER (SYM ) The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to control fast interrupt processing (see Figure 5-5). A reset clears SYM.1, and SYM.0 to "0". The 3-bit value for fast interrupt level selection, SYM.4[...]

INTERRUPT STRUCTURE S3C8245/P8245/C8249 /P8249 5- 10 INTERRUPT MASK REGISTER (IMR ) The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine[...]

S3C8245/P8245/C8249/P8249 INTERRUPT STRUCTURE 5 - 11 INTERRUPT PRIORITY REGISTER (IPR ) The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be written to their re[...]

INTERRUPT STRUCTURE S3C8245/P8245/C8249 /P8249 5- 12 Interrupt Priority Register (IPR) FFH, Set 1, Bank 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB Group A: 0 = IRQ0 > IRQ1 1 = IRQ1 > IRQ0 Subgroup B: 0 = IRQ3 > IRQ4 1 = IRQ4 > IRQ3 Group C: 0 = IRQ5 > (IRQ6, IRQ7) 1 = (IRQ6, IRQ7) > IRQ5 Subgroup C: 0 = IRQ6 > IRQ7 1 = IRQ7 > IR[...]

S3C8245/P8245/C8249/P8249 INTERRUPT STRUCTURE 5 - 13 INTERRUPT REQUEST REGISTER (IRQ ) You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the same number: bit 0 to IRQ0, bit 1 to[...]

INTERRUPT STRUCTURE S3C8245/P8245/C8249 /P8249 5- 14 INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits: o ne type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared in the interrupt service routine. Pending Bits Cleared Auto[...]

S3C8245/P8245/C8249/P8249 INTERRUPT STRUCTURE 5 - 15 INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request bit to "1". 2. The CPU polling procedure identifies a pending condition for that source. 3. The CPU checks th[...]

INTERRUPT STRUCTURE S3C8245/P8245/C8249 /P8249 5- 16 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (00H–FFH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence: 1. Push the program counter's low-byte va[...]

S3C8245/P8245/C8249/P8249 INTERRUPT STRUCTURE 5 - 17 FAST INTERRUPT PROCESSING ( Continued) Two other system registers support fast interrupt processing: — The instruction pointer (IP) contains the starting address of the service routine (and is later used to swap the program counter values), and — When a fast interrupt occurs, the contents of [...]

INTERRUPT STRUCTURE S3C8245/P8245/C8249 /P8249 5- 18 NOTES[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 1 6 INSTRUCTION SET OVERVIEW The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the instruction set include: — A full complement of [...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 2 Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD dst,src Load LDB dst,src Load bit LDE dst,src Load external data memory LDC dst,src Load program memory LDED dst,src Load external data memory and decrement LDCD dst,src Load program memory and decrem[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 3 Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Arithmetic Instructions ADC dst,src Add with carry ADD dst,src Add CP dst,src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst,src Divide INC dst Increment INCW dst Increment word MULT dst,src[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 4 Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions BTJRF dst,src Bit test and jump relative on false BTJRT dst,src Bit test and jump relative on true CALL dst Call procedure CPIJE dst,src Compare, increment and jump on equal CPIJNE dst,src Compa[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 5 Table 6-1. Instruction Group Summary (Concluded) Mnemonic Operands Instruction Rotate and Shift Instructions RL dst Rotate left RLC dst Rotate left through carry RR dst Rotate right RRC dst Rotate right through carry SRA dst Shift right arithmetic SWAP dst Swap nibbles CPU Control Instructions CCF Com[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 6 FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and FLAGS.2 are used for BCD arithmetic. The FLAGS register also [...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 7 FLAG DESCRIPTIONS C Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register. Program instru[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 8 INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description C Carry flag Z Zero flag S Sign flag V Overflow flag D Decimal-adjust flag H Half-carry flag 0 Cleared to logic zero 1 Set to logic one * Set or cleared according to operation – Value is unaffected x Value is undefined Ta[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 9 Table 6-4. Instruction Notation Conventions Notation Description Actual Operand Range cc Condition code See list of condition codes in Table 6-6. r Working register only Rn (n = 0–15) rb Bit (b) of working register Rn.b (n = 0–15, b = 0–7) r0 Bit 0 (LSB) of working register Rn (n = 0–15) rr Wo[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 10 Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – 012345 6 7 U 0 DEC R1 DEC IR1 ADD r1,r2 ADD r1,Ir2 ADD R2,R1 ADD IR2,R1 ADD R1,IM BOR r0–Rb P 1 RLC R1 RLC IR1 ADC r1,r2 ADC r1,Ir2 ADC R2,R1 ADC IR2,R1 ADC R1,IM BCP r1.b, R2 P 2 INC R1 INC IR1 SUB r1,r2 SUB r1,Ir2 SUB R2,R1 SUB I[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 11 Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) – 8 9 AB CD E F U 0 LD r1,R2 LD r2,R1 DJNZ r1,RA JR cc,RA LD r1,IM JP cc,DA INC r1 NEXT P 1 ↓↓↓↓↓↓↓ ENTER P 2 EXIT E 3 WFI R 4 SB0 5 SB1 N 6 IDLE I 7 ↓↓↓↓↓↓↓ STOP B 8 DI B 9 EI L A RET E B IRET C[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 12 CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 13 INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction de[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 14 ADC — Add with carry ADC dst,src Operation: dst ← dst + src + c The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. In mu[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 15 ADD — Add ADD dst,src Operation: dst ← dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. Flags: C: Set if there is a carry from the most significant bit[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 16 AND — Logical AND AND dst,src Operation: dst ← dst AND src The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic [...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 17 BAND — Bit AND BAND dst,src.b BAND dst.b,src Operation: dst(0) ← dst(0) AND src(b) or dst(b) ← dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or source). The resultant bit is stored in the specified bit of th[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 18 BCP — Bit Compare BCP dst,src.b Operation: dst(0) – src(b) The specified bit of the source is compared to (subtracted from) bit zero (L SB) of the destination. The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffected by the comparison. F[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 19 BITC — Bit Complement BITC dst.b Operation: dst(b) ← NOT dst(b) This instruction complements the specified bit within the destination without affecting any other bits in the destination. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Cleared to "0". V[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 20 BITR — Bit Reset BITR dst.b Operation: dst( b) ← 0 The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst | b | 0 2 4 77 rb NOTE : In the second[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 21 BITS — Bit Set BITS dst.b Operation: dst(b) ← 1 The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst | b | 1 2 4 77 rb NOTE : In the second byte[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 22 BOR — Bit OR BOR dst,src.b BOR dst.b,src Operation: dst(0) ← dst(0) OR src(b) or dst(b) ← dst(b) OR src(0) The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source). The resulting bit value is stored in the specified bit of the[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 23 BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b Operation: If src(b) is a "0", then PC ← PC + dst The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statement whose addr[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 24 BTJRT — Bit Test, Jump Relative on True BTJRT dst,src.b Operation: If src(b) is a "1", then PC ← PC + dst The specified bit within the source operand is tested. If it is a "1", the relative address is added to the program counter and control passes to the statement whose addre[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 25 BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src Operation: dst(0) ← dst(0) XOR src(b) or dst(b) ← dst(b) XOR src(0) The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or source). The result bit is stored in the specified bit of [...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 26 CALL — Call Procedure CALL dst Operation: SP ← SP – 1 @SP ← PCL SP ← SP –1 @SP ← PCH PC ← dst The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The sp[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 27 CCF — Complement Carry Flag CCF Operation: C ← NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one. Flags: C: Complemented. No other flags are affected. Form[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 28 CLR — Clear CLR dst Operation: dst ← "0" The destination location is cleared to "0". Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 B0 R 4 B1 IR Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: CLR 00H [...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 29 COM — Complement COM dst Operation: dst ← NOT dst The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the resu[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 30 CP — Compare CP dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Set if a "borrow" occurred (src > dst); c[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 31 CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,RA Operation: If dst – src = "0", PC ← PC + RA Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter an[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 32 CPIJNE — Compare, Increment, and Jump on Non-Equal CPIJNE dst,src,RA Operation: If dst – src "0", PC ← PC + RA Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is not "0", the relative address is added to the program co[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 33 DA — Decimal Adjust DA dst Operation: dst ← DA dst The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed. (The operation is undefined[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 34 DA — Decimal Adjust DA (Continued) Example: Given: Working register R0 contains the value 15 (BCD), working register R1 contains 27 (BCD), and address 27H contains 46 (BCD): ADD R1,R0 ; C ← "0", H ← "0", Bits 4–7 = 3, bits 0–3 = C, R1 ← 3CH DA R1 ; R1 ← 3CH + 06 If a[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 35 DEC — Decrement DEC dst Operation: dst ← dst – 1 The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared other[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 36 DECW — Decrement Word DECW dst Operation: dst ← dst – 1 The contents of the destination location (whic h must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one. Flags: C: Unaffected. Z: Set if the result is "0";[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 37 DI — Disable Interrupts DI Operation: SYM (0) ← 0 Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 38 DIV — Divide (Unsigned) DIV dst,src Operation: dst ÷ src dst (UPPER) ← REMAINDER dst (LOWER) ← QUOTIENT The destination operand (16 bits) i s divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored in the up[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 39 DJNZ — Decrement and Jump if Non-Zero DJNZ r,dst Operation: r ← r – 1 If r ≠ 0, PC ← PC + dst The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control [...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 40 EI — Enable Interrupts EI Operation: SYM (0) ← 1 An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was set while interrupt processing wa[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 41 ENTER — Enter ENTER Operation: SP ← SP – 2 @SP ← IP IP ← PC PC ← @IP IP ← IP + 2 This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction point[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 42 EXIT — Exit EXIT Operation: IP ← @SP SP ← SP + 2 PC ← @IP IP ← IP + 2 This instruction is useful when imple menting threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loade[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 43 IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 44 INC — Increment INC dst Operation: dst ← dst + 1 The contents of the destination operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared oth[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 45 INCW — Increment Word INCW dst Operation: dst ← dst + 1 The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherw[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 46 IRET — Interrupt Return IRET IRET (Normal) IRET (Fast) Operation: FLAGS ← @SP PC ↔ IP SP ← SP + 1 FLAGS ← FLAGS' PC ← @SP FIS ← 0 SP ← SP + 2 SYM(0) ← 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. I[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 47 JP — Jump JP cc,dst (Conditional) JP dst (Unconditional) Operation: If cc is true, PC ← dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction [...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 48 JR — Jump Relative JR cc,dst Operation: If cc is true, PC ← PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction foll[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 49 LD — Load LD dst,src Operation: dst ← src The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src dst | opc src 2 4 rC r IM 4 r8 r R src | opc dst 2 4 r9 R r r = 0 to F[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 50 LD — Load LD (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: LD R0,#10H → R0 = 10H LD R0,01H → R0 = 20H, register 01H = 20H LD 01H,R0 → Register 01H = 01H, R0 = 01H LD R1,@R0 → R1 = 20H, R0 = 0[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 51 LDB — Load Bit LDB dst,src.b LDB dst.b,src Operation: dst(0) ← src(b) or dst(b) ← src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 52 LDC/LDE — Load Memory LDC/LDE dst,src Operation: dst ← src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes 'Irr' or 'rr' [...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 53[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 54 LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H: LDC R0,@RR2 ; R0 ← contents of [...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 55 LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src Operation: dst ← src rr ← rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The con[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 56 LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src Operation: dst ← src rr ← rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The conte[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 57 LDCPD/LDEPD — Load Memory with Pre-Decrement LDCPD/ LDEPD dst,src Operation: rr ← rr – 1 dst ← src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is firs[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 58 LDCPI/LDEPI — Load Memory with Pre-Increment LDCPI/ LDEPI dst,src Operation: rr ← rr + 1 dst ← src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first [...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 59 LDW — Load Word LDW dst,src Operation: dst ← src The contents of the source (a word) are loaded into the destination. The contents of the source are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc src dst 3 8 C4 RR RR 8 C5 RR IR opc dst src 4 8 C6[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 60 MULT — Multiply (Unsigned) MULT dst,src Operation: dst ← dst × src The 8-bit destination operand (even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address. Both operands are trea[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 61 NEXT — Next NEXT Operation: PC ← @ IP IP ← IP + 2 The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two. Flags: No fla[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 62 NOP — No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 FF Example: When the [...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 63 OR — Logical OR OR dst,src Operation: dst ← dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the correspo[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 64 POP — Pop From Stack POP dst Operation: dst ← @SP SP ← SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: No flags affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 8 50 R 8 5[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 65 POPUD — Pop User Stack (Decrementing) POPUD dst,src Operation: dst ← src IR ← IR – 1 This instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 66 POPUI — Pop User Stack (Incrementing) POPUI dst,src Operation: dst ← src IR ← IR + 1 The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 67 PUSH — Push To Stack PUSH src Operation: SP ← SP – 1 @SP ← src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack. Flags: N[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 68 PUSHUD — Push User Stack (Decrementing) PUSHUD dst,src Operation: IR ← IR – 1 dst ← src This instruction is used to address user-defined stacks in the register file. PUSHUD decreme nts the user stack pointer and loads the contents of the source into the register addressed by the decremented s[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 69 PUSHUI — Push User Stack (Incrementing) PUSHUI dst,src Operation: IR ← IR + 1 dst ← src This instruction is used for user-defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the increment[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 70 RCF — Reset Carry Flag RCF RCF Operation: C ← 0 The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 CF Example: Given: C = "1" or "0": The instruct[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 71 RET — Return RET Operation: PC ← @SP SP ← SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The nex[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 72 RL — Rotate Left RL dst Operation: C ← dst (7) dst (0) ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The co ntents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag. 7 0 C Flags: C: Se[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 73 RLC — Rotate Left Through Carry RLC dst Operation: dst (0) ← C C ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C); the initial value of the carry fla[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 74 RR — Rotate Right RR dst Operation: C ← dst (0) dst (7) ← dst (0) dst (n ) ← dst (n + 1), n = 0–6 The contents of the destinat ion operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C). 7 0 C Flags: C: Se[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 75 RRC — Rotate Right Through Carry RRC dst Operation: dst (7) ← C C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the initial value of the car[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 76 SB0 — Select Bank 0 SB0 Operation: BANK ← 0 The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 4F Examp[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 77 SB1 — Select Bank 1 SB1 Operation: BANK ← 1 The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not implemented in some S3C8-series microcontrollers.) Flags: No flags a[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 78 SBC — Subtract with Carry SBC dst,src Operation: dst ← dst – src – c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed [...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 79 SCF — Set Carry Flag SCF Operation: C ← 1 The carry flag (C) is set to logic one, regardless o f its previous value. Flags: C: Set to "1". No other flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 DF Example: The statement SCF sets the carry flag to logic one.[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 80 SRA — Shift Right Arithmetic SRA dst Operation: dst (7) ← dst (7) C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and [...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 81 SRP/SRP0/SRP1 — Set Register Pointer SRP src SRP0 src SRP1 src Operation: If src (1) = 1 and src (0) = 0 then: RP0 (3–7) ← src (3–7) If src (1) = 0 and src (0) = 1 then: RP1 (3–7) ← src (3–7) If src (1) = 0 and src (0) = 0 then: RP0 (4–7) ← src (4–7), RP0 (3) ← 0 RP1 (4–7) ←[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 82 STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and syste m clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 83 SUB — Subtract SUB dst,src Operation: dst ← dst – src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the d[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 84 SWAP — Swap Nibbles SWAP dst Operation: dst (0 – 3) ↔ dst (4 – 7) The contents of the lower four bits and upper four bits of the destination operand are swapped. 7 0 4 3 Flags: C: Undefined. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared o[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 85 TCM — Test Complement Under Mask TCM dst,src Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). The TCM sta[...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 86 TM — Test Under Mask TM dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the desti[...]

S3C8245/P8245/C8249/P8249 INSTRUCTION S ET 6- 87 WFI — Wait for Interrupt WFI Operation: The CPU is effectively halted until an interrupt oc curs, except that DMA transfers can still take place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrupt . Flags: No flags are affected. Format: Bytes [...]

INSTRUCTION SET S3C8245/ P8245/C8249/P8249 6- 88 XOR — Logical Exclusive OR XOR dst,src Operation: dst ← dst XOR src The so urce operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in t[...]

S3C8245/P8245/C8249/P8249 CLOCK CIRCUIT 7- 1 7 CLOCK CIRCUIT OVERVIEW The clock frequency generated for the S3C8245/C8249 by an external crystal can range from 1 MHz to 10 MHz. The maximum CPU clock frequency is 10 MHz. The X IN and X OUT pins connect the external oscillator or clock source to the on-chip clock circuit. SYSTEM CLOCK CIRCUIT The sys[...]

CLOCK CIRCUIT S3C8245/P8245/C8249 /P8249 7- 2 C LOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: — In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator is started, by a reset operation or an external interrupt (with RC delay noise filter) ,[...]

S3C8245/P8245/C8249/P8249 CLOCK CIRCUIT 7- 3 SYSTEM CLOCK CONTROL REGISTER (CLKCON ) The system clock control register, CLKCON , is located in the bank 0 of set 1, address D4H. It is read/write addressable and has the following functions: — Oscil lator frequency divide-by value After the main oscillator is activated, and the fxx/16 (the slowest c[...]

CLOCK CIRCUIT S3C8245/P8245/C8249 /P8249 7- 4 Oscillator Control Register (OSCCON) F3H, Set 1, bank 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB Not used System clock selection bit: 0 = Main oscillator select 1 = Subsystem oscillator select Not used Subsystem oscillator control bit: 0 = Subsystem oscillator RUN 1 = Subsystem oscillator STOP Mainsystem os[...]

S3C8245/P8245/C8249/P8249 n RESET and POWER-DOWN 8- 1 8 nRESET a nd POWER-DOWN SYSTEM n RESET OVERVIEW During a power-on reset, the voltage at V DD goes to High level and the n RESET pin is forced to Low level. The n RESET signal is input through a s chmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings the [...]

n RESET and POWER-DOWN S3C8245/P8245/C8249 /P8249 8- 2 HARDWARE n RESET VALUES Table 8-1 , 8-2, 8-3 list the reset values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation. The following notation is used to represent reset values: — A "1" or a "0" shows the re[...]

S3C8245/P8245/C8249/P8249 n RESET and POWER-DOWN 8- 3 Table 8 - 2 . S3C8245/C8249 Set 1, Bank 0 Register Values after n RESET Register Name Mnemonic Address Bit Values a fter n RESET Dec Hex 76543210 Port 0 Control High Register P0CONH 224 E0H 00000000 Port 0 Control Low Register P0CONL 225 E1H 00000000 Port 0 interrupt Control Register P0INT 226 E[...]

n RESET and POWER-DOWN S3C8245/P8245/C8249 /P8249 8- 4 Table 8 - 3 . S3C8245/P8245 Set 1, Bank 1 Register Values after n RESET Register Name Mnemonic Address Bit Values a fter n RESET Dec Hex 76543210 Port 4 control High register P4CONH 236 ECH 00000000 Port 4 control Low register P4CONL 237 EDH 00000000 Port 5 Control High Register P5CONH 238 EEH [...]

S3C8245/P8245/C8249/P8249 n RESET and POWER-DOWN 8- 5 POWER-DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than 3 µ A. All system functions stop when the clock ?[...]

n RESET and POWER-DOWN S3C8245/P8245/C8249 /P8249 8- 6 IDLE MODE Idle mode is i nvoked by the instruction IDLE (opcode 6FH). In idle mode, CPU operations are halted while some peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU, but all peripherals timers remain active. Port pins retain the mode (input [...]

S3C8245/P8245/C8249/P8249 I/O PORTS 9- 1 9 I/O PORTS OVERVIEW The S3C8245/C8249 microcontroller has two nibble-programmable and four bit-programmable I/O ports , P0–P5. The port 3 is a 5-bit port and the others are 8-bit ports. This gives a total of 45 I/O pins . Each port can be flexibly configured to meet a pplication design requirements. The C[...]

I/O PORTS S3C8245/P 8245/C8249/P8249 9- 2 PORT DATA REGISTERS Table 9-2 gives you an overview of t he register locations of all four S3C8245/C8249 I/O port data registers. Data registers for ports 0 , 1, 2, 3, 4, and 5 have the general format shown in Figure 9-1 . Table 9-2. Port Data Register Summary Register Name Mnemonic Decimal Hex Location R/W[...]

S3C8245/P8245/C8249/P8249 I/O PORTS 9- 3 PORT 0 Port 0 is an 8-bit I/O Port that you can use two ways: — General-purpose I/O — External interrupt inputs for INT0–INT7 Port 0 is accessed directly by writing or reading the port 0 data register, P0 at location F6H in set 1, bank 0. Port 0 Control Register (P0CONH, P0CONL) Port 0 pins are configu[...]

I/O PORTS S3C8245/P 8245/C8249/P8249 9- 4 Port 0 Control Register, High Byte (P0CONH) E0H, Set 1, Bank 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P0.7 (INT7) P0.6 (INT6) P0.5 (INT5) P0.4 (INT4) P0CONH bit-pair pin configuration: 00 01 10 11 Schmitt trigger input mode, pull-up, interrupt on falling edge Schmitt trigger input mode, interrupt on rising ed[...]

S3C8245/P8245/C8249/P8249 I/O PORTS 9- 5 Port 0 Interrupt Control Register (P0INT) E2H, Set 1, Bank 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P0INT bit configuration settings: 0 1 Interrupt Disable INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 Interrupt Enable Figure 9-3. Port 0 Interrupt Control Register (P0INT) Port 0 Interrupt Pending Register (P0PND) E3[...]

I/O PORTS S3C8245/P 8245/C8249/P8249 9- 6 PORT 1 Port 1 is an 8-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading the port 1 data register, P1 at location F7H in set 1, bank 0. P1.0–P1.7 can serve inputs, as outputs (push pull or open-drain) or you can configure the following alternative fun[...]

S3C8245/P8245/C8249/P8249 I/O PORTS 9- 7 Port 1 Control Register, Low Byte (P1CONL) E5H, Set 1, Bank 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P1.3 P1CONL bit-pair pin configuration settings: 00 01 10 11 Alternative function (T1OUT, T1PWM, other pins are push-pull are push-pull output mode) Output mode, push-pull P1.2/T1OUT /T1PWM P1.1/T1CLK P1.0/T1CA[...]

I/O PORTS S3C8245/P 8245/C8249/P8249 9- 8 PORT 2 Port 2 is an 8-bit I/O port that can be used for general-purpose I/O as A/D converter inputs, ADC0–ADC7. The pins are accessed directly by writing or reading the port 2 data register, P2 at location F8H in set 1, bank 0. To individually configure the port 2 pins P2.0–P2.7, you make bit-pair setti[...]

S3C8245/P8245/C8249/P8249 I/O PORTS 9- 9 Port 2 Control Register,Low Byte (P2CONL) E7H, Set 1, Bank 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P2.2 (ADC2) P2.1 (ADC1) P2.0 (ADC0) P2CONL bit-pair pin configuration: 00 01 10 11 Alternative function (ADC mode) Output mode, push-pull Input mode, pull-up NOTE: If a pin is enabled for ADC mode by ADCEN, norm[...]

I/O PORTS S3C8245/P 8245/C8249/P8249 9- 10 PORT 3 Port 3 is an 5-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading the port 3 data register, P3 at location F9H in set 1, bank 0. P3.0–P3.3 can serve as inputs (with or without pull-ups), as push-pull outputs, or you can configure the following[...]

S3C8245/P8245/C8249/P8249 I/O PORTS 9- 11 Port 3 Control Register, Low Byte (P3CONL) E9H, Set 1, Bank 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P3.2/TACLK P3.1/TAOUT/ TAPWM P3.0/TBPWM P3CONL bit-pair pin configuration settings: 00 01 10 11 Alternative function (TAOUT,TAPWM, TBPWM P3.2, P3.3 is push-pull output mode) Output mode, push-pull Input mode, [...]

I/O PORTS S3C8245/P 8245/C8249/P8249 9- 12 PORT 4 Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or reading the port 4 data register, P4 at location FAH in set 1, bank 0. P4.0–P4.7 can serve as inputs (with or without pull- ups), as output (open drain or push-pull). And, they can serv[...]

S3C8245/P8245/C8249/P8249 I/O PORTS 9- 13 Port 4 Control Register, Low Byte (P4CONL) EDH, Set 1, Bank 1, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P4.2/SEG18 P4.1/SEG17 P4.0/SEG16 P4CONL bit-pair pin configuration settings: 00 01 10 11 Output mode, push-pull Input mode, pull-up P4.3/SEG19 Input mode Opendrain output mode NOTE: If LCD is enabled by LCON.4[...]

I/O PORTS S3C8245/P 8245/C8249/P8249 9- 14 PORT 5 Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading the port 5 data register, P5 at location FBH in set 1, bank 0. P5.0–P5.7 can serve as inputs (with without pull-ups), as output (open drain or push-pull). And, they can serve as[...]

S3C8245/P8245/C8249/P8249 I/O PORTS 9- 15 Output mode, push-pull Port 5 Control Register, Low Byte (P5CONL) EFH, Set 1, Bank 1, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P5.2/SEG26 P5.1/SEG25 P5.0/SEG24 P5CONL bit-pair pin configuration settings: 00 01 10 11 Input mode, pull-up P5.3/SEG27 Input mode Opendrain output mode NOTE: If LCD is enabled by LCON.6[...]

I/O PORTS S3C8245/P 8245/C8249/P8249 9- 16 NOTES[...]

S3C8245/P8245/C8249/P8249 BASIC TIMER 10- 1 10 BASIC TIMER OVERVIEW S3C8245/C8249 has an 8-bit basic timer . BASIC TIMER (BT) You can use the basic timer (BT) in two different ways: — As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction, or — To signal t he end of the required oscillation stabilizatio[...]

BASIC TIMER S3C8245/P8245/C824 9/P8249 10- 2 Basic TImer Control Register (BTCON) D3H, Set 1, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB Divider clear bit: 0 = No effect 1= Clear dvider Basic timer counter clear bit: 0 = No effect 1= Clear BTCNT Basic timer input clock selection bits: 00 = f XX /4096 01 = f XX /1024 10 = f XX /128 11 = f XX /16 Watchdog t[...]

S3C8245/P8245/C8249/P8249 BASIC TIMER 10- 3 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than " 1010B " . (The " 1010B " value disables the watchdog function.) A reset clears BTCON to " 00H[...]

BASIC TIMER S3C8245/P8245/C824 9/P8249 10- 4 NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows). MUX f XX /4096 DIV f XX /1024 f XX /128 f XX /16 f XX Bits 3, 2 Bit 0 Basic Timer Control Register (Write '1010xxxxB' to Disable) C[...]

S3C8245/P8245/C8249/P8249 8-BIT TIMER A /B 11- 1 11 8-BIT TIMER A/B 8-BIT TIMER A OVERVIEW The 8-bit timer A is an 8-bit general-purpose timer/counter. Timer A has three operating modes, one of which you select using the appropriate TACON setting: — Interval timer mode (Toggle output at TAOUT pin) — Capture input mode with a rising or falling e[...]

8-BIT TIMER A/B S3 C8245/P8245/C8249/P8249 11- 2 FUNCTION DESCRIPTION Timer A Interrupts (IRQ0, Vectors E0H and E2H) The timer A module can generate two interrupts: the timer A overflow interrupt (TAOVF), and the timer A match/ capture interrupt (TAINT). TAOVF is interrupt level IRQ0, vector E2H. TAINT also belongs to interrupt level IRQ0, but is a[...]

S3C8245/P8245/C8249/P8249 8-BIT TIMER A /B 11- 3 TIMER A CONTROL REGISTER (TACON) You use the timer A control register, TACON, to — Select the timer A operating mode (interval timer, capture mode, or PWM mode) — Select the timer A input clock frequency — Clear the timer A counter, TACNT — Enable the timer A overflow interrupt or timer A mat[...]

8-BIT TIMER A/B S3 C8245/P8245/C8249/P8249 11- 4 BLOCK DIAGRAM Timer A Data Register (Read/Write) Timer A Buffer Reg 8-bit Comparator 8-bit Up-Counter (Read Only) Clear Match TACON.7-.6 f XX /1024 f XX /256 f XX /64 TACLK TACON.2 Pending TACON.3 M U X Overflow TAOVF M U X M U X TACAP TAINT TACON.1 TAOUT TAPWM TACON.0 Pending TACON.5.4 TACON.5.4 Dat[...]

S3C8245/P8245/C8249/P8249 8-BIT TIMER A /B 11- 5 8-BIT TIMER B OVERVIEW The S3C8245/C8249 micro-controller has an 8-bit counter called timer B. Timer B, which can be used to generate the carrier frequency of a remote controller signal. Pending condition of timer B is cleared automatically by hardware. Timer B has two functions: — As a normal inte[...]

8-BIT TIMER A/B S3C 8245/P8245/C8249/P8249 11- 6 Timer B Control Register (TBCON) ECH, Set 1, Bank 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB Timer B mode selection bit: 0 = One-shot mode 1 = Repeating mode Timer B output flip-flop control bit: 0 = TBOF is low 1 = TBOF is high Timer B start/stop bit: 0 = Stop timer B 1 = Start timer B Timer B interrupt[...]

S3C8245/P8245/C8249/P8249 8-BIT TIMER A/B 11- 7 TIMER B PULSE WIDTH CALCULATIONS t LOW t HIGH t LOW To generate the above repeated waveform consisted of low period time, t LOW , and high period time, t HIGH . When TBOF = 0, t LOW = (TBDATAL + 2) x 1/fx, 0H < TBDATAL < 100H, where fx = The selected clock. t HIGH = (TBDATAH + 2) x 1/fx, 0H <[...]

8-BIT TIMER A/B S3C 8245/P8245/C8249/P8249 11- 8 Timer B Clock 0H TBOF = '0' TBDATAL = 01-FFH TBDATAH = 00H TBOF = '0' TBDATAL = 00H TBDATAH = 01-FFH TBOF = '0' TBDATAL = 00H TBDATAH = 00H TBOF = '1' TBDATAL = 00H TBDATAH = 00H Low High Low High Timer B Clock TBOF = '1' TBDATAL = DEH TBDATAH = 1EH T[...]

S3C8245/P8245/C8249/P8249 8-BIT TIMER A/B 11- 9 F PROGRAMMING TIP — To generate 38 kHz, 1/3duty signal through P3.0 This example sets Timer B to the repeat mode, sets the oscillation frequency as the Timer B clock source, and TBDATAH and TBDATAL to make a 38 kHz,1/3 Duty carrier frequency. The program parameters are: 17.59 µ s 37.9 kHz 1/3 Duty [...]

8-BIT TIMER A/B S3C 8245/P8245/C8249/P8249 11- 10 F PROGRAMMING TIP — To generate a one pulse signal through P3.0 This example sets Timer B to the one shot mode, sets the oscillation frequency as the Timer B clock source, and TBDATAH and TBDATAL to make a 40 µ s width pulse. The program parameters are: 40 µ s — Timer B is used in one shot mod[...]

S3C8245/P8245/C8249/P8249 16-BIT TIMER 0/1 12- 1 12 16-BIT TIMER 0/ 1 16-BIT TIMER 0 OVERVIEW The 16-bit timer 0 is an 16-bit general-purpose timer. Timer 0 has the interval timer mode by using the appropriate T0CON setting. Timer 0 has the following functional components: — Clock frequency divider (fxx d ivided by 256, 64, 8 or 1) with multiplex[...]

16-BIT TIMER 0/1 S 3C8245/P8245/C8249/P8249 12- 2 TIMER 0 CONTROL REGISTER (T0CON) You use the timer 0 control register, T0CON, to — Enable the timer 0 operating (interval timer) — Select the timer 0 input clock frequency — Clear the timer 0 counter, T0CNT — Enable the timer 0 interrupt and clear timer 0 interrupt pending condition T0CON is[...]

S3C8245/P8245/C8249/P8249 16-BIT TIMER 0/1 12- 3 BLOCK DIAGRAM Timer 0 Data H/L Reg (Read/Write) Timer 0 Buffer Reg 16-bit Comparator 16-bit up-Counter H/L (Read Only) Match Bit 3 T0INT Counter clear signal (T0CON.3) Bits 7, 6, 5 M U X fxx/256 fxx/64 fxx/8 fxx/1 TBOF Bit 2 Clear Bit 0 Bit 1 IRQ2 Pending R Data Bus 8 Data Bus 8 NOTES: 1. To be loade[...]

16-BIT TIMER 0/1 S 3C8245/P8245/C8249/P8249 12- 4 Timer 0 Counter Register, High-Byte (T0CNTH) F2H, Set 1, Bank 1, R .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB Reset Value: 00H Timer 0 Counter Register, Low-Byte (T0CNTL) F3H, Set 1, Bank 1, R .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB Reset Value: 00H Figure 12-3. Timer 0 Counter Register (T0CNTH/L) Timer 0 Data Registe[...]

S3C8245/P8245/C8249/P8249 16-BIT TIMER 0/1 12- 5 16-BIT TIMER 1 OVERVIEW The 16-bit timer 1 is an 16-bit general-purpose timer/counter. Timer 1 has three operating modes, one of which you select using the appropriate T1CON setting: — Interval t imer mode (Toggle output at T1OUT pin) — Capture input mode with a rising or falling edge trigger at [...]

16-BIT TIMER 0/1 S 3C8245/P8245/C8249/P8249 12- 6 FUNCTION DESCRIPTION Timer 1 Interrupts (IRQ3, Vectors E8H and EAH) The timer 1 module can generate two interrupts, the timer 1 overflow interrupt (T1OVF), and the timer 1 match/capture interrupt (T1INT). T1OVF is interrupt level IRQ3, vector EAH. T1INT also belongs to interrupt level IRQ3, but is a[...]

S3C8245/P8245/C8249/P8249 16-BIT TIMER 0/1 12- 7 TIMER 1 CONTROL REGISTER (T1CON) You use the timer 1 control register, T1CON, to — Select the timer 1 operating mode (interval timer, capture mode, or PWM mode) — Select the timer 1 input clock frequency — Clear the timer 1 counter, T1CNTH/L — Enable the timer 1 overflow interrupt or timer 1 [...]

16-BIT TIMER 0/1 S 3C8245/P8245/C8249/P8249 12- 8 BLOCK DIAGRAM Timer 1 Data H/L Register Timer 1 Buffer Reg 16-bit Comparator 16-bit Up-Counter (Read Only) Counter Clear Signal or Match Clear Match T1CON.7-5 f XX /1024 f XX /8 f XX /256 f XX /64 f XX /1 T1OVF IRQ3 T1CON.0 OVF Pending T1CON.2 T1INT IRQ3 Pending T1CON.1 T1OUT T1PWM T1CON.4-.3 R M U [...]

S3C8245/P8245/C8249/P8249 16-BIT TIMER 0/1 12- 9 Timer 1 Counter Register, High-Byte (T1CNTH) FCH, Set 1, Bank 1, R MSB LSB Reset Value: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 LSB Timer 1 Counter Register, Low-Byte (T1CNTL) FDH, Set 1, Bank 1, R Reset Value: 00H Figure 12-7. Timer 1 Control Register (T1CNTH/L) .7 .6 .5 .4 .3 .2 .1 [...]

16-BIT TIMER 0/1 S 3C8245/P8245/C8249/P8249 12- 10 NOTES[...]

S3C8245/P8245/C8249/P8249 WATCH TIMER 13- 1 13 WATCH TIMER OVERVIEW Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To start watch timer operation, set bit1 and bit 6 of the watch timer mode register, WTCON.1and 6, to “1”. After the watch timer starts and elapses a time, the watch tim[...]

WATCH TIMER S3C8245 /P8245/C8249/P8249 13- 2 WATCH TIMER CONTROL REGISTER (WTCON: R/W) FBH WTCON.7 WTCON.6 WTCON.5 WTCON.4 WTCON.3 WTCON.2 WTCON.1 WTCON.0 nRESET "0" "0" "0" "0" "0" "0" "0" "0" Table 13-1. Watch Timer Control Register (WTCON): Set 1, Bank 1, FAH, R/W Bi[...]

S3C8245/P8245/C8249/P8249 WATCH TIMER 13- 3 WATCH TIMER CIRCUIT DIAGRAM WTCON.1 WTCON.2 WTCON.3 WTCON.4 WTCON.5 Enable/Disable Selector Circuit MUX WTCON.0 WTINT WTCON.6 BUZZER Output f W /2 14 f W /2 13 f W /2 12 f W /2 6 f W /64 (0.5 kHz) f W /32 (1 kHz) f W /16 (2 kHz) f W /8 (4 kHz) 1 Hz f xx = Main System Clock (4.19 MHz) f x t = Subsystem Clo[...]

WATCH TIMER S3C8245 /P8245/C8249/P8249 13- 4 NOTES[...]

S3C8245/P8245/C8249/P8249 LCD CONTROLL ER/DRIVER 14- 1 14 LCD CONTROLLER/DRIVER OVERVIEW The S3C8245/C8249 micro-controller can directly drive an up-to-16-digit (32-segment) LCD panel. The LCD module has the following components: — LCD controller/driver — Display RAM (00H–0FH) for storing display data in page 4 — 32 segment output pins (SEG[...]

LCD CONTROLLER/DRIVER S3C8245/P8245/C8249 /P8249 14- 2 LCD CIRCUIT DIAGRAM COM2 COM0 COM3 LMOD LCON Timing Controller 05H.1 05H.0 04H.7 04H.6 00H.3 00H.2 00H.1 00H.0 OFH.4 OFH.5 OFH.6 OFH.7 MUX MUX MUX 8 8 8 8 8 f LCD COM Control COM1 V LC0 V LC1 V LC2 CA CB SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG0 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 Segment Driver[...]

S3C8245/P8245/C8249/P8249 LCD CONTROLLE R/DRIVER 14- 3 LCD RAM ADDRESS AREA RAM addresses 00H - 0FH of page 4, or page 2, according to ROM size, are used as LCD data memory. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off. Display RAM data are sen[...]

LCD CONTROLLER/DRIVER S3C8245/P8245/C8249 /P8249 14- 4 LCD CONTROL REGISTER (LCON), D0H Table 14-1. LCD Control Register (LCON) Organization LCON Bit Setting Description LCON.7 0 P5.4–P5.7 I/O is selected 1 SEG28–SEG31 is selected, P5.4–P5.7 I/O is disabled LCON.6 0 P5.0–P5.3 I/O is selected 1 SEG24–SEG27 is selected, P5.0–P5.3 I/O is d[...]

S3C8245/P8245/C8249/P8249 LCD CONTROLLE R/DRIVER 14- 5 LCD MODE REGISTER (LMOD) The LCD mode control register LMOD is mapped to RAM addresses D1H. LMOD controls these LCD functions: — Duty and bias selection (LMOD.3–LMOD.0) — LCDCK clock frequency selection (LMOD.5–LMOD.4) The LCD clock signal, LCDCK, determines the frequency of COM signal [...]

LCD CONTROLLER/DRIVER S3C8245/P8245/C8249 /P8249 14- 6 Table 14-4. LCD Mode Control Register (LMOD) Organization, D1H LMOD.7 Always logic zero. LMOD.6 Always logic zero. LMOD.5 LMOD.4 LCD Clock (LCDCK) Frequency 0 0 32.768 kHz watch timer clock (fw)/2 9 = 64 Hz 0 1 32.768 kHz watch timer clock (fw)/2 8 = 128 Hz 1 0 32.768 kHz watch timer clock (fw)[...]

S3C8245/P8245/C8249/P8249 LCD CONTROLLE R/DRIVER 14- 7 LCD DRIVE VOLTAGE The LCD display is turned on only when the voltage difference between the common and segment signals is greater than V LCD . The LCD display is turned off when the difference between the common and segment signal voltages is less than V LCD. The turn-on voltage, + V LCD or - V[...]

LCD CONTROLLER/DRIVER S3C8245/P8245/C8249 /P8249 14- 8 FR Select Non-Select 1 Frame COM V LC1, 2 V LC 0 V ss SEG V ss COM-SEG V ss -V LC 0 -V LC1, 2 V LC1, 2 V LC 0 V LC1, 2 V LC 0 Figure 14-5. Select/No-Select Bias Signals in 1/2 Duty, 1/2 Bias Display Mode FR Select Non-Select 1 Frame SEG COM COM-SEG V LC 2 V SS V LC 2 V SS V LC 2 V SS -V LC 2 Fi[...]

S3C8245/P8245/C8249/P8249 LCD CONTROLLE R/DRIVER 14- 9 FR 1 Frame COM0 COM1 SEG0 SEG1 COM0 -SEG0 COM0 -SEG1 COM1 -SEG0 COM1 -SEG1 0 1 0 1 NOTE: V LC1 = V LC0 SEG1 SEG2 SEG3 SEG0 SEG3.1 x C1 .0 .1 .2 .3 1 0 X X 1 1 X X .4 .5 .6 .7 0 1 X X .0 .1 .2 .3 1 0 X X .4 .5 .6 .7 Data Register page 4, address 00H LD 00H, #31h Data Register page 4, address 01H[...]

LCD CONTROLLER/DRIVER S3C8245/P8245/C8249 /P8249 14- 10 COM0 COM1 SEG0 SEG1 COM0 -SEG0 COM0 -SEG1 COM1 -SEG0 COM1 -SEG1 COM2 V LC2 V SS V LC1 V LC0 V LC2 V SS V LC1 V LC0 V LC2 V SS V LC1 V LC0 V LC2 V SS V LC1 V LC0 V LC2 V SS V LC1 V LC0 FR 1 Frame 0 1 2 0 1 2 SEG1.6 x C2 SEG2.1 x C1 SEG2.0 x C0 SEG0.0 x C0 SEG2.1 x C1 SEG1.4 x C0 SEG0.2 x C2 SEG[...]

S3C8245/P8245/C8249/P8249 LCD CONTROLLE R/DRIVER 14- 11 1 Frame 0 1 2 3 1 2 V LC2 V SS V LC1 V LC0 V LC2 V SS V LC1 V LC0 COM0 COM1 COM3 SEG0 COM0 -SEG0 COM0 -SEG1 COM1 -SEG1 COM2 FR 0 3 V LC2 V SS V LC1 V LC0 V LC2 V SS V LC1 V LC0 V LC2 -V LC1 V LC1 V LC0 V SS -V LC0 -V LC2 V LC2 -V LC1 V LC1 V LC0 V SS -V LC0 -V LC2 V LC2 -V LC1 V LC1 V LC0 V SS[...]

LCD CONTROLLER/DRIVER S3C8245/P8245/C8249 /P8249 14- 12 LCD VOLTAGE DRIVING METHOD By Voltage Booster For run the voltage booster — Make enable the watch timer for f booster — Set LCON.2 to "0" and LCON.1 to "1" for make enable voltage booster — Recommendable capacitance value is 0.1 uF (CAB, C0, C1, C2) By Voltage Dividin[...]

S3C8245/P8245/C8249/P8249 A/D CONVERTER 15- 1 15 10-BIT ANALOG-TO-DIGITAL CONVERTER OVERVIEW The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10 -bit digital values. The a nalog input level must lie between the AV REF and AV SS values. The A/[...]

A/D CONVERTER S3C8 245/P8245/C8249/P8249 15- 2 CONVERSION TIMING The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: When fxx/8 is selected for conversion clock with an 8 MHz fxx clock frequency, one clock[...]

S3C8245/P8245/C8249/P8249 A/D CONVERTER 15- 3 A/D Converter Data Register, High Byte (ADDATAH) F8H, Set 1, Bank 1, Read Only .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB A/D Converter Data Register, Low Byte (ADDATAL) F9H, Set 1, Bank 1, Read Only .1 .0 MSB LSB Figure 15-2. A/D Converter Data Register (ADDATAH/L) INTERNAL REFERENCE VOLTAGE LEVELS In the ADC fun[...]

A/D CONVERTER S3C8 245/P8245/C8249/P8249 15- 4 BLOCK DIAGRAM Input Pins ADC0-ADC7 (P2.0-P2.7) Clock Selector Conversion Result (ADDATAH/L F8, F9H, Set 1, Bank 1) - + Upper 8-bit is loaded to A/D Conversion Data Register To ADCON.3 (EOC Flag) Successive Approximation Logic & Register AV REF AV SS Analog Comparator 10-bit D/A Converter M U X ADCO[...]

S3C8245/P8245/C8249/P8249 A/D CONVERTER 15- 5 NOTE: The symbol "R" signifies an offset resistor with a value of from 50 Ω to 100 Ω . If this resistor is omitted, the absolute accuracy will be maximum of 3 LSBs. V SS S3C8245/C8249 ADC0-ADC7 AV REF Reference Voltage Input Analog Input Pin R V DD V DD 10 pF 103 C 101 C + - Figure 15-4. R[...]

A/D CONVERTER S3C8 245/P8245/C8249/P8249 15- 6 NOTES[...]

S3C8245/P8245/C8249/P8249 SERIAL I/O INTERFACE 1 6- 1 16 SERIAL I/O INTERFACE OVERVIEW Serial I/O module, SIO can interface with various types of external device that require serial data transfer. The components of each SIO function block are: — 8-bit control register (S IOCON ) — Clock selector logic — 8-bit data buffer (SIODATA) — 8-bit p[...]

SERIAL I/O INTERFACE S3C8245/P8245/C824 9/P8249 1 6- 2 SIO CONTROL REGISTER (SIOCON) The control register for serial I/O interface module, SIOCON, is located at F0H in set 1, bank 0. It has the control settings for SIO module. — Clock source selection (internal or external) for shift clock — Interrupt enable — Edge selection for shift operati[...]

S3C8245/P8245/C8249/P8249 SERIAL I/O INTERFACE 1 6- 3 SIO PRE-SCALER REGISTER (SIOPS) The control register for serial I/O interface module, SIOPS, is located at F2H in set 1, bank 0. The value stored in the SIO pre-scale registers, SIOPS, lets you determine the SIO clock rate (baud rate) as follows: Baud rate = Input clock (fxx/4)/(Pre-scaler value[...]

SERIAL I/O INTERFACE S3C8245/P8245/C824 9/P8249 1 6- 4 SERIAL I/O TIMING DIAGRAM SO Transmit Complete IRQS Set SIOCON.3 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SI SCK Figure 16-4 . Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0) IRQS DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SCK[...]

S3C8245/P8245/C8249/P8249 VOLTAGE BOOST ER 17- 1 17 VOLTAGE BOOSTER OVERVIEW This voltage booster works for the power control of LCD : generates 3 × V R (V LC2 ), 2 × V R (V LC1 ), 1 × V R (V LC0 ). This voltage booster allows low voltage operation of LCD display with high quality. This voltage booster circuit provides constant LCD contrast leve[...]

VOLTAGE BOOSTER S3C8245/P8245/C8249/P8249 17- 2 BLOCK DIAGRAM V DD Clock LCON.0 LCON.2 Voltage Regulator V SS V LC0 (V R ) CAB CAB V LC1 (2 x V R ) V LC2 (3 x V R ) C0 C1 C2 LCON.1 Figure 17-1. Voltage Booster Block Diagram LCD Drive V LC1 V LC2 Voltage Booster V LC2 Voltage Regulator (1.5 V) V LC0 COM0-3 SEG0-SEG31 CA CB CAB C2 C1 V LC1 C0 V LC0 L[...]

S3C8245/P8245/C8249/P8249 VOLTAGE LEVEL DETEC TOR 18 - 1 18 VOLTAGE LEVEL DETECTOR OVERVIEW The S3C8245/C8249 micro-controller has a built-in VLD (Voltage Level Detector) circuit which allows detection of power voltage drop or external input level through software. Turning the VLD operation on and off can be controlled by software. Because the IC c[...]

VOLTAGE LEVEL DETECTOR S3C8245/P8245/C8249/P8249 18 - 2 VOLTAGE LEVEL DETECTOR CONTROL REGISTER (VLDCON) The bit 2 of VLDCON controls to run or disable the operation of Voltage level detect. Basically this V VLD is set as 2.2 V by system reset and it can be changed in 4 kinds voltages by selecting Voltage Level Detect Control register (VLDCON). Whe[...]

S3C8245/P8245/C8249/P8249 ELECTRICAL DA TA 19- 1 19 ELECTRICAL DATA OVERVIEW In this chapter, S3C8245/C8249 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — Input/output capacitance — D. C. electrical characteristics — A.C. electrical characterist[...]

ELECTRICAL DATA S3C 8245/P8245/C8249/P8249 19- 2 Table 19-1. Absolute Maximum Ratings (T A = 25 ° C) Parameter Symbol Conditions Rating Unit Supply voltage V DD – 0.3 to +6.5 V Input voltage V I – 0.3 to V DD + 0.3 Output voltage V O – 0.3 to V DD + 0.3 Output current high I OH One I/O pin active – 18 mA All I/O pins active – 60 Output c[...]

S3C8245/P8245/C8249/P8249 ELECTRICAL DA TA 19- 3 Table 19-2. D.C. Electrical Characteristics (Continued) (T A = -25 ° C to + 85 ° C, V DD = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Output high voltage V OH V DD = 5 V; I OH = -1 mA All output pins V DD –1.0 – – V Output low voltage V OL V DD = 5 V; I OL = 2 mA All output [...]

ELECTRICAL DATA S3C 8245/P8245/C8249/P8249 19- 4 NOTE: Low leakage current is absolute value.[...]

S3C8245/P8245/C8249/P8249 ELECTRICAL DA TA 19- 5 Table 19-2. D.C. Electrical Characteristics (Concluded) (T A = -25 ° C to + 85 ° C, V DD = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Supply current (1) I DD1 (2) V DD = 5 V ± 10 % 10 MHz crystal oscillator – 12 25 mA 3 MHz crystal oscillator 4 10 V DD = 3 V ± 10 % 10 MHz crys[...]

ELECTRICAL DATA S3C 8245/P8245/C8249/P8249 19- 6 In case of S3C8245, the characteristic of V OH and V OL is differ with the characteristic of S3C8249 like as following. Other characteristics are same each other. Table 19-3. D.C Electrical Characteristics of S3C8245 (T A = -25 ° C to +85 ° C, V DD = 1.8 V to 5.5 V) Parameter Symbol Conditions Min [...]

S3C8245/P8245/C8249/P8249 ELECTRICAL DA TA 19- 7 Table 19-4. A.C. Electrical Characteristics (T A = -25 ° C to +85 ° C, V DD = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Interrupt input high, low width (P0.0–P0.7) tINTH, tINTL P0.0–P0.7, V DD = 5 V ––– ns nRESET input low width tRSL V DD = 5 V 5–– us NOTE : User mu[...]

ELECTRICAL DATA S3C 8245/P8245/C8249/P8249 19- 8 Table 19-5. Input/Output Capacitance (T A = -25 ° C to +85 ° C, V DD = 0 V ) Parameter Symbol Conditions Min Typ Max Unit Input capacitance C IN f = 1 MHz; unmeasured pins are returned to V SS – – 10 pF Output capacitance C OUT I/O capacitance C IO Table 19-6. Data Retention Supply Voltage in S[...]

S3C8245/P8245/C8249/P8249 ELECTRICAL DA TA 19- 9 Execution of STOP Instruction ~ ~ V DDDR ~ ~ Stop Mode Idle Mode Data Retention Mode t WAIT V DD Interrupt Normal Operating Mode Oscillation Stabilization Time 0.2 V DD NOTE: t WAIT is the same as 16 x BT clock. Figure 19-4. Stop Mode (Main) Release Timing Initiated by Interrupts Execution of STOP In[...]

ELECTRICAL DATA S3C 8245/P8245/C8249/P8249 19- 10 Table 19-7. A/D Converter Electrical Characteristics (T A = -25 ° C to +85 ° C, V DD = 2.7 V to 5.5 V, V SS = 0 V) Parameter Symbol Conditions Min Typ Max Unit Resolution – 10 – bit Total accuracy V DD = 5.12 V AV REF = 5.12 V AV SS = 0 V – – ± 3 LSB Integral Linearity Error ILE CPU clock[...]

S3C8245/P8245/C8249/P8249 ELECTRICAL DA TA 19- 11 Table 19-8. Voltage Booster Electrical Characteristics (T A = 25 ° C, V DD = 2.0 V to 5.5 V, V SS = 0 V) Parameter Symbol Test Conditions Min Typ Max Unit Operating Voltage VDD 2.0 – 5.5 V Regulated Voltage V LC0 I LC0 = 5 uA (1/3 bias) 0.9 1.0 1.15 Booster Voltage V LC1 Connect 1 M Ω load betw[...]

ELECTRICAL DATA S3C 8245/P8245/C8249/P8249 19- 12 Table 19-10. Synchronous SIO Electrical Characteristics (T A = -25 ° C to +85 ° C, V DD = 1.8 V to 5.5 V, V SS = 0 V, fxx = 10 MHz oscillator) Parameter Symbol Conditions Min Typ Max Unit SCK Cycle time t CYC – 200 – – ns Serial Clock High Width t SCKH – 60 – – Serial Clock Low Width t[...]

S3C8245/P8245/C8249/P8249 ELECTRICAL DA TA 19- 13 Table 19-11. Main Oscillator Frequency (f OSC1 ) (T A = -25 ° C to +85 ° C, V DD = 1.8 V to 5.5 V) Oscillator Clock Circuit Test Condition Min Typ Max Unit Crystal X IN C1 C2 X OUT Crystal oscillation frequency 1 – 10 MHz Ceramic X IN C1 C2 X OUT Ceramic oscillation frequency 1 – 10 MHz Extern[...]

ELECTRICAL DATA S3C 8245/P8245/C8249/P8249 19- 14 X IN , XT IN 1/fosc1, 1/fosc2 0.1V t XL , t XTL t XH , t XTH V DD - 0.1V Figure 19-7. Clock Timing Measurement at X IN Table 19-13. Sub Oscillator Frequency (f OSC2 ) (T A = -25 ° C + 85 ° C, V DD = 1.8 V to 5.5 V) Oscillator Clock Circuit Test Condition Min Typ Max Unit Crystal C1 C2 XT IN XT OUT[...]

S3C8245/P8245/C8249/P8249 ELECTRICAL DA TA 19- 15 Table 19-14. Sub Oscillator(crystal) Stabilization Time (t ST2 ) (T A = 25 ° C) Oscillator Test Condition Min Typ Max Unit Crystal Normal mode V DD =4.5V to 5.5V –12 sec V DD =2.0V to 4.5V – – 10 sec Crystal Strong mode V DD =3.0V to 5.5V ––6 sec V DD =2.0V to 3.0V ––2 sec External cl[...]

ELECTRICAL DATA S3C 8245/P8245/C8249/P8249 19- 16 NOTES[...]

S3C8245/P8245/C8249/P8249 MECHANICAL DATA 20 - 1 20 MECHANICAL DATA OVERVIEW The S3C8245/C8249 micr ocontroller is currently available in 80 -pin -QFP/TQFP package. 80-QFP-1420C #80 20.00 ± 0.20 23.90 ± 0.30 14.00 ± 0.20 17.90 ± 0.30 #1 0.80 0.35 + 0.10 NOTE : Dimensions are in millimeters. 0.15 MAX (0.80) 0.15 + 0.10 - 0.05 0-8 0.10 MAX 0.80 ?[...]

MECHANICAL DATA S3C8245/P8245/C824 9/P8249 20 - 2 80-TQFP-1212 #80 12.00 BSC 14.00 BSC 12.00 BSC 14.00 BSC 0.09-0.20 0-7 NOTE : Dimensions are in millimeters. #1 (1.25) 0.50 0.60 ?0.15 0.05-0.15 1.00 ± 0.05 1.20 MAX 0.17-0.27 0.08 MAX M Figure 20-2. Package Dimensions (80-TQFP-1212)[...]

S3C8245/P8245/C8249/P8249 S3P8245/P8249 OTP 21- 1 21 S3P8245/P8249 OTP OVERVIEW The S3P8245/P8249 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C8245/C8249 microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is accessed by serial data format. The S3P8245/P8249 is fully compatible with[...]

S3P8245/P8249 OTP S3 C8245/P8245/C8249/P8249 21- 2 SEG25/P5.1 SEG24/P5.0 SEG23/P4.7 SEG22/P4.6 SEG21/P4.5 SEG20/P4.4 SEG19/P4.3 SEG18/P4.2 SEG17/P4.1 SEG16/P4.0 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 P0.5/INT5 P0.6/INT6 P0.7/INT7 P1.0/T1CAP P1.1/T1CLK P1.2//T1OUT/T1PWM P1.3 P1.4/BUZ P1.5/SIO P1.6/SCK P1.7/SI P2.0/ADC0 P2.1/ADC1 P2.2/ADC2 P2.3/ADC3 P2.[...]

S3C8245/P8245/C8249/P8249 S3P8245/P8249 OTP 21- 3 Table 21-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P3.3 SDAT 10 I/O Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. P3.4 SCLK 11 I Serial clock pin.[...]

S3P8245/P8249 OTP S3 C8245/P8245/C8249/P8249 21- 4 OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the V PP (TEST) pin of the S3P8245/P8249, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 21-3 below. Table 21-3. Operating Mo[...]

S3C8245/P8245/C8249/P8249 S3P8245/P8249 OTP 21- 5 Table 21-4. D.C. Electrical Characteristics (Continued) (T A = -25 ° C to +85 ° C, V DD = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Input high leakage current I LIH1 V IN = V DD All input pins except I LIH2 ––3 I LIH2 V IN = V DD X IN , XT IN 20 Input low leakage current I L[...]

S3P8245/P8249 OTP S3 C8245/P8245/C8249/P8249 21- 6 Table 21-4. D.C. Electrical Characteristics (Concluded) (T A = -25 ° C to + 85 ° C, V DD = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Supply current (1) I DD1 (2) V DD = 5 V ± 10 % 10 MHz crystal oscillator – 12 25 mA 3 MHz crystal oscillator 4 10 V DD = 3 V ± 10 % 10 MHz cr[...]

S3C8245/P8245/C8249/P8249 S3P8245/P8249 OTP 21- 7 Case of S3P8245, the characteristic of V OH and V OL is differ with the characteristic of S3P8249 like as bellow. Other characteristics are same each other. Table 21-5. D.C Electrical Characteristics of S3C8245 (T A = -25 ° C to +85 ° C, V DD = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ M[...]

S3P8245/P8249 OTP S3 C8245/P8245/C8249/P8249 21- 8 NOTES[...]

S3C8245/P8245/C8249/P8249 D EVELOPMENT TOOLS 22- 1 22 DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy-to-use development support system in turnkey form. The development support system is configured with a host system, debugging tools, and support software. For the host system, any standard computer that operates with MS-DOS , Window[...]

DEVELOPMENT TOOLS S3C8245/P8245/C824 9/P8249 22- 2 BUS SMDS2+ RS-232C POD Probe Adapter PROM/OTP Writer Unit RAM Break/Display Unit Trace/Timer Unit SAM8 Base Unit Power Supply Unit IBM-PC AT or Compatible TB8249 Target Board EVA Chip Target Application System Figure 22-1. SMDS Product Configuration (SMDS2+)[...]

S3C8245/P8245/C8249/P8249 D EVELOPMENT TOOLS 22- 3 TB8245/9 TARGET BOARD The TB8245/9 target board is used for the S3C8245/C8249 microcontroller. It is supported with the SMDS2+. TB8245/8249 SM1317A GND V CC + Idle + Stop J101 50-Pin Connector 2 1 39 40 50-Pin Connector 42 41 79 80 100-Pin Connector 25 1 RESET 7411 144 QFP S3E8240 EVA Chip J102 XI [...]

DEVELOPMENT TOOLS S3C8245/P8245/C824 9/P8249 22- 4 Table 22-1. Power Selection Settings for TB8245/9 " To User_Vcc " S ettings Operating Mode Comments To User_V CC Off On Target System SMDS2/SMDS2+ TB8245 TB8249 V CC V SS V CC The SMDS2 /SMDS2+ supplies V CC to the target board (evaluation chip) and the target system. To User_V CC Off On [...]

S3C8245/P8245/C8249/P8249 D EVELOPMENT TOOLS 22- 5 Table 22-3. Device Selection Settings for TB8245/9 " To User_Vcc " S ettings Operating Mode Comments Device Selection 8245 8249 Target System TB8249 Operate with TB8249 Device Selection 8245 8249 Target System TB8245 Operate with TB8245 SMDS2+ SELECTION (SAM8) In order to write data into [...]

DEVELOPMENT TOOLS S3C8245/P8245/C824 9/P8249 22- 6 J101 SEG26/P5.2 SEG28/P5.4 SEG30/P5.6 P3.0/TBPWM P3.2/TACLK P3.4/SCLK V SS X IN XT IN nRESET P0.1/INT1 P0.3/INT3 P0.5/INT5 P0.7/INT7 P1.1/T1CLK P1.3 P1.5/SO P1.7/SI P2.1/ADC1 P2.3/ADC3 SEG27/P5.3 SEG29/P5.5 SEG31/P5.7 P3.1/TAOUT/TAPWM P3.3/TACAP/SDAT V DD X OUT TEST XT OUT P0.0/INT0 P0.2/INT2 P0.4/[...]