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SMSC LAN91C111 manuel d'utilisation

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Tout d'abord, le manuel d’utilisation SMSC LAN91C111 devrait contenir:
- informations sur les caractéristiques techniques du dispositif SMSC LAN91C111
- nom du fabricant et année de fabrication SMSC LAN91C111
- instructions d'utilisation, de réglage et d’entretien de l'équipement SMSC LAN91C111
- signes de sécurité et attestations confirmant la conformité avec les normes pertinentes

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Habituellement, cela est dû au manque de temps et de certitude quant à la fonctionnalité spécifique de l'équipement acheté. Malheureusement, la connexion et le démarrage SMSC LAN91C111 ne suffisent pas. Le manuel d’utilisation contient un certain nombre de lignes directrices concernant les fonctionnalités spécifiques, la sécurité, les méthodes d'entretien (même les moyens qui doivent être utilisés), les défauts possibles SMSC LAN91C111 et les moyens de résoudre des problèmes communs lors de l'utilisation. Enfin, le manuel contient les coordonnées du service SMSC en l'absence de l'efficacité des solutions proposées. Actuellement, les manuels d’utilisation sous la forme d'animations intéressantes et de vidéos pédagogiques qui sont meilleurs que la brochure, sont très populaires. Ce type de manuel permet à l'utilisateur de voir toute la vidéo d'instruction sans sauter les spécifications et les descriptions techniques compliquées SMSC LAN91C111, comme c’est le cas pour la version papier.

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Tout d'abord, il contient la réponse sur la structure, les possibilités du dispositif SMSC LAN91C111, l'utilisation de divers accessoires et une gamme d'informations pour profiter pleinement de toutes les fonctionnalités et commodités.

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Table des matières du manuel d’utilisation

  • Page 1

    SMSC LAN91C1 1 1 REV C DA T ASHEET Revision 1.91 ( 08-18-08) Datasheet PRODUCT FEA TURES LAN91C1 1 1 10/100 Non-PCI Ethernet Single Chip MAC + PHY  Single Chip Ethernet C ontroller  Dual S pe ed - 10/100 Mbps  Fully Suppo rts Full Duplex Switched Ethernet  Supports Burst Data T ransfer  8 Kbytes Intern al Memory for Receive and Trans[...]

  • Page 2

    ORDER NUMBERS: LAN91C1 1 1-NC, LAN91C1 1 1i-NC (INDUSTRIAL T EMPERATURE) FOR 128-PIN QFP PACKAGES L A N 91 C 111 - N S , L A N 9 1 C 111 i - N S (INDUSTRIAL T EMPERATURE) FOR 128-PIN QFP LEAD-FREE ROHS COMPLIANT PACKAGES LAN91C1 1 1-NE (1.0MM HEIGHT); LAN91C 1 1 1i-N E (INDUSTRIAL T EMPERATU RE) FOR 128-PIN TQFP PACKAGES LAN91C1 1 1-NU (1.0MM HEIGH[...]

  • Page 3

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 3 Revision 1.91 (0 8-18-08) DA T A SHEET T able of Content s Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 2 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

  • Page 4

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 4 SMSC LAN91C1 1 1 REV C DA T A SHEET 8.4 Bank Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.5 Bank 0 - Tr ansmit Contr ol Register . . . . . . . . . . . . . . . . . . . . . . [...]

  • Page 5

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 5 Revision 1.91 (0 8-18-08) DA T A SHEET Chapter 15 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Chapter 16 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

  • Page 6

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 6 SMSC LAN91C1 1 1 REV C DA T A SHEET List of Figures Figure 2.1 Pin Configuration - LAN91C111-FEAST 128 PIN TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2.2 Pin Configuration - LAN91C111-FEAST 128 PIN QFP . . . . . . . . . . . . . . . . . . [...]

  • Page 7

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 7 Revision 1.91 (0 8-18-08) DA T A SHEET List of T ables Table 4.1 LAN91C111 Pin Requirements (128 Pin QFP an d 1.0mm TQFP package) . . . . . . . . . . . . . . 14 Table 7.1 4B/5B Sy mbol Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

  • Page 8

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 8 SMSC LAN91C1 1 1 REV C DA T A SHEET Chapter 1 General Description The SMSC LAN91C1 1 1 is design ed to facilitate the imple mentation of a third generation of Fast Ethernet connectivity solutions for embedded appl ic ations. For this third generation of products, fle[...]

  • Page 9

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 9 Revision 1.91 (0 8-18-08) DA T A SHEET Chapter 2 Pin Configurations Figure 2.1 Pin Configuration - LAN91C1 1 1-FEAST 128 PIN TQFP 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 128 127 126 125 124 123 122 121 120 119 118[...]

  • Page 10

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 10 SMSC LAN91C1 1 1 REV C DA T A SHEET Figure 2.2 Pin Configuration - LAN91 C1 1 1-FEAST 128 PIN QFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113[...]

  • Page 11

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 1 1 Revision 1.91 (08-18-08) DA T A SHEET Chapter 3 Block Diagrams The diagram sho wn in Figure 3.1, "Basic Functional Bl ock Diagram", describe s the device basic functional blocks. The SMSC LAN91C1 1 1 is a single chip solution for embedded desig ns with mini[...]

  • Page 12

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 12 SMSC LAN91C1 1 1 REV C DA T A SHEET The diagram shown in Figure 3.2 describes the su pported Host i nterfaces, which i nclude ISA or Generic Embedded. The Ho st interface is an 8 , 16 or 32 bit wide addres s / data bus with extensions for 32, 16 and 8 bit embedded R[...]

  • Page 13

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 13 Revision 1.91 (0 8-18-08) DA T A SHEET Figure 3.3 LAN91C1 1 1 Physica l Layer to Internal M AC Block Diagram C O L L I S I O N 4 B 5 B D E C O D E R D E S C R A M B L E R C L O C K & D A T A R E C O V E R Y A U T O N E G O T I A T I O N & L I N K S Q U E L C H[...]

  • Page 14

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 14 SMSC LAN91C1 1 1 REV C DA T A SHEET Chapter 4 Signal Descriptions Table 4.1 LAN91C111 Pin Requ irements (128 Pin QFP and 1.0mm TQFP packa ge) FUNCTION PIN SYMBOLS NUMBER OF PINS System Address Bus A1-A15, AEN, nBE0-nBE3 20 System Data Bus D0-D31 32 System Control Bu[...]

  • Page 15

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 15 Revision 1.91 (0 8-18-08) DA T A SHEET Chapter 5 Description of Pin Functions PIN NO. NAME SYMBOL BUFFER TYPE DESCRIPTION TQFP QFP 81-92 83-94 Address A4-A15 I** Input. Decoded by LAN91C1 1 1 to determine access to its registers. 78-80 80-82 Address A1-A3 I** Input. U[...]

  • Page 16

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 16 SMSC LAN91C1 1 1 REV C DA T A SHEET 42 44 Local Bus Clock LCLK I** Input. Used to interface synchro nous buses. Maximum frequency is 50 MHz. Limited to 8.33 MHz for EISA DMA burst mode. This pin should be tied high if it is in asynchronous mode. 38 40 Asynchronous R[...]

  • Page 17

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 17 Revision 1.91 (0 8-18-08) DA T A SHEET 9 1 1 EEPROM Clock EESK O4 Output. 4 μ sec clock used to shift data in and out of the serial EEPROM. 10 12 EEPROM Select EECS O4 Output. Serial EEPROM chip select. Used for selection and co mmand framin g of the serial EEPROM. 7[...]

  • Page 18

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 18 SMSC LAN91C1 1 1 REV C DA T A SHEET Note 5.1 If the EEPROM is enabled. 125 127 Rec eive Data Va l i d RX_DV I with pulldown Input from MII PHY . Envelope of data valid reception. Used for receive data framing. 1 12 1 14 Collision Detect 100 Mbps COL100 I with pulldo[...]

  • Page 19

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 19 Revision 1.91 (0 8-18-08) DA T A SHEET Chapter 6 Signal Description Parameters This section provides a detailed description of each SMSC LAN91C1 1 1 signal. The si gnals are arranged in functional groups according to their associated function. The ‘n’ symbol at th[...]

  • Page 20

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 20 SMSC LAN91C1 1 1 REV C DA T A SHEET Chapter 7 Functional Description 7.1 Clock Generator Block 1. The XT AL 1 and XT AL 2 pins are to be connected to a 25 MHz crystal. 2. TX25 is an input clock. It will b e the nibble rate of th e particular PHY connected to the MII[...]

  • Page 21

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 21 Revision 1.91 (0 8-18-08) DA T A SHEET 7.4 BIU Block The Bus Interface Unit can handle synchronous as well as asynchronous buses; different signals are used for each one. Transp a rent latches are added on the address path using rising nADS for latching. When working [...]

  • Page 22

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 22 SMSC LAN91C1 1 1 REV C DA T A SHEET The MAC and external PHY communicate via MDIO a nd MDC of the MII Management serial interface. MDIO:Management Data input/output. Bi-directi onal between MAC and PHY that carries management data. All control and status informa tio[...]

  • Page 23

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 23 Revision 1.91 (0 8-18-08) DA T A SHEET Figure 7.1 MI Serial Port Frame Timing Diagram M D I O M D C 0 2 1 3 4 7 6 5 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 0 0 1 1 P 4 P 1 P 2 P 3 P 0 R 4 R 3 R 2 R 1 R 0 1 0 D 1 5 D [...]

  • Page 24

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 24 SMSC LAN91C1 1 1 REV C DA T A SHEET 7.5.4 MII Packet Data Communi cation with External PHY The MIl is a nibble wide packet data interface defin ed in IEEE 80 2.3. The LAN91C1 1 1 meets all the MIl requirements outlined in IEEE 802.3 and shown in Figure 7.2 . The Mll[...]

  • Page 25

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 25 Revision 1.91 (0 8-18-08) DA T A SHEET edges. RXD0 carries the l east signifi cant bit an d RX D3 the most significant bit of the nibble. RX_DV goes inactive when the la st valid nibble of the packet (CRC) is presente d at RXD0-RXD3. RX_ER might be asserted during pac[...]

  • Page 26

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 26 SMSC LAN91C1 1 1 REV C DA T A SHEET On the transmit side for 100 Mbps TX operation, data is received on the controll er and then se nt to the 4B5B encoder for formatting . The encoded data is then sent to the scrambler . The scrambled and encoded data is then sen t [...]

  • Page 27

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 27 Revision 1.91 (0 8-18-08) DA T A SHEET 10Mbps operation is similar to the 100Mbp s TX operation except , (1) there is no scrambler/descrambler , (2) the encod er/decoder is Manchester i nstead of 4B5B, (3) the da ta rate is 10Mbps instead of 100Mbps, and (4) the twist[...]

  • Page 28

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 28 SMSC LAN91C1 1 1 REV C DA T A SHEET * These 5B cod es are not used. For decod er , these 5B codes are decode d to 4B 0000. For encod er , 4B 0000 is encoded to 5B 1 1 1 10, as shown in symbol D ata 0. The 4B5B decoder detects SSD, ESD and codeword er ro rs in the in[...]

  • Page 29

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 29 Revision 1.91 (0 8-18-08) DA T A SHEET 7.7.4 Clock and Data Recovery Clock Reco very - 100 Mbp s Clock recovery is done wi th a PL L. If there i s no vali d data present on the T P inputs, the PLL is locked to the 25 MHz TX25. When valid data is detected on the TP inp[...]

  • Page 30

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 30 SMSC LAN91C1 1 1 REV C DA T A SHEET If 25 consecutive descrambled idle pattern 1's are not detected within th e 1ms interval, the descrambler goes out of synchronization and restarts the synchronization process. If the descrambler i s in the unsynchronized stat[...]

  • Page 31

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 31 Revision 1.91 (0 8-18-08) DA T A SHEET Figure 7.4 TP Output V oltage T emplate - 10 MBPS REFERENCE TIME (NS) INTERNAL MAU VOL T AGE (V) A0 0 B1 5 1 . 0 C1 5 0 . 4 D2 5 0 . 5 5 E3 2 0 . 4 5 F3 9 0 G5 7 - 1 . 0 H4 8 0 . 7 I6 7 0 . 6 J8 9 0 K7 4 - 0 . 5 5 L7 3 - 0 . 5 5 [...]

  • Page 32

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 32 SMSC LAN91C1 1 1 REV C DA T A SHEET T ransmit Leve l Adjust The transmit output current level is de rived from an internal referen ce voltage and the external resistor on RBIAS pin. The transmit l evel can be adjusted wi th either (1) th e external resistor on the R[...]

  • Page 33

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 33 Revision 1.91 (0 8-18-08) DA T A SHEET STP (150 Ohm) Cable Mode The transmitter can be configured to drive 150 Ohm sh ielded twisted pair cable. The STP mode can be selected by appropriatel y setting the cable type se lect bit in the PHY MI se rial port Co nfiguration[...]

  • Page 34

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 34 SMSC LAN91C1 1 1 REV C DA T A SHEET TP Squelch - 100 Mbps The squelch block determines if the TP input contai ns valid data. The 100 Mbps TP squelch is one of the criteria used to determine l ink integri ty . The sq uelch comparators compare the T P in puts against [...]

  • Page 35

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 35 Revision 1.91 (0 8-18-08) DA T A SHEET Equalizer Disable The adaptive equalizer can be disabl ed b y setting the equal izer disable bit in th e PHY Ml serial port Configuration 1 re gister . When d isa bled, the equalizer is forced into the response it would normally [...]

  • Page 36

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 36 SMSC LAN91C1 1 1 REV C DA T A SHEET SSD) is signaled to the control ler interface. W hen False Carrier i s detect ed, the MAC is notified of false carrier and invalid received, and the bad SSD bit is set in the PHY Ml serial port S tatus Output register . Once a Fal[...]

  • Page 37

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 37 Revision 1.91 (0 8-18-08) DA T A SHEET 7.7.12 Link Integrity & AutoNegotiation General The LAN91C1 1 1 can be configu red to implement ei th er the standard lin k integrity algori thms or the AutoNegotia tion algori thm. The standard link integrity algorithms a re[...]

  • Page 38

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 38 SMSC LAN91C1 1 1 REV C DA T A SHEET 100BASE-TX Link Integr ity Algorithm -100Mb p s Since 100BASE-TX is defined to have an active idle signal, then there is no need to have separate link pulses like those define d for 10BASE-T . The LAN91C1 1 1 uses the squelch crit[...]

  • Page 39

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 39 Revision 1.91 (0 8-18-08) DA T A SHEET The AutoNegotiation algorithm is initiated by any of these events: (1 ) AutoNegotiation enabled, (2) a device enters the Link Fail S tate, (3) AutoNegotiatio n Reset. Once a negotiation has been initiated, the LAN91C1 1 1 first d[...]

  • Page 40

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 40 SMSC LAN91C1 1 1 REV C DA T A SHEET device halts all transmissi ons including link pul ses fo r 1200-1500 ms, en ters the Link F ail S tate, and restarts the negotiation process. When AutoN egotiation mode is turned on or reset, software driver should wait for at le[...]

  • Page 41

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 41 Revision 1.91 (0 8-18-08) DA T A SHEET Autopolarity Disable The autopolarity feature can be disabl ed by setting the autopolari ty disable bit in the PHY MI serial port Configuration 2 register . 7.7.15 Full Duplex Mode 100 Mbps Full Duplex mode allows transmission an[...]

  • Page 42

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 42 SMSC LAN91C1 1 1 REV C DA T A SHEET R/L T bits are also interrupt bits if they are not masked out with the Mask register bits. Interrupt bits automatically latch themselves into their register location s and assert the interrupt indication when they change state. In[...]

  • Page 43

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 43 Revision 1.91 (0 8-18-08) DA T A SHEET Chapter 8 MAC Dat a Structures and Registers 8.1 Frame Format In Buffer Memory The frame format in memory is similar for the T ransmi t and Receive areas. The first word is re served for the status word. The next word is used to [...]

  • Page 44

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 44 SMSC LAN91C1 1 1 REV C DA T A SHEET The receive byte coun t always appears as even ; the ODDFRM bit of the recei ve status word indicates if the low byte of the last word is relevant. The transmit byte count least significant b it will be assumed 0 by the controller[...]

  • Page 45

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 45 Revision 1.91 (0 8-18-08) DA T A SHEET BROADCAST - Receive frame was br oadcast. When a broad cast packet is received, the MUL TCAST bit may be also set on the status word in addition to the BRODCAST bit. T he software implement may just ignore the MUL TCAST bit if fo[...]

  • Page 46

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 46 SMSC LAN91C1 1 1 REV C DA T A SHEET Regardless of the functional descriptio n, all register s can be accessed as dou blewords, words or bytes. The default bit values u pon hard reset are hi ghlighted below ea ch register . A special BANK (BANK7) exists to support th[...]

  • Page 47

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 47 Revision 1.91 (0 8-18-08) DA T A SHEET Bank 7 is a new register Bank to the SMSC LAN9 1C1 1 1 device. Thi s bank has extended registers that allow the extended feature se t of the SMSC LAN91C1 1 1. 8.5 Bank 0 - T ransmit Control Register This register holds bits progr[...]

  • Page 48

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 48 SMSC LAN91C1 1 1 REV C DA T A SHEET FORCOL - When set, the FORCOL bit will force a collisio n by not deferring delib erately . This bit is set and cleared only by the CPU. Wh en TXENA is enabl ed with no packets in the queue and while the FORCOL bit is set, the LAN9[...]

  • Page 49

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 49 Revision 1.91 (0 8-18-08) DA T A SHEET SQET - Signal Quality Error T est. This bit is set und er the following conditions: 1. LAN91C1 1 1 is set to operate in Hal f Duplex mode (SWFDUP=0); 2. When STP_SQET=1 and SW FDUP=0, SQET bit will be set u pon completion of a tr[...]

  • Page 50

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 50 SMSC LAN91C1 1 1 REV C DA T A SHEET ABORT_ENB - Enables abort of recei ve when collisi on occurs. Defaults low . Wh en set, the LAN91C1 1 1 wil l automatically abort a packet being recei ved when the appropri ate collision input is activated. This bit has no effect [...]

  • Page 51

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 51 Revision 1.91 (0 8-18-08) DA T A SHEET 8.9 Bank 0 - Memory Information Register FREE MEMORY A V AILABLE - This register can be rea d at any time to determine the amount of free memory . The register defau lts to the MEMORY SI ZE upon POR (Power On Reset) or upon the R[...]

  • Page 52

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 52 SMSC LAN91C1 1 1 REV C DA T A SHEET Register) and de termine the duple x mode. When this bit is set (1), the Internal PHY w ill operate at full duplex mode. When this bit is clea red (0), the Intern al PHY will operate at half Dup lex mode. Wh en the ANEG bit = 1, t[...]

  • Page 53

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 53 Revision 1.91 (0 8-18-08) DA T A SHEET LS2A, LS1A, LS0A – LED select Signal Enable. Thes e bits define what LED control signal s are routed to the LEDA output pin on the LAN91C1 1 1 Etherne t Controller . T he default i s 10/100 Link detected. LS2B, LS1B, LS0B – L[...]

  • Page 54

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 54 SMSC LAN91C1 1 1 REV C DA T A SHEET Reserved – Must be 0. 8.1 1 Bank 1 - Configuration Register The Configuration Register holds b its that define the adapter c onfiguration and are not expected to change during run-time. Th is register is part of the EEPROM saved[...]

  • Page 55

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 55 Revision 1.91 (0 8-18-08) DA T A SHEET 8.12 Bank 1 - Base Address Register This register holds the I/O address decode option chosen for th e LAN91 C1 1 1 . It is part of the EEPROM saved setup and is not usua lly modified during run-time. A15 - A13 and A9 - A5 - These[...]

  • Page 56

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 56 SMSC LAN91C1 1 1 REV C DA T A SHEET 8.14 Bank 1 - Genera l Purpose Register This register can be used as a way of storing a nd retrieving non-vo latile informat ion in the EEPROM to be used by the software driver . The storage is word oriented, and th e EEPROM word [...]

  • Page 57

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 57 Revision 1.91 (0 8-18-08) DA T A SHEET 8.15 Bank 1 - Control Register RCV_BAD - When set, bad CRC packet s are re ceived. When clear bad CRC packets do not generate interrupts and their me mory is released. AUTO RELEASE - When set, transmit pages are rel eased by tran[...]

  • Page 58

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 58 SMSC LAN91C1 1 1 REV C DA T A SHEET 8.16 Bank 2 - MMU Command Register This register is used by the CPU to control the memory allocation, de-a llocation, TX FIFO and RX FIFO control. The three command b its determine the command issued as descri bed below: COMMAND S[...]

  • Page 59

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 59 Revision 1.91 (0 8-18-08) DA T A SHEET Note:  When using the RESET TX FIFOS command, the CP U is responsible for releasi ng the memory associated with outstanding packets, or re-enqueuing them. Packet numbers in the compl etion FIFO can be read via th e FIFO ports [...]

  • Page 60

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 60 SMSC LAN91C1 1 1 REV C DA T A SHEET This register is updated u pon an ALLOCA TE MEMORY MMU command. F AILED - A zero indicates a successful allocation completion. If the allocatio n fails the bit is set and only cleared when the pending allocation is satisfied. Defa[...]

  • Page 61

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 61 Revision 1.91 (0 8-18-08) DA T A SHEET TEMPTY - No transmit p ackets in completion queu e. For polling purposes, uses the TX_INT bit in the Interrupt S tatus Register . TX FIFO P ACKET NUMBER - Packet number presently at the output of the TX FIFO. Only valid if TEMPTY[...]

  • Page 62

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 62 SMSC LAN91C1 1 1 REV C DA T A SHEET 8.20 Bank 2 - Dat a Register DA T A REGISTER - Used to read or write the data bu ffer byte/word presently addressed by the pointer register . This register is mapped into two uni-direction a l FIFOs that allow mo ving words to and[...]

  • Page 63

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 63 Revision 1.91 (0 8-18-08) DA T A SHEET This register can be read and written as a word o r as two individual bytes. The Interrupt Mask Register bits enable the appropri ate b its when high and disable them when lo w . A MASK bit being set will ca use a hardware interr[...]

  • Page 64

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 64 SMSC LAN91C1 1 1 REV C DA T A SHEET  LA TC OL - Late Collision  16COL - 16 collisions Any of the above interrupt so urces can be masked by the appropria te ENABLE bits in the Control Register . 1. 1) LE ENABLE (Link Error Enable), 2) CR ENABLE (Counter Roll Ov[...]

  • Page 65

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 65 Revision 1.91 (0 8-18-08) DA T A SHEET Figure 8.2 Interrupt St r ucture TX FI FO EMPT Y DQ S nQ IntAck1 DQ S nQ IntAck2 DQ S nQ IntAck4 DQ S nQ IntAck7 RX_OVRN MDINT nWRACK TX Complete Fatal TX Error SQET LOST CARR LATCOL 16COL Interrupt Stat us Register 76543210 nRDI[...]

  • Page 66

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 66 SMSC LAN91C1 1 1 REV C DA T A SHEET 8.22 Bank 3 - Multicast T able Registers The 64 bit multicast table is used for group address filtering. The ha sh value is defined as the six most significant bits of the CRC of the destination addresses. The three msb's det[...]

  • Page 67

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 67 Revision 1.91 (0 8-18-08) DA T A SHEET 8.23 Bank 3 - Management Interface MSK_CRS100 - Disables CRS100 detection during transmit in half duplex mode (SWFDUP=0). MDO - MII Management output. The va lue of this bit drives the MDO pin. MDI - MII Management input. The val[...]

  • Page 68

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 68 SMSC LAN91C1 1 1 REV C DA T A SHEET 8.25 Bank 3 - RCV Register RCV DISCRD - Set to discard a packet being received. Wi ll discard packets only in the process of being received. When set prior to the end of recei v e packet, bit 4 (RXOVRN) of the interrup t status re[...]

  • Page 69

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 69 Revision 1.91 (0 8-18-08) DA T A SHEET CYCLE NCSOUT LAN91C1 1 1 DA T A BUS AEN=0 A3=0 A4-15 matches I/O BASE BANK SEL ECT = 7 Driven low . Transp arently latched on nADS rising edge. Ignored on write s. T ri-stated on reads. BANK SELECT = 4,5,6 High Ignore cycle. Othe[...]

  • Page 70

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 70 SMSC LAN91C1 1 1 REV C DA T A SHEET Chapter 9 PHY MII Registers Multiple Register Acces s Multiple registers can be accessed on a single PHY Ml serial port access cycle with the multiple register access features. The mult iple register access features can be enab le[...]

  • Page 71

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 71 Revision 1.91 (0 8-18-08) DA T A SHEET PHY Register Description D[15:0] ↓ Register 0 Control Register 1 S tatus Register 2 PHY ID #1 Register 3 PHY ID #2 Register 4 AutoNegotiation Advertisement Register 5 AutoNegotiation Remote End Capability Register 16 Configurat[...]

  • Page 72

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 72 SMSC LAN91C1 1 1 REV C DA T A SHEET REGAD[4:0] Register Address If REGAD[4:0] = 00000-1 1 1 1 0, thes e bi ts determine the specific register from which D[15:0] is read/writte n. If multiple register access i s e n a b l e d a n d R E G A D [ 4 : 0 ] = 1111 1 , a l [...]

  • Page 73

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 73 Revision 1.91 (0 8-18-08) DA T A SHEET T able 9.2 MII Serial Port Register MAP R/LT R/LT R R R/LT R/LT R R 0 1 R/LT R/LT R/LT R/LT R R/LT R/LT R/LT 0 0 00 00 0 00 00 0 0 x.6 x.7 x.8 x.9 x.13 x.10 x.15 x.14 x.11 x.12 x.3 x.0 x. 5 x.4 x.1 x.2 R/W R/W R/W R/W R/W R/W R/W[...]

  • Page 74

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 74 SMSC LAN91C1 1 1 REV C DA T A SHEET 9.1 Register 0. Control Register RST - Reset A ‘1’ written to this bit will initiate a reset of the PHY . The bit is self-clearing, and the PHY wil l return a ‘1’ on reads to this bit until the reset is completed. Wr ite t[...]

  • Page 75

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 75 Revision 1.91 (0 8-18-08) DA T A SHEET DPLX - Duplex mode When Auto Negotiation is disab led this bit can be used to manually select the link duplex state. Writing a ‘1’ to this bit selects full duplex while a ‘0’ selects half duplex. When Auto-Negotiation is [...]

  • Page 76

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 76 SMSC LAN91C1 1 1 REV C DA T A SHEET REM_FL T - Remote Fault Detect ‘1’ indicate s a Remote Fault. Latches the ‘1’ cond ition and is cl eared by reading this register or resetting the PHY . CAP_ANEG - AutoNegotiation Cap able Indicates the ability (‘1’) t[...]

  • Page 77

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 77 Revision 1.91 (0 8-18-08) DA T A SHEET NP - Next Page A ‘1’ indicates the PHY wishes to exchang e Next Page informati on. ACK - Acknowledge It is used by the Auto-negotiation function to indi cate that a device has successfully received its Link Partner ’s Link [...]

  • Page 78

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 78 SMSC LAN91C1 1 1 REV C DA T A SHEET 9.6 Register 16. Config uration 1 - S tructur e and Bit Definition LNKDIS X MTDIS XMTPDN Reserved Reserved BYPSCR UNSCDS EQLZR RW RW RW RW RW RW RW RW 00 0 0 0 0 0 0 CABLE R L VL0 TL VL3 TL VL2 TL VL1 TL VL0 TRF1 TRF0 RW RW RW RW [...]

  • Page 79

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 79 Revision 1.91 (0 8-18-08) DA T A SHEET 9.7 Register 17. Config uration 2 - Structure and Bit Definition Select 0 = Receive Equalizer On (For 100MB Mode Only) CABLE Cable T ype Select 1 = STP (150 Ohm) 0 = UTP (100 Ohm) RL VL0 Receive Input 1 = Receive Squelch Levels R[...]

  • Page 80

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 80 SMSC LAN91C1 1 1 REV C DA T A SHEET 9.8 Register 18. S tatu s Output - S tructur e and Bit Definition 0 = No Multiple Register Access 0 = No Multiple Register Access INTMDIO: Interrupt Scheme Select 1 = Interrupt Signaled With MDIO Pulse During Idle 1 = Interrupt Si[...]

  • Page 81

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 81 Revision 1.91 (0 8-18-08) DA T A SHEET 9.9 Register 19. Mask - St ructure and Bit Definition SSD: S tart Of S tream Error 1 = No St art Of S tream Delimi ter Detected on Receive Data 0 = Normal ESD: End Of S tream Error 1 = No End Of S tream Delimi ter Detected on Rec[...]

  • Page 82

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 82 SMSC LAN91C1 1 1 REV C DA T A SHEET 9.10 Register 20. Reserved - Structure and Bit Definition MLNKF AIL: Interrupt Mask Link Fail Detect 1 = Mask Interrupt For LNKF AIL In Register 18 0 = No Mask MLOSSSYN: Interrupt Mask Descrambler Loss 1 = Mask Interrupt For LOSSS[...]

  • Page 83

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 83 Revision 1.91 (0 8-18-08) DA T A SHEET Reserv ed: Reserved for Factory Use Reserved Reserved Reserved Reserved Re served Reserved Reserved Reserve d RW RW RW RW RW RW RW R W 10 1 0 0 0 0 0[...]

  • Page 84

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 84 SMSC LAN91C1 1 1 REV C DA T A SHEET Chapter 10 Sof tware Driver and Hardware Sequence Flow 10.1 Sof tware Driver and Hardwa re Sequence Flow for Power Management This section describes the sequ ence of events and the interactio n between the Host Driver an d the Eth[...]

  • Page 85

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 85 Revision 1.91 (0 8-18-08) DA T A SHEET 10.2 T ypical Flow of Event s fo r T ransmit (Auto Release = 0) T able 10.2 Flow Of Events For Restoring Device In Normal Power Mode S/W DRIVER CONTROLLER FUNCTION 1 Write and set (1) the “EPH Pow er E N” B it, loca ted in th[...]

  • Page 86

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 86 SMSC LAN91C1 1 1 REV C DA T A SHEET 10.3 T ypical Flow of Event s fo r T ransmit (Auto Release = 1) 6 Upon transmit completion the first word in memory is written with the status word. The packet number is moved from th e TX FIFO into the TX comple tion FIFO. Interr[...]

  • Page 87

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 87 Revision 1.91 (0 8-18-08) DA T A SHEET 10.4 T ypical Flow of Event For Receive 7 The MAC generates a TXEMPTY interrupt upon a completion of a sequence of e nqueued packets. If a TX failure occurs on any packets, TX INT is generated and TXENA is cleared, transmission s[...]

  • Page 88

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 88 SMSC LAN91C1 1 1 REV C DA T A SHEET Figure 10.1 Interrupt Service Routine ISR Save Bank Select & A ddress Ptr Registers Mask SMC91C111 Int errupts Read Int e rrupt Register Call TX INTR or TXEMPTY INT R TX INTR? Get N ext TX RX I NTR? Yes No No Yes Call RXI NTR [...]

  • Page 89

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 89 Revision 1.91 (0 8-18-08) DA T A SHEET Figure 10.2 RX INTR RX INTR W rite Ad. Ptr. Reg. & Read W ord 0 f rom RAM Destination Multicast? Read W ords 2, 3, 4 from RAM for Address Filtering Address Filtering Pass? Status W ord OK? Do Receive Lookahead Get Copy Specs [...]

  • Page 90

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 90 SMSC LAN91C1 1 1 REV C DA T A SHEET Figure 10.3 TX INTR TX Interrupt With AUTO_RELEASE = FALSE 1. S ave the P acket Num ber Regi ster Saved _PNR = R ead By te (Bank 2, Offset 2) 2. Re ad the EPH St atus Regi ster Temp = Read (Bank 0, Offse t 2) 3. Acknow ledge T X I[...]

  • Page 91

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 91 Revision 1.91 (0 8-18-08) DA T A SHEET Figure 10.4 TXEMPTY INTR (Assumes Auto Re lease Optio n Selected) TXEM PTY INT R Write Ac knowledge Reg. with TXEM PT Y Bit Set Read T XEM PT Y & T X INT R Acknowledge TXINTR Re-Enabl e T XEN A R e tu r n to IS R Issue "[...]

  • Page 92

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 92 SMSC LAN91C1 1 1 REV C DA T A SHEET MEMOR Y P ARTITIONING Unlike other controllers, the LAN91C1 1 1 does not r equire a fixed memory partitioning betwee n transmit and receive resources. The MMU allocates and de-allocates memory upon dif ferent events. An additional[...]

  • Page 93

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 93 Revision 1.91 (0 8-18-08) DA T A SHEET multicast packet s that might not be for the node, and that ar e not subject to upper la yer software flow control. INTERRUPT GENERA TION The interrupt strategy for the transmit an d receive pr ocesses i s such that it does n ot [...]

  • Page 94

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 94 SMSC LAN91C1 1 1 REV C DA T A SHEET Figure 10.6 Interrupt Generation for T ransmit, Receive, MMU T X F I F O T X C O M P L E T I O N F I F O R X F I F O C S M A / C D L O G I C A L A D D R E S S P A C K E T # M M U P H Y S I C A L A D D R E S S R A M CPU ADDRESS CSM[...]

  • Page 95

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 95 Revision 1.91 (0 8-18-08) DA T A SHEET Chapter 1 1 Board Setup Information The following parameter s ar e obtained from the EEPROM as board setu p information:  ETHERNET INDIVIDUAL ADDRESS  I/O BASE ADDRESS  MII INTERF ACE All the above mentioned values ar e [...]

  • Page 96

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 96 SMSC LAN91C1 1 1 REV C DA T A SHEET STORE and RELOAD bits of CTR will readback as both bits high. No o ther bits of the L AN91C111 can be read or written until the EEPROM operatio n complete s and both bits are clear. This mechan ism is also valid for reset initiate[...]

  • Page 97

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 97 Revision 1.91 (0 8-18-08) DA T A SHEET Figure 1 1.1 64 X 16 Serial EEPROM Map CONFI G UR A TION REG. BASE REG. CONFI G UR A TION REG. BASE REG. CONFI G UR A TION REG. BASE REG. CONFI G UR A TION REG. BASE REG. CONFI G UR A TION REG. BASE REG. CONFI G UR A TION REG. BA[...]

  • Page 98

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 98 SMSC LAN91C1 1 1 REV C DA T A SHEET Chapter 12 Application Considerations The LAN91C1 1 1 is envisioned to fit a few differ ent bus types. This section descri bes the basic guidelines, system level imp lications and sample conf igurations for the most relevant bus t[...]

  • Page 99

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 99 Revision 1.91 (0 8-18-08) DA T A SHEET D0-D31 D0-D31 32 bit data bus. The bus byte(s) used to access the device are a function of nBE0-nBE3: Not used = tri-state on reads, ignored on writes. Note that nBE2 and nBE3 override the value of A1, wh ich is tied low in th is[...]

  • Page 100

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 100 SMSC LAN91C1 1 1 REV C DA T A SHEET HIGH-END ISA OR NON- BURST EISA MACHINES On ISA machines, the LAN91C1 1 1 is accessed as a 16 bit perip heral. T he sign al connection s a re listed in the following table: Figure 12.1 LAN91C1 1 1 on VL BUS T abl e 12.2 High-End [...]

  • Page 101

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 101 Revision 1.91 (0 8-18-08) DA T A SHEET nIOWR nWR I/O Write strobe - asynchronous write access. Address is valid before leading edge. D ata is latched on traili ng edge. IOCHRDY ARD Y This signal is n egated on lead ing nRD, nWR if necessary . It is then asserted on C[...]

  • Page 102

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 102 SMSC LAN91C1 1 1 REV C DA T A SHEET EISA 32 BIT SLA VE On EISA the LAN91C1 1 1 is accessed as a 32 bit I/O slave, along with a Slave DMA type "C" data path option. As an I/O slave, the LAN91C1 1 1 us es asynchronous accesses. In creating nRD and nWR input[...]

  • Page 103

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 103 Revision 1.91 (0 8-18-08) DA T A SHEET Latched W-R combined with nCMD nRD I/O Read strobe - asynchronous re ad accesses. Address is valid before its leading edge. Must not be active during DMA bursts if DMA is supported. Latched W-R combined with nCMD nWR I/O Write s[...]

  • Page 104

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 104 SMSC LAN91C1 1 1 REV C DA T A SHEET GND A1 Figure 12.3 LAN91C1 11 on EISA BUS T able 12.3 EISA 32 Bit Slave Signal Connection s (continued) EISA BUS SIGNAL LAN91C1 1 1 SIGNAL NOTES A2-A15 RESET AEN INT R0 nRD nW R LCLK nADS nLDEV LA N91C111 LA2- LA15 RESET O.C. EIS[...]

  • Page 105

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 105 Revision 1.91 (0 8-18-08) DA T A SHEET Chapter 13 Operational Description 13.1 Maximum Guar anteed Ratings* *S tresse s above those listed above co uld cause permanent d amage to the device. Th is is a stress rating only and functio nal operation of the de vice at an[...]

  • Page 106

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 106 SMSC LAN91C1 1 1 REV C DA T A SHEET Input Leakage (All I and IS buffers except pins with pullups/pulldowns) Low Input Leakage High Input Leakage I IL I IH -10 -10 +10 +10 µA µA V IN = 0 V IN = V CC IP T ype Buffers Input Current I IL -1 10 -45 μ AV IN = 0 ID T y[...]

  • Page 107

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 107 Revision 1.91 (0 8-18-08) DA T A SHEET CAP ACIT ANCE T A = 25 ° C; fc = 1MHz; V CC = 3.3V CAP ACITIVE LOAD ON OUTPUTS I/O24 T ype Buffer Low Output Level High Output Level Output Leakage V OL V OH I OL 2.4 -10 0.4 +10 V V µA I OL = 35 mA I OH = -15 mA V IN = 0 to V[...]

  • Page 108

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 108 SMSC LAN91C1 1 1 REV C DA T A SHEET 13.3 T wisted Pair Char acteristics, T ransmit V DD = 3.3v +/- 5% RBIAS = 1 1K +/- 1 %, no load SYM P ARAMETER LIMI T UNIT CONDITIONS MIN TYP MAX T ov TP Differential Output Vo l t a g e 0.950 1.000 1.050 Vpk 100 Mbps, UTP Mode, [...]

  • Page 109

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 109 Revision 1.91 (0 8-18-08) DA T A SHEET 13.4 T wisted Pair Char acteristics, Receive Unless otherwise noted, a ll test conditions are as fol lows:  Vcc = 3.3V +/-5%  RBIAS = 1 1 K +/- 1 %, no load  62.5/10 Mhz Square Wave on TP inputs in 100/10 Mbps T OIR TP [...]

  • Page 110

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 1 10 SMSC LAN91C1 1 1 REV C DA T A SHEET Chapter 14 T iming Diagrams Figure 14.1 Asynchronous Cycle - nADS=0 P ARAMETER MIN TYP MAX UNITS t1 A1-A15, AEN, nBE[3:0] V alid to nRD, nWR Active 2 ns t2 A1-A15, AEN, nBE[3:0] Hold Afte r nRD, nWR Inactive (Assumin g nADS T i [...]

  • Page 111

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 1 1 1 Revision 1.91 (08-18-08) DA T A SHEET Figure 14.2 Asynchronous Cycl e - Using nADS P ARAMETER MIN TYP MAX UNITS t1 A1-A15, AEN, nBE[ 3:0] V alid to nRD, nWR Acti ve 2 ns t3 nRD Low to V ali d Data 15 ns t4 nRD High to Data Invalid 2 15 ns t5 Data Setup to nWR Inact[...]

  • Page 112

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 1 12 SMSC LAN91C1 1 1 REV C DA T A SHEET Figure 14.3 Asynchronous Cycle - nADS=0 P ARAMETER MIN TYP MAX UNITS t1A nDA T ACS Setup to nRD, nWR Active 2 ns t2 nDA T ACS Hold After nRD, nWR Inactive (Assu ming nADS Tied Low) 5n s t3A nRD Low to V alid Data 30 ns t4 nRD Hi[...]

  • Page 113

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 1 13 Revision 1.91 (0 8-18-08) DA T A SHEET P ARAMETER MIN TYP MAX UNITS t26 ARDY Low Pulse Width 100 1 50 ns t26A Con trol Active to ARDY Lo w 10 ns t13 V alid Data to ARDY High 10 ns Figure 14.5 Burst Write Cycles - nVLBUS=1 P ARAMETER MIN T YP MAX UNITS t12 nDA T ACS [...]

  • Page 114

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 1 14 SMSC LAN91C1 1 1 REV C DA T A SHEET Figure 14.6 Burst Read Cycles - nVLBUS=1 P ARAMETER MIN TYP MAX UNITS t12 nDA T ACS Setup to LCLK Rising 20 ns t12A nDA T ACS Hold after LCLK Rising 0 ns t14 nRDYRTN Setup to LCLK Falling 10 ns t15 nRDYRTN Hold after LCLK Fallin[...]

  • Page 115

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 1 15 Revision 1.91 (0 8-18-08) DA T A SHEET Figure 14.7 Address Latching for All Modes P ARAMETER MIN TYP MAX UNITS t8 A1-A15, AEN, nBE[3:0 ] Setup to nADS Rising 8 ns t9 A1-A15, AEN, nBE[3:0 ] Hold After nADS Rising 5 ns t25 A4-A15, AEN to nLDEV Delay 30 ns Figure 14.8 [...]

  • Page 116

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 1 16 SMSC LAN91C1 1 1 REV C DA T A SHEET P ARAMETER MIN TYP MAX UNITS t8 A1-A15, AEN, nBE[3:0] Setup to nADS Rising 8 ns t9 A1-A15, AEN, nBE[3:0] Hold After nADS Rising 5 ns t10 nCYCLE Setup to LCLK Ri sing 5 ns t1 1 nCYCLE Hold after LCLK Rising (Non-Burst Mode) 3 ns [...]

  • Page 117

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 1 17 Revision 1.91 (0 8-18-08) DA T A SHEET P ARAMETER MIN TYP MAX UNITS t8 A1-A15, AEN, nBE[3:0] Setup to nADS Rising 8 ns t9 A1-A15, AEN, nBE[3:0] Hold After nADS Rising 5 ns t10 nCYCLE Setup to LC LK Rising 5 ns t1 1 nCYCLE Hold after LCLK Rising (Non-Burst Mode) 3 ns[...]

  • Page 118

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 1 18 SMSC LAN91C1 1 1 REV C DA T A SHEET AC TEST TIMING CONDITI ONS Unless otherwise noted, a ll test conditions are as fol lows: 1. V DD = 3.3V +/-5% 2. RBIAS = 1 1 K +/- 1%, no load 3. Measurement Points: 4. TPO±, TPI±: 0.0 V During Data , ±0.3V at start/end of p [...]

  • Page 119

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 1 19 Revision 1.91 (0 8-18-08) DA T A SHEET T ab le 14.2 Receive Timing Characteristics SYM P ARAMETER LIMIT UNIT CONDITIONS MIN TYP MAX t36 Receive Input Jitte r ±3.0 nS p k-pk 100Mbps ±13.5 nS pk-pk 1 0Mbps t37 SOI Pulse Minimum Width Required for Idle Detection 125 [...]

  • Page 120

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 120 SMSC LAN91C1 1 1 REV C DA T A SHEET Figure 14.13 Collision Timing, Receive t 34 LEDn t 35 t 34 t 35 LEDn TPI± I TPO± I DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA I K J I I DATA I I R T DATA DATA DATA DATA DATA t 38 MII 100 Mbps MII 10 Mbps TPI± TPO±[...]

  • Page 121

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 121 Revision 1.91 (0 8-18-08) DA T A SHEET Figure 14.14 Collision Timing, T ransmit t 34 t 35 t 34 t 35 LEDn LEDn TPO± I TPI± I DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA I K J I I DATA I I R T DATA DATA DATA DATA DATA t 39 MII 100 Mbps MII 10 Mbps TPO± TP[...]

  • Page 122

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 122 SMSC LAN91C1 1 1 REV C DA T A SHEET Figure 14.15 Jam Timing t 41 t 40 MII 100 Mbps MII 10 Mbps TPI± TPO± II DATA DATA DATA DATA K J DATA DATA TPO± II JAM I I R JAM JAM K JAM I II J T I DATA DATA DATA DATA DATA DATA JAM JAM JAM JAM t 40 TPO± Collision Observed b[...]

  • Page 123

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 123 Revision 1.91 (0 8-18-08) DA T A SHEET T able 14.4 Link Pulse Ti ming Characteristics SYM P ARAMETER LIMIT UNIT CONDITIONS MIN TYP MAX t42 N LP T ransmit Li nk Pulse Width See F igure 7.8 nS t43 N LP T ransmit Li nk Pulse Period 8 24 mS t44 N LP Receive Link Pulse Wi[...]

  • Page 124

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 124 SMSC LAN91C1 1 1 REV C DA T A SHEET Figure 14.16 Link Pulse T iming TPO± t 42 a.) Transmit NLP t 43 TPI± t 44 b.) Receive NLP t 45 t 47 t 46 LEDn[...]

  • Page 125

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 125 Revision 1.91 (0 8-18-08) DA T A SHEET Figure 14.17 FLP Link Pulse Timing TPO± t 48 a.) Transmit FLP and Transmit FLP Burst t 49 TPI± t 52 b.) Receive FLP t 54 TPI± CLK DATA CLK DATA DATA CLK CLK t 51 CLK DATA DATA CLK t 53 31.25 62.5 93.75 125 156.25 t 55 t 56 c.[...]

  • Page 126

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 126 SMSC LAN91C1 1 1 REV C DA T A SHEET Chapter 15 Package Outlines Notes: 1. Controlling Unit: millime ter 2. T oler ance on the position of the leads is ± 0.035 mm maximum 3. Package body dimensions D1 and E1 do not inclu de the mold protrusion. Maximum mold protrus[...]

  • Page 127

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C1 1 1 REV C 127 Revision 1.91 (0 8-18-08) DA T A SHEET Notes: 1. Controlling Unit: millime ter 2. T oler ance on the position of the leads is + 0.04 mm maximum. 3. Package body dimensions D1 and E1 do not inclu de the mold protrusion. Maximum mold protrusion is 0.25 mm. 4. Dimension[...]

  • Page 128

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Revision 1.91 (08-18-08) 128 SMSC LAN91C1 1 1 REV C DA T A SHEET Chapter 16 Revision History T able 16.1 Customer Revision History REVISION LEVEL & DATE SECTI ON/FIGURE/ENTRY CORRECTION Rev . 1.9 (07-17-08) All Updated document references to Rev . C. Rev . 1.9 (07-17-08) Section 13.1, &quo[...]