Texas Instruments TMS320C6454 manuel d'utilisation

www.ti.com PRODUCT PREVIEW 1 TMS320C6454 Fixed-Point Digital Signal Processor 1.1 Features TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 • 32-Bit DDR2 Memory Controller (DDR2-533 • High-Performance Fixed-Point DSP (C6454) SDRAM) – 1.39-, 1.17-, and 1-ns Instruction Cycle Time • EDMA3 Cont[...]

www.ti.com PRODUCT PREVIEW 1.1.1 ZTZ/GTZ BGA Package (Bottom View) ZTZ/GTZ 697-PIN BALL GRID ARRA Y (BGA) P ACKAGE ( BOTT OM VIEW ) A 2 B 1 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 27 28 29 AG AH AJ NOTE: The ZTZ mechanical package designator represents the version of th[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles the multi[...]

www.ti.com PRODUCT PREVIEW 1.3 Functional Block Diagram L2 Memory Controller (Memory Protect/ Bandwidth Mgmt) DDR2 Mem Ctlr System (B) C64x+ DSP Core Data Path B B Register File B31−B16 B15−B0 Instruction Fetch Data Path A A Register File A31−A16 A15−A0 Device Configuration Logic .L1 .S1 .M1 xx xx .D1 .D2 .M2 xx xx .S2 .L2 64 SBSRAM SRAM L1[...]

www.ti.com PRODUCT PREVIEW Contents TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 1 TMS320C6454 Fixed-Point Digital Signal 5.5 Megamodule Resets ................................ 81 Processor .................................................. 1 5.6 Megamodule Revision .............................[...]

www.ti.com PRODUCT PREVIEW 2 Device Overview 2.1 Device Characteristics TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-1 , provides an overview of the C6454 DSP. The tables show significant features of the C6454 device, including the capacity of on-chip RAM, the peripherals, the CPU freque[...]

www.ti.com PRODUCT PREVIEW 2.2 CPU (DSP Core) Description TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-1. Characteristics of the C6454 Processor (continued) HARDWARE FEATURES C6454 TMX320C6454ZTZ7, (For more details on the C64x+™ DSP part Device Part Numbers TMX320C6454ZTZ8, numbering,[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Other new features include: • SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the co[...]

www.ti.com PRODUCT PREVIEW src2 src2 .D1 .M1 .S1 .L1 long src odd dst src2 src1 src1 src1 src1 even dst even dst odd dst dst1 dst src2 src2 src2 long src DA1 ST1b LD1b LD1a ST1a Data path A Odd register file A (A1, A3, A5...A31) Odd register file B (B1, B3, B5...B31) .D2 src1 dst src2 DA2 LD2a LD2b src2 .M2 src1 dst1 .S2 src1 even dst long src odd [...]

www.ti.com PRODUCT PREVIEW 2.3 Memory Map Summary TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-2 shows the memory map address ranges of the C6454 device. The external memory configuration register address ranges in the C6454 device begin at the hex address location 0x7000 0000 for EMIFA [...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-2. C6454 Memory Map Summary (continued) MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE Reserved 256M 2000 0000 - 2FFF FFFF McBSP 0 Data 256 3000 0000 - 3000 00FF Reserved 64M - 256 3000 0100 - 33FF FFF[...]

www.ti.com PRODUCT PREVIEW 2.4 Boot Sequence 2.4.1 Boot Modes Supported TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The boot sequence is a process by which the DSP's internal memory is loaded with program and data sections and the DSP's internal registers are programmed with predeterm[...]

www.ti.com PRODUCT PREVIEW 2.4.2 2nd-Level Bootloaders TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 such as Code Composer Studio. For the PCI host boot, the CPU is out of reset, but it executes an IDLE instruction until a DSP interrupt is generated by the host. The host can generate a DSP interr[...]

www.ti.com PRODUCT PREVIEW 2.5 Pin Assignments 2.5.1 Pin Map AG AF AE AD AC AB AA Y W V U T R 13 12 1 1 10 9 8 7 6 5 4 3 2 1 13 12 1 1 10 9 8 7 6 5 4 3 2 1 CLKR1/ GP[0] HD15/ AD15 HD2/ AD2 PGNT/ GP[12] HD22/ AD22 DV DD 33 RSV15 PIDSEL RSV16 HDS1/ PSERR HINT/ PFRAME DV DD 33 HHWIL/ PCLK V SS HD12/ AD12 HD24/ AD24 RSV03 HD20/ AD20 HD18/ AD18 HD6/ AD6[...]

www.ti.com PRODUCT PREVIEW AG AF AE AD AC AB AA Y W V U T R 17 18 19 20 21 22 23 24 25 26 27 28 29 17 18 19 20 21 22 23 24 25 26 27 28 29 SDA AED27 V SS ASADS/ ASRE AED17 AHOLD PLL V1 AEA13/ LENDIAN AEA4/ SYSCLKOUT _EN AEA5/ MCBSP1 _EN AEA6/ PCI66 AECLKOUT ACE5 ACE4 ABA0/ DDR2_EN ABE7 ACE2 RSV41 AAOE/ ASOE RSV42 RSV44 ABE2 ABE0 AED29 AED31 ACE3 AEA[...]

www.ti.com PRODUCT PREVIEW C D E F G H J K L M N P 17 18 19 20 21 22 23 24 25 26 27 28 29 17 18 19 20 21 22 23 24 25 26 27 28 29 RSV09 AED52 DV DD 33 V SS V SS V SS AECLKIN AEA9/ MACSEL0 CLKIN1 DV DD 33 AEA15/ AECLKIN _SEL AED40 AED44 AED42 AED34 ABE6 AED32 ABE4 AEA18/ BOOT MODE2 AED37 ABUSREQ AED46 AEA16/ BOOT MODE0 AEA19/ BOOT MODE3 AHOLDA AEA10/[...]

www.ti.com PRODUCT PREVIEW A D E F G H J K L M N P 13 12 1 1 10 9 8 7 6 5 4 3 2 1 13 12 1 1 10 9 8 7 6 5 4 3 2 1 RGRXD2 RGTXD3 DV DD 33 MTXD2 V SS MTXD0/ RMTXD0 CV DD MON MTXD6 V SS PREQ/ GP[15] PINT A/ GP[14] MRXD2 MRXD3 MRXD0/ RMRXD0 V SS MTXD3 MCOL MRXD5 MTXD1/ RMTXD1 DV DD 15 MTXD4 MCRS/ RMCRSDV PTRDY MTXD7 MTCLK/ RMREFCLK MDCLK RGRXD3 DV DD 18[...]

www.ti.com PRODUCT PREVIEW 2.6 Signal Groups Description TRST IEEE Standard 1 149.1 (JT AG) Emulation Reserved Reset and Interrupts Control/Status TDI TDO TMS TCK NMI RESET RSV03 RSV04 Clock/PLL1 and PLL Controller CLKIN1 EMU0 EMU1 SYSCLK4/GP[1] (A) EMU14 EMU15 EMU16 EMU17 RSV02 EMU18 RSV06 RSV07 RSV05 RSV77 RSV78 RSV76 • • • • • • RESE[...]

www.ti.com PRODUCT PREVIEW A. This pin functions as GP[1] by default. For more details, see the Device Configuration section of this document. B. These McBSP1 peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO peripheral pins. For more details, see the Device Configuration section of this document.[...]

www.ti.com PRODUCT PREVIEW ACE4 (A ) AECLKOUT AED[63:0] ACE3 (A ) ACE2 (A ) AEA[19:0] AARDY Data Memory Map Space Select Address Byte Enables 64 20 External Memory I/F Control EMIF A (64-bit Data Bus) AECLKIN AHOLD AHOLDA ABUSREQ Bus Arbitration ABE3 ABE2 ABE1 ABE0 ASWE/AA WE DDR2CLKOUT DED[31:0] DCE0 DEA[13:0] Data Memory Map Space Select Address [...]

www.ti.com PRODUCT PREVIEW McBSPs (Multichannel Buffered Serial Ports) (B) CLKX0 FSX0 DX0 CLKR0 FSR0 DR0 T ransmit McBSP0 Receive Clock CLKX1/GP[3] FSX1/GP[1 1] DX1/GP[9] CLKR1/GP[0] FSR1/GP[10] DR1/GP[8] T ransmit McBSP1 Receive Clock HHWIL/PCLK HCNTL0/PST OP HCNTL1/PDEVSEL Data Register Select Half-W ord Select Control HPI (A ) (Host-Port Interfa[...]

www.ti.com PRODUCT PREVIEW RGTXCTL, RGRXCTL MRXER/RMRXER, MRXDV , MCRS/RMCRSDV , MCOL, MTXEN/RMTXEN Ethernet MAC (EMAC) and MDIO MDIO MDCLK MDIO Clock Clocks Error Detect and Control Input/Output Receive RGMDIO RGMDCLK RGTXD[3:0] A. RGMII signals are mutually exclusive to all other EMAC signals. RGTXC, RGRXC, RGREFCLK MTXD[7:2], MTXD[1:0]/RMTXD[1:0[...]

www.ti.com PRODUCT PREVIEW HD[15:0]/AD[15:0] HR/W/PCBE2 HDS2/PCBE1 PCBE0 /GP[2] HHWIL/PCLK HINT/PFRAME PINT A/GP[14] Data/Address Arbitration 32 Clock Control PCI Interface (A) HAS/PP AR PRST/GP[13] HRDY/PIRDY HCNTL0/PST OP PTRDY PCBE3 PIDSEL HCNTL1/PDEVSEL HDS1/PSERR Error Command Byte Enable HCS/PPERR PGNT/GP[12] PREQ/GP[15] HD[31:16]/AD[31:16] A[...]

www.ti.com PRODUCT PREVIEW 2.7 Terminal Functions TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The terminal functions table ( Table 2-3 ) identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. Nonmaskable interrupt, edge-driven (rising edge) Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin NMI[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. PTRDY P4 I/O/Z PCI target ready ( PRTDY) ( I/O/Z ). By default, this pin has no function. HD31/AD31 AA3 HD30/AD30 AA5 HD29/AD29 AC4 H[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. ACE5 V27 O/Z IPU EMIFA memory space enables ACE4 V28 O/Z IPU • Enabled by bits 28 through 31 of the word address ACE3 W26 O/Z IPU ?[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. EMIFA (64-BIT) - ADDRESS AEA19/BOOTMODE3 N25 EMIFA external address (word address) ( O/Z ) Controls initialization of the DSP modes a[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. AEA10/MACSEL1 M25 • EMAC/MDIO interface select bits (MACSEL[1:0]) There are two configuration pins — MACSEL[1:0] — to select th[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. EMIFA (64-BIT) - DATA AED63 F25 AED62 A27 AED61 C27 AED60 C28 AED59 E27 AED58 D28 AED57 D27 AED56 F27 AED55 G25 AED54 G26 AED53 A28 A[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. AED21 AD29 AED20 AJ28 AED19 AF29 AED18 AH28 AED17 AE29 AED16 AG28 AED15 AF28 AED14 AH26 AED13 AE28 AED12 AE26 AED11 AD26 I/O/Z IPU EM[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. DSDDQS3 E23 I/O/Z DSDDQS2 E20 I/O/Z DDR2 Memory Controller data strobe [3:0] positive DSDDQS1 E8 I/O/Z DSDDQS0 E11 I/O/Z DSDDQS3 D23 [...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. DDR2 MEMORY CONTROLLER (32-BIT) - DATA DED31 B25 DED30 A25 DED29 B24 DED28 A24 DED27 D22 DED26 C22 DED25 B22 DED24 A22 DED23 D21 DED2[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. MULTICHANNEL BUFFERED SERIAL PORT 1 AND MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP1 and McBSP0) McBSP external clock source (as oppos[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. This pin is the EMAC collision sense (MCDL) ( I ) for MII [default] or GMII. MCOL K3 I/O/Z MACSEL[1:0] dependent. This pin is either [...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. Reserved. This pin must be connected to the 1.8-V I/O supply (DV DD18 ) via a 200- Ω resistor for proper device operation. NOTE: If[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. RSV17 AE21 A RSV18 E13 A RSV19 F18 A RSV20 U29 A RSV21 A6 A RSV22 B26 O RSV23 C26 O RSV24 B6 O RSV25 C6 O RSV26 AJ11 A RSV27 AH11 A R[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. Reserved. This pin must be connected to the 1.8-V I/O supply (DV DD18 ) via a RSV34 E6 1-k Ω resistor for proper device operation. [...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. (DV DD15 /2)-V reference for HSTL buffer (EMAC RGMII). V REFHSTL can be generated directly from DV DD15 using two 1-k Ω resistors t[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. A29 E26 E28 G2 H23 H28 J6 J24 K1 K7 K23 L24 M7 M23 M28 N24 P6 P28 R1 R6 R23 DV DD33 T7 S 3.3-V I/O supply voltage T24 U23 V1 V7 V24 W[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. AD5 AD7 AD14 AD18 AD22 AD24 AE6 AE8 AE15 AF1 AF16 DV DD33 AF24 S 3.3-V I/O supply voltage AG12 AG17 AG23 AH14 AH16 AH24 AJ1 AJ7 AJ15 [...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. R18 T11 T13 T15 T17 T19 U12 CV DD S 1.2-V core supply voltage U14 U18 V11 V13 V19 W12 W14 GROUND PINS A8 A11 A20 A23 B1 B29 C5 D1 E5 [...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. F20 F22 F24 G1 G5 G7 G9 G11 G13 G15 G17 G19 G21 G23 H6 H24 V SS GND Ground pins H29 J7 J23 K2 K6 K24 L7 L11 L13 L15 L17 L19 L23 M6 M1[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. M16 M18 M24 M26 M29 N2 N13 N15 N17 N19 N23 P7 P12 P14 P16 P18 P29 V SS GND Ground pins R2 R7 R11 R13 R15 R17 R19 R24 T6 T12 T14 T16 T[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. U15 U17 U19 U24 V2 V6 V12 V14 V16 V18 V23 W7 W11 W13 W15 W17 V SS GND Ground pins W19 W24 Y6 Y23 AA2 AA7 AA24 AB6 AB23 AC7 AC8 AC10 A[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. AC20 AC22 AC24 AC28 AD6 AD13 AD15 AD17 AD19 AD21 AD23 AE4 AE7 AE16 AE18 AE20 AE22 AE24 V SS GND Ground pins AF2 AF19 AF21 AG13 AG16 A[...]

www.ti.com PRODUCT PREVIEW 2.8 Development 2.8.1 Development Support 2.8.2 Device Support TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 In case the customer would like to develop their own features and software on the C6454 device, TI offers an extensive line of development tools for the TMS320C6[...]

www.ti.com PRODUCT PREVIEW C64x+ t DSP: C6454 PREFIX TMX 320 C6454 ZTZ TMX = Experimental device TMS = Qualified device DEVICE F AMIL Y 320 = TMS320 t DSP family P ACKAGE TYPE (A) ZTZ = 697-pin plastic BGA, with Pb-Free solder balls GTZ = 697-pin plastic BGA, with Pb-ed solder balls DEVICE A. BGA = Ball Grid Array DEVICE SPEED RANGE 7 = 720 MHz 8 =[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 objective of this document is to indicate differences between the two cores. Functionality in the devices that is identical is not included. SPRU889 High-Speed DSP Systems Design Reference Guide. Provides recommendations for[...]

www.ti.com PRODUCT PREVIEW 3 Device Configuration 3.1 Device Configuration at Device Reset TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 On the C6454 device, certain device configurations like boot mode, pin multiplexing, and endianess, are selected at device reset. The status of the peripherals [...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 3-1. C6454 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN) (continued) CONFIGURATION IPD/ NO. FUNCTIONAL DESCRIPTION PIN IPU (1) HPI peripheral bus width select (HPI_WIDTH). 0 HPI operates in HPI16 mode (de[...]

www.ti.com PRODUCT PREVIEW 3.2 Peripheral Configuration at Device Reset TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 3-1. C6454 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN) (continued) CONFIGURATION IPD/ NO. FUNCTIONAL DESCRIPTION PIN IPU (1) PCI pin function enable bit (PCI[...]

www.ti.com PRODUCT PREVIEW 3.3 Peripheral Selection After Device Reset TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 3-2. PCI_EN, PCI66, PCI_EEAI, and HPI_WIDTH Peripheral Selection (HPI and PCI) (continued) CONFIGURATION PIN SETTING (1) PERIPHERAL FUNCTION SELECTED PCI66 PCI_EEAI HPI_WIDTH[...]

www.ti.com PRODUCT PREVIEW Reset Static Powerdown Disabled Enable In Progress Enabled Unlock the PERCFG0 register by using the PERLOCK register . W rite to the PERCFG0 register within 16 SYSCLK3 clock cycles to change the state of the peripherals. Poll the PERST A T registers to verify state change. TMS320C6454 Fixed-Point Digital Signal Processor [...]

www.ti.com PRODUCT PREVIEW 3.4 Device State Control Registers TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The C6454 device has a set of registers that are used to control the status of its peripherals. These registers are shown in Table 3-5 and described in the next sections. NOTE The device st[...]

www.ti.com PRODUCT PREVIEW 3.4.1 Peripheral Lock Register Description TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 When written with correct 32-bit key (0x0F0A0B00), the Peripheral Lock Register (PERLOCK) allows one write to the PERCFG0 register within 16 SYSCLK3 cycles. NOTE The instructions th[...]

www.ti.com PRODUCT PREVIEW 3.4.2 Peripheral Configuration Register 0 Description TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The Peripheral Configuration Register (PERCFG0) is used to change the state of the peripherals. One write is allowed to this register within 16 SYSCLK3 cycles after the c[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 3-7. Peripheral Configuration Register 0 (PERCFG0) Field Descriptions (continued) Bit Field Value Description 12 I2CCTL Mode control for I2C 0 Set I2C to disabled mode 1 Set I2C to enabled mode 11 Reserved Reserved. 10[...]

www.ti.com PRODUCT PREVIEW 3.4.3 Peripheral Configuration Register 1 Description TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The Peripheral Configuration Register (PERCFG1) is used to enable the EMIFA and DDR2 Memory Controller. EMIFA and the DDR2 Memory Controller do not have corresponding sta[...]

www.ti.com PRODUCT PREVIEW 3.4.4 Peripheral Status Registers Description TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The Peripheral Status Registers (PERSTAT0 and PERSTAT1) show the status of the C6454 peripherals. 31 30 29 27 26 24 Reserved HPISTAT McBSP1STAT R-0 R-0 R-0 23 21 20 18 17 16 McBS[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 3-9. Peripheral Status Register 0 (PERSTAT0) Field Descriptions (continued) Bit Field Value Description 17:15 GPIOSTAT GPIO status 000 GPIO is in the disabled state 001 GPIO is in the enabled state 011 GPIO is in the s[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 31 16 Reserved R-0 15 3 2 0 Reserved PCISTAT R-0 R-0 LEGEND: R = Read only; - n = value after reset Figure 3-7. Peripheral Status Register 1 (PERSTAT1) - 0x02AC 0018 Table 3-10. Peripheral Status Register 1 (PERSTAT1) Field [...]

www.ti.com PRODUCT PREVIEW 3.4.5 EMAC Configuration Register (EMACCFG) Description TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The EMAC Configuration Register (EMACCFG) is used to assert and deassert the reset of the Reduced Media Independent Interface (RMII) logic of the EMAC. For more details[...]

www.ti.com PRODUCT PREVIEW 3.4.6 Emulator Buffer Powerdown Register (EMUBUFPD) Description TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The Emulator Buffer Powerdown Register (EMUBUFPD) is used to control the state of the pin buffers of emulator pins EMU[18:2]. These buffers can be powered down [...]

www.ti.com PRODUCT PREVIEW 3.5 Device Status Register Description TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The device status register depicts the device configuration selected upon device reset. Once set, these bits will remain set until a device reset. For the actual register bit names and [...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 3-13. Device Status Register (DEVSTAT) Field Descriptions (continued) Bit Field Value Description 14 MCBSP1_EN McBSP1 Enable (MCBSP1_EN) status bit Shows the status of which function is enabled on the McBSP1/GPIO muxed[...]

www.ti.com PRODUCT PREVIEW 3.6 JTAG ID (JTAGID) Register Description 3.7 Pullup/Pulldown Resistors TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 3-13. Device Status Register (DEVSTAT) Field Descriptions (continued) Bit Field Value Description 3:0 BOOTMODE[3:0] Boot mode configuration bits S[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 • Other Input Pins : If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail. For the device configuration pins (listed in Table 3-1 ), if the[...]

www.ti.com PRODUCT PREVIEW 3.8 Configuration Examples Shading denotes a peripheral module not available for this configuration. McBSP0 TIMER0 EMIF A GPIO PLL2 and PLL2 Controller TIMER1 PLL1 and PLL1 Controller DDR2 EMIF AED[63:0] 64 AECLKIN, AARDY , AHOLD AEA[22:3], ACE[3:0] , ABE[7:0] , AECLKOUT , ASDCKE, AHOLDA , ABUSREQ, ASADS /ASRE , AAOE /ASO[...]

www.ti.com PRODUCT PREVIEW Shading denotes a peripheral module not available for this configuration. McBSP0 TIMER0 EMIF A GPIO TIMER1 PLL1 and PLL1 Controller DDR2 EMIF AED[63:0] 64 AECLKIN, AARDY , AHOLD AEA[22:3], ACE[3:0] , ABE[7:0] , AECLKOUT , ASDCKE, AHOLDA , ABUSREQ, ASADS /ASRE , AAOE /ASOE , AA WE /ASWE SCL SDA CLKIN1, PLL V1 SYSCLK4 HRDY [...]

www.ti.com PRODUCT PREVIEW 4 System Interconnect 4.1 Internal Buses, Bridges, and Switch Fabrics TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 On the C6454 device, the C64x+ Megamodule, the EDMA3 transfer controllers, and the system peripherals are interconnected through two switch fabrics. The s[...]

www.ti.com PRODUCT PREVIEW 4.2 Data Switch Fabric Connections TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Figure 4-1 shows the connection between slaves and masters through the data switched central resource (SCR). Masters are shown on the right and slaves on the left. The data SCR connects mas[...]

www.ti.com PRODUCT PREVIEW EMAC HPI M M 128-bit (SYSCLK2) M3 M0 S M M M McBSPs S DDR2 Memory Controller S EMIF A S PCI S MASTER S M Bridge CFG SCR S Bridge PCI M EDMA3 Channel Controller EDMA3 Transfer Controllers Megamodule M1 M2 S3 S0 S1 S2 S S Events M Megamodule Data SCR 128 (SYSCLK2) 128 (SYSCLK2) 128 (SYSCLK2) 128 (SYSCLK2) 32 (SYSCLK3) 32 (S[...]

www.ti.com PRODUCT PREVIEW 4.3 Configuration Switch Fabric TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 4-1. SCR Connection Matrix DDR2 MEMORY McBSPs CONFIGURATION SCR PCI EMIFA MEGAMODULE CONTROLLER TC0 N N N Y Y Y TC1 Y Y Y Y Y Y TC2 N N Y Y Y Y TC3 N N Y Y Y Y EMAC N N N Y Y Y HPI N Y N[...]

www.ti.com PRODUCT PREVIEW Megamodule M CFG SCR S M McBSPs S T imers S HPI S PCI S S Bridge 7 GPIO S EMAC/MDIO M Data SCR S S I2C S S PLL Controllers (A) S S Device Configuration Registers (A) EDMA3 TC0 S EDMA3 TC1 S S EDMA3 TC2 S EDMA3 CC S S EDMA3 TC3 S M 32 (SYSCLK3) MUX 32 (SYSCLK2) 32 (SYSCLK2) 32 (SYSCLK2) 32 (SYSCLK3) 32 (SYSCLK2) 32 (SYSCLK[...]

www.ti.com PRODUCT PREVIEW 4.4 Priority Allocation TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 On the C6454 device, each of the masters (excluding the C64x+ Megamodule) are assigned a priority via the Priority Allocation Register (PRI_ALLOC), see Figure 4-3 . The priority is enforced when sever[...]

www.ti.com PRODUCT PREVIEW 5 C64x+ Megamodule A register file Data path 1 Data path 2 B register file D2 S2 xx xx M2 L2 Instruction decode M1 xx xx L1 S1 D1 16/32−bit instruction dispatch Instruction fetch SPLOOP buf fer 64 64 C64x+ CPU 256 32 L1D cache/SRAM Bandwidth management Memory protection L1 data memory controller IDMA 256 256 Bandwidth m[...]

www.ti.com PRODUCT PREVIEW 4K bytes 8K bytes 16K bytes L1P memory 00E0 0000h 00E0 4000h 00E0 6000h 00E0 7000h 00E0 8000h direct mapped SRAM 1/2 dm 3/4 SRAM SRAM 7/8 All SRAM 000 001 010 01 1 100 Block base address L1P mode bits cache 4K bytes cache direct mapped cache direct mapped cache 4K bytes 8K bytes 16K bytes L1D memory 00F0 0000h 00F0 4000h [...]

www.ti.com PRODUCT PREVIEW 32K bytes 32K bytes 64K bytes 128K bytes 792K bytes L2 memory 0080 0000h 008C 0000h 008E 0000h 008F 0000h 008F 8000h 0090 0000h 3/4 SRAM 4-way cache 4-way cache SRAM 7/8 4-way 15/16 SRAM 4-way SRAM 31/32 All SRAM 000 001 010 01 1 1 1 1 Block base address L2 mode bits cache TMS320C6454 Fixed-Point Digital Signal Processor [...]

www.ti.com PRODUCT PREVIEW 5.2 Memory Protection 5.3 Bandwidth Management TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided[...]

www.ti.com PRODUCT PREVIEW 5.4 Power-Down Control 5.5 Megamodule Resets TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The C64x+ Megamodule supports the ability to power-down various parts of the C64x+ Megamodule. The power-down controller (PDC) of the C64x+ Megamodule can be used to power down L1[...]

www.ti.com PRODUCT PREVIEW 5.6 Megamodule Revision TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The version and revision of the C64x+ Megamodule can be read from the Megamodule Revision ID Register (MM_REVID) located at address 0181 2000h. The MM_REVID register is shown in Figure 5-5 and describ[...]

www.ti.com PRODUCT PREVIEW 5.7 C64x+ Megamodule Register Description(s) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 5-4. Megamodule Interrupt Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0180 0000 EVTFLAG0 Event Flag Register 0 (Events [31:0]) 0180 0004 EVTFLAG1 Event Flag Register 1[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 5-4. Megamodule Interrupt Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0180 0184 INTXCLR Interrupt Exception Clear Register 0180 0188 INTDMASK Dropped Interrupt Mask Register 0180 0188 - 0180 01BC - Re[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 5-8. Megamodule Cache Configuration Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 0000 L2CFG L2 Cache Configuration Register 0184 0004 - 0184 001F - Reserved 0184 0020 L1PCFG L1P Configuration Register 0184 00[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 5-8. Megamodule Cache Configuration Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 8294 MAR165 Controls EMIFA CE2 Range A500 0000 - A5FF FFFF 0184 8298 MAR166 Controls EMIFA CE2 Range A600 0000 - A6[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 5-8. Megamodule Cache Configuration Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 8350 MAR212 Controls EMIFA CE5 Range D400 0000 - D4FF FFFF 0184 8354 MAR213 Controls EMIFA CE5 Range D500 0000 - D5[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 5-9. Megamodule L1/L2 Memory Protection Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 A20C L2MPPA3 L2 memory protection page attribute register 3 0184 A210 L2MPPA4 L2 memory protection page attribu[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 5-9. Megamodule L1/L2 Memory Protection Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 AD08 L1DMPLK2 L1D memory protection lock key bits [95:64] 0184 AD0C L1DMPLK3 L1D memory protection lock key bit[...]

www.ti.com PRODUCT PREVIEW 6 Device Operating Conditions 6.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise 6.2 Recommended Operating Conditions TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Noted) (1) Supply voltage range: CV DD (2) -0.5 V to 1.5 V DV DD33 (2) -[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Recommended Operating Conditions (continued) MIN NOM MAX UNIT 3.3 V pins (except PCI-capable and 0.8 V I2C pins) PCI-capable pins -0.5 0.3DV DD33 V V IL Low-level input voltage I2C pins 0 0.3DV DD33 V RGMII pins -0.3 V REFHS[...]

www.ti.com PRODUCT PREVIEW 6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Case Temperature (Unless Otherwise Noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT 3.3-V pins (except DV DD33 = MIN, PCI-capable an[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted) (continued) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT AECLKOUT, CLKR1/GP[0], CLKX1/GP[3], 8 mA[...]

www.ti.com PRODUCT PREVIEW 7 C64x+ Peripheral Information and Electrical Specifications 7.1 Parameter Information T ransmission Line 4.0 pF 1.85 pF Z0 = 50 Ω (see Note) T ester Pin Electronics Data Sheet T iming Reference Point Output Under T est NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin el[...]

www.ti.com PRODUCT PREVIEW 7.1.3 Timing Parameters and Board Routing Analysis 1 2 3 4 5 6 7 8 10 1 1 AECLKOUT (Output from DSP) AECLKOUT (Input to External Device) Control Signals (A) (Output from DSP) Control Signals (Input to External Device) Data Signals (B) (Output from External Device) Data Signals (B) (Input to DSP) 9 TMS320C6454 Fixed-Point [...]

www.ti.com PRODUCT PREVIEW 7.2 Recommended Clock and Control Signal Transition Behavior 7.3 Power Supplies 7.3.1 Power-Supply Sequencing DV DD33 CV DD12 All other power supplies 1 2 7.3.2 Power-Supply Decoupling 7.3.3 Power-Down Operation TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 All clocks a[...]

www.ti.com PRODUCT PREVIEW 7.3.4 Preserving Boundary-Scan Functionality on RGMII and DDR2 Memory Pins TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Peripherals used for booting, like I2C and HPI, are automatically enabled after device reset. It is not possible to disable these peripherals after t[...]

www.ti.com PRODUCT PREVIEW 7.4 Enhanced Direct Memory Access (EDMA3) Controller 7.4.1 EDMA3 Device-Specific Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped slave endpoints on the devi[...]

www.ti.com PRODUCT PREVIEW 7.4.2 EDMA3 Channel Synchronization Events TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The EDMA3 supports up to 64 DMA channels that can be used to service system peripherals and to move data between system memories. DMA channels can be triggered by synchronization ev[...]

www.ti.com PRODUCT PREVIEW 7.4.3 EDMA3 Peripheral Register Description(s) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-3. C6454 EDMA3 Channel Synchronization Events (continued) EDMA BINARY EVENT NAME EVENT DESCRIPTION CHANNEL 58 011 1010 GPINT10 GPIO event 10 59 011 1011 GPINT11 GPIO eve[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 0180 DCHMAP32 DMA Channel 32 Mapping Register 02A0 0184 DCHMAP33 DMA Channel 33 Mapping Register 02A0 0188 DCHMAP34 DMA C[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 0300 EMR Event Missed Register 02A0 0304 EMRH Event MissedRegister High 02A0 0308 EMCR Event Missed Clear Register 02A0 0[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 0440 Q1E0 Event Queue 1 Entry Register 0 02A0 0444 Q1E1 Event Queue 1 Entry Register 1 02A0 0448 Q1E2 Event Queue 1 Entry[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 04FC Q3E15 Event Queue 3 Entry Register 15 02A0 0500 - 02A0 051C - Reserved 02A0 0520 - 02A0 05FC - Reserved 02A0 0600 QS[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 105C IECRH Interrupt Enable Clear High Register 02A0 1060 IESR Interrupt Enable Set Register 02A0 1064 IESRH Interrupt En[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-5. EDMA3 Parameter RAM (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME ... ... 02A0 47E0 - 02A0 47FF - Parameter Set 63 02A0 4800 - 02A0 481F - Parameter Set 64 02A0 4820 - 02A0 483F - Parameter Set 65 ... ... 02[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-6. EDMA3 Transfer Controller 0 Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A2 0348 DFCNT1 Destination FIFO Count Register 1 02A2 034C DFDST1 Destination FIFO Destination Address Register 1 02A2 03[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-7. EDMA3 Transfer Controller 1 Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A2 8284 DFSRCBREF Destination FIFO Set Destination Address B Reference Register 02A2 8288 DFDSTBREF Destination FIFO Set [...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-8. EDMA3 Transfer Controller 2 Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A3 0144 - 02A3 023C - Reserved 02A3 0240 SAOPT Source Active Options Register 02A3 0244 SASRC Source Active Source Addres[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-9. EDMA3 Transfer Controller 3 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A3 8000 PID Peripheral Identification Register 02A3 8004 TCCFG EDMA3TC Configuration Register 02A3 8008 - 02A3 80FC - Reserved 02A3 8[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-9. EDMA3 Transfer Controller 3 Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A3 8394 DFMPPRXY2 Destination FIFO Memory Protection Proxy Register 2 02A3 8398 - 02A3 83BC - Reserved 02A3 83C0 DFOPT3 D[...]

www.ti.com PRODUCT PREVIEW 7.5 Interrupts 7.5.1 Interrupt Sources and Interrupt Controller TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The CPU interrupts on the C6454 device are configured through the C64x+ Megamodule Interrupt Controller. The interrupt controller allows for up to 128 system ev[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-10. C6454 DSP Interrupts (continued) EVENT NUMBER INTERRUPT EVENT INTERRUPT SOURCE 59 GPINT8 GPIO interrupt 60 GPINT9 GPIO interrupt 61 GPINT10 GPIO interrupt 62 GPINT11 GPIO interrupt 63 GPINT12 GPIO interrupt 64 GP[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-10. C6454 DSP Interrupts (continued) EVENT NUMBER INTERRUPT EVENT INTERRUPT SOURCE 125 L2_DMPA L2 DMA memory protection fault 126 IDMA_CMPA IDMA CPU memory protection fault 127 IDMA_BUSERR IDMA bus error interrupt C6[...]

www.ti.com PRODUCT PREVIEW 7.5.2 External Interrupts Electrical Data/Timing 2 1 NMI TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-11. Timing Requirements for External Interrupts (1) (see Figure 7-6 ) -720 -850 NO. UNIT -1000 MIN MAX 1 t w(NMIL) Width of the NMI interrupt pulse low 6P ns 2[...]

www.ti.com PRODUCT PREVIEW 7.6 Reset Controller 7.6.1 Power-on Reset ( POR Pin) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The reset controller detects the different type of resets supported on the C6454 device and manages the distribution of those resets throughout the device. The C6454 devic[...]

www.ti.com PRODUCT PREVIEW 7.6.2 Warm Reset ( RESET Pin) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 all the system clocks are invalid at this point. • The RESETSTAT pin stays asserted (low), indicating the device is in reset. 3. The POR pin may now be deasserted (driven high). When the POR p[...]

www.ti.com PRODUCT PREVIEW 7.6.3 System Reset 7.6.4 CPU Reset TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 4. The device is now out of reset, device execution begins as dictated by the selected boot mode (see Section 2.4 , Boot Sequence ). NOTE The POR pin should be held inactive (high) througho[...]

www.ti.com PRODUCT PREVIEW 7.6.5 Reset Priority 7.6.6 Reset Controller Register TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 If any of the above reset sources occur simultaneously, the PLLCTRL only processes the highest priority reset request. The rest request priorities are as follows (high to [...]

www.ti.com PRODUCT PREVIEW 7.6.7 Reset Electrical Data/Timing TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 NOTE If a configuration pin must be routed out from the device and 3-stated (not driven), the internal pullup/pulldown (IPU/IPD) resistor should not be relied upon; TI recommends the use of[...]

www.ti.com PRODUCT PREVIEW CLKIN1 PCLK RESET RESETST A T SYSREFCLK (PLL1C) Z Group POR SYSCLK3 SYSCLK4 SYSCLK5 AECLKOUT (Internal) Boot and Device Configuration Pins Low Group High Group CLKIN2 Internal Reset PLL2C SYSREFCLK (PLL2C) SYSCLK1 (PLL2C) SYSCLK2 5 9 7 8 Undefined Undefined Low High-Z Undefined High PLL2 Unlocked PLL2 Locked (A) PLL2 Unlo[...]

www.ti.com PRODUCT PREVIEW CLKIN1 CLKIN2 POR RESET (A)(B) RESETST A T Boot and Device Configuration Pins (C) 9 7 6 8 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 A. RESET should only be used after device has been powered up. For more details on the use of the RESET pin, see Section 7.6 , Reset C[...]

www.ti.com PRODUCT PREVIEW 7.7 PLL1 and PLL1 Controller TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The primary PLL controller generates the input clock to the C64x+ megamodule (including the CPU) as well as most of the system peripherals such as the multichannel buffered serial ports (McBSPs) [...]

www.ti.com PRODUCT PREVIEW 1 0 0 1 DIVIDER D4 CLKIN1 (B) PLLEN (PLLCTL.[0]) SYSCLK2 SYSCLK3 AECLKIN (External EMIF Clock Input) EMIF A DIVIDER PREDIV DIVIDER D2 (A) DIVIDER D3 (A) AECLKOUT PLL V1 C2 C1 EMI Filter +1.8 V 560 pF 0.1 m F SYSCLK5 (Emulation and T race) SYSREFCLK (C64x+ MegaModule) AECLKINSEL (AEA[15] pin) DIVIDER D5 PLL1 Controller (EM[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 • SYSCLK4 is used as the internal clock for the EMIFA. It is also used to clock other logic within the DSP. • SYSCLK5 clocks the emulation and trace logic of the DSP. The divider ratio bits of dividers D2 and D3 are fixe[...]

www.ti.com PRODUCT PREVIEW 7.7.2 PLL1 Controller Memory Map TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1 with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). [...]

www.ti.com PRODUCT PREVIEW 7.7.3 PLL1 Controller Register Descriptions TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 This section provides a description of the PLL1 controller registers. For details on the operation of the PLL controller module, see the TMS320C645x DSP Software-Programmable Phase[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.2 PLL Multiplier Control Register The PLL multiplier control register (PLLM) is shown in Figure 7-12 and described in Table 7-20 . The PLLM register defines the input reference clock frequency multiplier in conjunction[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.3 PLL Pre-Divider Control Register The PLL pre-divider control register (PREDIV) is shown in Figure 7-13 and described in Table 7-21 . 31 16 Reserved R-0 15 14 5 4 0 PREDEN Reserved RATIO R/W-1 R-0 R/W-2h LEGEND: R/W =[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.4 PLL Controller Divider 4 Register The PLL controller divider 4 register (PLLDIV4) is shown in Figure 7-14 and described in Table 7-22 . Besides being used as the EMIFA internal clock, SYSCLK4 is also used in other pa[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.5 PLL Controller Divider 5 Register The PLL controller divider 5 register (PLLDIV5) is shown in Figure 7-15 and described in Table 7-23 . 31 16 Reserved R-0 15 14 5 4 0 D5EN Reserved RATIO R/W-1 R-0 R/W-3 LEGEND: R/W =[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.6 PLL Controller Command Register The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is shown in Figure 7-16 and described in Table 7-24 . 31 16 Reserved R-0 15 2 1 0 Reserve[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.7 PLL Controller Status Register The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in Figure 7-17 and described in Table 7-25 . 31 16 Reserved R-0 15 1 0 Reserved GOSTAT R-0[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.8 PLL Controller Clock Align Control Register The PLL controller clock align control register (ALNCTL) is shown in Figure 7-18 and described in Table 7-26 . 31 16 Reserved R-0 15 5 4 3 2 0 Reserved ALN5 ALN4 Reserved R[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.9 PLLDIV Ratio Change Status Register Whenever a different ratio is written to the PLLDIV n registers, the PLLCTRL flags the change in the PLLDIV ratio change status registers (DCHANGE). During the GO operation, the PL[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.10 SYSCLK Status Register The SYSCLK status register (SYSTAT) shows the status of the system clocks (SYSCLK n ). SYSTAT is shown in Figure 7-20 and described in Table 7-28 . 31 16 Reserved R-0 15 8 Reserved R-0 7 54321[...]

www.ti.com PRODUCT PREVIEW 7.7.4 PLL1 Controller Input and Output Clock Electrical Data/Timing CLKIN1 2 3 4 4 5 1 SYSCLK4 3 4 4 2 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-29. Timing Requirements for CLKIN1 Devices (1) (2) (3) (see Figure 7-21 ) -720 -850 -1000 NO. PLL MODES UNIT x1 ([...]

www.ti.com PRODUCT PREVIEW 7.8 PLL2 and PLL2 Controller PLL V2 PLL2 SYSCLK2 (From PLL1 Controller) SYSCLK1 DDR2 Memory Controller EMAC CLKIN2 (B)(C) C162 560 pF EMI Filter +1.8 V C161 0.1 pF PLL2 Controller TMS320C6454 DSP PLLM x20 /2 1 0 /x (A ) 1 SYSREFCLK SYSCLK3 (From PLL1 Controller) PLLREF PLLOUT DIVIDER D1 TMS320C6454 Fixed-Point Digital Sig[...]

www.ti.com PRODUCT PREVIEW 7.8.1 PLL2 Controller Device-Specific Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.8.1.1 Internal Clocks and Maximum Operating Frequencies As shown in Figure 7-23 , the output of PLL2, PLLOUT, is divided by 2 and directly fed to the DDR2 memory controller[...]

www.ti.com PRODUCT PREVIEW 7.8.2 PLL2 Controller Memory Map 7.8.3 PLL2 Controller Register Descriptions TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The memory map of the PLL2 controller is shown in Table 7-32 . Note that only registers documented here are accessible on the TMS320C6454. Other ad[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.8.3.1 PLL Controller Divider 1 Register The PLL controller divider 1 register (PLLDIV1) is shown in Figure 7-24 and described in Table 7-33 . 31 16 Reserved R-0 15 14 5 4 0 D1EN Reserved RATIO R/W-1 R-0 R/W-1 LEGEND: R/W =[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.8.3.2 PLL Controller Command Register The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is shown in Figure 7-25 and described in Table 7-34 . 31 16 Reserved R-0 15 2 1 0 Reserve[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.8.3.3 PLL Controller Status Register The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in Figure 7-26 and described in Table 7-35 . 31 16 Reserved R-0 15 1 0 Reserved GOSTAT R-0[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.8.3.5 PLLDIV Ratio Change Status Register Whenever a different ratio is written to the PLLDIV1 register, the PLLCTRL flags the change in the DCHANGE status register. During the GO operation, the PLL controller will only ch[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.8.3.6 SYSCLK Status Register The SYSCLK status register (SYSTAT) shows the status of the system clock (SYSCLK1). SYSTAT is shown in Figure 7-29 and described in Table 7-38 . 31 16 Reserved R-0 15 1 0 Reserved SYS1ON R-0 R-[...]

www.ti.com PRODUCT PREVIEW 7.8.4 PLL2 Controller Input Clock Electrical Data/Timing CLKIN2 2 3 4 4 5 1 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-39. Timing Requirements for CLKIN2 (1) (2) (3) (see Figure 7-30 ) -720 -850 NO. UNIT -1000 MIN MAX 1 t c(CLKIN2) Cycle time, CLKIN2 37.5 80 [...]

www.ti.com PRODUCT PREVIEW 7.9 DDR2 Memory Controller 7.9.1 DDR2 Memory Controller Device-Specific Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The 32-bit DDR2 Memory Controller bus of the C6454 is used to interface to JESD79D-2A standard-compliant DDR2 SDRAM devices. The DDR2 extern[...]

www.ti.com PRODUCT PREVIEW 7.9.2 DDR2 Memory Controller Peripheral Register Description(s) 7.9.3 DDR2 Memory Controller Electrical Data/Timing TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-40. DDR2 Memory Controller Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 7800 0000 MIDR DDR2 Mem[...]

www.ti.com PRODUCT PREVIEW 7.10 External Memory Interface A (EMIFA) 7.10.1 EMIFA Device-Specific Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The EMIFA can interface to a variety of external devices or ASICs, including: • Pipelined and flow-through Synchronous-Burst SRAM (SBSRAM) ?[...]

www.ti.com PRODUCT PREVIEW 7.10.2 EMIFA Peripheral Register Description(s) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-41. EMIFA Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 7000 0000 MIDR Module ID and Revision Register 7000 0004 STAT Status Register 7000 0008 - Reserved 7000 000C[...]

www.ti.com PRODUCT PREVIEW 7.10.3 EMIFA Electrical Data/Timing AECLKIN 2 3 4 4 5 1 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-42. Timing Requirements for AECLKIN for EMIFA (1) (2) (see Figure 7-31 ) -720 -850 NO. UNIT -1000 MIN MAX 1 t c(EKI) Cycle time, AECLKIN 6 (3) 40 ns 2 t w(EKIH)[...]

www.ti.com PRODUCT PREVIEW 4 5 1 2 AECLKIN AECLKOUT1 3 3 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-43. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the EMIFA Module (1) (2) (3) (see Figure 7-32 ) -720 -850 NO. PARAMETER UNIT -1000 MIN MAX 1 t c(EKO)[...]

www.ti.com PRODUCT PREVIEW AECLKOUT ACEx ABE[7:0] AEA[19:0]/ ABA[1:0] AED[63:0] AAOE/ASOE ( A) AR/W AA WE/ASWE ( A) AARDY (B ) Byte Enables Address Read Data Hold = 1 2 Strobe = 4 Setup = 1 2 2 4 10 10 1 1 1 3 A AAOE/ASOE and AAWE /ASWE operate as AAOE (identified under select signals) and AA WE , respectively , during asynchronous memory accesses.[...]

www.ti.com PRODUCT PREVIEW AECLKOUT ACEx ABE[7:0] AEA[19:0]/ ABA[1:0] AED[63:0] AAOE/ASOE (A ) AR/W AA WE/ASWE ( A) AARDY (B ) Byte Enables Address W rite Data Hold = 1 12 Strobe = 4 Setup = 1 12 12 12 12 13 13 1 1 1 1 1 1 1 1 1 1 A AAOE/ASOE and AA WE /ASWE operate as AAOE (identified under select signals) and AA WE , respectively , during asynchr[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.10.3.2 Programmable Synchronous Interface Timing Table 7-46. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module (see Figure 7-36 ) -720 -850 NO. UNIT -1000 MIN MAX 6 t su(EDV-EKOH) Setup tim[...]

www.ti.com PRODUCT PREVIEW AECLKOUT ACEx ABE[7:0] AEA[19:0]/ABA[1:0] AED[63:0] ASADS/ASRE (B) AAOE/ASOE (B ) AA WE/ASWE ( B) BE1 BE2 BE3 BE4 Q1 Q2 Q3 9 1 4 5 8 9 6 7 3 1 2 BE1 BE2 BE3 BE4 EA1 EA2 EA4 8 READ latency = 2 EA3 A The following parameters are programmable via the EMIF A Chip Select n Configuration Register (CESECn): − Read latency (R_L[...]

www.ti.com PRODUCT PREVIEW AECLKOUT ACEx ABE[7:0] AEA[19:0]/ABA[1:0] AED[63:0] ASADS/ASRE (B) AAOE/ASOE (B) AA WE /ASWE (B) BE1 BE2 BE3 BE4 Q1 Q2 Q3 1 1 3 12 10 4 2 1 8 5 8 EA1 EA2 EA3 EA4 10 W rite Latency = 1 (B) 1 Q4 12 A The following parameters are programmable via the EMIF A Chip Select n Configuration Register (CESECn): − Read latency (R_L[...]

www.ti.com PRODUCT PREVIEW 7.10.4 HOLD/ HOLDA Timing HOLD HOLDA EMIF Bus (A) DSP Owns Bus External Requestor Owns Bus DSP Owns Bus DSP DSP 1 3 2 5 4 AECLKOUT TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-48. Timing Requirements for the HOLD/ HOLDA Cycles for EMIFA Module (1) (see Figure 7[...]

www.ti.com PRODUCT PREVIEW 7.10.5 BUSREQ Timing AECLKOUTx 1 ABUSREQ 1 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-50. Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles for EMIFA Module (see Figure 7-40 ) -720 -850 NO. PARAMETER UNIT -1000 MIN MAX 1 t [...]

www.ti.com PRODUCT PREVIEW 7.11 I2C Peripheral 7.11.1 I2C Device-Specific Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The inter-integrated circuit (I2C) module provides an interface between a C64x+ DSP and other devices compliant with Philips Semiconductors Inter-IC bus (I 2 C bus) [...]

www.ti.com PRODUCT PREVIEW Clock Prescale I2CPSC Peripheral Clock (CPU/6) I2CCLKH Generator Bit Clock I2CCLKL Noise Filter SCL I2CXSR I2CDXR T ransmit T ransmit Shift T ransmit Buffer I2CDRR Shift I2CRSR Receive Buffer Receive Receive Filter SDA I2C Data Noise I2COAR I2CSAR Slave Address Control Address Own I2CMDR I2CCNT Mode Data Count V ector Int[...]

www.ti.com PRODUCT PREVIEW 7.11.2 I2C Peripheral Register Description(s) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-51. I2C Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02B0 4000 ICOAR I2C own address register 02B0 4004 ICIMR I2C interrupt mask/status register 02B0 4008 ICSTR I2C [...]

www.ti.com PRODUCT PREVIEW 7.11.3 I2C Electrical Data/Timing TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.11.3.1 Inter-Integrated Circuits (I2C) Timing Table 7-52. Timing Requirements for I2C Timings (1) (see Figure 7-42 ) -720 -850 -1000 NO. UNIT STANDARD MODE FAST MODE MIN MAX MIN MAX 1 t c([...]

www.ti.com PRODUCT PREVIEW 10 8 4 3 7 12 5 6 14 2 3 13 Stop Start Repeated Start Stop SDA SCL 1 1 1 9 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Figure 7-42. I2C Receive Timings Table 7-53. Switching Characteristics for I2C Timings (1) (see Figure 7-43 ) -720 -850 -1000 NO. PARAMETER UNIT STAN[...]

www.ti.com PRODUCT PREVIEW 25 23 19 18 22 27 20 21 17 18 28 Stop Start Repeated Start Stop SDA SCL 16 26 24 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Figure 7-43. I2C Transmit Timings Submit Documentation Feedback C64x+ Peripheral Information and Electrical Specifications 165[...]

www.ti.com PRODUCT PREVIEW 7.12 Host-Port Interface (HPI) Peripheral 7.12.1 HPI Device-Specific Information 7.12.2 HPI Peripheral Register Description(s) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The C6454 device includes a user-configurable 16-bit or 32-bit Host-port interface (HPI16/HPI32).[...]

www.ti.com PRODUCT PREVIEW 7.12.3 HPI Electrical Data/Timing TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-55. Timing Requirements for Host-Port Interface Cycles (1) (2) (see Table 7-56 through Figure 7-51 ) -720 -850 NO. UNIT -1000 MIN MAX 9 t su(HASL-HSTBL) Setup time, HAS low before HS[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-56. Switching Characteristics for Host-Port Interface Cycles (1) (2) (see Table 7-56 through Figure 7-51 ) -720 -850 NO. PARAMETER UNIT -1000 MIN MAX Case 1. HPIC or HPIA read 5 15 Case 2. HPID read with no 9 * M + 2[...]

www.ti.com PRODUCT PREVIEW HCS HAS HCNTL[1:0] HR/W HHWIL HSTROBE (A ) HD[15:0] HRDY (B) 16 15 37 13 14 16 15 37 13 3 1 2 3 1 2 38 7 4 6 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT( HDS1 XOR HDS2)] OR HCS. B. Depen[...]

www.ti.com PRODUCT PREVIEW HCS HAS HR/W HHWIL HSTROBE (A ) HD[15:0] HRDY (B) 2 3 1 37 9 10 14 2 38 12 1 1 12 1 1 12 1 1 13 7 6 1 3 13 37 9 10 36 HCNTL[1:0] 12 1 1 12 1 1 12 1 1 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS[...]

www.ti.com PRODUCT PREVIEW HCS HAS HCNTL[1:0] HR/W HHWIL HSTROBE (A ) HD[15:0] HRDY (B) 34 5 17 18 17 18 34 5 4 38 37 13 16 15 14 13 16 15 37 35 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT( HDS1 XOR HDS2)] OR HCS.[...]

www.ti.com PRODUCT PREVIEW HCS HAS HCNTL[1:0] HR/W HHWIL HSTROBE (A ) HD[15:0] HRDY (B) 5 34 17 18 13 10 12 9 37 12 12 1 1 1 1 1 1 17 18 14 1 1 1 1 1 1 37 10 9 13 12 12 12 5 34 38 35 36 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 A. HSTROBE refers to the following logical operation on HCS, HDS1[...]

www.ti.com PRODUCT PREVIEW 15 16 3 2 4 1 38 13 7 6 HCS (input) HAS (input) HSTROBE (A ) (input) HR/W (input) HRDY (B) (output) HD[31:0] (output) HCNTL[1:0] (input) 37 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT( H[...]

www.ti.com PRODUCT PREVIEW 36 1 1 10 12 9 1 38 13 2 3 6 HCS (input) HAS (input) HSTROBE (A ) (input) HR/W (input) HRDY (B) (output) HD[31:0] (output) HCNTL[1:0] (input) 7 37 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [...]

www.ti.com PRODUCT PREVIEW 17 15 38 5 16 13 18 34 35 4 HCS (input) HAS (input) HSTROBE (A ) (input) HR/W (input) HRDY (B) (output) HD[31:0] (input) HCNTL[1:0] (input) 37 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT[...]

www.ti.com PRODUCT PREVIEW HRDY (B) (output) 5 1 1 9 17 18 34 HAS (input) HR/W (input) HSTROBE (A ) (input) HCS (input) 35 36 38 HD[31:0] (input) HCNTL[1:0] (input) 10 12 13 37 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS[...]

www.ti.com PRODUCT PREVIEW 7.13 Multichannel Buffered Serial Port (McBSP) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The McBSP provides these functions: • Full-duplex communication • Double-buffered data registers, which allow a continuous data stream • Independent framing and clocking f[...]

www.ti.com PRODUCT PREVIEW 7.13.1 McBSP Device-Specific Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The CLKS signal is shared by both McBSP0 and McBSP1 on this device. Also, the CLKGDV field of the Sample Rate Generator Register (SRGR) must always be set to a value of 1 or greater. [...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-58. McBSP 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS The CPU and EDMA controller can only read 0290 0000 DRR1 McBSP1 Data Receive Register via Configuration Bus this register; they cannot write to i[...]

www.ti.com PRODUCT PREVIEW 7.13.2 McBSP Electrical Data/Timing TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.13.2.1 Multichannel Buffered Serial Port (McBSP) Timing Table 7-59. Timing Requirements for McBSP (1) (see Figure 7-52 ) -720 -850 NO. UNIT -1000 MIN MAX 2 t c(CKRX) Cycle time, CLKR/X C[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-60. Switching Characteristics Over Recommended Operating Conditions for McBSP (see Figure 7-52 ) (continued) -720 -850 NO. PARAMETER UNIT -1000 MIN MAX 3 t w(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int[...]

www.ti.com PRODUCT PREVIEW Bit(n-1) (n-2) (n-3) Bit 0 Bit(n-1) (n-2) (n-3) 14 12 1 1 10 9 3 3 2 8 7 6 5 4 4 3 1 3 2 CLKS CLKR FSR (int) FSR (ext) DR CLKX FSX (int) FSX (ext) FSX (XDA TDL Y=00b) DX 13 (A) 13 (A) 2 1 CLKS FSR external CLKR/X (no need to resync) CLKR/X (needs resync) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL [...]

www.ti.com PRODUCT PREVIEW Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 CLKX FSX DX DR TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-62. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 (1) (2) (see Figure 7-54 ) -720 -850 [...]

www.ti.com PRODUCT PREVIEW Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 4 3 7 6 2 1 CLKX FSX DX DR 5 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-64. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 (1) (2) (see Figure 7-55 ) -720 -850 -1[...]

www.ti.com PRODUCT PREVIEW Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 CLKX FSX DX DR TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-66. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 (1) (2) (see Figure 7-56 ) -720 -850 [...]

www.ti.com PRODUCT PREVIEW Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 5 4 3 7 6 2 1 CLKX FSX DX DR TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-68. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 (1) (2) (see Figure 7-57 ) -720 -850 -1[...]

www.ti.com PRODUCT PREVIEW 7.14 Ethernet MAC (EMAC) Configuration Bus DMA Memory T ransfer Controller Peripheral Bus EMAC Control Module EMAC Module MDIO Module MDIO Bus EMAC/MDIO Interrupt Interrupt Controller Ethernet Bus TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The Ethernet Media Access C[...]

www.ti.com PRODUCT PREVIEW 7.14.1 EMAC Device-Specific Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Interface Modes The EMAC module on the TMS320C6454 supports four interface modes: Media Independent Interface (MII), Reduced Media Independent Interface (RMII), Gigabit Media Independe[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-70. EMAC/MDIO Multiplexed Pins (MII, RMII, and GMII Modes) BALL NUMBER DEVICE PIN NAME MII RMII GMII (MAC_SEL = (MAC_SEL = (MAC_SEL = 00b) 01b) 10b) J2 MRXD0/RMRXD0 MRXD0 RMRXD0 MRXD0 H3 MRXD1/RMRXD1 MRXD1 RMRXD1 MRX[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Interface Mode Clocking The on-chip PLL2 and PLL2 Controller generate all the clocks to the EMAC module. When enabled, the input clock to the PLL2 Controller (CLKIN2) must have a 25 MHz frequency. For more information, see S[...]

www.ti.com PRODUCT PREVIEW 7.14.2 EMAC Peripheral Register Description(s) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-71. Ethernet MAC (EMAC) Control Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02C8 0000 TXIDVER Transmit Identification and Version Register 02C8 0004 TXCONTROL Tran[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-71. Ethernet MAC (EMAC) Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02C8 0154 RX5FREEBUFFER Receive Channel 5 Free Buffer Count Register 02C8 0158 RX6FREEBUFFER Receive Channel 6 Free Buffer[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-71. Ethernet MAC (EMAC) Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME Transmit Channel 2 Completion Pointer (Interrupt Acknowledge) 02C8 0648 TX2CP Register Transmit Channel 3 Completion Point[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-72. EMAC Statistics Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02C8 0228 RXFILTERED Filtered Receive Frames Register 02C8 022C RXQOSFILTERED Received QOS Filtered Frames Register Receive Octet Fram[...]

www.ti.com PRODUCT PREVIEW 7.14.3 EMAC Electrical Data/Timing MRCLK (Input) 2 3 1 4 4 MTCLK (Input) 2 3 1 4 4 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.14.3.1 EMAC MII and GMII Electrical Data/Timing Table 7-75. Timing Requirements for MRCLK - MII and GMII Operation (see Figure 7-59 ) -720 [...]

www.ti.com PRODUCT PREVIEW GMTCLK (Output) 2 3 1 4 4 MRCLK (Input) 1 2 MRXD7−MRXD4(GMII only), MRXD3−MRXD0, MRXDV , MRXER (Inputs) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-77. Switching Characteristics Over Recommended Operating Conditions for GMTCLK - GMII Operation (see Figure [...]

www.ti.com PRODUCT PREVIEW 1 MTCLK (Input) MTXD7−MTXD4(GMII only), MTXD3−MTXD0, MTXEN (Outputs) 1 GMTCLK (Output) MTXD7−MTXD0, MTXEN (Outputs) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-79. Switching Characteristics Over Recommended Operating Conditions for EMAC MII and GMII Tran[...]

www.ti.com PRODUCT PREVIEW RMREFCLK (Input) 1 2 3 3 1 RMREFCLK (Input) MTXD1-MTXD0, MTXEN (Outputs) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.14.3.2 EMAC RMII Electrical Data/Timing The RMREFCLK pin is used to source a clock to the EMAC when it is configured for RMII operation. The RMREFCLK[...]

www.ti.com PRODUCT PREVIEW RMREFCLK (Input) 1 2 3 3 4 5 MRXD1-MRXD0, MCRSDV , MRXER (Inputs) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-83. Timing Requirements for EMAC RMII Input Receive for 100 Mbps (1) (see Figure 7-67 ) -720 -850 NO. UNIT -1000 MIN MAX Setup time, receive selected [...]

www.ti.com PRODUCT PREVIEW RGREFCLK (Output) 2 3 4 4 1 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.14.3.3 EMAC RGMII Electrical Data/Timing An extra clock signal, RGREFCLK, running at 125 MHz is included as a convenience to the user. Note that this reference clock is not a free-running clock.[...]

www.ti.com PRODUCT PREVIEW RXD[3:0] (A) RXCTL (A) RXC (at DSP) (B) 5 RXERR RXDV 6 1st Half-byte 2nd Half-byte RXD[7:4] RXD[3:0] 2 3 1 4 4 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-86. Timing Requirements for EMAC RGMII Input Receive for 10/100/1000 Mbps (1) (see Figure 7-69 ) -720 -85[...]

www.ti.com PRODUCT PREVIEW TXC (at DSP) (B) TXD[3:0] (A) TXCTL (A) 5 6 1st Half-byte TXERR TXEN 2nd Half-byte 1 2 Internal TXC TXC at DSP pins 4 4 2 3 1 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-88. Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII Transmi[...]

www.ti.com PRODUCT PREVIEW 7.14.4 Management Data Input/Output (MDIO) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to interrogate and controls up to 32 Ethernet PHY(s) connected to the device, using a[...]

www.ti.com PRODUCT PREVIEW 1 3 4 MDCLK MDIO (input) 1 7 MDCLK MDIO (output) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.14.4.3 MDIO Electrical Data/Timing Table 7-90. Timing Requirements for MDIO Input (R)(G)MII (see Figure 7-71 ) -720 -850 NO. UNIT -1000 MIN MAX 1 t c(MDCLK) Cycle time, MDCL[...]

www.ti.com PRODUCT PREVIEW 7.15 Timers 7.15.1 Timers Device-Specific Information 7.15.2 Timers Peripheral Register Description(s) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The timers can be used to: time events, count events, generate pulses, interrupt the CPU, and send synchronization events[...]

www.ti.com PRODUCT PREVIEW 7.15.3 Timers Electrical Data/Timing TINPLx T OUTLx 4 3 2 1 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-94. Timing Requirements for Timer Inputs (1) (see Figure 7-73 ) -720 -850 NO. UNIT -1000 MIN MAX 1 t w(TINPH) Pulse duration, TINPLx high 12P ns 2 t w(TINPL[...]

www.ti.com PRODUCT PREVIEW 7.16 Peripheral Component Interconnect (PCI) 7.16.1 PCI Device-Specific Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The C6454 DSP supports connections to a PCI backplane via the integrated PCI master/slave bus interface. The PCI port interfaces to DSP inte[...]

www.ti.com PRODUCT PREVIEW 7.16.2 PCI Peripheral Register Description(s) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-97. PCI Configuration Registers PCI HOST ACCESS ACRONYM PCI HOST ACCESS REGISTER NAME HEX ADDRESS OFFSET 0x00 PCIVENDEV Vendor ID/Device ID 0x04 PCICSR Command/Status 0x0[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-98. PCI Back End Configuration Registers DSP ACCESS ACRONYM DSP ACCESS REGISTER NAME HEX ADDRESS RANGE 02C0 0000 - 02C0 000F - Reserved 02C0 0010 PCISTATSET PCI Status Set Register 02C0 0014 PCISTATCLR PCI Status Cle[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-98. PCI Back End Configuration Registers (continued) DSP ACCESS ACRONYM DSP ACCESS REGISTER NAME HEX ADDRESS RANGE 02C0 0308 PCIMCFGCMD PCI Master Configuration/IO Access Command Register 02C0 030C - 02C0 030F - Rese[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-100. PCI Hook Configuration Registers DSP ACCESS ACRONYM DSP ACCESS REGISTER NAME HEX ADDRESS RANGE 02C0 0394 PCIVENDEVPRG PCI Vendor ID and Device ID Program Register 02C0 0398 PCICMDSTATPRG PCI Command and Status P[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-101. PCI External Memory Space (continued) HEX ADDRESS OFFSET ACRONYM REGISTER NAME 4780 0000 - 47FF FFFF - PCI Master Window 15 4800 0000 - 487F FFFF - PCI Master Window 16 4880 0000 - 48FF FFFF - PCI Master Window [...]

www.ti.com PRODUCT PREVIEW 7.16.3 PCI Electrical Data/Timing TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Texas Instruments (TI) has performed the simulation and system characterization to ensure that the PCI peripheral meets all AC timing specifications as required by the PCI Local Bus Specific[...]

www.ti.com PRODUCT PREVIEW 7.17 General-Purpose Input/Output (GPIO) 7.17.1 GPIO Device-Specific Information 7.17.2 GPIO Peripheral Register Description(s) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 On the C6454 the GPIO peripheral pins GP[15:8] and GP[3:0] are muxed with the PCI and McBSP1 per[...]

www.ti.com PRODUCT PREVIEW 7.17.3 GPIO Electrical Data/Timing GPIx GPOx 4 3 2 1 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-103. Timing Requirements for GPIO Inputs (1) (2) (see Figure 7-74 ) -720 -850 NO. UNIT -1000 MIN MAX 1 t w(GPIH) Pulse duration, GPIx high 12P ns 2 t w(GPIL) Pulse[...]

www.ti.com PRODUCT PREVIEW 7.18 IEEE 1149.1 JTAG 7.18.1 JTAG Device-Specific Information 7.18.2 JTAG Peripheral Register Description(s) 7.18.3 JTAG Electrical Data/Timing TCK TDO TDI/TMS/TRST 1 2 3 4 2 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.18.1.1 IEEE 1149.1 JTAG Compatibility Statement[...]

www.ti.com PRODUCT PREVIEW 8 Mechanical Data 8.1 Thermal Data 8.2 Packaging Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 8-1 shows the thermal resistance characteristics for the PBGA - ZTZ/GTZ mechanical package. Table 8-1. Thermal Resistance Characteristics (S-PBGA Package) [Z[...]

www.ti.com PRODUCT PREVIEW Revision History TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 This data sheet revision history highlights the technical changes made to the SPRS311 device-specific data sheet to make it an SPRS311A revision. Scope: Applicable updates to the C64x device family, specific[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 C6454 Revision History (continued) SEE ADDITIONS/MODIFICATIONS/DELETIONS Section 3.4.2 Peripheral Configuration Register 0 Description: Updated paragraph and added Note Changed all bit field resets to R/ W-0 and updated Figu[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 C6454 Revision History (continued) SEE ADDITIONS/MODIFICATIONS/DELETIONS Section 7.7.3 PLL1 Controller Register Descriptions: Added Values and Descriptions for RATIO bit field in Table 7-21 , PLL Pre-Divider Control Register[...]

www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 C6454 Revision History (continued) SEE ADDITIONS/MODIFICATIONS/DELETIONS Section 7.14.3.3 EMAC RGMII Electrical Data/Timing: Updated Table 7-84 , Switching Characteristics Over Recommended Operating Conditions for EMAC RGREF[...]

PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TMS320C6454BZTZ ACTIVE FCBGA ZTZ 697 44 Pb-Free (RoHS Exempt) SNAGCU Level-4-260C-72HR TMS320C6454BZTZ7 ACTIVE FCBGA ZTZ 697 44 Pb-Free (RoHS Exempt) SNAGCU Level-4-260C-72HR TMS320C6454BZTZ8 ACTIVE FCBGA Z[...]

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