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Texas Instruments TMS320DM355 manuel d'utilisation

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  • Page 1

    www.ti.com PRODUCT PREVIEW 1 TMS320DM355 Digital Media System-on-Chip (DMSoC) 1.1 Features TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 encoder • High-Performance Digital Media System-on-Chip • External Memory Interfaces (EMIFs) – 216- and 270-MHz ARM926EJ-S Clock Rate – DDR2 and mD[...]

  • Page 2

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 – IEEE-1149.1 (JTAG) • 337-Pin Ball Grid Array (BGA) Package Boundary-Scan-Compatible (ZCE Suffix), 0.65-mm Ball Pitch – ETB (Embedded Trace Buffer) with • 90nm Process Technology 4K-Bytes Trace Buffer memory ?[...]

  • Page 3

    www.ti.com PRODUCT PREVIEW 1.2 Description TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The DM355 is a highly integrated, programmable platform for digital still camera, digital photo frames, IP security cameras, 4-channel digital video recorders, video door bell application, and other low [...]

  • Page 4

    www.ti.com PRODUCT PREVIEW 1.3 Functional Block Diagram Peripherals 64bitDMA/DataBus JT AG 24MHz 27MHz (optional) CCD/ CMOS Module DDR2/MDDR16 CLOCK PLL CLOCKctrl PLLs JT A JT AG I/F Clocks ARM z ) ARM926EJ-S_Z8 I- cach e 16 K B l-cache 16KB B RA M 32 K B RAM 32KB B D- cach e 8 K D-cache 8KB RO M 8 K ROM 8KB CCD C CCDC 3 A 3A DMA [...]

  • Page 5

    www.ti.com PRODUCT PREVIEW Contents TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 1 TMS320DM355 Digital Media System-on-Chip 4.2 Recommended Operating Conditions ............... 92 (DMSoC) ................................................... 1 4.3 Electrical Characteristics Over Recommended R[...]

  • Page 6

    www.ti.com PRODUCT PREVIEW 2 Device Overview 2.1 Device Characteristics TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-1 provides an overview of the DMSoC. The table shows significant features of the device, including the peripherals, capacity of on-chip RAM, ARM operating frequency, [...]

  • Page 7

    www.ti.com PRODUCT PREVIEW 2.2 Memory Map Summary TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-3 shows the memory map address ranges of the device. Table 2-3 depicts the expanded map of the Configuration Space (0x01C0 0000 through 0x01FF FFFF). The device has multiple on-chip memori[...]

  • Page 8

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-3. DM355 ARM Configuration Bus Access to Peripherals (continued) Address Accessibility UART1 0x01C2 0400 0x01C2 07FF 1K √ √ Timer4/5 0x01C2 0800 0x01C2 0BFF 1K √ √ Real-time out 0x01C2 0C00 0x01C2 0FFF 1[...]

  • Page 9

    www.ti.com PRODUCT PREVIEW 2.3 Pin Assignments 2.3.1 Pin Map (Bottom View) 9 J 8 V SSA_PLL2 7 V DDA33_USB 6 5 4 3 1 H G V DDA13_USB V SS F E D CIN2 C B A VREF CIN3 CIN0 V DDA_PLL2 V SS LCD_OE FIELD VCLK V SS V SS CV DD VSYNC EXTCLK VFB V DD_VOUT V DD_VOUT V DD_VOUT HSYNC COUT0 COUT1 TVOUT TDO EMU0 EMU1 V SS_USB USB_VBUS COUT2 COUT3 IOUT TDI TMS V S[...]

  • Page 10

    www.ti.com PRODUCT PREVIEW W 9 DDR_CLK 8 DDR_CLK 7 6 5 4 DDR_A05 3 2 DDR_A02 1 V DDR_A07 DDR_A04 DDR_A00 U V SS T PCLK R P N M L K DDR_A1 1 DDR_A09 DDR_A08 V SS DDR_CAS DDR_BA[2] DDR_A12 DDR_A10 DDR_A01 V SS DDR_BA[0] DDR_BA[1] DDR_A13 DDR_A06 DDR_A03 V SS V SS V SS V SS DDR_ZN DDR_CS DDR_RAS V SS V SS MXO2 V DD_DDR CV DD CV DD V SS CAM_WEN_ FIELD [...]

  • Page 11

    www.ti.com PRODUCT PREVIEW CV DD 19 W 18 DDR_GA TE0 17 DDR_DQ15 16 DDR_DQ13 15 DDR_DQ1 1 14 DDR_DQ10 13 DDR_DQ07 12 DDR_DQ05 1 1 DDR_DQ01 10 DDR_WE EM_A13 V V SS DDR_GA TE1 DDR_DQ14 DDR_DQS[1] DDR_DQ09 DDR_DQ06 DDR_DQS[0] DDR_DQ00 DDR_CKE EM_A12 U UART0_RXD V SS DDR_DQ12 DDR_DQM[1] V SS DDR_DQ08 DDR_DQ04 DDR_DQ02 DDR_VREF EM_A08 T UART0_TXD CV DD V[...]

  • Page 12

    www.ti.com PRODUCT PREVIEW 19 18 17 16 15 14 13 12 11 10 EM_D05 J EM_D02 H EM_CE1 G F E D C V DD B A EM_D03 EM_D01 EM_CE0 EM_WE V SS EM_D00 EM_ADV ASP0_DX V SSA_PLL1 CV DD EM_WAIT ASP0_FSX GIO003 V DDA_PLL1 EM_OE ASP0_CLKX ASP0_CLKR ASP0_FSR GIO002 EM_CLK ASP0_DR ASP1_FSR ASP1_FSX GIO001 SPI1_ SDENA[0] SPI1_SDO RTCK TCK ASP1_CLKX ASP1_CLKR ASP1_CLK[...]

  • Page 13

    www.ti.com PRODUCT PREVIEW 2.4 Pin Functions 2.4.1 Image Data Input - Video Processing Front End TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The pin functions tables ( Table 2-4 through Table 2-22 ) identify the external signal names, the associated pin (ball) numbers along with the mechan[...]

  • Page 14

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-5. CCD Controller/Video Input Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. Standard CCD Analog Front End (AFE): NOT USED • YCC 16-bit: Time multiplexed between chroma: CB/SR[07] CIN7[...]

  • Page 15

    www.ti.com PRODUCT PREVIEW 2.4.2 Image Data Output - Video Processing Back End (VPBE) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-5. CCD Controller/Video Input Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. Standard CCD Analog Front End (AFE): R[...]

  • Page 16

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-6. Signals for VPBE Display Modes PIN NAME YCC16 YCC8/ PRGB SRGB REC656 HSYNC HSYNC HSYNC HSYNC HSYNC GIO073 VSYNC VSYNC VSYNC VSYNC VSYNC GIO072 LCD_OE As needed As needed As needed As needed GIO071 FIELD As ne[...]

  • Page 17

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-7. Digital Video Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION (4) NAME NO. YOUT7-R7 C3 I/O/Z V DD_VOUT Digital Video Out: VENC settings determine function YOUT6-R6 A4 I/O/Z V DD_VOUT Digital Vi[...]

  • Page 18

    www.ti.com PRODUCT PREVIEW 2.4.3 Asynchronous External Memory Interface (AEMIF) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-8. Analog Video Terminal Functions TERMINAL TYPE (1) OTHER (2) DESCRIPTION NAME NO. Video DAC: Reference voltage output (0.45V, 0.1uF to GND). When the DAC is[...]

  • Page 19

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. EM_A06/ Async EMIF: Address bus bit[06] P18 I/O/Z V DD GIO060 GIO: GIO[60] EM_A05/ Async EMIF[...]

  • Page 20

    www.ti.com PRODUCT PREVIEW 2.4.4 DDR Memory Interface TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. Async EMIF: Lowest numbered chip select. Can be programmed to be u[...]

  • Page 21

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-10. DDR Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. DDR_A10 V6 I/O/Z V DD_DDR DDR Address Bus bit 10 DDR_A09 W6 I/O/Z V DD_DDR DDR Address Bus bit 09 DDR_A08 W5 I/O/Z V DD[...]

  • Page 22

    www.ti.com PRODUCT PREVIEW 2.4.5 GPIO TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The General Purpose I/O signals provide generic I/O to external devices. Most of the GIO signals are multiplexed with other functions. Table 2-11. GPIO Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) DESCR[...]

  • Page 23

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-11. GPIO Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. MMCSD1 _DATA1 / MMCSD1: DATA1 GIO020 / B15 I/O/Z V DD GIO: GIO[020] UART2_R UART2: Receive Data XD MMCSD1 _DATA2 / MMC[...]

  • Page 24

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-11. GPIO Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. EM_D01 / Async EMIF: Data Bus bit[01] J17 I/O/Z V DD GIO039 GIO: GIO[039] EM_D02 / Async EMIF: Data Bus bit[02] H19 I/[...]

  • Page 25

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-11. GPIO Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. Async EMIF: Address Bus bit[09] EM_A09 / PD GIO: GIO[063] System: AECFG[3:0] sampled at Power-on-Reset to set AEMIF GI[...]

  • Page 26

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-11. GPIO Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. COUT5- G2 / Digital Video Out: VENC settings determine function GIO: GIO[079] PWM2A GIO079 / C1 I/O/Z V DD_VOUT RTO0 P[...]

  • Page 27

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-11. GPIO Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. Standard CCD Analog Front End (AFE): raw[07] YCC 16-bit: time multiplexed between luma: Y[07] YCC 08-bit (which allows[...]

  • Page 28

    www.ti.com PRODUCT PREVIEW 2.4.6 Multi-Media Card/Secure Digital (MMC/SD) Interfaces TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The DM355 includes two Multi-Media Card/Secure Digital card interfaces that are compatible with the MMC/SD and SDIO protocol. Table 2-12. MMC/SD Terminal Functio[...]

  • Page 29

    www.ti.com PRODUCT PREVIEW 2.4.7 Universal Serial Bus (USB) Interface 2.4.8 Audio Interfaces TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The Universal Serial Bus (USB) interface supports the USB2.0 High-Speed protocol and includes dual-role Host/Slave support. However, no charge pump is in[...]

  • Page 30

    www.ti.com PRODUCT PREVIEW 2.4.9 UART Interface TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-14. ASP Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. ASP0_CL ASP0: Transmit Clock KX / F18 I/O/Z V DD GIO: GIO[029] GIO029 ASP0_DR ASP0: Receive DataF [...]

  • Page 31

    www.ti.com PRODUCT PREVIEW 2.4.10 I 2 C Interface 2.4.11 Serial Interface TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-15. UART Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. MMCSD1_DA MMCSD1: DATA0 TA0/ A18 I/O/Z V DD GIO: GIO019 GIO019/ UART2: [...]

  • Page 32

    www.ti.com PRODUCT PREVIEW 2.4.12 Clock Interface TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-17. SPI Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. Standard CCD Analog Front End (AFE): Not used • YCC 16-bit: time multiplexed between chroma. C[...]

  • Page 33

    www.ti.com PRODUCT PREVIEW 2.4.13 Real Time Output (RTO) Interface 2.4.14 Pulse Width Modulator (PWM) Interface TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The provides Real Time Output (RTO) interface. Table 2-19. RTO Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO.[...]

  • Page 34

    www.ti.com PRODUCT PREVIEW 2.4.15 System Configuration Interface TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-20. PWM Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. COUT3- B6 / Digital Video Out: VENC settings determine function GIO: GIO[077] GIO[...]

  • Page 35

    www.ti.com PRODUCT PREVIEW 2.4.16 Emulation TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-21. System/Boot Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. Async EMIF: Address bus bit 08 GIO: GIO[062] EM_A08/ PD System: AECFG[0] sets default for: GIO[...]

  • Page 36

    www.ti.com PRODUCT PREVIEW 2.5 Pin List TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23 provides a complete pin description list in pin number order. Table 2-23. DM355 Pin Descriptions Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State CIN7[...]

  • Page 37

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State CIN3 / GIO097 J4 I/O CCDC V DD_VIN PD in Standard CCD Analog Front End (AFE): [...]

  • Page 38

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State YIN5 / GIO091 M5 I/O CCDC V DD_VIN PD in Standard CCD Analog Front End (AFE): [...]

  • Page 39

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State CAM_HD / N5 I/O CCDC V DD_VIN PD in Horizontal synchronization signal that can[...]

  • Page 40

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State COUT5-G2 / C1 I/O VENC V DD_VOUT in Digital Video Out: VENC settings determine[...]

  • Page 41

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State FIELD / GIO070 H4 I/O VENC V DD_VOUT in Video Encoder: Field identifier for in[...]

  • Page 42

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State DDR_DQS[0] V12 I/O DDR V DD_DDR in Data strobe input/outputs for each byte of [...]

  • Page 43

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State DDR_VREF U10 PWR DDRI V DD_DDR DDR: Voltage input for the SSTL_18 IO O buffers[...]

  • Page 44

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State EM_A09 / P17 I/O AEMI V DD PD in L Async EMIF: Address Bus bit[09] PINMUX2[0].[...]

  • Page 45

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State EM_A01 N17 I/O AEMI V DD out L Async EMIF: Address Bus bit[01] F NAND/SM/xD: A[...]

  • Page 46

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State EM_D09 / K18 I/O AEMI V DD in Async EMIF: Data Bus bit[09] PINMUX2[4].EM_D1 GI[...]

  • Page 47

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State EM_WE / J15 I/O AEMI V DD out H Async EMIF: Write Enable PINMUX2[8].EM_W GIO03[...]

  • Page 48

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State MMCSD1_DAT B16 I/O MMC V DD in MMCSD1: DATA3 PINMUX3[9:8].GIO2 A3 / GIO022 / S[...]

  • Page 49

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State SPI1_SCLK / C13 I/O SPI1 / V DD in SPI1: Clock PINMUX3[24].GIO1 GIO010 GIO 0 G[...]

  • Page 50

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State USB_VBUS E5 A I/O USBP For host or device mode operation, tie the HY VBUS/USB [...]

  • Page 51

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State SPI0_SDO B11 I/O SPI0 V DD in SPI0: Data Out ASP1_DX C18 I/O ASP5 V DD in ASP1[...]

  • Page 52

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State RSV03 L1 A Reserved. This signal should be left as a No I/O/Z Connect or conne[...]

  • Page 53

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State CV DD R8 PWR Core power (1.3 V) CV DD T17 PWR Core power (1.3 V) CV DD W19 PWR[...]

  • Page 54

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State V SS K9 GND Digital ground V SS K10 GND Digital ground V SS K14 GND Digital gr[...]

  • Page 55

    www.ti.com PRODUCT PREVIEW 2.6 Device Support 2.6.1 Development Tools 2.6.2 Device Nomenclature TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 TI offers an extensive line of development tools for DM355 systems, including tools to evaluate the performance of the processors, generate code, deve[...]

  • Page 56

    www.ti.com PRODUCT PREVIEW DM355 PREFIX TMX 320 DM355 ZCE TMX = Experimentaldevice TMS = Qualifieddevice DEVICEF AMILY 320 = TMS320 DSP family P ACKAGE TYPE (A) ZCE = 337-pinplasticBGA,withPb-freesolderedballs DEVICE (B ) A. BGA =BallGrid Array B. () SILICONREVISION Blank=InitialSilicon1.1 SPEED[...]

  • Page 57

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Digital Media System-on-Chip (DMSoC). The primary audio modes that are supported by the ASP are the AC97 and IIS modes. In addition to the primary audio modes, the ASP supports general serial port receive and transmit o[...]

  • Page 58

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 SPRUEE7 TMS320DM35x DMSoC Pulse-Width Modulator (PWM) Reference Guide This document describes the pulse-width modulator (PWM) peripheral in the TMS320DM35x Digital Media System-on-Chip (DMSoC). SPRUEH7 TMS320DM35x DMSoC[...]

  • Page 59

    www.ti.com PRODUCT PREVIEW 3 Detailed Device Description 3.1 ARM Subsystem Overview 3.1.1 Components of the ARM Subsystem TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 This section provides a detailed overview of the DM355 device. The ARM Subsystem contains components required to provide the[...]

  • Page 60

    www.ti.com PRODUCT PREVIEW ARM926EJ-S 16KI$ 8KD$ MMU CP15 Arbiter Arbiter I-AHB D-AHB Master IF DMAbus I-T CM D-T CM 16K RAM0 RAM1 16K ROM 8K Arbiter Slav e IF MasterIF CFGbus ARM inter r upt controller (AINT C) control System PLLC2 PLLC1 (PSC) controller sleep Po wer Peripherals ... 3.2 ARM926EJ-S RISC CPU TMS320DM355 Digital Media [...]

  • Page 61

    www.ti.com PRODUCT PREVIEW 3.2.1 CP15 3.2.2 MMU 3.2.3 Caches and Write Buffer TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 • Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available at ht[...]

  • Page 62

    www.ti.com PRODUCT PREVIEW 3.2.4 Tightly Coupled Memory (TCM) 3.2.5 Advanced High-performance Bus (AHB) 3.2.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB) 3.3 Memory Mapping 3.3.1 ARM Internal Memories TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The write buffer is used f[...]

  • Page 63

    www.ti.com PRODUCT PREVIEW 3.3.2 External Memories 3.3.3 Peripherals 3.4 ARM Interrupt Controller (AINTC) 3.4.1 Interrupt Mapping TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The ARM has access to the following External memories: • DDR2 / mDDR Synchronous DRAM • Asynchronous EMIF / OneN[...]

  • Page 64

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-1. AINTC Interrupt Connections (continued) Interrupt Acronym Source Interrupt Acronym Source Number Number 5 VPSSINT5 VPSS - INT5 37 PWMINT1 PWM 1 6 VPSSINT6 VPSS - INT6 38 PWMINT2 PWM2 7 VPSSINT7 VPSS - INT7 39[...]

  • Page 65

    www.ti.com PRODUCT PREVIEW 3.5 Device Clocking 3.5.1 Overview TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The DM355 requires one primary reference clock . The reference clock frequency may be generated either by crystal input or by external oscillator. The reference clock is the clock at t[...]

  • Page 66

    www.ti.com PRODUCT PREVIEW ARMsubsystem MPEG/JPEG Coprocessor SYSCLK1 SYSCLK2 VPFE VPBE DAC DDRPHY DDR PLLDIV1(/1) BPDIV(/8) PLL controller2 PLL controller1 PLLDIV3(/n) PLLDIV2(/4) PLLDIV1(/2) SYSCLK3 I2C T imers(x4) PWMs(x4) SPI(x3) MMC/SD(x2) EMIF/NAND ASP (x2) GPIO UART2 ARMINTC USB 60MHz Reference cl[...]

  • Page 67

    www.ti.com PRODUCT PREVIEW 3.5.2 Supported Clocking Configurations for DM355-216 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 This section describes the only supported device clocking configurations for DM355-216. The DM355 supports either 24 MHz (typical) or 36 MHz reference clock (crystal[...]

  • Page 68

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 3.5.2.2 Supported Clocking Configurations for DM355-216 (36 MHz reference) 3.5.2.2.1 DM355-216 PLL1 (36 MHz reference) All supported clocking configurations for DM355-216 PLL1 with 36 MHz reference clock are shown in Ta[...]

  • Page 69

    www.ti.com PRODUCT PREVIEW 3.5.3 Supported Clocking Configurations for DM355-270 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 This section describes the only supported device clocking configurations for DM355-270. The DM355 supports either 24 MHz (typical) or 36 MHz reference clock (crystal[...]

  • Page 70

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-7. PLL2 Supported Clocking Configurations for DM355-270 (24 MHz reference) (continued) PREDIV PLLM POSTDIV PLL2 VCO DDR PHY DDR Clock 8 108 1 324 1 324 162 8 102 1 306 1 306 153 8 96 1 288 1 288 144 12 133 1 266[...]

  • Page 71

    www.ti.com PRODUCT PREVIEW 3.5.4 Peripheral Clocking Considerations TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 3.5.3.2.2 DM355-270 PLL2 (36 MHz reference) All supported clocking configurations for DM355-270 PLL2 with 36 MHz reference clock are shown in Table 3-5 Table 3-9. PLL2 Supported [...]

  • Page 72

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 divided internally by three) to the USB PHY. The USB PHY is capable of accepting only 24 MHz and 12 MHz; thus you must use either a 24 MHz or 36 MHz crystal at MXI1/MXO1. See the TMS320DM355 DMSoC Univeral Serial Bus (U[...]

  • Page 73

    www.ti.com PRODUCT PREVIEW 3.6 PLL Controller (PLLC) 3.6.1 PLL Controller Module TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 This section describes the PLL Controllers for PLL1 and PLL2. See the TMS320DM355 Digital Media System-on-Chip ARM Subsystem User's Guide for more information o[...]

  • Page 74

    www.ti.com PRODUCT PREVIEW 3.6.2 PLLC1 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 PLLC1 provides most of the DM355 clocks. Software controls PLLC1 operation through the PLLC1 registers. The following list, Table 3-10 , and Figure 3-3 describe the customizations of PLLC1 in the DM355. • [...]

  • Page 75

    www.ti.com PRODUCT PREVIEW PLLDIV1(/2) PLLDIV2(/4) PLLDIV3(/3) SYSCLK1 (ARMandMPEG/JPEG Coprocessor) SYSCLK2 (peripherals) SYSCLK3 (VPBE) 1 0 PLL 0 1 CLKMODE CLKIN OSCIN PLLEN AUXCLK (Peripherals, CLKOUT1) SYSCLKBP (CLKOUT2) Pre-DIV (/8) Post-DIV (/2or/1) PLLM (programmable) BPDIV(/3) PLLDIV4 (/4or/2) SYSCLK4 (VPSS) TM[...]

  • Page 76

    www.ti.com PRODUCT PREVIEW 3.6.3 PLLC2 PLLDIV1(/1) 1 0 PLL 0 1 CLKMODE CLKIN OSCIN PLLEN SYSCLK1 (DDRPHY) SYSCLKBP (CLKOUT3) BPDIV(/8) PLLM (programmable) Pre-DIV (programmable) Post-DIV (/1) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 PLLC2 provides the DDR PHY clock and CLKOUT3.[...]

  • Page 77

    www.ti.com PRODUCT PREVIEW 3.7 Power and Sleep Controller (PSC) arm_clock arm_mreset arm_power AINTC ARM module_power module_mreset MODx module_clock Alwayson domain Interrupt PSC clks PLLC Emulation RESETN VDD DMSoC 3.8 System Control Module TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 [...]

  • Page 78

    www.ti.com PRODUCT PREVIEW 3.9 Pin Multiplexing 3.9.1 Hardware Controlled Pin Multiplexing TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 • Power management – Deep sleep and fast NAND boot control • Bandwidth Management – Bus master DMA priority control For more information on the Sys[...]

  • Page 79

    www.ti.com PRODUCT PREVIEW 3.9.2 Software Controlled Pin Multiplexing 3.10 Device Reset TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-13. AECFG (Async EMIF Configuration) Pin Mux Coding 1101(NAND) 1100 1010 (OneNAND) 1000 (8-bit SRAM) 0010 (16-bit SRAM) 0000 GPIO[54] GPIO[54] EM_A[14[...]

  • Page 80

    www.ti.com PRODUCT PREVIEW 3.11 Default Device Configurations 3.11.1 Device Configuration Pins TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-14. Reset Types (continued) Type Initiator Effect Module Reset ARM software Resets a specific module. Allows the ARM to independently reset any[...]

  • Page 81

    www.ti.com PRODUCT PREVIEW 3.11.2 PLL Configuration 3.11.3 Power Domain and Module State Configuration TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 After POR, warm reset, and max reset, the PLLs and clocks are set to their default configurations. The PLLs are in bypass mode and disabled by [...]

  • Page 82

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-16. Module Configuration Default States Module Module Name Power Domain Power Domain State Module State Number 0 VPSS Master AlwaysOn ON SyncRst 1 VPSS Slave AlwaysOn ON SyncRst 2 EDMA (CC) AlwaysOn ON BTSEL[1:0[...]

  • Page 83

    www.ti.com PRODUCT PREVIEW 3.11.4 ARM Boot Mode Configuration 3.11.5 AEMIF Configuration 3.12 Device Boot Modes TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-16. Module Configuration (continued) Default States 31 ARM AlwaysOn ON Enable 32 BUS AlwaysOn ON Enable 33 BUS AlwaysOn ON Ena[...]

  • Page 84

    www.ti.com PRODUCT PREVIEW 3.12.1 Boot Modes Overview TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The boot selection pins (BTSEL[1:0]) determine the ARM boot process. After reset (POR, warm reset, or max reset), ARM program execution begins in ARM ROM at 0x0000: 8000, except when BTSEL[1:0[...]

  • Page 85

    www.ti.com PRODUCT PREVIEW Boot mode ? Reset Boot mode ? Bootfrom NANDflash InternalROM BootOK? No Y es Bootfrom UART Bootfrom MMC/SD BootOK? BootOK? Y es No Invokeloaded Program Invoke OneNAND No Y es 3.13 Power Management TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED S[...]

  • Page 86

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 to static current leakage and occurs regardless of the clock rate. Leakage, or standby power, is unavoidable while power is applied and scales roughly with the operating junction temperatures. Leakage power can only be [...]

  • Page 87

    www.ti.com PRODUCT PREVIEW 3.14 64-Bit Crossbar Architecture 3.14.1 Crossbar Connections 3.14.2 EDMA Controller TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The DM355 uses a 64-bit crossbar architecture to control access between device processors, subsystems and peripherals. It includes an [...]

  • Page 88

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The EDMA Controller consists of two major blocks: the Transfer Controller (TC) and the Channel Controller (CC). The CC is a highly flexible Channel Controller that serves as the user interface and event interface for th[...]

  • Page 89

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 DMA Channels: Can be triggered by: " External events (for example, ASP TX Evt and RX Evt), " Software writing a '1' to the given bit location, or channel, of the Event Set register, or, " Chaini[...]

  • Page 90

    www.ti.com PRODUCT PREVIEW 3.15 MPEG/JPEG Overview TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-19. EDMA Channel Synchronization Events (continued) EDMA EVENT NAME EVENT DESCRIPTION CHANNEL 21 UART1: UTXEVT1 UART 1 Transmit Event 22 UART2: URXEVT2 UART 2 Receive Event 23 UART2: UTXE[...]

  • Page 91

    www.ti.com PRODUCT PREVIEW 4 Device Operating Conditions 4.1 Absolute Maximum Ratings Over Operating Case Temperature Range TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 (Unless Otherwise Noted) (3) (4) All 1.3 V supplies -0.5 V to 1.7 V All digital 1.8 V supplies -0.5 V to 2.5 V Supply volt[...]

  • Page 92

    www.ti.com PRODUCT PREVIEW 4.2 Recommended Operating Conditions TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 MIN NOM MAX UNIT CV DD Supply voltage, Core 1.235 1.3 1.365 V V DDA_PLL1 Supply voltage, PLL1 1.235 1.3 1.365 V V DDA_PLL2 Supply voltage, PLL2 1.235 1.3 1.365 V V DDD13_USB Supply v[...]

  • Page 93

    www.ti.com PRODUCT PREVIEW 4.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Case Temperature (Unless Otherwise Noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT V OH High-level output voltage (2) VDD=MIN,[...]

  • Page 94

    www.ti.com PRODUCT PREVIEW 5 Peripheral Information and Electrical Specifications 5.1 Parameter Information Device-Specific Information T ransmissionLine 4.0pF 1.85pF Z0=50 Ω (seenote) T ester PinElectronics Data SheetT imingReferencePoint Output Under T est 42 Ω 3.5nH DevicePin (seenote) 5.1.1 Signal Tran[...]

  • Page 95

    www.ti.com PRODUCT PREVIEW 5.1.2 Timing Parameters and Board Routing Analysis TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into[...]

  • Page 96

    www.ti.com PRODUCT PREVIEW 5.2 Recommended Clock and Control Signal Transition Behavior 5.3 Power Supplies TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 All clocks and control signals should transition between V IH and V IL (or between V IL and V IH ) in a monotonic manner. The power supplie[...]

  • Page 97

    www.ti.com PRODUCT PREVIEW 5.3.1 Power-Supply Sequencing TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 In order to ensure device reliability, the DM355 requires the following power supply power-on and power-off sequences. See table Table 5-1 for a description of DM355 power supplies. Power-O[...]

  • Page 98

    www.ti.com PRODUCT PREVIEW 5.4 Reset 5.4.1 Reset Electrical Data/Timing 1 2 3 RESET BootConfigurationPins (BTSEL[1:0],AECFG[3:0]) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-2. Timing Requirements for Reset (1) (2) (see Figure 5-4 ) DM355 NO. UNIT MIN MAX 1 t w(RESET) Acti[...]

  • Page 99

    www.ti.com PRODUCT PREVIEW 5.5 Oscillators and Clocks 5.5.1 MXI1 (24-MHz) Oscillator Crystal 24MHzor 36MHz C1 C2 MXI1/CLKIN MXO1 V SS_MX1 0.1 F 1 F L1 V DD A_PLL 1 V SSA_PLL 1 C L C 1 C 2 (C 1 C 2 ) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 has two oscillator input/output pairs [...]

  • Page 100

    www.ti.com PRODUCT PREVIEW 5.5.2 MXI2 (27-MHz) Oscillator (optional oscillator) Crystal 27MHz C1 C2 MXI2 MXO2 V SS_M X2 L1 V DD A_PLL 2 V SSA_PLL 2 0.1 F 1 F C L C 1 C 2 (C 1 C 2 ) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-3. Switching Characteristics Over Recommended Operatin[...]

  • Page 101

    www.ti.com PRODUCT PREVIEW 5.5.3 Clock PLL Electrical Data/Timing (Input and Output Clocks) MXI/CLKIN 2 3 4 4 5 1 MXI/CLKIN 2 3 4 4 5 1 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-5. Timing Requirements for MXI1/CLKIN1 (1) (2) (see Figure 5-7 ) DM355 NO UNIT . MIN TYP MAX 1 t c(MXI[...]

  • Page 102

    www.ti.com PRODUCT PREVIEW CLKOUT1 1 2 4 4 MXI/CLKIN 5 6 3 MXI/CLKIN CLK OUT2 1 2 3 4 5 6 4 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-7. Switching Characteristics Over Recommended Operating Conditions for CLKOUT1 (1) (2) (see Figure 5-9 ) DM355 UNI NO. PARAMETER T MIN TYP MAX 1 t[...]

  • Page 103

    www.ti.com PRODUCT PREVIEW 5 6 1 2 3 4 4 MXI/CLKIN CLK OUT3 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-9. Switching Characteristics Over Recommended Operating Conditions for CLKOUT3 (1) (2) (see Figure 5-11 ) DM355 NO. PARAMETER UNIT MIN TYP MAX 1 t C(CLKOUT3) Cycle time, CLKOUT3 [...]

  • Page 104

    www.ti.com PRODUCT PREVIEW 5.6 General-Purpose Input/Output (GPIO) 5.6.1 GPIO Peripheral Input/Output Electrical Data/Timing TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs. When configured as [...]

  • Page 105

    www.ti.com PRODUCT PREVIEW GPIx GPOx 4 3 2 1 5.6.2 GPIO Peripheral External Interrupts Electrical Data/Timing EXT_INTx 2 1 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Figure 5-12. GPIO Port Timing Table 5-12. Timing Requirements for External Interrupts/EDMA Events (1) (see Figure 5-13 ) DM[...]

  • Page 106

    www.ti.com PRODUCT PREVIEW 5.7 External Memory Interface (EMIF) 5.7.1 Asynchronous EMIF (AEMIF) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 supports several memory and external device interfaces, including: • Asynchronous EMIF (AEMIF) for interfacing to SRAM. • OneNAND flash memories ?[...]

  • Page 107

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.7.1.3 AEMIF Electrical Data/Timing Table 5-13. Timing Requirements for Asynchronous Memory Cycles for AEMIF Module (1) (see Figure 5-14 and Figure 5-15 ) DM355 NO UNIT . MIN Nom MAX READS and WRITES Pulse duration, EM[...]

  • Page 108

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-14. Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for AEMIF Module (see Figure 5-14 and Figure 5-15 ) (continued) DM355 UNI NO. PARAMETER T MIN Nom MAX Output set[...]

  • Page 109

    www.ti.com PRODUCT PREVIEW EM_CE[1:0] EM_BA[1:0] 13 12 EM_A[13:0] EM_OE EM_D[15:0] EM_WE 10 5 9 7 4 8 6 3 1 EM_CE[1:0] EM_BA[1:0] EM_A[13:0] EM_WE EM_D[15:0] EM_OE 15 1 16 18 20 22 24 17 19 21 23 26 27 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-14. Switching Characteristics Over R[...]

  • Page 110

    www.ti.com PRODUCT PREVIEW EM_CE[1:0] 1 1 Asserted Dea sser ted 2 2 14 EM_BA[1:0] EM_A[13:0] EM_D[15:0] EM_OE EM_W AIT SETU P STROBE Extend ed Due to EM_W AIT STR OBE HOLD EM_CE[1:0] 25 Asserted Dea sser ted 2 2 EM_BA[1:0] EM_A[13:0] EM_D[15:0] EM_WE EM_W AIT SETU P STROB E Extended D ue to EM_W AIT STR OBE HOL D 28 TMS320DM355 Digital Media System[...]

  • Page 111

    www.ti.com PRODUCT PREVIEW 34 33 35 36 37 30 31 Da Da+1 Da+2 Da+3 Da+4 Da+5 Da+n Da+n+1 EM_CLK EM_CE[1:0] EM_AD V EM_BA0, EM_A[13:0], EM_BA1 EM_D[15:0] EM_OE EM_WAIT 38 39 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Figure 5-18. Synchronous OneNAND Flash Read Timing Submit Documentation Fe[...]

  • Page 112

    www.ti.com PRODUCT PREVIEW 5.7.2 DDR2 Memory Controller TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The DDR2 / mDDR Memory Controller is a dedicated interface to DDR2 / mDDR SDRAM. It supports JESD79D-2A standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices. DDR2 / m[...]

  • Page 113

    www.ti.com PRODUCT PREVIEW 5.8 MMC/SD 5.8.1 MMC/SD Electrical Data/Timing TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The DM355 includes two separate MMC/SD Controllers which are compliant with MMC V3.31, Secure Digital Part 1 Physical Layer Specification V1.1 and Secure Digital Input Outp[...]

  • Page 114

    www.ti.com PRODUCT PREVIEW ST ART XMIT V alid V alid V alid END SD_CLK SD_CMD 13 7 10 9 13 13 13 ST ART XMIT V alid V alid V alid END SD_CLK SD_CMD 10 9 7 1 2 ST ART D0 D1 Dx END SD_CLK SD_DA Tx 7 14 14 10 9 14 14 Start D0 D1 Dx End 7 SD_CLK SD_DA Tx 9 10 4 3 3 4 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVIS[...]

  • Page 115

    www.ti.com PRODUCT PREVIEW 5.9 Video Processing Sub-System (VPSS) Overview 5.9.1 Video Processing Front-End (VPFE) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The contains a Video Processing Sub-System (VPSS) that provides an input interface (Video Processing Front End or VPFE) for externa[...]

  • Page 116

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 • Support for program lens shading correction. • Support for 10-bit to 8-bit A-law compression. • Support for a low-pass filter prior to writing to SDRAM. If this filter is enabled, 2 pixels each in the left and r[...]

  • Page 117

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.9.1.3 Hardware 3A (H3A) The H3A module is designed to support the control loops for Auto Focus, Auto White Balance and Auto Exposure by collecting metrics about the imaging/video data. The metrics are to adjust the va[...]

  • Page 118

    www.ti.com PRODUCT PREVIEW PCLK 2 1 3 4 4 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.9.1.4 VPFE Electrical Data/Timing Table 5-17. Timing Requirements for VPFE PCLK Master/Slave Mode (see Figure 5-23 ) DM355-216 DM355-270 NO. UNIT MIN MAX MIN MAX 1 t c(PCLK) Cycle time, PCLK (1) 18.52 1[...]

  • Page 119

    www.ti.com PRODUCT PREVIEW PCLK (Positive Edge C l ocking ) PCLK (Neg ative Edge Clockin g) 7,9 HD/VD CI[7:0]/YI[7:0]/ CCD[13:0] 8,10 1 1,13 12,14 5 6 C_WE /C_FIELD PCLK (PositiveEdgeClocking) 15 16 23 24 CI[7:0]/YI[7:0]/ CCD[13:0] C_WE /C_FIELD PCLK (PositiveEdgeClocking) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPR[...]

  • Page 120

    www.ti.com PRODUCT PREVIEW PCLK (PositiveEdgeClocking) 18 20 HD VD PCLK (NegativeEdgeClocking) 5.9.2 Video Processing Back-End (VPBE) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-20. Switching Characteristics Over Recommended Operating Conditions for VPFE (CCD) Master Mo[...]

  • Page 121

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 blending for that corresponding video pixel) • Ability to resize from VGA to NTSC/PAL (640x480 to 720x576) for both the OSD and video windows • Horizontal rescaling x1.5 is supported • Support for a rectangular cu[...]

  • Page 122

    www.ti.com PRODUCT PREVIEW 1 PCLK 2 3 7 5 6 4 8 EXTCLK 4 8 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 • Internal Color Bar Generation (100%/75%) • YUV/RGB modes support HDTV output (720p/1080i) with 74.25 MHz external clock input 5.9.2.3 VPBE Electrical Data/Timing Table 5-21. Timing [...]

  • Page 123

    www.ti.com PRODUCT PREVIEW VCLKIN (A) (Positive Edge C l ocking ) 9 VCLKIN (A) (Neg ati ve Edg e Clocking ) 10 VCTL (B ) A. VCLKIN=PCLKorEXTCLK B. VCTL=HSYNC,VSYNC,andFIELD VCLKIN (A) (Positive Edge C locking) 13 VCLKIN (A) (Neg ative Edge Clo cki ng ) 1 1 VCTL (B ) A. VCLKIN=PCLKorEXTCLK B. VCTL=HSYNC,?[...]

  • Page 124

    www.ti.com PRODUCT PREVIEW VCLK (Positive Edge Clocking ) VCLK (Neg ative Edge Clocking ) 17 VCTL (B ) VDA T A (C) 19 18 22 21 23 24 25 26 VCLKIN (A) A. VCLKIN=PCLKorEXTCLK B. VCTL=HSYNC,VSYNC,FIELD,andLCD_OE C. VDA T A=COUT[7:0],YOUT[7:0],R[7:3],G[7:2],andB[7:3] 20 20 TMS320DM355 Digital Media [...]

  • Page 125

    www.ti.com PRODUCT PREVIEW DIN<9:0> MSB LSB DACDigitalInput ExampleforExternalCircuit Iout[mA] 1.4mA 0 DACOutputCurrent C BG 0.1 F m VREF V ideoDAC R BIAS 2550 W IBIAS RLO AD 499 W IOUT Buffer VFB TVOUT TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 A. C[...]

  • Page 126

    www.ti.com PRODUCT PREVIEW DIN<9:0> DACDigitalInput C BG 0.1 F m VREF VideoDACandBuffer R BIAS 2550 Ω IBIAS R fb = 1000 Ω IOUT VFB TVOUT R out =1070 Ω TVmonitor TVOUT[V] VideoBuf ferOutputV oltage MSB LSB V OL(VIDBUF) V OH(VIDBUF) 0 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPT[...]

  • Page 127

    www.ti.com PRODUCT PREVIEW 5.10 USB 2.0 5.10.1 USB2.0 Electrical Data/Timing TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 DM355 includes a USB Controller Module that is built around the Mentor USB Multi-Point High-Speed Dual Role Controller, endpoint memory, CPPI DMA controller and UTMI+ PH[...]

  • Page 128

    www.ti.com PRODUCT PREVIEW t r t f V CR S 90%V OH 10%V OL USB_DM USB_DP t per − t jr V SS_USB_REF USB_R1 USB 10K ±1% W TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Figure 5-33. USB2.0 Integrated Transceiver Interface Timing Figure 5-34. USB Reference Resistor Routing 128 Periphe[...]

  • Page 129

    www.ti.com PRODUCT PREVIEW 5.11 Universal Asynchronous Receiver/Transmitter (UART) 5.11.1 UART Electrical Data/Timing TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The contains 3 separate UART modules (1 with hardware flow control). These modules performs serial-to-parallel conversion on dat[...]

  • Page 130

    www.ti.com PRODUCT PREVIEW 3 2 Start Bit DataBits UART_TXDn UART_RXDn 5 DataBits Bit Start 4 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Figure 5-35. UART Transmit/Receive Timing 130 Peripheral Information and Electrical Specifications Submit Documentation Feedback[...]

  • Page 131

    www.ti.com PRODUCT PREVIEW 5.12 Serial Port Interface (SPI) 5.12.1 SPI Electrical Data/Timing SPIx_CLK (ClockPolarity=0) 1 2 3 SPIx_CLK (ClockPolarity=1) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The contains 3 separate SPI modules. These modules provide a programmable [...]

  • Page 132

    www.ti.com PRODUCT PREVIEW SPI_CLK (ClockPolarity=0) SPI_CLK (ClockPolarity=1) SPI_DI (Input) SPI_DO (Output) 4 MSBIN DA T A LSBIN LSBOUT MSBOUT DA T A 9 10 8 6 5 7 SPI_EN 1 1 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 SPI Master Mode Timings (Clock Phase = 0[...]

  • Page 133

    www.ti.com PRODUCT PREVIEW SPI_CLK (ClockPolarity=0) SPI_CLK (ClockPolarity=1) SPI_DI (Input) SPI_DO (Output) 13 MSBIN DA T A LSBIN LSBOUT MSBOUT DA T A 17 15 14 16 SPI_EN 19 18 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 SPI Master Mode Timings (Clock Phase =[...]

  • Page 134

    www.ti.com PRODUCT PREVIEW 5.13 Inter-Integrated Circuit (I2C) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The inter-integrated circuit (I2C) module provides an interface between and other devices compliant with Philips Semiconductors Inter-IC bus (I 2 C-bus) specification version 2.1 and [...]

  • Page 135

    www.ti.com PRODUCT PREVIEW 5.13.1 I2C Electrical Data/Timing 10 8 4 3 7 12 5 6 14 2 3 13 Stop Start Repeated Start Stop SDA SCL 1 1 1 9 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.13.1.1 Inter-Integrated Circuits (I2C) Timing Table 5-33. Timing Requirements for I2C Timings (1) (see Figur[...]

  • Page 136

    www.ti.com PRODUCT PREVIEW 23 19 18 22 20 21 17 18 28 Stop Start Repeated Start Stop SDA SCL 16 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-34. Switching Characteristics for I2C Timings (1) (see Figure 5-40 ) DM355 STANDARD NO. PARAMETER FAST MODE UNIT MODE MIN MAX MIN MAX 16 t c(S[...]

  • Page 137

    www.ti.com PRODUCT PREVIEW 5.14 Audio Serial Port (ASP) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 DM355 includes two separate ASP controllers. The primary use for the audio serial port (ASP) is for audio interface purposes. The primary audio modes that are supported by the ASP are the AC[...]

  • Page 138

    www.ti.com PRODUCT PREVIEW 5.14.1 ASP Electrical Data/Timing TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.14.1.1 Audio Serial Port (ASP) Timing Table 5-35. Timing Requirements for ASP (1) (see Figure 5-41 ) DM355 NO. UNIT MIN MAX 15 tc(CLK) Cycle time, CLK CLK ext 38.5 or 2P (2) (3) ns 16[...]

  • Page 139

    www.ti.com PRODUCT PREVIEW Bit(n-1) (n-2) (n-3) Bit0 Bit(n-1) (n-2) (n-3) 14 1 1 10 9 3 3 2 8 6 5 4 4 13 (A) 13 (A) A. ParameterNo.13appliestothefirstdatabit only whenXDA TDL Y ≠ 0. CLKR FSR(int) FSR(ext) DR CLKX FSX(int) FSX(ext) FSX (XDA TDL Y=00b) DX 15 CLKS 16 16 17 17 3 2 3 7 12 TMS320DM355 Digital M[...]

  • Page 140

    www.ti.com PRODUCT PREVIEW Bit0 Bit(n-1) (n-2) (n-3) (n-4) Bit0 Bit(n-1) (n-2) (n-3) (n-4) M31 M30 M26 M27 M25 M24 CLKX FSX DX DR M33 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-37. ASP as SPI Timing Requirements CLKSTP = 10b, CLKXP = 0 (see Figure 5-42 ) MASTER NO. UNIT MIN [...]

  • Page 141

    www.ti.com PRODUCT PREVIEW Bit0 Bit(n-1) (n-2) (n-3) (n-4) Bit0 Bit(n-1) (n-2) (n-3) (n-4) M39 M36 M38 M37 M35 M34 CLKX FSX DX DR M40 M42 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-39. ASP as SPI Timing Requirements CLKSTP = 11b, CLKXP = 0 MASTER NO. UNIT MIN MAX M39 t su(DR[...]

  • Page 142

    www.ti.com PRODUCT PREVIEW Bit0 Bit(n-1) (n-2) (n-3) (n-4) Bit0 Bit(n-1) (n-2) (n-3) (n-4) M50 M49 M45 M46 M44 M43 CLKX FSX DX DR M52 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-41. ASP as SPI Timing Requirements CLKSTP = 10b, CLKXP = 1 (see Figure 5-44 ) MASTER NO. UNIT MIN [...]

  • Page 143

    www.ti.com PRODUCT PREVIEW Bit0 Bit(n-1) (n-2) (n-3) (n-4) Bit0 Bit(n-1) (n-2) (n-3) (n-4) M59 M58 M55 M57 M56 M54 M53 CLKX FSX DX DR M62 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-43. ASP as SPI Timing Requirements CLKSTP = 11b, CLKXP = 1 (see Figure 5-45 ) MASTER NO. UNIT [...]

  • Page 144

    www.ti.com PRODUCT PREVIEW 5.15 Timer 5.15.1 Timer Electrical Data/Timing 1 2 4 4 3 TIM_IN TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The contains four software-programmable timers. Timer 0, Timer 1, and Timer 3 (general-purpose timers) can be programmed in 64-bit mode, dual 32-bit unchai[...]

  • Page 145

    www.ti.com PRODUCT PREVIEW 5.16 Pulse Width Modulator (PWM) 5.16.1 PWM0/1/2/3 Electrical/Timing Data PWM0/1/2/3 1 3 3 2 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The DM355 contains 4 separate Pulse Width Modulator (PWM) modules. The pulse width modulator (PWM) feature is very common in e[...]

  • Page 146

    www.ti.com PRODUCT PREVIEW 4 VD(CCDC) 4 4 INV ALID INV ALID INV ALID V ALID V ALID V ALID PWM0 PWM1 PWM2 4 INV ALID V ALID PWM3 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Figure 5-48. PWM Output Delay Timing 146 Peripheral Information and Electrical Specifications Submit Documentation Fee[...]

  • Page 147

    www.ti.com PRODUCT PREVIEW 5.17 Real Time Out (RTO) 5.17.1 RTO Electrical/Timing Data RTO0/1/2/3 1 3 3 2 4 TINT12/TINT34 (Timer3) 4 4 INV ALID INV ALID INV ALID V ALID V ALID V ALID RTO0 4 INV ALID V ALID RTO1 RTO2 RTO3 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The Real Time Out (RTO) pe[...]

  • Page 148

    www.ti.com PRODUCT PREVIEW 5.18 IEEE 1149.1 JTAG TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The JTAG (1) interface is used for BSDL testing and emulation of the device. The device requires that both TRST and RESET be asserted upon power up to be properly initialized. While RESET initializ[...]

  • Page 149

    www.ti.com PRODUCT PREVIEW 5.18.1 JTAG Test-Port Electrical Data/Timing RTCK TDO TDI 4 5 TMS 6 7 TCK 1 2 3 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-48. Timing Requirements for JTAG Test Port (see Figure 5-51 ) DM355 NO. UNIT MIN MAX 1 t c(TCK) Cycle time, TCK 20 ns 2 tw(TCKH) Pu[...]

  • Page 150

    www.ti.com PRODUCT PREVIEW RTCK TDO 13 8 9 10 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-49. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see Figure 5-51 ) DM355 NO. PARAMETER UNIT MIN MAX 8 t c(RTCK) Cycle time, RTCK 20 ns 9 tw(RTCKH) Pulse [...]

  • Page 151

    www.ti.com PRODUCT PREVIEW 6 Revision History TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 This data sheet revision history highlights the technical changes made to the SPRS463 device-specific data sheet to make it an SPRS463A revision. Scope: Updated DM355 Pin Descriptions table, etc. ADDS[...]

  • Page 152

    www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 ADDS/CHANGES/DELETES Updated Section 5.9.1 , Video Processing Front-End (VPFE) Updated Section 5.9.1.1 , CCD Controller (CCDC) Updated Section 5.9.1.2 , IPIPE - Image Pipe Removed "CFALD – CFA Multiply Mask / Len[...]

  • Page 153

    www.ti.com PRODUCT PREVIEW 7 Mechanical Data 7.1 Thermal Data for ZCE 7.1.1 Packaging Information TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The following table(s) show the thermal resistance characteristics for the PBGA – ZCE mechanical package. Note that micro-vias are not required. C[...]

  • Page 154

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