Toshiba TX39 manuel d'utilisation

32-Bit RISC MICROPROCESSOR TX39 FA MI LY CORE ARCHITECTURE USER'S MANUAL Jul. 27, 1995[...]

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R3000A is a Trademark of MIPS Technologies, Inc. The information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from[...]

CONTENTS i CONTENTS Architecture Chapter 1 Introduction --------------------------------------------------------------------------- 3 1.1 Features ------------------------------------------------------------------------------ 3 1.1.1 High-performance RISC techniques ---------------------------------------------------- 3 1.1.2 Functions fo r embedde[...]

CONTENTS ii Chapter 4 Pipeline Architecture ----------------------------------------------------------------- 39 4.1 Overview -------------------------------------------------------------------------------- 39 4.2 Delay Slot ------------------------------------------------------------------------------- 40 4.2.1 Delayed load -----------------------[...]

CONTENTS iii 6.3.5 Coprocessor Unusable exception -------------------------------------------------------- 68 6.3.6 Interrupts ---------------------------------------------------------------------------------------- 69 6.3.7 Overflow exception --------------------------------------------------------------------------- 70 6.3.8 Reserved Instruction [...]

CONTENTS iv TMPR3901F Chapter 1 Introduction --------------------------------------------------------------------------- 201 1.1 Features ------------------------------------------------------------------------------ 201 1.2 Internal Blocks ----------------------------------------------------------------------- 203 Chapter 2 Configuration ---------[...]

CONTENTS v 4.5 Bus Arbitration ----------------------------------------------------------------------- 227 4.5.1 Bus request and bus grant ----------------------------------------------------------------- 227 4.5.2 Cache snoop ---------------------------------------------------------------------------------- 228 4.6 Reset --------------------------[...]

Architecture 1 Architecture[...]

Architecture 2[...]

Architecture 3 Chapter 1 Introduction 1. 1 Features The R3900 Processor Core is a high-performance 32-bit microprocessor core developed by Toshiba based on the R3000A RISC (Reduced Instruction Set Computer) microprocessor. The R3000A was developed by MIPS Technologies, Inc. Toshiba develops ASSPs (Application Specific Standard Products) using the R[...]

Architecture 4 • Real-time performance − Cache Lock Function: Lock one set of the two-way set associative cache memory to keep data in cache memory • Debug support − Breakpoint − Single step execution • Real-time debug system interface 1. 1 .3 Low power consumption • Power Down mode − Prepare for Reduced Frequency mode: Control the [...]

Architecture 5 1. 2 Notation Used in This Manual Mathematical notation • Hexadecimal numbers are expressed as follows (example shown for decimal number 42) 0x2A • A K(kilo)byte is 2 10 = 1,024 bytes, a M(mega)byte is 2 20 = 1,024 x 1,024 = 1,048,576 bytes, and a G(giga)byte is 2 30 = 1,024 x 1,024 x 1,024 = 1,073,741,824 bytes. Data notation ?[...]

Architecture 6 2.[...]

Architecture 7 Chapter 2 Architecture 2. 1 Overview A block diagram of the R3900 Processor Core is shown in Figure 2-1. It includes the CPU core, an instruction cache and a data cache. You can select an optimum data and instruction cache configuration for your system from among a variety of possible configurations. The CPU Core comprises the follow[...]

Architecture 8 2.2 Registers 2.2.1 CPU registers The R3900 Processor Core has the following 32-bit registers. • Thirty-two general-purpose registers • A program counter (PC) • HI/LO registers for storing the result of multiply and divide operations The configuration of the registers is shown in Figure 2-2. The r0 and r31 registers have specia[...]

Architecture 9 2. 2 .2 System control coprocessor (CP0) registers The R3900 Processor Core can be connected to as many as three coprocessors, referred to as CP1, CP2 and CP3. The R3900 also has built-in system control coprocessor (CP0) functions for exception handling and for configuring the system. Figure 2-3 shows the functional breakdown of the [...]

Architecture 10 Table 2-1 lists the CP0 registers built into the R3900 Processor Core. Some of these registers are reserved for use by an external memory management unit. Table 2-1. List of system control coprocessor (CP0) registers No Mnemonic Description 0 - (reserved) † 1 - (reserved) † 2 - (reserved) † 3 Config †† Hardware configurati[...]

Architecture 11 2. 3 Instruction Set Overview All R3900 Processor Core instructions are 32 bits in length. There are three instruction formats: immediate (I-type), jump (J-type) and register (R-type), as shown in Figure 2-4. Having just three instruction formats simplifies instruction decoding. If more complex functions or addressing modes are requ[...]

Architecture 12 The instruction set is classified as follows. (1) Load/store These instructions transfer data between memory and general registers. All instructions in this group are I-type. “ Base register + 16 bit signed immediate offset ” is the only supported addressing mode. (2) Computational These instructions perform arithmetic, logical [...]

Architecture 13 The instruction set supported by all MIPS R-Series processors is listed in Table 2-2. Table 2-3 shows extended instructions supported by the R3900 Processor Core, and Table 2-4 lists coprocessor 0 (CP0) instructions. Table 2-5 shows R3000A instructions not supported by the R3900 Processor Core. Table 2-2. Instructions supported by M[...]

Architecture 14 Table 2-2(cont.). Instructions supported by MIPS R-Series processors (ISA) Instruction Description (Shift) SLL Shift Left Logical SRL Shift Right Logical SRA Shift Right Arithmetic SLLV Shift Left Logical Variable SRLV Shift Right Logical Variable SRAV Shift Right Arithmetic Variable (Multiply/Divide) MULT Multiply MULTU Multiply Un[...]

Architecture 15 Table 2-3. R3900 extended instructions Instruction Description Load/Store Instruction SYNC Sync Computational Instructions MULT Multiply (3-operand instruction) MULTU Multiply Unsigned (3-operand instruction) MADD Multiply/ADD MADDU Multiply/ADD Unsigned Jump/Branch Instructions BEQL Branch on Equal Likely BNEL Branch on Not Equal L[...]

Architecture 16 2.4 Data Formats and Addressing This section explains how data is organized in R3900 registers and memory. The R3900 uses the following data formats: 64-bit doubleword, 32-bit word, 16-bit halfword and 8-bit byte. The byte order can be set to either big endian or little endian. Figure 2-5 shows how bytes are ordered in words, and ho[...]

Architecture 17[...]

Architecture 18 In this document (bit 0 is always the rightmost bit). Byte addressing is used with the R3900 Processor Core, but there are alignment restrictions for halfword and word access. Halfword access is aligned on an even byte boundary (0, 2, 4...) and word access on a byte boundary divisible by 4 (0, 4, 8... ) . The address of multiple-byt[...]

Architecture 19 2. 5 Pipeline Processing Overview The R3900 Processor Core executes instructions in five pipeline stages (F: instruction fetch; D: decode; E: execute; M: memory access; W: register write-back). Each pipeline stage is executed in one clock cycle. When the pipeline is fully utilized, five instructions are executed at the same time res[...]

Architecture 20 2. 6 Memory Management Unit (MMU) 2. 6 .1 R3900 Processor Core operating modes The R3900 Processor Core has two operating modes, user mode and kernel mode. Normally the processor operates in user mode. It switches to kernel mode if an exception is detected. Once in kernel mode, it remains there until an RFE (Restore From Exception) [...]

Architecture 21 2. 6 .2 Direct segment mapping The R3900 Processor Core includes a direct segment mapping MMU. The following virtual address spaces are available depending on the processor mode (Figure 2-8 shows the address mapping). (1) User mode One 2 Gbyte virtual address space (kuseg) is available. Virtual addresses from 0x0000 0000 to 0x7FFF F[...]

Architecture 22 0xFFFF FFFF 16MB Kernel Reserved 0xC000 0000 Kernel Cached (kseg2) 0xA000 0000 Kernel Uncached (kseg1) 0x8000 0000 Kernel Cached (kseg0) 16MB User Reserved 0x0000 0000 Kernel/User Cached (kuseg) Kernel Cached Tasks 1024MB Kernel/User Cached Tasks 2048MB Inaccessible 512MB Kernel Boot and I/O Cached/uncached 512MB Physical address sp[...]

Architecture 22 3.[...]

Architecture 23 Chapter 3 Instruction Set Overview This chapter summarizes each of the R3900 Processor Core instruction types in table format and explains each instruction briefly. Details of individual instructions are given in Appendix A. 3. 1 Instruction Formats Each of the R3900 Processor Core instructions is aligned on a word boundary and has [...]

Architecture 24 3.3 Load and Store Instructions Load and Store instructions move data between memory and general registers and are all I-type instructions. The only directly supported addressing mode is base register plus 16-bit signed immediate offset. With the R3900 Processor Core, the result of a load instruction can be used by the immediately f[...]

Architecture 25 Table 3-2. Load/store instructions (1/2) Instruction Format and Description Load Byte LB rt, offset (base) Generate the address by sign-extending a 32-bit offset and adding it to the contents of register base. Sign-extend the contents of the addressed byte and load into register rt. Load Byte Unsigned LBU rt, offset (base) Generate [...]

Architecture 26 Table 3-2. Load/store instructions (2/2) Instruction Format and Description Store Word SW rt, offset (base) Generate the address by sign-extending a 32-bit offset and adding it to the contents of register base. Store the contents of the least significant word of register rt at the addressed byte. Store Word Left SWL rt, offset (base[...]

Architecture 27 3. 4 Computational Instructions Computational instructions perform arithmetic, logical or shift operations on values in registers. The instruction format can be R-type or I-type. With R-type instructions, the two operands and the result are register values. With I-type instructions, one of the operands is 16-bit immediate data. Comp[...]

Architecture 28 Table 3-5. Three-operand register-type instructions Instruction Format and Description Add ADD rd, rs, rt Add the contents of registers rs and rt, and store the result in register rd. An exception is raised in the event of a two ’ s-complement overflow. Add Unsigned ADDU rd, rs, rt Add the contents of registers rs and rt, and stor[...]

Architecture 29 Table 3-6. Shift instructions (a) SLL, SRL, SRA Instruction Format and Description Shift Left Logical SLL rd, rt, sa Left-shift the contents of register rt by the number of bits indicated in sa (shift amount), and zero-fill the low-order bits. Store the resulting 32 bits in register rd. Shift Right Logical SRL rd, rt, sa Right-shift[...]

Architecture 30 Table 3-7. Multiply/Divide Instructions (a) MULT, MULTU, DIV, DIVU Instruction Format and Description Multiply MULT rs, rt Multiply the contents of registers rs and rt as two's complement integers, and store the doubleword (64-bit) result in multiply/divide registers HI and LO. Multiply Unsigned MULTU rs, rt Multiply the conten[...]

Architecture 31 Table 3-8. Multiply, multiply / add instructions (R3000A extended instruction set) MULT, MULTU, MADD, MADDU (ISA extended set) Instruction Format and Description Multiply MULT rd, rs, rt Multiply the contents of registers rs and rt as two ’ s complement integers, and store the doubleword (64-bit) result in multiply/divide register[...]

Architecture 32 3. 5 Jump/Branch Instructions Jump/branch instructions change the program flow. A jump/branch instruction will delay the pipeline by one instruction cycle, however, an instruction inserted into the delay slot (immediately following a branch instruction) can be executed while the instruction at the branch target address is being fetc[...]

Architecture 33 instruction in the delay slot is executed during the jump). The following notes apply to Table 3-10. • The target address of a branch instruction is generated by adding the address of the instruction in the delay slot (the instruction to be executed during the branch) to the 16-bit offset (that has been left-shifted two bits and s[...]

Architecture 34 (d) BEQL, BNEL, BLEZL, BGTZL, BLTZL, BGEZL, BLTZALL, BGEZALL (ISA Extended Set) Instruction Format and Description Branch on Equal Likely BEQL rs, rt, offset Branch to the target if the contents of registers rs and rt are equal. Branch on Not Equal Likely BNEL rs, rt, offset Branch to the target if the contents of registers rs and r[...]

Architecture 35 3. 6 Special Instructions There are three special instructions used for software traps. The instruction format is R-type for all three. Table 3-11. Special instructions (a) SYSCALL Instruction Format and Description System Call SYSCALL code Raise a system call exception, passing control to an exception handler. (b) BREAK Instruction[...]

Architecture 36 3. 7 Coprocessor Instructions Coprocessor instructions invoke coprocessor operations. The format of these instructions depends on which coprocessor is used. Table 3-12. Coprocessor instructions (a) MTCz, MFCz, CTCz, CFCz Instruction Format and Description Move To Coprocessor MTCz rt, rd Move the contents of CPU general register rt t[...]

Architecture 37 (d) BCzTL, BCzFL (ISA Extended Set) Instruction Format and Description Branch on Coprocessor z True Likely BCzTL offset Generate the branch target address by adding the address of the instruction in the delay slot (the instruction to be executed during the branch) and the 16-bit offset (after left-shifting two bits and sign-extendin[...]

Architecture 38 3. 8 System Control Coprocessor (CP0) Instructions Coprocessor 0 instructions are used for operations involving the system control coprocessor (CP0)registers, processor memory management and exception handling. Note :Attempting to execute a CP0 instruction in user mode when the CU0 bit in the status register is not set will return a[...]

Architecture 39 Chapter 4 Pipeline Architecture 4. 1 Overview The R3900 Processor Core executes instructions in five pipeline stages (F: instruction fetch; D: decode; E: execute; M: memory access; W: register write-back). The five stages have the following roles. F : An instruction is fetched from the instruction cache. D : The instruction is decod[...]

Architecture 40 4.2 Delay Slot Some R3900 Processor Core instructions are executed with a delay of one instruction cycle. The cycle in which an instruction is delayed is called a delay slot. A delay occurs with load instructions and branch/jump instructions. 4.2.1 Delayed load With load instructions, a one-cycle delay occurs while waiting for the d[...]

Architecture 41 • The R3900 Processor Core provides Branch Likely instructions in addition to the normal Branch instructions that allow the instruction at the target branch address to be placed in the delay slot. If the branch condition of the Branch Likely instruction is met, the instruction in the delay slot is executed and the branch is taken.[...]

Architecture 42 4. 5 Divide Instruction (DIV, DIVU) The R3900 Processor Core performs division instructions in the division unit independently of the pipeline. Division starts from the pipeline E stage and takes 35 cycles. Figure 4-6 shows an example of a divide instruction. Division in the division unit E1 E2 E3 E34 E35 div r5,r1 F D E M W mflo r4[...]

Architecture 43 Chapter 5 Memory Management U nit (MMU) The R3900 Processor Core doesn't have TLB. 5. 1 R3900 Processor Core Operating Modes The R3900 Processor Core has two operating modes, user mode and kernel mode. Normally it operates in user mode, but when an exception is detected it goes to kernel mode. Once in kernel mode, it remains un[...]

Architecture 44 5. 2 Direct Segment Mapping The R3900 Processor Core has a direct segment mapping MMU. Figure 5-2 shows the virtual address space of the internal MMU. (1) User mode One 2 Gbyte virtual address space (kuseg) is available in user mode. In this mode, the most significant bit of each kuseg address is 0. The virtual address range of kuse[...]

Architecture 45 (a) kuseg This is the same virtual address space available in user mode. Virtual addresses 0x0000 0000 to 0x7FFF FFFF are translated to physical addresses 0x4000 0000 to 0xBFFF FFFF, respectivery. The upper 16-Mbyte area of kuseg (0x7F00 0000 to 0x7FFF FFFF) is reserved for on-chip resources and is not cacheable. (b) kseg 0 This is [...]

Architecture 46 Table 5-1. Address segment attributes Segment Virtual address Physical address Cacheable Mode kseg2 (reserved) 0xFF00 0000-0xFFFF FFFF 0xFF00 0000-0xFFFF FFFF Uncacheable kernel kseg2 0xC000 0000-0xFEFF FFFF 0xC000 0000-0xFEFF FFFF Cacheable kernel kseg1 0xA000 0000-0xBFFF FFFF 0x0000 0000-0x1FFF FFFF Uncacheable kernel kseg0 0x8000[...]

Architecture 47 Chapter 6 Exception Processing This chapter explains how exceptions are handled by the R3900 Processor Core, and describes the registers of the system control coprocessor CP0 used during exception handling. 6. 1 Overview When the R3900 Processor Core detects an exception, it suspends normal instruction execution. The processor goes [...]

Architecture 48 Table 6-1. Exceptions defined for the R3900 Processor Core Exception Mnemonic Cause Reset Reset † This exception is raised when the reset signal is de-asserted after having been asserted. UTLB Refill UTLB Reserved for an MMU with TLB. TLB Refill TLBL (load) TLBS (store) Reserved for an MMU with TLB. Used for exception request by a[...]

Architecture 49 Table 6-2 shows the vector address of each exception and the values in the exception code (ExcCode) field of the Cause register. Table 6-2. Exception vector addresses and exception codes Exception Mnemonic Vector address † Exception code Reset Reset 0xBFC0 0000 (0xBFC0 0000) undefined Non-maskable Interrupt NmI undefined UTLB Refi[...]

Architecture 50 6. 2 Exception Processing Registers The system control coprocessor (CP0) has seven registers for exception processing, shown in Figure 6-1. (a) Cause register Indicates the nature of the most recent exception. (b) EPC (Exception Program Counter) register Holds the program counter at the time the exception occurred, indicating the ad[...]

Architecture 51 6. 2 .1 Cause register (register no.13) 31 30 29 28 27 16 15 10 9 8 7 6 2 1 0 BD 0 CE[1:0] 0 IP[5:0] Sw[1:0] 0 ExCode 0 1 1 2 12 6 2 1 5 2 Bits Mnemonic Field name Description Value on Reset Read/Write 31 BD Branch Delay Set to 1 when the most recent exception was caused by an instruction in the branch delay slot (executed during a [...]

Architecture 52 Table 6-3. ExcCode field ExcCode Field of Cause Register No. Mnemonic Cause 0 Int External interrupt 1 Mod TLB Modified exception 2 TLBL TLB Refill exception (load instruction or instruction fetch) 3 TLBS TLB Refill exception (store instruction) 4 AdEL Address Error exception (load instruction or instruction fetch) 5 AdES Address Er[...]

Architecture 53 6. 2 .3 Status register (register no.12) This register holds the operating mode status (user mode or kernel mode), interrupt masking status, diagnosis status and similar information. 31 28 25 22 21 20 19 16 15 8 76 5 4 3 2 1 0 CU[3:0] 0 RE 0 BEV T S Nml 0 IntMask Int[5:0] Sw[1:0] 0 KUo IEo KUp IEp KUc IEc 4 2 1 2 1 1 1 4 8 2 1 1 1 1[...]

Architecture 54 Figure 6-4. Status register (1/2)[...]

Architecture 55 Bits Mnemonic Field name Description Value on Reset Read/ Write 27-26 24-23 19-16 7-6 0 Ignored on write; 0 when read. 0 Read Figure 6-4. Status register (2/2) (1) CU (Coprocessor Usability) The CU bits CU0 - CU3 control the usability of the four coprocessors CP0 through CP3. Setting a bit to 1 allows the corresponding coprocessor t[...]

Architecture 56 (5) NmI (Non-maskable Interrupt) This bit is set to 1 when a non-maskable interrupt is raised by the falling edge of the non- maskable interrupt signal. The bit is cleared to 0 by writing a 1 to it or when a Reset exception is raised. (6) IntMask (Interrupt Mask) The IntMask bits separately enable or mask each of six hardware and tw[...]

Architecture 57 6. 2 .4 Cache register (register no.7) This register controls the cache lock function. 31 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 IAL o DAL o IAL p DAL p IAL c DAL c 0 18 1 1 1 1 1 1 0 Bits Mnemonic Field name Description Value on Reset Read/ Write 13 IALo Instruction Cache Lock(old) 1 = cache lock enable; 0 = cache lock disable 0 Read[...]

Architecture 58 (1) DALc/DALp/DALo (Data Cache Auto-Lock: current/previous/old) The three bits DALc/DALp/DALo form a three-level stack, indicating the current, previous and old auto-lock status of the data cache. For each bit, 1 means the lock is in effect, and 0 means it is not. A Reset exception clears DALc, DALp and DALo to 0. When the R3900 Pro[...]

Architecture 59 6. 2 .5 Status register and Cache register mode bit and exception processing When the R3900 Processor Core responds to an exception, it saves the values of the current operating mode bit (KUc) and current interrupt enabled mode bit (IEc) in the previous mode bits (KUp and IEp). It saves the values of the previous mode bits (KUp and [...]

Architecture 60 After an exception handler has executed to perform exception processing, it must issue an RFE (Restore From Exception) instruction to restore the system to its previous status. The RFE instruction returns control to processing that was in progress when the exception occurred. When a RFE instruction is executed, the previous interrup[...]

Architecture 61 6. 2 .6 BadVAddr (Bad Virtual Address) register (register no.8) When an Address Error exception (AdEL or AdES) is raised, the virtual address that caused the error is saved in the BadVAddr register. When a TLB Refill, TLB Modified or UTLB Refill exception is raised, the virtual address for which address translation failed is saved i[...]

Architecture 62 6. 2 .8 Config (Configuration) register (register no.3) This register designates the R3900 Coprocessor Core configuration. 31 21 19 18 16 11 10 9 8 7 6 5 4 3 2 1 0 0 ICS DCS 0 RF IRSize DRSize Bits Mnemonic Field name Description Value on Reset Read/ Write 21-19 ICS Instruction Cache Size Indicates the instruction cache size. 000: 1[...]

Architecture 63 Bits Mnemonic Field name Description Value on Reset Read/ Write 8 Halt †† Halt Setting this bit to 1 puts the R3900 Processor Core in Halt mode. This state is canceled by a Reset exception when a reset signal is received, or when cancelled by a non-maskable interrupt signal or interrupt signal that clears the Halt bit to 0. The [...]

Architecture 64 6. 3 Exception Details 6. 3 .1 Memory location of exception vectors Exception vector addresses are stored in an area of kseg0 or kseg1. The vector address of the Reset and NmI exceptions is always in a non-cacheable area of kseg1. Vector addresses of the other exceptions depend on the Status register BEV bit. When BEV is 0 the other[...]

Architecture 65 6. 3 .2 Address Error exception • Causes − Attempting to load, fetch or store a word not aligned on a word boundary. − Attempting to load or store a halfword not aligned on a halfword boundary. − Attempting to access kernel mode address space kseg while in user mode. • Exception mask The Address Error exception is not mask[...]

Architecture 66 6. 3 .3 Breakpoint exception • Cause − Execution of a BREAK command. • Exception mask The Breakpoint exception is not maskable. • Applicable instructions BREAK • Processing − The common exception vector (0x8000 0080) is used. − BP(9) is set for ExcCode in the Cause register. − The EPC register points to the address o[...]

Architecture 67 6. 3 .4 Bus Error exception • Causes − This exception is raised when a bus error signal is input to the R3900 Processor Core during a memory bus cycle. This occurs during execution of the instruction causing the bus error. The memory bus cycle ends upon notification of a bus error. When a bus error is raised during a burst refil[...]

Architecture 68 − When a bus error occurs with a load instruction, the destination register value will be undefined. − In the following cases, a Bus Error exception may be raised even though the instruction causing the bus error did not actually execute. (1) When a bus error occurs during an instruction cache refill, but the instruction sequenc[...]

Architecture 69 6. 3 .5 Coprocessor Unusable exception • Cause − Attempting to execute a coprocessor CPz instruction when its corresponding CUz bit in the Status register is cleared to 0 (coprocessor unusable). − In user mode, attempting to execute a CP0 instruction when the CU0 bit is cleared to 0. (In kernel mode, an exception is not raised[...]

Architecture 70 6. 3 .6 Interrupts • Cause − An Interrupt exception is raised by any of eight interrupts (two software and six hardware). A hardware interrupt is raised when the interrupt signal goes active. A software interrupt is raised by setting the Sw1 or Sw0 bits in the Cause register. • Exception mask − Each of the eight interrupts c[...]

Architecture 71 6. 3 .7 Overflow exception • Cause − A two's complement overflow results from the execution of an ADD, ADDI or SUB instruction. • Exception mask The Overflow exception is not maskable. • Applicable instructions ADD, ADDI, SUB • Processing − The common exception vector (0x8000 0080) is used. − Ov(12) is set for Exc[...]

Architecture 72 6. 3 .9 Reset exception • Cause − The reset signal in the R3900 Processor Core is asserted and then de-asserted. • Exception mask The Reset exception is not maskable. • Processing − A special interrupt vector (0xBFC0 0000) that resides in an uncached area is used. It is therefore not necessary for hardware to initialize ca[...]

Architecture 73 6. 3 .10 System Call exception • Cause − Execution of an R3900 Processor Core SYSCALL instruction. • Exception mask The System Call exception is not maskable. • Applicable instructions SYSCALL • Processing − The common exception vector (0x8000 0080) is used. − Sys(8) is set for ExcCode in the Cause register. − The EP[...]

Architecture 74[...]

Architecture 75 6. 4 Priority of Exceptions More than one exception may be raised for the same instruction, in which case only the exception with the highest priority is reported. The R3900 Processor Core instruction exception priority is shown in Table 6-5. See chapter 8 for the priority of debug exceptions. Table 6-5. Priority of Exceptions Prior[...]

Architecture 74 7.[...]

Architecture 75 Chapter 7 Caches The R3900 Processor Core is equipped with separate on-chip caches for data and instructions. These caches can be configured in a variety of sizes as required by the user system. Note : Currently only the cache configuration described below is supported. It consists of a 4 Kbyte instruction cache and 1 Kbyte data cac[...]

Architecture 76 7. 2 Data Cache The data cache has the following specifications. − Cache size : 1 Kbyte (Config register DCS bits = 000) − Two-way set-associative − Replace algorithm : LRU (Least Recently Used) − Block (line) size : 1 word (4 bytes) − Write-through − Physical cache − Refill size : Choice of size 1/4/8/16/32 words (set[...]

Architecture 77 Figure 7-4 shows the data cache address field. 31 9 8 1 0 Physical Tag Cache Tag Index When a data store misses, the data is stored to main memory only, not to the cache (no write allocate). The data cache can be written in individual bytes. (When a byte or halfword store is used, there is no read- modify-write.) 7. 2 .1 Lock functi[...]

Architecture 78 (3) Lock bit clearing 13 12 11 10 9 8 IALo DALo IALp DALp IALc DALc exception raised 0 0 IALo DALo IALp DALp IALc DALc 13 12 11 10 9 8 IALo DALo IALp DALp IALc DALc RFE executed IALo DALo IALp DALp IALc DALc IALo,IALp and IALc are reserved for the instruction cache. The lock bit for an entry is cleared using the CACHE instruction In[...]

Architecture 79 7. 3 Cache Test Function (1) Cache di sabling The Config register bits ICE (Instruction Cache Enable) and DCE (Data Cache Enable) are used to enable and disable the instruction cache and data cache, respectively. When a cache is disabled, all cache accesses are misses and there is no refill (nor is there any burst bus cycle; this is[...]

Architecture 80 7. 4 Cache Refill A physical cache line in the R3900 Processor Core comprises 4 words for the instruction cache and 1 word for the data cache. The refill size can be designated independently of the line size. The refill size can be 4/8/16/32 words for the instruction cache, and 1/4/8/16/32 words for the data cache. In a burst read o[...]

Architecture 81 7. 5 Cache Snoop The R3900 Processor Core has a bus arbitration function that releases bus mastership to an external bus master. Consistency between cache memory and main memory could deteriorate when an external bus master has write access to main memory. The purpose of the cache snoop function is to maintain this data consistency.[...]

Architecture 82[...]

Architecture 83 Chapter 8 Debugging Functions The R3900 Processor Core has the following support functions for debugging that have been added to the R3000A instruction base. They are independent of the R3000A architecture, which makes them transparent to user programs. The real-time debugging system is supported by a third party. Debug exceptions ([...]

Architecture 84 The CP0 registers are listed in Table 8-1. Table 8-1. List of system control coprocessor (CP0) registers No Mnemonic Description 0 - (reserved) 1 - (reserved) 2 - (reserved) 3 Config † Hardware configuration 4 - (reserved) 5 - (reserved) 6 - (reserved) 7 Cache † Cache lock function 8 BadVAddr Last virtual address triggering erro[...]

Architecture 85 (1) DEPC (D ebug Exception Program Counter) register (register no.17) The DEPC register holds the address where processing is to resume after the debug exception has been taken care of. (Note : DEPC is a read/write register.) The address that goes in the DEPC register is the virtual address of the instruction that caused the debug e[...]

Architecture 86 n NIS (Non-maskable Interrupt Status) This bit is set to 1 when a Non-maskable interrupt occurs at the same time as a debug exception. In this case the Status, Cause, EPC and BadVAddr registers assume their usual status after the occurrence of a Non-maskable interrupt, but the address in DEPC is not the non-maskable interrupt except[...]

Architecture 87 n DSS (bit 0) Set to 1 to indicate a Single Step exception. DBp and DSS bits indicate the most recent debug exception. Each bit represents one of the two debug exceptions and is set to 1 accordingly when that exception occurs. Note : DSS has a higher priority than DBp, since they occur in the pipeline E stage. For this reason DSS an[...]

Architecture 88 (2) Debug exception handling i) Raising a debug exception n DEPC and Debug register updates DEPC : The address where the exception was raised is put in this register. DBD : Set to 1 when the exception was raised for an instruction in the branch delay slot. DM : Set to 1. DSS, DBp : Set to 1 if the corresponding exception was raised.[...]

Architecture 89 iii) Return from a debug exception handler n When a user program exception occurs at the same time as a Debug exception, change the DEPC value so that a return will be made to the exception handler. When NIS = 1, change DEPC to 0xBFC0 0000. When OES = 1, change DEPC to 0x8000 0080 (if BEV = 0) or 0xBFC0 0180 (if BEV = 0). n Executin[...]

Architecture 90 8. 3 Details of Debug Exceptions (1) Single Step exception • Cause − When the Debug register SSt bit is set, a Single Step exception is raised each time one instruction is executed. • Exception masking − The Single Step exception can be masked by the Debug register SSt bit. When SSt is cleared to 0, a Single Step exception c[...]

Architecture 91 (2) Debug Breakpoint exception • Cause − A Debug Breakpoint exception is raised when an SDBBP instruction is executed. • Exception masking − The Breakpoint exception cannot be masked. (Note : Its behavior during another debug exception is undefined.) • Instruction causing this exception SDBBP • Processing − When this e[...]

Architecture 92[...]

Architecture 93 Appendix A Instruction Set Details This appendix presents each instruction in alphabetical order, explaining its operation in detail. Exceptions that might occur during the execution of each instruction are listed at the end of each explanation. The direct causes of exceptions and how they are handled are explained elsewhere in this[...]

Architecture 94 Instruction Classes The R3900 Processor Core has five classes of CPU instructions, as follows. • Load/store These instructions transfer data between memory and general-purpose registers. "Base register + 16-bit signed immediate offset" is the only supported addressing mode, so the format of all instructions in this class[...]

Architecture 95 Instruction Formats Every instruction consists of a single word (32 bits) aligned on a word boundary. The main instruction formats are shown in Figure A-1. 31 26 25 21 20 16 15 0 op rs rt immediate 31 26 25 0 op target 31 26 25 21 20 16 15 11 10 6 5 0 op rs rt rd sa funct op Operation code (6 bits) rs Source register (5 bits) rt Tar[...]

Architecture 96 Instruction Notation Conventions In this appendix all variable subfields in an instruction format are written in lower-case letters (rs, rt, immediate, etc.). For some instructions, an alias is used for subfield names, for the sake of clarity. For example, rs in a load/store instruction may be referred to as “ base ” . Such an a[...]

Architecture 97 Table A-1. Symbols used in instruction operation notation Symbol Meaning ← Assignment || Bit string concatenation x y Replication of bit value x into a y-bit string. Note that x is always a single-bit value. x y..z Selection of bits y through z of bit string x. Little endian bit notation is always used here. If y is less than z, t[...]

Architecture 98 Examples of Instruction Notation Two examples of the notation used in explaining instructions are given below. Example 1: GPR[r t] ← immediate || 0 16 This means that 16 zero bits are concatenated with an immediate value (normally 16 bits), and the resulting 32-bit string (with the lower 16 bits cleared to 0) is assigned to genera[...]

Architecture 99 Load and Store Instructions With the R3900 Processor Core, the instruction immediately following a load instruction can use the loaded value. Hardware is interlocked for this purpose, causing a delay of one instruction cycle. Programming should be carried out with an awareness of the potential effects of the load delay slot. The des[...]

Architecture 100 Table A-3. Load/Store access type designations Mnemonic Value Meaning WORD 3 Word access (32 bits) TRIPLEBYTE 2 Triplebyte access (24 bits) HALFWORD 1 Halfword access (16 bits) BYTE 0 Byte access (8 bits) The individual bytes in an addressed word can be determined directly from the access type and the low-order two bits of the addr[...]

Architecture 101 Jump and Branch Instructions All jump and branch instructions are executed with a delay of one instruction cycle. This means that the immediately following instruction (the instruction in the delay slot) is executed while the branch target instruction is being fetched. A jump or branch instruction should never be put in the delay s[...]

Architecture 102 ADD Add ADD 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 ADD 100000 6 5 5 5 5 6 Format : ADD rd, rs, rt Description : Adds the contents of general-purpose registers rs and rt and puts the result in general-purpose register rd. If carry-out bits 31 and 30 differ, a two's complement overflow exception is rais[...]

Architecture 103 ADDI Add Immediate ADDI 31 26 25 21 20 16 15 0 ADDI 001000 rs rt immediate 6 5 5 16 Format : ADDI rt, rs, immediate Description : Sign-extends a 16-bit immediate value, adds it to the contents of general-purpose register rs and puts the result in general-purpose register rt. If carry-out bits 31 and 30 differ, a two's compleme[...]

Architecture 104 ADDIU Add Immediate Unsigned ADDIU 31 26 25 21 20 16 15 0 ADDIU 001001 rs rt immediate 6 5 5 16 Format : ADDIU rt, rs, immediate Description : Sign extends a 16-bit immediate value, adds it to the contents of general-purpose register rs and puts the result in general-purpose register rt. The only difference from ADDI is that ADDIU [...]

Architecture 105 ADDU Add Unsigned ADDU 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 ADDU 100001 6 5 5 5 5 6 Format : ADDU rd, rs, rt Description : Adds the contents of general-purpose registers rs and rt and puts the result in general-purpose register rd. The only difference from ADD is that ADDU cannot cause an overflow except[...]

Architecture 106 AND And AND 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 AND 100100 6 5 5 5 5 6 Format : AND rd, rs, rt Description : Bitwise ANDs the contents of general-purpose registers rs and rt and puts the result in general- purpose register rd. Operation : T: GPR[rd] ← GPR[rs] and GPR[rt] Exceptions : None[...]

Architecture 107 ANDI And Immediate ANDI 31 26 25 21 20 16 15 0 ANDI 001100 rs rt immediate 6 5 5 16 Format : ANDI rt, rs, immediate Description : Zero-extends a 16-bit immediate value, bitwise logical ANDs it with the contents of general-purpose register rs and puts the result in general-purpose register rt. Operation : T: GPR[rt] ← 0 16 || (imm[...]

Architecture 108 BCzF Branch On Coprocessor z False BCzF 31 26 25 21 20 16 15 0 COPz 0100xx* BC 01000 BCF 00000 offset 6 5 5 16 Format : BCzF offset Description : Generates a branch target address by adding the address of the instruction in the delay slot to the 16- bit offset (that has been left-shifted two bits and sign-extended to 32 bits). If t[...]

Architecture 109 BCzF Branch On Coprocessor z False (cont.) BCzF Exceptions : Coprocessor Unusable exception Operation Code Bit Encoding : BCzF Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 BC0F 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 BC1F 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 Bit No. 31 30 29[...]

Architecture 110 BCzFL Branch On Coprocessor z False Likely BCzFL 31 26 25 21 20 16 15 0 COPz 0100xx* BC 01000 BCFL 00010 offset 6 5 5 16 Format : BCzFL offset Description : Generates a branch target address by adding the address of the instruction in the delay slot to the 16- bit offset (that has been left-shifted two bits and sign-extended to 32 [...]

Architecture 111 BCzFL Branch On Coprocessor z False Likely (cont.) BCzFL Operation : T − 1: T: T + 1: condition ← not COC[z] target ← (offset 15 ) 14 || offset || 0 2 if condition then PC ← PC + target else NullifyCurrentInstruction endif Exceptions : Coprocessor Unusable exception Operation Code Bit Encoding : BCzFL Bit No. 31 30 29 28 27[...]

Architecture 112 BCzT Branch On Coprocessor z True BCzT 31 26 25 21 20 16 15 0 COPz 0100xx* BC 01000 BCT 00001 offset 6 5 5 16 Format : BCzT offset Description : Generates a branch target address by adding the address of the instruction in the delay slot to the 16- bit offset (that has been left-shifted two bits and sign-extended to 32 bits). If th[...]

Architecture 113 BCzT Branch On Coprocessor z True (cont.) BCzT Exceptions : Coprocessor Unusable exception Operation Code Bit Encoding : BCzT Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 BC0T 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 BC1T 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 Bit No. 31 30 29 [...]

Architecture 114 BCzTL Branch On Coprocessor z True Likely BCzTL 31 26 25 21 20 16 15 0 COPz 0100xx* BC 01000 BCTL 00011 offset 6 5 5 16 Format : BCzTL offset Description : Generates a branch target address by adding the address of the instruction in the delay slot to the 16- bit offset (that has been left-shifted two bits and sign-extended to 32 b[...]

Architecture 115 BCzTL Branch On Coprocessor z True Likely (cont.) BCzTL Exceptions : Coprocessor Unusable exception Operation Code Bit Encoding : BCzTL Bit No . 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 BC0TL 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 BC1TL 0 1 0 0 0 1 0 1 0 0 0 0 0 0 1 1 Bit [...]

Architecture 116 BEQ Branch On Equal BEQ 31 26 25 21 20 16 15 0 BEQ 000100 rs rt offset 6 5 5 16 Format : BEQ rs, rt, offset Description : Generates a branch target address by adding the address of the instruction in the delay slot to the 16- bit offset (that has been left-shifted two bits and sign-extended to 32 bits). The contents of general regi[...]

Architecture 117 BEQL Branch On Equal Likely BEQL 31 26 25 21 20 16 15 0 BEQL 010100 rs rt offset 6 5 5 16 Format : BEQL rs, rt, offset Description : Generates the branch target address by adding the address of the instruction in the delay slot to the 16-bit offset (that has been left-shifted two bits and sign-extended to 32 bits). It compares the [...]

Architecture 118 BGEZ Branch On Greater Than Or Equal To Zero BGEZ 31 26 25 21 20 16 15 0 BCOND 000001 rs BGEZ 00001 offset 6 5 5 16 Format : BGEZ rs, offset Description : Generates a branch target address by adding the address of the instruction in the delay slot to the 16- bit offset (that has been left-shifted two bits and sign-extended to 32 bi[...]

Architecture 119 BGEZAL Branch On Greater Than Or Equal To Zero And Link BGEZAL 31 26 25 21 20 16 15 0 BCOND 000001 rs BGEZAL 10001 offset 6 5 5 16 Format : BGEZAL rs, offset Description : Generates a branch target address by adding the address of the instruction in the delay slot to the 16- bit offset (that has been left-shifted two bits and sign-[...]

Architecture 120 BGEZALL Branch On Greater Than Or Equal To Zero And Link Likely BGEZALL 31 26 25 21 20 16 15 0 BCOND 000001 rs BGEZALL 10011 offset 6 5 5 16 Format : BGEZALL rs, offset Description : Generates a branch target address by adding the address of the instruction in the delay slot to the 16- bit offset (that has been left-shifted two bit[...]

Architecture 121 BGEZL Branch On Greater Than Or Equal To Zero Likely BGEZL 31 26 25 21 20 16 15 0 BCOND 000001 rs BGEZL 00011 offset 6 5 5 16 Format : BGEZL rs, offset Description : Generates a branch target address by adding the address of the instruction in the delay slot to the 16- bit offset (that has been left-shifted two bits and sign-extend[...]

Architecture 122 BGTZ Branch On Greater Than Zero BGTZ 31 26 25 21 20 16 15 0 BGTZ 000111 rs 0 00000 offset 6 5 5 16 Format : BGTZ rs, offset Description : Generates a branch target address by adding the address of the instruction in the delay slot to the 16- bit offset (that has been left-shifted two bits and sign-extended to 32 bits). If the valu[...]

Architecture 123 BGTZL Branch On Greater Than Zero Likely BGTZL 31 26 25 21 20 16 15 0 BGTZL 010111 rs 0 00000 offset 6 5 5 16 Format : BGTZL rs, offset Description : Generates a branch target address by adding the address of the instruction in the delay slot to the 16- bit offset (that has been left-shifted two bits and sign-extended to 32 bits). [...]

Architecture 124 BLEZ Branch On Less Than Or Equal To Zero BLEZ 31 26 25 21 20 16 15 0 BLEZ 000110 rs 0 00000 offset 6 5 5 16 Format : BLEZ rs, offset Description : Generates a branch target address by adding the address of the instruction in the delay slot to the 16- bit offset (that has been left-shifted two bits and sign-extended to 32 bits). If[...]

Architecture 125 BLEZL Branch On Less Than Or Equal To Zero Likely BLEZL 31 26 25 21 20 16 15 0 BLEZL 010110 rs 0 00000 offset 6 5 5 16 Format : BLEZL rs, offset Description : Generates a branch target address by adding the address of the instruction in the delay slot to the 16- bit offset (that has been left-shifted two bits and sign-extended to 3[...]

Architecture 126 BLTZ Branch On Less Than Zero BLTZ 31 26 25 21 20 16 15 0 BCOND 000001 rs BLTZ 00000 offset 6 5 5 16 Format : BLTZ rs, offset Description : Generates a branch target address by adding the address of the instruction in the delay slot to the 16- bit offset (that has been left-shifted two bits and sign-extended to 32 bits). If the val[...]

Architecture 127 BLTZAL Branch On Less Than Zero And Link BLTZAL 31 26 25 21 20 16 15 0 BCOND 000001 rs BLTZAL 10000 offset 6 5 5 16 Format : BLTZAL rs, offset Description : Generates a branch target address by adding the address of the instruction in the delay slot to the 16- bit offset (that has been left-shifted two bits and sign-extended to 32 [...]

Architecture 128 BLTZALL Branch On Less Than Zero And Link Likely BLTZALL 31 26 25 21 20 16 15 0 BCOND 000001 rs BLTZALL 10010 offset 6 5 5 16 Format : BLTZALL rs, offset Description : Generates a branch target address by adding the address of the instruction in the delay slot to the 16- bit offset (that has been left-shifted two bits and sign-exte[...]

Architecture 129 BLTZL Branch On Less Than Zero Likely BLTZL 31 26 25 21 20 16 15 0 BCOND 000001 rs BLTZL 00010 offset 6 5 5 16 Format : BLTZL rs, offset Description : Generates a branch target address by adding the address of the instruction in the delay slot to the 16- bit offset (that has been left-shifted two bits and sign-extended to 32 bits).[...]

Architecture 130 BNE Branch On Not Equal BNE 31 26 25 21 20 16 15 0 BNE 000101 rs rt offset 6 5 5 16 Format : BNE rs, rt, offset Description : Generates a branch target address by adding the address of the instruction in the delay slot to the 16- bit offset (that has been left-shifted two bits and sign-extended to 32 bits). The contents of general [...]

Architecture 131 BNEL Branch On Not Equal Likely BNEL 31 26 25 21 20 16 15 0 BNEL 010101 rs rt offset 6 5 5 16 Format : BNEL rs, rt, offset Description : Generates a branch target address by adding the address of the instruction in the delay slot to the 16- bit offset (that has been left-shifted two bits and sign-extended to 32 bits). The contents [...]

Architecture 132 BREAK Breakpoint BREAK 31 26 25 6 5 0 SPECIAL 000000 code BREAK 001101 6 20 6 Format : BREAK code Description : Raises a Breakpoint exception, then immediately passes control to an exception handler. The code field can be used to pass software parameters, but the only way to have the code field retrieved by the exception handler is[...]

Architecture 133 CACHE Cache CACHE 31 26 25 21 20 16 15 0 CACHE 101111 base op offset 6 5 5 16 Format : CACHE op, offset(base) Description : Generates a virtual address by sign-extending the 16-bit offset and adding the result to the contents of register base. The virtual address is translated to a physical address, and a 5-bit sub-opcode designate[...]

Architecture 134 CACHE Cache (cont.) CACHE Bits 20..18 of the Cache instruction select the operation to be performed as follows. Bit# Cache Operation Description 20 19 18 ID Name 000 I IndexInvalidate Sets the cache state of the cache block to Invalid. This instruction is valid only when the instruction cache is invalid (Config register ICE bit is [...]

Architecture 135 CFCz Move Control From Coprocessor CFCz 31 26 25 21 20 16 15 11 10 0 COPz 0100xx* CF 00010 rt rd 0 000 0000 0000 6 5 5 5 11 Format : CFCz rt, rd Description : Loads the contents of coprocessor z's control register rd into general-purpose register rt. This instruction is not valid when issued for CP0. Operation : T: GPR[rt] ←[...]

Architecture 136 COPz Coprocessor Operation COPz 31 26 25 24 0 COPz 0100xx* CO 1 cofun 6 1 25 Format : COPz cofun Description : Performs the operation designated by cofun in coprocessor z. This operation may involve selecting or accessing internal coprocessor registers or changing the status of the coprocessor condition signal (CPCOND), but will no[...]

Architecture 137 CTCz Move Control To Coprocessor CTCz 31 26 25 21 20 16 15 11 10 0 COPz 0100xx* CT 00110 rt rd 0 000 0000 0000 6 5 5 5 11 Format : CTCz rt, rd Description : Loads the contents of general register rt into control register rd of coprocessor z. This instruction is not valid when issued for CP0. Operation : T: CCR[z, rd] ← GPR[rt] Ex[...]

Architecture 138 DERET Debug Exception Return DERET 31 26 25 24 6 5 0 COP0 010000 CO 1 0 000 0000 0000 0000 0000 DERET 011111 6 1 19 6 Format : DERET Description : Executes a return from a self-debug interrupt or exception. This instruction requires a branch delay slot like that of the branch or jump instructions, and executes with a delay of one i[...]

Architecture 139 DIV Divide DIV 31 26 25 21 20 16 15 6 5 0 SPECIAL 000000 rs rt 0 00 0000 0000 DIV 011010 6 5 5 10 6 Format : DIV rs, rt Description : Divides the contents of general register rs by the contents of general register rt, treating both operands as two's complement integers. An overflow exception is never raised. If the divisor is [...]

Architecture 140 DIVU Divide Unsigned DIVU 31 26 25 21 20 16 15 6 5 0 SPECIAL 000000 rs rt 00000 0 00 0000 0000 DIVU 011011 6 5 5 10 6 Format : DIVU rs, rt Description : This instruction divides the contents of general register rs by the contents of general register rt, treating both operands as two's complement integers. An integer overflow e[...]

Architecture 141 J Jump J 31 26 25 0 J 000010 target 6 26 Format : J target Description : Generates a jump target address by left-shifting the 26-bit target by two bits and combining the result with the high-order 4 bits of the address of the instruction in the delay slot. The program jumps unconditionally to this address after a delay of one instr[...]

Architecture 142 JAL Jump And Link JAL 31 26 25 0 JAL 000011 target 6 26 Format : JAL target Description : Generates a jump target address by left-shifting the 26-bit target by 2 bits and combining the result with the high-order 4 bits of the address of the instruction in the delay slot. The program jumps unconditionally to this address after a del[...]

Architecture 143 JALR Jump And Link Register JALR 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs 0 00000 rd 0 00000 JALR 001001 6 5 5 5 5 6 Format : JALR rs JALR rd, rs Description : Causes the program to jump unconditionally to the address in general register rs after a delay of one instruction cycle. The address of the instruction following t[...]

Architecture 144 JR Jump Register JR 31 26 25 21 20 6 5 0 SPECIAL 000000 rs 0 000 0000 0000 0000 JR 001000 6 5 15 6 Format : JR rs Description : Causes the program to jump unconditionally to the address in general register rs after a delay of one instruction cycle. Since instructions must be aligned on a word boundary, the two low-order bits of tar[...]

Architecture 145 LB Load Byte LB 31 26 25 21 20 16 15 0 LB 100000 base rt offset 6 5 5 16 Format : LB rt, offset(base) Description : Generates a 32-bit effective address by sign-extending the 16-bit offset and adding it to the contents of general-purpose register base. It then sign-extends the byte at the memory location pointed to by the effective[...]

Architecture 146 LBU Load Byte Unsigned LBU 31 26 25 21 20 16 15 0 LBU 100100 base rt offset 6 5 5 16 Format : LBU rt, offset(base) Description : Generates a 32-bit effective address by sign-extending the 16-bit offset and adding it to the contents of general-purpose register base. It then zero-extends the byte at the memory location pointed to by [...]

Architecture 147 LH Load Halfword LH 31 26 25 21 20 16 15 0 LH 100001 base rt offset 6 5 5 16 Format : LH rt, offset(base) Description : Generates a 32-bit effective address by sign-extending the 16-bit offset and adding it to the contents of general-purpose register base. It then sign-extends the halfword at the memory location pointed to by the e[...]

Architecture 148 LHU Load Halfword Unsigned LHU 31 26 25 21 20 16 15 0 LHU 100101 base rt offset 6 5 5 16 Format : LHU rt, offset(base) Description : Generates a 32-bit effective address by sign-extending the 16-bit offset and adding it to the contents of general-purpose register base. It then zero-extends the halfword at the memory location pointe[...]

Architecture 149 LUI Load Upper Immediate LUI 31 26 25 21 20 16 15 0 LUI 00111 0 00000 rt immediate 6 5 5 16 Format : LUI rt, immediate Description : Left-shifts 16-bit immediate by the 16 bits, zero-fills the low-order 16 bits of the word, and puts the result in general register rt. Operation : T: GPR[rt] ← immediate || 0 16 Exceptions : None[...]

Architecture 150 LW Load Word LW 31 26 25 21 20 16 15 0 LW 100011 base rt offset 6 5 5 16 Format : LW rt, offset(base) Description : Generates a 32-bit effective address by sign-extending the 16-bit offset and adding it to the contents of general-purpose register base. It then loads the word at the memory location pointed to by the effective addres[...]

Architecture 151 LWL Load Word Left LWL 31 26 25 21 20 16 15 0 LWL 100010 base rt offset 6 5 5 16 Format : LWL rt, offset(base) Description : Used together with LWR to load four consecutive bytes to a register when the bytes cross a word boundary. LWL loads the left part of the register from the appropriate part of the high-order word; LWR loads th[...]

Architecture 152 LWL Load Word Left (cont.) LWL It is alright to put a load instruction that uses the same rt as the LWL instruction immediately before LWL (or LWR). The contents of general-purpose register rt are bypassed internally in the processor, eliminating the need for a NOP between the two instructions. No Address Error instruction is raise[...]

Architecture 153 LWR Load Word Right LWR 31 26 25 21 20 16 15 0 LWR 100110 base rt offset 6 5 5 16 Format : LWR rt, offset(base) Description : Used together with LWL to load four consecutive bytes to a register when the bytes cross a word boundary. LWR loads the right part of the register from the appropriate part of the low-order word; LWL loads t[...]

Architecture 154 LWR Load Word Right (cont.) LWR It is alright to put a load instruction that uses the same rt as the LWR instruction immediately before LWR. The contents of general-purpose register rt are bypassed internally in the processor, eliminating the need for a NOP between the two instructions. No Address Error instruction is raised due to[...]

Architecture 155 MADD Multiply/Add MADD 31 26 25 21 20 16 15 11 10 6 5 0 MADD / MADDU 011100 rs rt rd 0 00000 MADD 000000 6 5 5 5 5 6 Format : MADD rs, rt MADD rd, rs, rt Description : Multiplies the contents of general registers rs and rt, treating both values as two's complement, and puts the double-word result in special registers HI and LO[...]

Architecture 156 MADDU Multiply/Add Unsigned MADDU 31 26 25 21 20 16 15 11 10 6 5 0 MADD/MADDU 011100 rs rt rd 0 00000 MADDU 000001 6 5 5 5 5 6 Format : MADDU rs, rt MADDU rd, rs, rt Description : Multiplies the contents of general registers rs and rt, treating both values as unsigned , and puts the double-word result in special registers HI and LO[...]

Architecture 157 MFC0 Move From System Control Coprocessor MFC0 31 26 25 21 20 16 15 11 10 0 COP0 010000 MF 00000 rt rd 0 000 0000 0000 6 5 5 5 11 Format : MFC0 rt, rd Description : Loads the contents of coprocessor CP0 register rd into general-purpose register rt. Operation : T: GPR[rt] ← CPR[0, rd] Exceptions : Coprocessor Unusable exception[...]

Architecture 158 MFCz Move From Coprocessor MFCz 31 26 25 21 20 16 15 11 10 0 COPz 0100xx* MF 00000 rt rd 0 000 0000 0000 6 5 5 5 11 Format : MFCz rt, rd Description : Loads the contents of coprocessor z register rd into general-purpose register rt. Operation : T: GPR[rt] ← CPR[z, rd] Exceptions : Coprocessor Unusable exception ∗ Refer also to [...]

Architecture 159 MFCz Move From Coprocessor (cont.) MFCz *Operation Code Bit Encoding : MFCz Bit No. 31 30 29 28 27 26 25 24 23 22 21 0 MFC0 01000 000000 Bit No. 31 30 29 28 27 26 25 24 23 22 21 0 MFC1 01000 100000 Bit No. 31 30 29 28 27 26 25 24 23 22 21 0 MFC2 01001 000000 Bit No. 31 30 29 28 27 26 25 24 23 22 21 0 MFC3 01001 100000 opcode coproc[...]

Architecture 160 MFHI Move From HI MFHI 31 26 25 16 15 11 10 6 5 0 SPECIAL 000000 0 00 0000 0000 rd 0 00000 MFHI 010000 6 10 5 5 6 Format : MFHI rd Description : Loads the contents of special register HI into general-purpose register rd. To guarantee correct operation even if an interrupt occurs, neither of the two instructions following MFHI shoul[...]

Architecture 161 MFLO Move From LO MFLO 31 26 25 16 15 11 10 6 5 0 SPECIAL 000000 0 00 0000 0000 rd 0 00000 MFLO 010010 6 10 5 5 6 Format : MFLO rd Description : Loads the contents of special register LO into general-purpose register rd. To guarantee correct operation even if an interrupt occurs, neither of the two instructions following MFLO shoul[...]

Architecture 162 MTC0 Move To System Control Coprocessor MTC0 31 26 25 21 20 16 15 11 10 0 COP0 010000 MT 00100 rt rd 0 000 0000 0000 6 5 5 5 11 Format : MTC0 rt, rd Description : Loads the contents of general-purpose register rt into CP0 coprocessor register rd. Executing this instruction may in some cases modify the state of the virtual address t[...]

Architecture 163 MTCz Move To Coprocessor MTCz 31 26 25 21 20 16 15 11 10 0 COPz 0100xx* MT 00100 rt rd 0 000 0000 0000 6 5 5 5 11 Format : MTCz rt, rd Description : Loads the contents of general-purpose register rt into coprocessor z register rd. Operation : T: CPR[z, rd] ← GPR[rt] Exceptions : Coprocessor Unusable exception * Operation Code Bit[...]

Architecture 164 MTHI Move To HI MTHI 31 26 25 21 20 6 5 0 SPECIAL 000000 rs 0 000 0000 0000 0000 MTHI 010001 6 5 15 6 Format : MTHI rs Description : Loads the contents of general-purpose register rs into special register HI. If executed after a DIV or DIVU instruction or before a MFLO, MFHI, MTLO or MTHI instruction, the contents of special regist[...]

Architecture 165 MTLO Move To LO MTLO 31 26 25 21 20 6 5 0 SPECIAL 000000 rs 0 000 0000 0000 0000 MTLO 010011 6 5 15 6 Format : MTLO rs Description : Loads the contents of general-purpose register rs into special register LO. If executed after a DIV or DIVU instruction or before a MFLO, MFHI, MTLO or MTHI instruction, the contents of special regist[...]

Architecture 166 MULT Multiply MULT 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 MULT 011000 6 5 5 5 5 6 Format : MULT rs, rt MULT rd, rs, rt Description : Multiplies the contents of general-purpose register rs by the contents of general register rt, treating both register values as 32-bit two's complement values. This inst[...]

Architecture 167 MULTU Multiply Unsigned MULTU 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 MULTU 011001 6 5 5 5 5 6 Format : MULTU rs, rt MULTU rd, rs, rt Description : Multiplies the contents of general-purpose register rs by the contents of general register rt, treating both register values as 32-bit unsigned values. This ins[...]

Architecture 168 NOR Nor NOR 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 NOR 100111 6 5 5 5 5 6 Format : NOR rd, rs, rt Description : Bitwise NORs the contents of general register rs with the contents of general register rt, and loads the result in general register rd. Operation : T: GPR[rd] ← GPR[rs] nor GPR[rt] Exceptions :[...]

Architecture 169 OR Or OR 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 OR 100101 6 5 5 5 5 6 Format : OR rd, rs, rt Description : Bitwise ORs the contents of general-purpose register rs with the contents of general-purpose register rt, and loads the result in general-purpose register rd. Operation : T: GPR[rd] ← GPR[rs] or GPR[...]

Architecture 170 ORI Or Immediate ORI 31 26 25 21 20 16 15 0 ORI 001101 rs rt immediate 6 5 5 16 Format : ORI rt, rs, immediate Description : Zero-extends the 16-bit immediate value, bitwise ORs the result with the contents of general-purpose register rs, and loads the result in general-purpose register rt. Operation : T: GPR[rt] ← GPR[rs] 31..16[...]

Architecture 171 RFE Restore From Exception RFE 31 26 25 24 6 5 0 COP0 010000 CO 1 0 000 0000 0000 0000 0000 RFE 010000 6 1 19 6 Format : RFE Description : Copies the Status register bits for previous interrupt mask mode and previous kernel/user mode (IEp and KUp) to the current mode bits (IEc and KUc), and copies the old mode bits (IEo and KUo) to[...]

Architecture 172 SB Store Byte SB 31 26 25 21 20 16 15 0 SB 101000 base rt offset 6 5 5 16 Format : SB rt, offset(base) Description : Generates a 32-bit effective address by sign-extending the 16-bit offset and adding it to the contents of general-purpose register base. It then stores the least significant byte of register rt at the resulting effec[...]

Architecture 173 SDBBP Software Debug Breakpoint SDBBP 31 26 25 6 5 0 SPECIAL 000000 code SDBBP 001110 6 20 6 Format : SDBBP code Description : Raises a Debug Breakpoint exception, passing control to an exception handler. The code field can be used for passing information to the exception handler, but the only way to have the code field retrieved b[...]

Architecture 174 SH Store Halfword SH 31 26 25 21 20 16 15 0 SH 101001 base rt offset 6 5 5 16 Format : SH rt, offset(base) Description : Generates an unsigned 32-bit effective address by sign-extending the 16-bit offset and adding it to the contents of general-purpose register base. It then stores the least significant halfword of register rt at t[...]

Architecture 175 SLL Shift Left Logical SLL 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 0 00000 rt rd sa SLL 000000 6 5 5 5 5 6 Format : SLL rd, rt, sa Description : Left-shifts the contents of general-purpose register rt by sa bits, zero-fills the low-order bits, and puts the result in register rd. Operation : T: GPR[rd] ← GPR[rt] 31-sa..0 |[...]

Architecture 176 SLLV Shift Left Logical Variable SLLV 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 0 0000 SLLV 000100 6 5 5 5 5 6 Format : SLLV rd, rt, rs Description : Left-shifts the contents of general-purpose register rt (by the number of bits designated in the low- order five bits of general-purpose register rs), zero-fills the [...]

Architecture 177 SLT Set On Less Than SLT 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 SLT 101010 6 5 5 5 5 6 Format : SLT rd, rs, rt Description : Compares the contents of general-purpose registers rt and rs as 32-bit signed integers. A 1, if rs is less than rt, or a 0, otherwise, is placed in general-purpose register rd as the[...]

Architecture 178 SLTI Set On Less Than Immediate SLTI 31 26 25 21 20 16 15 0 SLTI 001010 rs rt immediate 6 5 5 16 Format : SLTI rt, rs, immediate Description : Sign-extends the 16-bit immediate value and compares the result with the contents of general- purpose register rs, treating both values as 32-bit signed integers. A 1, if rs is less than the[...]

Architecture 179 SLTIU Set On Less Than Immediate Unsigned SLTIU 31 26 25 21 20 16 15 0 SLTIU 001011 rs rt immediate 6 5 5 16 Format : SLTIU rt, rs, immediate Description : Sign-extends the 16-bit immediate value and compares the result with the contents of general- purpose register rs, treating both values as 32-bit unsigned integers. A 1, if rs i[...]

Architecture 180 SLTU Set On Less Than Unsigned SLTU 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 SLTU 101011 6 5 5 5 5 6 Format : SLTU rd, rs, rt Description : Compares the contents of general registers rt and rs as 32-bit unsigned integers. A 1, if rs is less than rt, or a 0, otherwise, is placed in general-purpose register rd[...]

Architecture 181 SRA Shift Right Arithmetic SRA 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 0 00000 rt rd sa SRA 000011 6 5 5 5 5 6 Format : SRA rd, rt, sa Description : Right-shifts the contents of general-purpose register rt by sa bits, sign-extends the high-order bits, and puts the result in register rd. Operation : T: GPR[rd] ← (GPR[rt] 3[...]

Architecture 182 SRAV Shift Right Arithmetic Variable SRAV 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 SRAV 000111 6 5 5 5 5 6 Format : SRAV rd, rt, rs Description : Right-shifts the contents of general-purpose register rt (by the number of bits designated in the low- order five bits of general-purpose register rs), sign-extend[...]

Architecture 183 SRL Shift Right Logical SRL 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 0 00000 rt rd sa SRL 000010 6 5 5 5 5 6 Format : SRL rd, rt, sa Description : Right-shifts the contents of general-purpose register rt by sa bits, zero-fills the high-order bits, and puts the result in register rd. Operation : T: GPR[rd] ← 0 sa || GPR[rt][...]

Architecture 184 SRLV Shift Right Logical Variable SRLV 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 SRLV 000110 65555 6 Format : SRLV rd, rt, rs Description : Right-shifts the contents of general register rt (by the number of bits designated in the low-order five bits of general register rs), zero-fills the high-order bits, and[...]

Architecture 185 SUB Subtract SUB 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 SUB 100010 65555 6 Format : SUB rd, rs, rt Description : Subtracts the contents of general-purpose register rt from general-purpose register rs and puts the result in general-purpose register rd. If carry-out bits 31 and 30 differ, a two's comple[...]

Architecture 186 SUBU Subtract Unsigned SUBU 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 SUBU 100011 6 5 5 5 5 6 Format : SUBU rd, rs, rt Description : Subtracts the contents of general-purpose register rt from general-purpose register rs and puts the result in general-purpose register rd. The only difference from SUB is that S[...]

Architecture 187 SW Store Word SW 31 26 25 21 20 16 15 0 SW 101011 base rt offset 6 5 5 16 Format : SW rt, offset(base) Description : Generates a 32-bit effective address by sign-extending the 16-bit offset value and adding it to the contents of general-purpose register base. It then stores the contents of register rt at the resulting effective add[...]

Architecture 188 SWL Store Word Left SWL 31 26 25 21 20 16 15 0 SWL 101010 base rt offset 6 5 5 16 Format : SWL rt, offset(base) Description : Used together with SWR to store the contents of a register into four consecutive bytes of memory when the bytes cross a word boundary. SWL stores the left part of the register into the appropriate part of th[...]

Architecture 189 SWL Store Word Left (cont.) SWL Operation : T: vAddr ← ((offset 15 ) 16 || offset 15..0 ) + GPR[base] (pAddr, uncached) ← AddressTranslation (vAddr, DATA) pAddr ← pAddr 31..2 || (pAddr 1..0 xor ReverseEndian 2 ) If BigEndianMem = 0 then pAddr ← pAddr 31..2 || 0 2 endif byte ← vAddr 1..0 xor BigEndianCPU 2 data ← 0 24 - [...]

Architecture 190 SWR Store Word Right SWR 31 26 25 21 20 16 15 0 SWR 101110 base rt offset 6 5 5 16 Format : SWR rt, offset(base) Description : Used together with SWL to store the contents of a register into four consecutive bytes of memory when the bytes cross a word boundary. SWR stores the right part of the register into the appropriate part of [...]

Architecture 191 SWR Store Word Right (cont.) SWR Operation : T: vAddr ← ((offset 15 ) 16 || offset 15..0 ) + GPR[base] (pAddr, uncached) ← AddressTranslation (vAddr, DATA) pAddr ← pAddr 31..2 || (pAddr 1..0 xor ReverseEndian 2 ) If BigEndianMem = 0 then pAddr ← pAddr 31..2 || 0 2 endif byte ← vAddr 1..0 xor BigEndianCPU 2 data ← GPR[rt[...]

Architecture 192 SYNC Synchronize SYNC 31 26 25 6 5 0 SPECIAL 000000 0 0000 0000 0000 0000 0000 SNYC 001111 6 20 6 Format : SYNC Description : Interlocks the pipeline until the load, store or data cache refill operation of the previous instruction is completed. The R3900 Processor Core can continue processing instructions following a load instructi[...]

Architecture 193 SYSCALL System Call SYSCALL 31 26 25 6 5 0 SPECIAL 000000 code SYSCALL 001100 6 20 6 Format : SYSCALL code Description : Raises a System Call exception, then immediately passes control to an exception handler. The code field can be used to pass information to an exception handler, but the only way to have the code field retrieved b[...]

Architecture 194 XOR Exclusive Or XOR 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 XOR 100110 6 5 5 5 5 6 Format : XOR rd, rs, rt Description : Bitwise exclusive-ORs the contents of general-purpose register rs with the contents of general- purpose register rt and loads the result in general-purpose register rd. Operation : T: GP[...]

Architecture 195 XORI Exclusive Or Immediate XORI 31 26 25 21 20 16 15 0 XORI 001110 rs rt immediate 6 5 5 16 Format : XORI rt, rs, immediate Description : Zero-extends the 16-bit immediate value, bitwise exclusive-ORs it with the contents of general- purpose register rs, then loads the result in general-purpose register rt. Operation : T: GPR[rt] [...]

Architecture 196 Bit Encoding of CPU Instruction Opcodes Figure A-2 shows the bit codes for all CPU instructions (ISA and extended ISA). OPcode 28..26 31..29 0 1 2 3 4 5 6 7 0 SPECIAL BCOND J JAL BEQ BNE BLEZ BGTZ 1 ADDI ADDIU SLTI SLTIU ANDI ORI XORI LUI 2 COP0 COP1 COP2 COP3 BEQL δ BNEL δ BLEZL δ BGTZL δ 3 * * * * MADD/ MADDU δ * * * 4 LB LH[...]

Architecture 197 COPz rt 18..16 20..19 0 1 2 3 4 5 6 7 0 BCF BCT BCFL χ BCTL χ γ γ γ γ 1 γ γ γ γ γ γ γ γ 2 γ γ γ γ γ γ γ γ 3 γ γ γ γ γ γ γ γ CP0 Function 2.0 5..3 0 1 2 3 4 5 6 7 0 φ (TLBR) φ ( TLBWI ) φ φ φ φ ( TLBWR ) φ φ 1 (TLBP) φ φ φ φ φ φ φ φ 2 RFE φ φ φ φ φ φ φ 3 * φ φ φ φ φ φ DERET [...]

Architecture 198 Notation : * Reserved for future architecture implementations; use of this instruction with existing versions raises a Reserved Instruction exception. γ Invalid instruction, but dose not raise Reserved Instruction exception in the case of the R3900 Processor Core. δ Valid on the R3900 Processor Core but raises a Reserved Instruct[...]

TMPR3901F 199 TMPR3901F[...]

TMPR3901F 200[...]

TMPR3901F 201 Chapter 1 Introduction This document describes the specifications of the TMPR3901F microprocessor. The R3900 Processor Core is incorporated into the TMPR3901F. 1. 1 Features The TMPR3901F is a general-purpose microprocessor incorporating on-chip the 32-bit R3900 Processor Core, developed by Toshiba. In addition to the processor core i[...]

TMPR3901F 202 (4) Low power consumption, optimal for portable applications • 3.3 V operation • 600 mW (at 50 MHz operation) • Halt, Doze, Reduced-Frequency modes supported in processor core • PLL can be turned off externally (standby mode) (5) Debugging support functions on chip • Hardware break function, single-step function on chip • [...]

TMPR3901F 203 Address Protection Unit Debug Support Unit R3900 Processor Core 1KB Data Cache 4KB Instruction Cache CPU core Bus Controller / Write Buffer System Interface Interrupt Reset Real-time Debugger Interface Synchroni- zer Clock Generator 1. 2 Internal Blocks The TMPR3901F comprises the following blocks (Figure 1-1). (1) R3900 Processor Cor[...]

TMPR3901F 204 2.[...]

TMPR3901F 205 Address Protection Unit Debug Support Unit R3900 Processor Core 1KB Data Cache 4KB Instruction Cache CPU core Bus Controller / Write Buffer System Interface Interrupt Reset Real-time Debugger Interface Synchroni- zer Clock Generator Chapter 2 Configuration This chapter describes the configuration of the TMPR3901F. A block diagram of t[...]

TMPR3901F 206 2. 1 .2 Address mapping Address mapping in the TMPR3901F is performed by the direct segment mapping MMU in the R3900 Processor Core. The TMPR3901F uses the kseg2 reserved area (0xFF00 0000 - 0xFFFF FFFF) as follows. 0xFF00 0000 - 0xFF00 FFFF address protection unit 0xFF20 0000 - 0xFF3F FFFF debug support unit The TMPR3901F outputs bus[...]

TMPR3901F 207 2. 3 Bus Interface Unit (Bus Controller / Write Buffer) The bus interface unit controls TMPR3901F bus operations. Bus operations are synchronous with the rising edge of SYSCLK. The bus interface unit has a four-deep write buffer. The R3900 Processor Core can complete write operations without pipeline stall. There may be conflicts betw[...]

TMPR3901F 208 2.4 Address Protection Unit The TMPR3901F has an address protection unit that allows two virtual address breakpoints to be set. Figure 2-2 shows a block diagram of the address protection unit. 2.4.1 Registers (a) Break Address register (BAddr0-1) The break address register is used to set a break address. BAddr0 is for channel 0, and B[...]

TMPR3901F 209 (b) Break Mask register (BMsk0-1) The break mask register holds the bit mask used for address comparison. BMsk0 is for channel 0, and BMsk1 is for channel 1. BMsk[31:2] (Break Mask) This is the bit mask for address comparison. Only those bits in the BAddr register that have their corresponding bits set to 1 in the BMsk register are co[...]

TMPR3901F 210 (d) Break Status register (BSts) The break status register is used to set conditions for exception requests. MInv [9] (Master Overlay Invert) If this bit is set to 1, exception requests are triggered by an XOR of the channel 0 and channel 1 address comparison results.This means that an exception request occurs if the address compariso[...]

TMPR3901F 211 2. 4 .3 Register address map Seven registers associated with the memory protection scheme are mapped in from the kernel memory space. Table 2-1 shows the addresses of these registers. Table 2-1. Address protection unit control register addresses Register Virtual address BSts 0xFF00 0010 BAddr0 0xFF00 0020 Bcnt0 0xFF00 0024 BMsk0 0xFF0[...]

TMPR3901F 212 (2) INT[5:0]* The INT[5:0] * signal is synchronized with the processor clock in phase with SYSCLK (Figure 2-4). Figure 2-4 INT* signal synchronization Interrupt detection SYSCLK INT*(external) INT*(internal) (a) Full-speed bus mode Instruction at interrupt handler starts F D E M F D E Interrupt detection (b) Half-speed bus mode F D E [...]

TMPR3901F 213 (3) NMI* The NMI * signal is synchronized with the processor clock in phase with SYSCLK (Figure 2-5). Figure 2-5 NMI* signal synchronization NMI detection SYSCLK NMI*(external) NMI*(internal) (a) Full-speed bus mode Instruction at interrupt handler starts F D E M F D E NMI detection (b) Half-speed bus mode F D E M F D E SYSCLK Process[...]

TMPR3901F 214 (4) CPCOND[3:1] The CPCOND[3:1] signal is synchronized with the processor clock in phase with SYSCLK (Figure 2- 6). CPCOND*(external) CPCOND*(internal) BCzF target instruction BCzF Delay slot instruction SYSCLK CPCOND detection (a) Full-speed bus mode F D E M W F D E M W F D E M W (b) Half-speed bus mode Processor clock CPCOND*(extern[...]

TMPR3901F 215 Chapter 3 Pins The following table summarizes the TMPR3901F pins. NAME I/O DESCRIPTION A [31:2] I/O Address bus. When TMPR3901F has bus mastership, outputs the address to be accessed. When TMPR3901F releases bus mastership, inputs the data cache snoop address. BE [3:0]* O Byte-enable signal. At read and write, indicates which bytes of[...]

TMPR3901F 216 NAME I/O DESCRIPTION BUSGNT* O Bus grant signal. Used by TMPR3901F to indicate it has released bus mastership in response to a request by an external bus master. XIN I Connect to crystal oscillator. XOUT O Connect to crystal oscillator. PLLOFF* I Stops internal PLL oscillation. CLKEN I Enables internal PLL clock. SYSCLK O System clock[...]

TMPR3901F 217 Chapter 4 Operations This chapter shows TMPR3901F bus operations and timing. All TMPR3901F bus operations are synchronized with the rising edge of SYSCLK. The bus operation pin states are as follows when no bus operations are being performed. A [31:2] undefined D [31:0] high impedance BE [3:0] * H RD * , WR * H LAST * H BSTART * H BUR[...]

TMPR3901F 218 The relationship among the clocks is shown in the table below. Master clock (FCLK) RF [1:0] Processor clock HALF* System clock (SYSCLK) 00 1 H 1 L 1/2 01 1/2 H 1/2 1 L 1/4 10 1/4 H 1/4 L 1/8 11 1/8 H 1/8 L 1/16[...]

TMPR3901F 219 4.2 Read Operation The TMPR3901F supports two kinds of read operations single read and burst read . 4.2.1 Single Read The single read operation reads four bytes or less data. It is used in the following cases. • On a data cache miss (the data cache is not set for burst read) • An instruction fetch or data load from an uncached are[...]

TMPR3901F 220 At the start of a single read, the BSTART * signal is asserted for one clock cycle only. At the same time the RD * and LAST * signals are asserted. Then the address A[31:2] and BE[3:0] * signals are valid. An external circuit drives the data onto the data bus and asserts an ACK * signal. The TMPR3901F samples the ACK * signal at the r[...]

TMPR3901F 221 4. 2 .2 Burst Read Burst read operation is used to refill a multiword area in cache memory. Because the second and each succeeding data in a burst read operation can each be read in a single cycle, multiword data can be read in from memory very quickly in this mode. Burst read operation is issued whenever a cache miss occurs with eith[...]

TMPR3901F 222 Figure 4-3 Burst read (4 words : 1 wait) SYSCLK A[31:2] BE[3:0]* RD* BSTART* LAST* BURST* BSTSZ[1:0] ACK* BUSERR* D[31:0] 00[...]

TMPR3901F 223 BUSERR * is valid until the clock cycle in which the last data is read. In the clock cycle in which the TMPR3901F recognizes the assertion of BUSERR * , the TMPR3901F ends the burst read cycle and raises a Bus Error exception (see Figure 4-4). When a bus error occurs in a burst read, only those cache lines for which complete reads wer[...]

TMPR3901F 224 4. 3 Write Operation The TMPR3901F supports only single write operations for writes. Figure 4-5 shows the timing for a single-write operation. At the start of the operation, the BSTART * signal is asserted for one clock only. At the same time the WR * and LAST * signals are asserted. Then the address A[31:2] and BE[3:0] * signals are [...]

TMPR3901F 225 4. 4 Interrupts The TMPR3901F supports six hardware interrupts and two software interrupts. It also supports a non- maskable interrupt. The INT[5:0] * signals can be used to raise interrupt exceptions. The NMI * signal is used to raise a non-maskable interrupt exception. All of the interrupt signals are low-active and should be synchr[...]

TMPR3901F 226 4. 4 .2 INT[5:0]* The INT[5:0] * signals are used to invoke interrupt exceptions. These interrupts can be masked with the IntMask field of the Status register. The TMPR3901F recognizes an INT[5:0] * signal on the SYSCLK rising edge (Figure 4-7). 1 Recognize INT[5:0] * high signal. 2 Recognize INT[5:0] * low signal, thus invoking inter[...]

TMPR3901F 227 4. 5 Bus Arbitration 4. 5 .1 Bus request and bus grant An external bus master can request that the TMPR3901F grant control of the bus. This is done by asserting the BUSREQ * signal. In response, the TMPR3901F will release the bus and assert a BUSGNT * signal. If BUSREQ * is asserted, while the TMPR3901F is already engaged in a bus ope[...]

TMPR3901F 228 The BUSREQ * signal is confirmed on the rising edge of SYSCLK. If no bus operation is currently in progress, the BUSGNT * signal is asserted in the next clock after the BUSREQ * assertion is confirmed. The TMPR3901F stops driving the bus in the next clock, thus releasing it. During the time the bus is released by the TMPR3901F, the pi[...]

TMPR3901F 229 4. 6 Reset The TMPR3901F can be reset with the RESET * signal. The RESET * signal must be asserted for a certain number of R3900 Processor Core clock cycles in order for the TMPR3901F reset to take effect. Since the RESET * signal is clock-synchronized with in the TMPR3901F, it can be asserted asynchronously . TMPR3901F operations upo[...]

TMPR3901F 230 4. 7 Half-Speed Bus Mode To accommodate slower peripheral circuits, the TMPR3901F offers a half-speed bus mode in which bus operations are clocked at half the frequency of the R3900 Processor Core. This mode is selected by setting the HALF * signal to low. When HALF * is set to high, bus operations occur at the same frequency at which[...]

TMPR3901F 231 Chapter 5 Power-Down Mode The TMPR3901F has the following four power-down modes to enable lower power dissipation through control of the internal clock. • Halt mode • Standby mode • Doze mode • Reduced Frequency mode 5.1 Halt mode Figure 5-1 shows a state diagram of power down mode. The TMPR3901F stops internal operations in H[...]

TMPR3901F 232 The TMPR3901F sets the HALT signal according to the status of the Halt bit in the Config register. Output signals of the memory interface during Halt mode are the same as when a bus operation is not in progress.[...]

TMPR3901F 233 5. 2 Standby Mode Stopping the PLL clock in the TMPR3901F results in even less power dissipation than in Halt mode. This is referred to as standby mode. To transit from Active mode to Standby mode, first set the Halt bit the config register to 1. Then, follow the sequence below to empty the write buffer. Finally, set the Halt bit to 1[...]

TMPR3901F 234 5. 3 Doze Mode In this mode, the TMPR3901F stops internal operations the same as in Halt mode to reduce power dissipation. However, in Doze mode bus arbitration and data cache snooping can continue. Setting the Config register Doze bit to 1 switches from Active mode to Doze mode. During Doze mode, the TMPR3901F will assert the DOZE si[...]

TMPR3901F 235 5. 4 Reduced Frequency Mode The TMPR3901F processor clock frequency can be controlled with the Config register RF field. A slower processor clock frequency enables lower power dissipation by the TMPR3901F. The relationship between the RF field and processor clock is follows. RF[1:0] processor clock/master clock 00 1/1 01 1/2 10 1/4 11[...]