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Xilinx LogiCore PLB PCI Full Bridge manuel d'utilisation

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Le mot vient du latin "Instructio", à savoir organiser. Ainsi, le manuel d’utilisation Xilinx LogiCore PLB PCI Full Bridge décrit les étapes de la procédure. Le but du manuel d’utilisation est d’instruire, de faciliter le démarrage, l'utilisation de l'équipement ou l'exécution des actions spécifiques. Le manuel d’utilisation est une collection d'informations sur l'objet/service, une indice.

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Tout d'abord, le manuel d’utilisation Xilinx LogiCore PLB PCI Full Bridge devrait contenir:
- informations sur les caractéristiques techniques du dispositif Xilinx LogiCore PLB PCI Full Bridge
- nom du fabricant et année de fabrication Xilinx LogiCore PLB PCI Full Bridge
- instructions d'utilisation, de réglage et d’entretien de l'équipement Xilinx LogiCore PLB PCI Full Bridge
- signes de sécurité et attestations confirmant la conformité avec les normes pertinentes

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Habituellement, cela est dû au manque de temps et de certitude quant à la fonctionnalité spécifique de l'équipement acheté. Malheureusement, la connexion et le démarrage Xilinx LogiCore PLB PCI Full Bridge ne suffisent pas. Le manuel d’utilisation contient un certain nombre de lignes directrices concernant les fonctionnalités spécifiques, la sécurité, les méthodes d'entretien (même les moyens qui doivent être utilisés), les défauts possibles Xilinx LogiCore PLB PCI Full Bridge et les moyens de résoudre des problèmes communs lors de l'utilisation. Enfin, le manuel contient les coordonnées du service Xilinx en l'absence de l'efficacité des solutions proposées. Actuellement, les manuels d’utilisation sous la forme d'animations intéressantes et de vidéos pédagogiques qui sont meilleurs que la brochure, sont très populaires. Ce type de manuel permet à l'utilisateur de voir toute la vidéo d'instruction sans sauter les spécifications et les descriptions techniques compliquées Xilinx LogiCore PLB PCI Full Bridge, comme c’est le cas pour la version papier.

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Tout d'abord, il contient la réponse sur la structure, les possibilités du dispositif Xilinx LogiCore PLB PCI Full Bridge, l'utilisation de divers accessoires et une gamme d'informations pour profiter pleinement de toutes les fonctionnalités et commodités.

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Table des matières du manuel d’utilisation

  • Page 1

    0 PLB PCI Full Bridge (v1.00a) DS508 March 21, 20 06 0 0 Product Specification DS508 March 21, 2006 www .xilinx.com 1 Product Specification © 2005 Xilinx, Inc. All rights r eserved. All Xilinx trademarks, re gistered trademarks, patents, and furth er disclaimers are as listed at http://www .xilinx.com/legal.htm . All other trademarks and registere[...]

  • Page 2

    PLB PCI Full Bridge (v1.00 a) 2 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS Features • Independent PLB and PCI clocks • 33 MHz, 32-bit PCI bus support • Utilizes two pairs of FIFOs to exploit the separate master and slave PL B IPIF modules . • Includes a master IP module for r emote PCI init iator transactions,[...]

  • Page 3

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 3 Product Specification E AR L Y ACCESS default in al l transfers. Addr ess translation is performe d by high-order bit substitution. High-or der bit definition is defined only by parameters •R e g i s t e r s i n c l u d e - Interr upt and interrupt enable registers at differ ent [...]

  • Page 4

    PLB PCI Full Bridge (v1.00 a) 4 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS System Reset When the bridge is reset, both RST_N and PLB_reset must be simultaneously held at reset for at least twenty clock periods of the slowest clock. Ev aluation V er sion The PLB PCI Bridge is deliver ed with a hardwar e evaluation lice[...]

  • Page 5

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 5 Product Specification E AR L Y ACCESS core. These documents detail the v3.0 core operatio n, including configuration cycles, and are available from Xilinx. As re quired by the LogiCORE v3. 0 core, GNT_N must be asserted for two clock cycles to initiate a PCI transaction by the PLB [...]

  • Page 6

    PLB PCI Full Bridge (v1.00 a) 6 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS Example 3 outlines the use of the PCIBAR parameter sets for the address translation of PCI addresses within the range of a given PCIBAR to a r emote PLB addr ess space . Figure 2: T ranslation of Addresses Bus-to-Bus with High-Order Bit Substit[...]

  • Page 7

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 7 Product Specification E AR L Y ACCESS As in example 1, it is assumed that the pa rameter C_INCLUDE_BAROFFSET_REG=0, ther efore the C_IPIFBAR2PCIBAR_N parameters define the addr ess translation. In this example, where C_IPIFBAR_NUM=4, the following assignments for each range ar e ma[...]

  • Page 8

    PLB PCI Full Bridge (v1.00 a) 8 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS Accessing the PLB PCI Bridge PCIBAR_1 with address 0x1235FEDC on the PCI bus yields 0xFE35FEDC on the PLB bus. T able 1: PLB PCI Bridge Interface Design Parameter s Generic Feature / Description Pa rameter Name Allowable V alues Default Va l u [...]

  • Page 9

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 9 Product Specification E AR L Y ACCESS G13 IPIF BAR 2 memory designator C_IPIF_SP ACE TYPE_2 0 = I/O space 1 = Memory space 1 integer G14 IPIF de vice 3 BAR C_IPIFBAR_3 V alid PLB address (1), (2) 0xFFFFFFFF std_logi c_ vec t o r G15 IPIF BAR high address 3 C_IPIFBAR_ HIGHADDR_3 V a[...]

  • Page 10

    PLB PCI Full Bridge (v1.00 a) 10 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS G27 IPIF BAR to which PCI BAR 0 is mapped C_PCIBAR2 IPIFBAR_0 V ector of leng th C_PLB_A WIDTH 0x00000000 std_lo gic_ vec t o r G28 P ow er of 2 in the size in bytes of PCI BAR 0 space C_PCIBAR_ LEN_0 5 to 29 16 integer G29 IPIF BAR to which P[...]

  • Page 11

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 11 Product Specification E AR L Y ACCESS G40 PCI2IPIF FIFO occupancy le vel in double words that triggers the br idge to initiate an IPIF b urst write to remote PLB de vice C_TRIG_IPIF_ WRBURST_ OCC_LEVEL 2 to the lesser of 24 or the PCI2IPIF FIFO DEPTH-3. PCI2IPIF FIFO DEPTH given b[...]

  • Page 12

    PLB PCI Full Bridge (v1.00 a) 12 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS G50 Number of IDELA Y controllers instantiated. Ignored it not Vir tex-4 C_NUM_ IDELA YCTRL 2-6 (Vir tex-4 only) 2 integer G51 Includes IDELA Y primiti ve on GNT_N. Set by tcl-scripts and ignored i f not Vir te x-4. C_INCLUDE_ GNT_DELA Y 1=Inc[...]

  • Page 13

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 13 Product Specification E AR L Y ACCESS G61 Include configuration functionality via IPIF transactions C_INCLUDE_ PCI_CONFIG 0 = Not included 1 = Included 1 integer G62 Number of IDSEL signals suppor te d C_NUM_ IDSEL 1 to 16 8 integer G63 PCI address bit that PC I v3.0 core IDSEL is[...]

  • Page 14

    PLB PCI Full Bridge (v1.00 a) 14 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS PLB PCI Bus Interface I/O Signals The I/O signals for the PLB PCI Bridge are li sted in Ta b l e 2 . The interfaces r eferenced in this table are shown in Figure 1 in the PLB PCI Bridge block diagram. T able 2: PLB PCI Brid ge I/O Signals Po r[...]

  • Page 15

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 15 Product Specification E AR L Y ACCESS P27 Sl_rdBT er m PLB Bus O P28 Sl_MBusy(0:C_PLB_NU M_MASTERS-1) PLB Bus O P29 Sl_MErr(0:C_PLB_NUM _MASTERS-1) PLB Bus O P30 PLB_MAddrAck PLB Bus I P31 PLB_MSSiz e(0:1) PLB Bus I P32 PLB_MRearbitrate PLB Bus I P33 PLB_MBusy PLB Bus I P34 PLB_ME[...]

  • Page 16

    PLB PCI Full Bridge (v1.00 a) 16 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS P55 CBE[(C_PCI_DBUS_WI DTH/8)-1:0] PCI Bus I/O Ti me-multiplex ed bus command and byte enab le bus P56 PA R PCI Bus I/O Ge nerates and checks e ven parity across AD and CBE PCI T ransaction Control Signals P57 FRAME_N PCI Bus I/O Dr iven b y a[...]

  • Page 17

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 17 Product Specification E AR L Y ACCESS The REQ_N_toArb f acilitates an interfa ce to an intern al (i.e., in the FPGA) pci arbiter . The v3.0 input buffer for GNT_N is removed. This allows an inte rnal connection to GNT_N when using an internal arbiter . When an external arbiter is [...]

  • Page 18

    PLB PCI Full Bridge (v1.00 a) 18 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS P ort and P arameter Dependencies The dependencies between the IPI v3.0 Bridge design port (i.e., I/O signals) and parameters ar e shown in Ta b l e 1. T able 3: PLB PCI Bridge P arameters-P ort Dependencies Generic Pa r a m e t e r Affects De[...]

  • Page 19

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 19 Product Specification E AR L Y ACCESS G12 C_IPIFBAR2PCIBAR_2 G1, G10, G11 and G48 Meaningful only if G48 = 0 and G1>2. In this case only high-order bits that are the same in G10 and G11 are meaningful. G13 C_IPIF_SP ACETYPE_2 G1 Meaningful only if G1>2 G14 C_IPIFBAR_3 G15 G1[...]

  • Page 20

    PLB PCI Full Bridge (v1.00 a) 20 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS G26 C_PCIBAR_NUM G27-G32 The set of PCI/v3.0 BAR-parameters of N = 0 to C_PCIBAR_NUM-1 are meaningful and the parameters of N = C_PCIBAR_NUM up to an d including 2 hav e no effect. If C_PCIBAR_NUM = 3, the set of PCI/v3.0 BAR-parameters of N =[...]

  • Page 21

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 21 Product Specification E AR L Y ACCESS G43 C_NUM_PCI_RETRIES_IN _WRITES G44 C_NUM_PCI_PRDS_BET WN_RETRIES_IN_ WRITES G45 C_NUM_IPIF_RETRIES_ IN_WRITES G46 C_BASEADDR G47 G47 G46 to G47 define range in PLB-memo r y space that is responded to by PLB PCI bridge register address space [...]

  • Page 22

    PLB PCI Full Bridge (v1.00 a) 22 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS Suppor ted PCI Bus Commands The list of commands suppor ted by the LogiCORE PCI interface is pr ovided in Ta b l e 4 . G62 C_NUM_IDSEL G49 and G63 G61 and G63 If G61=0, G62 has no meaning. If G61=1, G62 sets the number of devices suppor ted in[...]

  • Page 23

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 23 Product Specification E AR L Y ACCESS PLB PCI Bridge Register Descriptions The PLB PCI Bridge contains addr essable r egist ers for read/write operations as shown in Ta b l e 5 . The base addr ess for these r egisters is set by the ba se address parameter (C_BASEADDR). The address[...]

  • Page 24

    PLB PCI Full Bridge (v1.00 a) 24 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS Register and P a rameter Dependencies The addr essable registers in the PLB PCI Bridge depend on the parame ter settings shown in Ta b l e 6 . T able 6: Register and P arameter Dependencies Regist er Name P arameter D ependence De vice Inte rr[...]

  • Page 25

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 25 Product Specification E AR L Y ACCESS Global Interrupt Ena ble Register De scription A global enable is provided to globally enable or disable interrupts from the PCI device. This bit is AND’d with the output to the interrupt controlle r . Bit assignment is shown in Ta b l e 7 .[...]

  • Page 26

    PLB PCI Full Bridge (v1.00 a) 26 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS Bridge Interrupt E nable Register Description The PLB PCI Bridge has interrupt enable featur es as described in IPSPEC 048 PLB Device Interrupt Architectur e . Bit assignment in the Bridge Interrupt Enable Re gister is shown in Ta b l e 9 . Th[...]

  • Page 27

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 27 Product Specification E AR L Y ACCESS PLB PCI Bridge Reset Register Description The IP Reset module is always instantiated in the PLB PCI Bridge. Details on the IPIF Reset modul e can be found in the Processor IP Reference Guide . The IP Reset module permits the softwar e reset of[...]

  • Page 28

    PLB PCI Full Bridge (v1.00 a) 28 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS Configuration Address P ort Register Description The Configuration Addres s Port Register exists only if the bridge is configured with PCI host bridge configuration functionality (i. e., C_INCLUDE_PCI_CONFIG=1). T h i s r e g i s t e r i s r e[...]

  • Page 29

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 29 Product Specification E AR L Y ACCESS bus number . The highest subordinate bus number is also an 8-bit value. The fields are defined in Ta b l e 12 . Reset clears all bits. T able 12: Bus Number/Subordi nate Bus Numb er Register Bit Defi nitions (Bit Assign ment Assumes 32-bi t Bu[...]

  • Page 30

    PLB PCI Full Bridge (v1.00 a) 30 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS The example below shows how the IPIFBAR2PCIBAR_N r egisters assignments define translation of PLB addr esses within the range of a given IPIFBAR to PCI address space. Setting C_INCLUDE_BAROFFS ET_REG=1 includes high-or der bit r egisters for a[...]

  • Page 31

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 31 Product Specification E AR L Y ACCESS W riting 0xFEDC00 00 to IPIFBAR2PCIBAR_1 High-Order Bit Register and then accessing the PLB PCI bridge IPIFBAR_1 with address 0xABCDF123 on th e PLB bus would yie ld 0xFEDC1123 on the PCI bus. W riting 0 x40000000 to IPIFBAR2PCIBAR_ 2 High-Ord[...]

  • Page 32

    PLB PCI Full Bridge (v1.00 a) 32 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS PLB PCI T ransactions The following subsections discuss detai ls of the following types of transactions for the PLB PCI bridge to realize data thr oughputs as high as 132 MB/sec. This assumes the PLB cloc k is 100 MHz or higher . Lower data ra[...]

  • Page 33

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 33 Product Specification E AR L Y ACCESS For all the transactions listed above, the following design requir ements are specified: • Both PCI and PLB clocks will be independent glob al buf fers. For V irtex-4, RCLK must als o be driven by global buffer . • The PLB clock can be slo[...]

  • Page 34

    PLB PCI Full Bridge (v1.00 a) 34 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS • Address translations in both directions ar e perfor med by high-or der addres s bits substitution in the address vector before cr ossing t o the other bus do main. Byte addressing integrity is maintained between buses. • The user ’s sy[...]

  • Page 35

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 35 Product Specification E AR L Y ACCESS mode). • If the PCI tar get address space is IO-space, the 2 LSBs are passed unchanged fr om that presented on the PLB bus. If the PLB transaction is not a burs t (i.e., PLB_rdBurst is not high), a single PCI transaction (I/O or Memory Read [...]

  • Page 36

    PLB PCI Full Bridge (v1.00 a) 36 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS • If a SERR occurs during a vali d data phase on a burst transfer , the PLB PCI Bridge causes an IPIF timeout and a sserts the IPIF Master Read SERR in terrupt. SERR err or on data phase could occur on the first PCI transaction or on a subse[...]

  • Page 37

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 37 Product Specification E AR L Y ACCESS Ta b l e 17 summarizes the abnormal cond itions with which a PCI targ et can respond and how the response is translated to the PLB master . T able 17: Response of PLB Master/v3. 0 Initiator read of a remote PCI ta r get with abnormal condition[...]

  • Page 38

    PLB PCI Full Bridge (v1.00 a) 38 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS when an incomplete PCI transactions occur or wh en PCI err ors occur . Details of the abnormal terminations are discussed in a late r section. In these transactions, the v3.0 cor e is the PCI initiator . The operation is essentially the same w[...]

  • Page 39

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 39 Product Specification E AR L Y ACCESS burst write data fr om the PLB to PCI beyond the valid IPIF BAR addr ess range. The PLB PCI Bridge does not support fast back-to-back PCI transactions. Abnormal T erminations In the context of the PLB PCI bridge, cacheline tran sactions are sp[...]

  • Page 40

    PLB PCI Full Bridge (v1.00 a) 40 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS transaction. The PLB PCI Bridge performs r etrie s up to a parameterized number of times as described earlier for the condition of disconne cts with/without data. A time-out cannot occur during a single transfer because the v3.0 cor e re quir [...]

  • Page 41

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 41 Product Specification E AR L Y ACCESS PCI Initiator Initiates a Re ad Request of a PLB Slave This section discusses the ope ration of a remote PCI initiator asserting both single and multiple read com ma nds to read d at a f rom a rem ot e P LB s la ve. For these transactions, the[...]

  • Page 42

    PLB PCI Full Bridge (v1.00 a) 42 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS Furthermore, it is the responsibili ty of the PCI initiator to prope rly read data fr om non-prefetchable PLB slaves. For example, it must perform single tr ansaction reads of non-prefetchable PLB slaves to avoid destructive read operations of[...]

  • Page 43

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 43 Product Specification E AR L Y ACCESS If the PLB clock is sl ower , the data flow is a series of PCI transa ctions that are terminated by the PLB PCI Bridge as a disconnect without data afte r the number of data phases specified by C_TRIG_PCI_DA T A_XFER_OCC_LEV EL, or a few mo r [...]

  • Page 44

    Ta b l e 1 9 : Response to PCI initiator doing a read of a re mote PLB sla ve that terminat es the transfer with an abnormal condition on PLB bus Abnormal condition Memory Read Memory Read Multiple SERR T arget ab or t by v3.0 core, but completes PLB transaction. Flush FIFOs and asser t PLB-side Read SERR interr upt. T arget ab or t by v3.0 core, b[...]

  • Page 45

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 45 Product Specification E AR L Y ACCESS number of double wor ds are written, the IPIF master burst writes starts a fter the PCI transaction ends. The bridge attempts to burst write all the data to the PLB slave device. Although dynamic byte enable is supported on the PCI bus, dynami[...]

  • Page 46

    PLB PCI Full Bridge (v1.00 a) 46 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS defined number of re tries are not successful, the PC I interr upt will be strobed. Data in the write buffer is flushed when the PCI interrupt is s trobed. • If during a write command a PLB slave asserts PLB_MW rBT erm which terminates the P[...]

  • Page 47

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 47 Product Specification E AR L Y ACCESS bridge is n ot used. As with M emory and IO data tr ansactions, byte addressing integrity is maintained in configuration transf ers across the bus. When host bridge configurati on functionality is implemented in the PLB PCI bridge, the v3.0 co[...]

  • Page 48

    T able 21: Results of v3.0 core Command Re gister con figuratio n by remote host bridge (PCI-side) and by self-configuration (PLB- side) Results in Command Register after write (PLB-side byte s wapped format) Data Written (PLB-side b yte swapped f ormat) by remote host br idge by self-configuration 0x0000 0x0000 0x4605 0x0100 0x0000 0x4605 0x0200 0[...]

  • Page 49

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 49 Product Specification E AR L Y ACCESS to the Configuration Data Port register initiates a Configuration W rite transaction on the PCI bus. Determination of whether the read or write transf er is type 0 or type 1 is done automatically . Both type 0 and type 1 configuratio n transac[...]

  • Page 50

    PLB PCI Full Bridge (v1.00 a) 50 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS subordinate buses. Device numbers are independen t for each PLB PCI bridge inst antiated, but bus numbering must be monotonically incr easing fo r all primary buses and their subor dinate buses. Abnormal T erminations Responses to abnormal ter[...]

  • Page 51

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 51 Product Specification E AR L Y ACCESS Design Debug The OBP PCI Bridge has a test vector output (PCI_mon itor) to facilitate system debug (i.e., adding an I L A t o a s y s t e m ) . T h e te s t v e ct o r a l lo w s m on i t o r i ng the P CI bus and is the output of IO-buffers t[...]

  • Page 52

    PLB PCI Full Bridge (v1.00 a) 52 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS The constraints ar e also implemented automatically in the EDK tool flow with any tool option that invokes bridge synthesi s. In this flow , tcl-scripts ge nerate the ucf-file constraints and place them in a file in the OPB PCI Bridg e directo[...]

  • Page 53

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 53 Product Specification E AR L Y ACCESS NET "*/RST_N" IOBDELAY = BOTH ; NET "*/AD<*>" IOBDELAY = BOTH ; NET "*/CBE<*>" IOBDELAY = BOTH ; NET "*/REQ_N" IOBDELAY = BOTH ; NET "*/GNT_N" IOBDELAY = BOTH ; NET "*/PAR"[...]

  • Page 54

    PLB PCI Full Bridge (v1.00 a) 54 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS # TIMEGRP "PCI_PADS_D" OFFSET=OUT 11.0 00 AFTER "PCI_CLK" TIMEGRP "FAST_FFS" ; TIMEGRP "PCI_PADS_B" OFFSET=OUT 11.0 00 AFTER "PCI_CLK" TIMEGRP "FAST_FFS" ; TIMEGRP "PCI_PADS_P&qu[...]

  • Page 55

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 55 Product Specification E AR L Y ACCESS one IDELA YCTRl withou t LOC constraints, the tools w ill replicate the primitive throughout the design. Replicating the primitive has the undesirable r esu lts of higher power consumption, higher power consumption, utilizatio n of more global[...]

  • Page 56

    PLB PCI Full Bridge (v1.00 a) 56 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS The parameter C_IDELA YCTRL_LOC has the syntax of IDELA YCTRL_XNYM where N and M are coordinates and multiple entries are concatenated by "-" (i.e., dash). The order of entr ies correspond to IDELA YCNTRL instance names XPCI _IDC0, X[...]

  • Page 57

    PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 57 Product Specification E AR L Y ACCESS the ucf-file in the implementati on directory of the bridge dir ectory to verify that the constraints are included. Alternatively , the user can include all constraints in the top-level ucf-file. When the constraints ar e included in both the [...]

  • Page 58

    PLB PCI Full Bridge (v1.00 a) 58 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS Reference Documents The following documents contain reference inform ation importa nt to understanding the PLB PCI Bridge design: • Processor IP Refe rence Guide • Xilinx LogiCO RE PCI Interface v3.0 Product Specification • Xilinx The Re[...]