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Yamaha YMF724F manuel d'utilisation

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- nom du fabricant et année de fabrication Yamaha YMF724F
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Habituellement, cela est dû au manque de temps et de certitude quant à la fonctionnalité spécifique de l'équipement acheté. Malheureusement, la connexion et le démarrage Yamaha YMF724F ne suffisent pas. Le manuel d’utilisation contient un certain nombre de lignes directrices concernant les fonctionnalités spécifiques, la sécurité, les méthodes d'entretien (même les moyens qui doivent être utilisés), les défauts possibles Yamaha YMF724F et les moyens de résoudre des problèmes communs lors de l'utilisation. Enfin, le manuel contient les coordonnées du service Yamaha en l'absence de l'efficacité des solutions proposées. Actuellement, les manuels d’utilisation sous la forme d'animations intéressantes et de vidéos pédagogiques qui sont meilleurs que la brochure, sont très populaires. Ce type de manuel permet à l'utilisateur de voir toute la vidéo d'instruction sans sauter les spécifications et les descriptions techniques compliquées Yamaha YMF724F, comme c’est le cas pour la version papier.

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Table des matières du manuel d’utilisation

  • Page 1

    YMF724F DS-1 YAMAHA CORPORAT ION September 21, 1998 Preliminary OVERVIEW YMF724F (DS -1) is a hi gh perf ormance au dio controller f or the PCI Bu s. DS-1 consists of tw o separated fun ctional blocks. One i s the PCI Au dio block and th e other is th e Legacy Audi o block. PC I Audio block allows Software Driver to handle maxim um of 73 concurrent[...]

  • Page 2

    YMF724F September 21, 1998 -2- LOGOS 1. GM system level 1 GM sy stem level 1 is a w orld standard f ormat about MIDI sy nthesizer w hich provides voice arrang ements and MI D I functions. 2. XG XG is a format abou t MIDI synthes izer that is proposed by YAMA HA, and keeps the upper com patibility of GM sy stem lev el 1. The good poin ts are the voi[...]

  • Page 3

    YMF724F September 21, 1998 -3- PIN CONFIGURATI ON YMF724F- V GP4 GP5 GP6 GP7 RXD TXD ROMDO/VOLDW# ROMSK/VOLUP# VDD5 VDD3 VSS VSS IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 INTA# VSS RST# VDD5 PVSS PCICLK GNT# REQ# AD31 AD30 AD29 PVSS AD28 AD27 AD26 PVSS AD25 AD24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108[...]

  • Page 4

    YMF724F September 21, 1998 -4- PIN DESCRIPTION 1. PCI Bus Interface (53-pin) name I/O T ype Size function PCIC LK I P PCI C lock RST# I P Reset AD[31: 0] IO Ptr Address / Data C/BE[3:0]# IO Ptr Co mmand / Byte Enable PAR IO P tr Parity FRAME# IO Pstr Frame IRDY# IO Pstr Initiator Ready TRDY# IO Pstr Target Ready STOP # IO Pstr Stop IDSEL I P ID Sel[...]

  • Page 5

    YMF724F September 21, 1998 -5- 3. YMF727( AC3F2) Interface (9-pin) name I/O type size function XRST# O C 2mA Reset for local device ACS # O T 3m A Chip se lect for AC 3F2 ASCL K O T 6m A Clock for Serial control data transf er of AC3F2 ACDO O T 3mA Serial control data output of AC3F2 ACDI I Tup - Serial co ntro l data input of AC3F2 AL RCK O T 3m A[...]

  • Page 6

    YMF724F September 21, 1998 -6- 6. Miscell aneous (15-pin) name I/O type Size function ROMCS O T 3mA Chip select for external EEPROM ROMSK / VOLUP# IO Tup 3mA Serial clock for external EEPROM or Hardw are Volume (Up) ROMDO / VOLDW# IO Tup 3mA Serial data outpu t for external EEPROM or Hardw are Volume (Dow n) ROMDI / T EST 2# I Tup - Serial data inp[...]

  • Page 7

    YMF724F September 21, 1998 -7- BLOCK DIAGRAM PCI Bus Interf ace BUS Master DMA Controller Memor y XG Synthesizer Direct Sound Acc. W av e In/Out PC-PCI / D-DMA / S-IRQ SB Pro OPL3 MPU401 Jo ystick Rate Conv er ter / Mix er A C-2 Interf ace SPDIF (output) A C3F2 Legacy A udio PCI A udio Interf ace[...]

  • Page 8

    YMF724F September 21, 1998 -8- SYSTEM DIAGRAM WaveIn Device WaveOut Device MidiOut Device XG/DLS Engine DS-1 Slot Manager (Up to 64-sound) Soft Effect DirectSound HAL DLS Appllication AC-3 Application DirectX Application DirectSound VxD YMF724F(DS-1) MMSystem MidiOut Device MidiIn Device DOS VM I/O Traps I/O Traps OPL3 SB Pro MPU401 VxD for PCI Aud[...]

  • Page 9

    YMF724F September 21, 1998 -9- FUNCTION OVERVIEW 1. PCI INTERFACE DS-1 su pports the PCI bus interf ace and complies to PCI revision 2.1. 1-1. PCI Bus Com mand DS-1 s upports th e follow ing PC I Bus com man ds. 1-1-1. T arget Device Mode C/BE[3:0]# Com man d 0000 I n t e r r u p t A c k n o w l e d g e ( n o t s u pport) 0001 S p e c i a l C y c l[...]

  • Page 10

    YMF724F September 21, 1998 -10- 1-2. PCI Config uration Reg ister In addition to the Configuration Register defined b y PCI Revision 2.1, DS-1 provides p roprietary PCI Configuratio n Registers in o rde r to contro l legacy audi o functio n, such as O P L3, Sound B laster Pro , M PU4 01 and Joystick. These additional registers are co nfigured by BI[...]

  • Page 11

    YMF724F September 21, 1998 -11- 00 - 01h: Vendor ID Read Only Default: 1073h Access Bus W idth: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Vendor ID b[15:0] ........Vendor ID This register contains the YAMAHA Vendor ID registered in Revision 2.1. This register is hardw ired to 1073h . 02 - 03h: Device ID Read Only Default: [...]

  • Page 12

    YMF724F September 21, 1998 -12- b8 ................ SER: SERR# Enable This bit enables DS-1 to drive SERR#. “0”: Do not dr ive SERR#. (default) “1”: Drives SERR# w hen DS-1 detects an A ddress Parity Error on norm al target cycle or a Data Parity Error on special cy cle. 06 - 07h: Stat us Read / W rite Clear Default: 0210h Access Bus W idth[...]

  • Page 13

    YMF724F September 21, 1998 -13- 08h: Revision ID Read Only Default: 03h Access Bus W idth: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Revision I D b[7:0] ..........Revision ID This re gister co ntains the r e vision number o f DS -1 . T his registe r is hard wired to 03h . 09h: Programming Interf ace Read Only Default: 00h Access Bus W idth: 8, 16, 32-b[...]

  • Page 14

    YMF724F September 21, 1998 -14- 0Dh: Latency Timer Read / W rite Default: 00h Access Bus W idth: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Latency Tim er b[7:0] ..........Latency Timer When DS-1 becomes a Bus Master device, this register indicates the initial value of the Master Latency Tim er . 0Eh: Header Ty pe Read Only Default: 00h Access Bus W idt[...]

  • Page 15

    YMF724F September 21, 1998 -15- 2C-2Dh: Subsystem Vendor ID Read Only Default: 1073h Access Bus W idth: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Subsys t em V endor I D b[15:0] ........Subsystem Vendor ID This register contains the Subsystem Vendor ID. In ge neral, this ID is used to distinguish ada pters o r system s mad[...]

  • Page 16

    YMF724F September 21, 1998 -16- 3Ch: Interrupt Li ne Read / W rite Default: 00h Access Bus W idth: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Interrupt Li ne b[7:0] ..........Interrupt Line This register indicates the interrupt channel that INT A# is assigned to. 3Dh: Interrupt Pi n Read Only Default: 01h Access Bus W idth: 8, 16, 32-bit b7 b6 b5 b4 b3 [...]

  • Page 17

    YMF724F September 21, 1998 -17- 40 - 41h: Legacy A udio Control Read / W rite Default: 907Fh Access Bus W idth: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 LAD SIEN MPUIR Q SBIRQ SDMA I/O MIEN MEN GPEN FMEN SBEN b0 ................ SBEN: Sound Blaster Enable This bit enables the m apping of th e Sound Blaster Pro block in th[...]

  • Page 18

    YMF724F September 21, 1998 -18- b[7:6] ..........SDM A : Sound Blaster DM A -8 Channel Select These bits select the DMA chan nel for the Sound Blaster Pro block. “0”: DMA ch0 “1”: DMA ch1 (default) “2”: reserved “3”: DMA ch3 b[10:8] ........SBIRQ: Sound Blaster IRQ Channel Select These bits select the interrupt ch annel for the Soun[...]

  • Page 19

    YMF724F September 21, 1998 -19- 42 - 43h: Extended Legacy A udio Control Read / W rite Default: 0000h Access Bus W idth: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 IMOD SBVER SMOD - - MA IM J SI O MPUI O SB IO FMIO b[1:0] ..........FM IO: FM I/O Address allocation These bits determ ine the base I/O address for the of the OP[...]

  • Page 20

    YMF724F September 21, 1998 -20- b[12:11] ......SM OD: SB DM A mode These bits det ermin e the protocol to achi eve the DMA C(8237) fun ction on th e PCI bus. “0”: PC/PCI (default) “1”: reserved “2”: Distribu ted DMA “3” reserved b[14:13] ......SBVER: SB Version Select These bits set the version of the SB P ro DSP. T he value set in [...]

  • Page 21

    YMF724F September 21, 1998 -21- 46-47h: Subsystem ID Write Regist er Read / W rite Default: 000Dh Access Bus W idth: 16-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Subsyste m ID W rite b[15:0] ........Subsystem ID Write Register This register sets the Subsy stem ID that is read from 2E-2Fh (Subsys tem ID regis ter). The default value [...]

  • Page 22

    YMF724F September 21, 1998 -22- b2 ................ DPLL1: Disable PLL1 Clock Oscillation Setting this bit to “1” disab les the o scillation of PLL for the PCI Audio function. “0”: Normal (default) “1” : D isa bl e b3 ................ PSL0: Power Save Legacy A udio Block 0 Setting this bit to “1” stops p roviding the cloc k with the[...]

  • Page 23

    YMF724F September 21, 1998 -23- b12 .............. PR4: A C-2 Power dow n Control 4 This bit contro ls the p ower state of the AC-link in AC -2. “0”: Normal (default) “1”: Pow er dow n b13 .............. PR5: A C-2 Power dow n Control 5 Setting this bit to “1” disables the internal clock of AC- 2. In case AC-2 is used w ith DS-1, the ma[...]

  • Page 24

    YMF724F September 21, 1998 -24- 4C-4Dh: D-DM A Slave Configurat i on Read / W rite Default: 0000h Access Bus W idth: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Base Addres s EA TS CE b0 ................ CE: Channel Enable This bit enables the Distrib uted DMA function. “0”: Disable Di stributed DMA (default) “1”: En[...]

  • Page 25

    YMF724F September 21, 1998 -25- 51h: Next It em Poi nt er Read Only Default: 00h Access Bus W idth: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Nex t Item Pointer b[7:0] ..........Next Item Pointer DS-1 does not provide other new capability besid es Power Management. This register is hardwired to 00h . 52-53h: Power Management Capabilities Read Only Defa[...]

  • Page 26

    YMF724F September 21, 1998 -26- 54-55h: Pow er Management Cont rol / Status Read / W rite Default: 0000h Access Bus W idth: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ---------- ---- PS b[1:0] ..........PS: Pow er State These bits determ ine th e power stat e of DS-1. DS-1 su pports the follow ing pow er states: “0” : D[...]

  • Page 27

    YMF724F September 21, 1998 -27- 2. ISA Comp atible Device DS-1 contains the following functions to maintain the compatibility w ith the past ISA Sound Devices. These devices are considered L egacy devices and the f unctions are ref erred to as Legacy Audio. Legacy Au dio is indepen dent from PCI Au dio and can be used s imu ltaneous ly. The configu[...]

  • Page 28

    YMF724F September 21, 1998 -28- DS-1 su pports PC/PCI and D-DMA protocols to em ulate the DMA of SB Pro on the PCI. In addition, DS-1 supports the old ty pe of inte rrupts used by ISA an d the Seriali zed IRQ protocol. Yamah a recomm ends the combination of PC/PCI and Serialized IRQ. T he system block diagram when usin g Intel 430TX chi p set is sh[...]

  • Page 29

    YMF724F September 21, 1998 -29- 2-1. OPL3 Block OPL3 Block is register com patible w ith YMF289B. However, Pow er Managem ent reg ister has been deleted because it is now controlled by the PCI Configu ration Register. The follo wing show s the FMBase I /O map of OPL3. FMBase (R) Status Register port FMBase (W) Add ress por t for Register Arra y 0 F[...]

  • Page 30

    YMF724F September 21, 1998 -30- 2-1-2. OPL3 Data Regist er OPL3 Data Register Array 0 (R/W) : A d d r e s s D 7D 6D 5D 4D 3D 2D 1D 0 00 - 01h LSI TES T 02h TIMER 1 03h TIMER 2 04h RST MT1 MT2 - - - ST2 ST1 0 8 h - N T S ---- -- 20 - 35h AM VIB EGT KSR MULT 40 - 55h KSL TL 60 - 75h AR DR 80 - 95h SL RR A0 - A8h F-NUM (L) B0 - B8h - - KON BLOCK F-NU [...]

  • Page 31

    YMF724F September 21, 1998 -31- 2-2. Sound Blast er Pro Block This block emu lates the DSP comm ands of Sound Blaster and Soun d B laster Pro. Only playback fun ctions are supported (record function s are not supported). However, to m aintain com patibility for gam es, it is designed so that every DSP comm and receives a correct response. The DMA t[...]

  • Page 32

    YMF724F September 21, 1998 -32- 2-2-1. DSP Com m and The follow ing show s the list of DSP Com man ds that are su pported by th e SB Pro engine. Both SB and SB Pro com mands are supported. CMD Support Function 10h o 8bit direct mode single byte digitiz ed sound output 14h o 8bit single-cycle DM A mode digitized sound output 16h 8bit to 2bit ADPCM s[...]

  • Page 33

    YMF724F September 21, 1998 -33- 2-2-2. Sound Blaster Pro Mixer The follow ing show s the register m ap of the Mixer section of Sound Blaster Pro. A d d r e s s b 7b 6b 5b 4b 3b 2b 1b 0 R e m a r k 00h Reset 04h Voi c e Volum e L "1" Voice Vol um e R "1" 0Ah - - - "1" - MIC Vol um e* 0Ch - - Ifilter* "1" Input[...]

  • Page 34

    YMF724F September 21, 1998 -34- (1) Volum e for MIDI MID I Vol. (26h) 01234567 mut e mute mu te mute mu te mu te mut e mute 0 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h mut e -52dB -42dB -36dB -32dB -30dB -28dB -26dB 1 0000h 0029h 0082h 0103h 019Bh 0206h 028Ch 0335h mut e -42dB -32dB -26dB -22dB -20dB -18dB -16dB 2 0000h 0082h 019Bh 0335h 0515[...]

  • Page 35

    YMF724F September 21, 1998 -35- 2-2-3. SB Suspend / Res ume The SB block can read the in ternal stat e as to support S uspend and Resum e functi ons. The intern al state is m ade up of 218 fl ip flops. To read the state, these st ates are shi fted in order and read 8 bits at a tim e from the SCAN DA T A register. These registers are m apped to the [...]

  • Page 36

    YMF724F September 21, 1998 -36- F1h: Scan In/ O ut Data Read / W rite Default: 00h b7 b6 b5 b4 b3 b2 b1 b0 SCAN DATA b[7:0] ..........SCA N DATA This is the data p o rt for reading and writing the internal state. F8h: Interrupt Fl ag Regi ster Read Only Default: 00h b7 b6 b5 b4 b3 b2 b1 b0 ------- S B I b0 ................ SBI: SB Interrupt Flag Th[...]

  • Page 37

    YMF724F September 21, 1998 -37- 2-3. MPU401 This block is for tran smitting and receiving MIDI data. It is compatible with UART mode of “MPU401”. Full duplex operation is possible using the 16-by te FIFO for each direction, transm itting and receiving . The follow ing show s the MPUBase I/O m ap for MPU401. MPUBase (R/W) MIDI Data port MPUBase [...]

  • Page 38

    YMF724F September 21, 1998 -38- 3. DMA Emulati on Protocol The form er syn thesizer LSI f or the ISA bus such as th e Sound Bl aster used the DMA controller (8237: ISA DMAC) on the sy stem to transfer the sound data fro m/to the host. For DS-1, however, ISA DMAC m ust be used to transfer the sound data to the Sound Blaster Pro Block of the L egacy [...]

  • Page 39

    YMF724F September 21, 1998 -39- 3-2. D- DMA DS-1 prov ides the f ollowin g registers to support D- DMA. D-DMA Slave C onfigurat ion Register (4C -4Dh) of the PCI Conf iguration register is used to set th e Base address of the Slave Address. Slave Address R/W Register Name Base + 0h W Base Address 0-7 Base + 0h R Current A ddress 0-7 Base + 1h W Bas[...]

  • Page 40

    YMF724F September 21, 1998 -40- 4. Interrupt Routi ng DS-1 su pports three ty pes of i nterrupts, i nterrupt s ignal on th e PCI bus (INTA#), in terrupt sig nal on th e ISA bus (IRQ[5,7,9,10,11]), an d Serialized IRQ. The IRQs on DS-1 are rout ed as shown below . Sound Blaster Pro MPU401 IRQ Selector Selector IRQ SBIRQ[2:0] ISA IRQ SERIRQ MPUIRQ[2:[...]

  • Page 41

    YMF724F September 21, 1998 -41- 6. Hard ware Volu me Co ntro l The hardware volume control de termines the A C-2 master volume without using any software control using the external circuit listed below. Two pins, VOL UP# for increasing the v olume and VOL DW# for decreasing the volu me, are used. 1k VOLDW# VOLUP# 1k 1000p 1000p Push SW Push SW DS-1[...]

  • Page 42

    YMF724F September 21, 1998 -42- ELECTRICAL CHARACTERISTI CS 1. Absolute Maximum Ratings Item Sym bol Min. Max. Un it Power Su pply Voltage 1 (PVDD, VDD5) V DD5 -0. 5 7.0 V Power Su pply Voltage 2 (VDD3, LVDD) V DD3 -0.3 4. 6 V Inpu t Voltage 1 (PVDD, VDD5) V IN5 -0.5 V DD5 +0.5 V Inpu t Voltage 2 (VDD3, LVDD) V IN3 -0 .3 V DD3 +0.3 V Operating Ambi[...]

  • Page 43

    YMF724F September 21, 1998 -43- 3. DC Charact eristics Item Symbol Condition Min. T yp. Max. Unit High Level Input Voltage 1 V IH1 *1 2. 2 V DD5 +0.5 V Low Level Input Voltage 1 V IL1 *1 -0 .5 0. 8 V High Level Input Voltage 2 V IH2 *2 2. 2 V DD5 +0.5 V Low Level Input Voltage 2 V IL2 *2 -0 .5 0. 6 V High Level Input Voltage 3 V IH3 *3 2. 2 V Low L[...]

  • Page 44

    YMF724F September 21, 1998 -44- 4. AC Charact eristics 4-1. Master Clock (Fig.1) Item Sym bol Min. Typ. Max. Unit XI24 Cy cle T ime t XICYC - 40.69 - ns XI24 High Tim e t XIHIGH 16 - 24 n s XI24 Low Time t XILOW 16 - 24 ns Note : T op = 0-70°C, PVDD=5.0 ± 0.25 V, VDD5= 5.0 ± 0.25 V, VDD3=3.3 ± 0.3 V, LVDD =3.3 ± 0.3 V t XI24 XICYC t XIHIGH 1.0[...]

  • Page 45

    YMF724F September 21, 1998 -45- 4-3. PCI Interface (Fig.3, 4) Item Sym bo l Condition Min. Typ. Max. Unit PCICLK Cy cle Time t PCYC 30 - - ns PCI CLK Hi gh T ime t PHIGH 11 - - ns PCI CLK Lo w Ti me t PLOW 11 - - n s PCIC LK S lew Rat e - 1 - 4 V/ns t PVAL (Bused signa l) 2 - 11 ns PCICLK to Signal Valid Delay t PVAL ( PTP ) (Point to P oint) 2 - 1[...]

  • Page 46

    YMF724F September 21, 1998 -46- 4-4. AC-2 / AC3F2 Master Clock (Fig.5) Item Sym bol Min. Typ. Max. Unit CMCLK Cycle Time t CMCYC - 40.69 - ns CMCLK High Time t CMHIGH 8- - n s CMCLK Low Time t CMLOW 8- n s CMCLK Rising Ti me t CMR -4 . 6- n s CMCLK Falling T i me t CMF -2 . 1- n s Note : T op = 0-70°C, PVDD=5.0 ± 0.25 V, VD D5=5.0 ± 0.25 V, VDD3[...]

  • Page 47

    YMF724F September 21, 1998 -47- CBCLK CSYNC CSDI CSDO 0.8 V 1.5 V 2.0 V 0.8 V 2.0 V 0.8 V 2.0 V 0.8 V 1.5 V 2.0 V t CBIHIGH t CV AL t CBILOW t CBICYC t CV AL t COH t CSYCYC t CSYHIGH t COH t CSYLOW t CISU t CIH Fig.6: AC-link timing 4-6 AC3F2 Interface (Fig.7, 8) Item Sym bo l Condition Min. T yp. Max. Unit ASCLK Cycle Time t ASCCYC - 325 - ns ASCL[...]

  • Page 48

    YMF724F September 21, 1998 -48- ASCLK A CDI A CS, ACDO 2.0 V 0.8 V 2.0 V 0.8 V 0.8 V 1.5 V 2.0 V t ASCHIGH t ASCLOW t ASCCYC t AC V A L t A COH t A CISU t A CIH Fig.7: AC 3F2 Control Interface tim ing ABCLK ASDI ASDO, ALRCK 2.0 V 0.8 V 2.0 V 0.8 V 0.8 V 1.5 V 2.0 V t ABIHIGH t ABILOW t ABICYC t ASV AL t ASOH t ASISU t ASIH Fig.8: AC 3F2 Audio Inter[...]

  • Page 49

    YMF724F September 21, 1998 -49- EXTERNAL DIMENSIONS YMF724F- V (1.00) 0-10˚ 0.50±0.20 LEAD THICKNESS : 0.15+0.10 -0.06 20.00±0.30 22.00±0.40 0.20±0.10 P-0.50TYP 36 1 37 72 73 108 109 144 1.40±0.20 1.70MAX. 0 MIN. (STAND OFF) 22.00±0.40 20.00±0.30 The shape of the m olded corner may slightly different from the sh ape in this diagram . The fi[...]

  • Page 50

    YMF724F September 21, 1998 -50- IMPORTANT NOTICE 1. Yamaha reserves the right to make changes to its Products and to this document without notice. The informati on contained in this docum ent has been carefully checked and is believed to be reliable. How ever, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or [...]