AMD LX 700@0.8W manuale d’uso

AMD Geode™ LX Processors Data Book AMD Geode™ LX Processors Data Book February 2009 Publicat ion ID: 33234H[...]

2 AMD Geode™ LX Processors Data Book © 2009 Advanced Micr o De vices, Inc. All r ights reser ved. The contents of this docu ment are pr o vided in connection with Adv anced Micro Devices , Inc. (“AMD”) products. AMD make s no representations or warranties with respect to the accuracy or completeness of the contents of this publication and re[...]

AMD Geode™ LX Processors Data Book 3 Contents 33234H Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.0 Overview . . [...]

4 AMD Geode™ LX Processors Data Book Contents 33234H 6.0 Integrated Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 6.1 GeodeLink™ Memor y Co ntroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 0 6.2 GeodeLink™ Memor y Con troller R[...]

AMD Geode™ LX Processors Data Book 5 List of Figures 33234H List of Figures Figure 1-1. Internal Bloc k Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 3-1. Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

6 AMD Geode™ LX Processors Data Book List of Figures 33234H Figure 6-42. Ancillary Data Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9 Figure 6-43. M essage Passing Data Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 Fig[...]

AMD Geode™ LX Processors Data Book 7 List of T ables 33234H List of T ab les Table 2-1. Graphics Pro cessor Feature Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 Table 3-1. Video Signal D efinitions Per M ode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 T[...]

8 AMD Geode™ LX Processors Data Book - List of T ables 33234H Table 6-11. Data Only Co mmand Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Table 6-12. Bit Descriptio ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Ta[...]

AMD Geode™ LX Processors Data Book 9 List of T ables 33234H Table 6-66. Panel Outpu t Signal Ma pping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 Table 6-67. Register Sett ings for Dither Enable/Disable Fe ature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 Table 6-68. Displa[...]

10 AMD Geode™ LX Processors Data Book - List of T ables 33234H Table 8-12. sr eg3 Field (FS an d GS Segment Register Selectio n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 24 Table 8-13. ss Field Encodin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 25 Table 8-[...]

AMD Geode™ LX Processors Data Book 11 1 Overview 33234H 1.0 Ov er vie w 1.1 General Description AMD Geode™ LX processors a re integrated x86 proces- sors specifically designed to power embedded devices f or enter tainment, e ducation, and business. Servin g the needs of consumers and business professionals alik e, it’ s an ex ce llent solutio[...]

12 AMD Geode™ LX Processors Data Book Overview 33234H 1.2 Features General Features ■ Functional blocks include: —C P U C o r e — GeodeLink™ Control Processor — GeodeLink Interface Units — GeodeLink Memor y Controller — Graphics Processor — Displa y Controller — Video Proc essor – TFT Controller/Video Output P or t — Video I[...]

AMD Geode™ LX Processors Data Book 13 Overview 33234H Display Contr olle r ■ Hardware frame buff er compression improves Unified Memory Architecture (U MA) memory efficiency ■ CRT resolutions suppor ted: — Suppor ts up to 1920x144 0x32 bpp at 85 Hz — Suppor ts up to 1600x120 0x32 bpp at 100 Hz ■ Suppor ts up to 1600x1200x32 bp p at 60 H[...]

14 AMD Geode™ LX Processors Data Book Overview 33234H[...]

AMD Geode™ LX Processors Data Book 15 2 Architecture Overview 33234H 2.0 Architecture Ov er vie w The CPU Core provides maximum compatibility with the vast amount of Internet content availab le w hile the intelli- gent integration of se veral other functions, including graph- ics, makes the AMD Geode™ LX processor a tr ue system- le vel m ultim[...]

16 AMD Geode™ LX Processors Data Book Architecture Overview 33234H 2.1.2 Memor y Managemen t Unit The memor y management uni t (MMU) translates the linear address supplied by the integer unit into a ph ysical address to be used by the cache unit and the inter nal bus interface unit. Memor y management pr oce dures are x86-compati- ble , adh ering[...]

AMD Geode™ LX Processors Data Book 17 Architecture Overview 33234H 2.5 Graphics Processor The Graphics Processor is based on the graphics proces- sor used in the AMD Ge ode GX processor with several f ea- tures added to enhance performa nce and functionality . Like its predeces sor , the AMD Geode LX proc essor’ s Graphi cs Processor is a BitBL[...]

18 AMD Geode™ LX Processors Data Book Architecture Overview 33234H 2.6 Display Contr oller The Display Controller perf or ms the f ollowing functions: 1) Retriev es graphics, video , and cursor data. 2) Serializes the streams. 3) P erforms any necessar y color lookups and output for- matting. 4) Interfaces to the Video Processor f or dr iving the[...]

AMD Geode™ LX Processors Data Book 19 Architecture Overview 33234H 2.10 Security Block The AMD Geode LX processor has an on-chip AES 128-bit cr ypto acceleration block capable of 44 Mbps throughput on either encr yption or decr yption at a processor speed of 500 MHz. The AES b lock runs asynchronously to the pro- cessor core and is DMA ba sed. Th[...]

20 AMD Geode™ LX Processors Data Book Architecture Overview 33234H[...]

AMD Geode™ LX Processors Data Book 21 3 Signal Definitions 33234H 3.0 Signal Definitions This chapter defines the sign als and describes th e e xter nal in terface of the AMD Geode™ LX processor . Figure 3-1 shows the pins organized by their functional groupings. Where signal s are multiplex ed, the default signal name is listed first and is se[...]

22 AMD Geode™ LX Processors Data Book Signal Definitions 33234H T able 3-1. Video Signal Definitions P er Mode Signal Name CRT w/16-bit VI P RGB w/1 6-bit VIP ARGB (Note 1) w/8-bit VIP TFT w/16-bit VIP (not 601) 8- or 16-bit V OP w/16-bit VIP RED RED GREEN GREEN BLUE BLUE DRGB[31:24] (I/O) VID[15:8] (I) VID[15:8] (I) Alpha VID[15:8] (I) VID[15:8][...]

AMD Geode™ LX Processors Data Book 23 Signal Definitions 33234H 3.1 Buffer T ypes The Ball Assignment tables star ting on page 26 include a column labeled “Buffer T ype”. The details of each buff er type listed in this column are given in T able 3-2. The col- umn headings in T able 3-2 are identified as follo ws: TS: Indicates whether the buf[...]

24 AMD Geode™ LX Processors Data Book Signal Definitions 33234H 3.2 Bootstrap Options The bootstrap options shown in T able 3-3 are suppor ted in the AMD Geode LX processor f or configuring the system. 3.3 Ball Assignments The tables in this chapter use several common abbre via- tions. T able 3-4 lists the mnemonics and their mean ings. T able 3-[...]

AMD Geode™ LX Processors Data Book 25 Signal Definitions 33234H Figure 3-2. BGU481 Ball Assignment Diagr am 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK[...]

26 AMD Geode™ LX Processors Data Book Signal Definitions 33234H Ball No. Signal Name (Note 1) Ty p e (PD) Buffer Ty p e A1 V SS GND --- A2 V MEM PWR --- A3 V SS GND --- A4 DQ21 I/O DDR A5 V SS GND --- A6 DQM2 I/O DDR A7 DQ22 I/O DDR A8 V SS GND --- A9 DQ28 I/O DDR A10 DQS3 I/O DDR A11 V SS GND --- A12 DQ26 I/O DDR A13 DQ31 I/O DDR A14 V MEM PWR -[...]

AMD Geode™ LX Processors Data Book 27 Signal Definitions 33234H H2 V SS GND --- H3 DQS1 I/O DDR H4 SDCLK1N O DDRCLK H28 SDCLK3N O DDRCLK H29 DQM6 I/O DDR H30 V SS GND --- H31 V MEM PWR --- J1 DQ9 I/O DDR J2 DQ8 I/O DDR J3 DQ12 I/O DDR J4 SDCLK1P O DDRCLK J28 SDCLK3P O DDRCLK J29 DQS6 I/O DDR J30 DQ55 I/O DDR J31 DQ54 I/O DDR K1 DQ7 I/O DDR K2 DQ3[...]

28 AMD Geode™ LX Processors Data Book Signal Definitions 33234H Y2 D A V SS A G ND --- Y3 V IO PWR --- Y4 V SS GND --- Y28 V COR E PWR --- Y29 V SS GND --- Y30 RESET# I PCI Y31 SYSREF I PCI AA1 V A V DD APWR --- AA2 V A V SS AGND --- AA3 VLPF A --- AA4 TMS I 24/Q7 AA28 GNT0# I/O PCI AA29 REQ0# I P CI AA30 V SS GND --- AA31 V IO PWR --- AB1 DOTREF[...]

AMD Geode™ LX Processors Data Book 29 Signal Definitions 33234H AK4 DRGB14 O (PD) 24/Q5 VOP 9 O AK5 V SS GND --- AK6 DRGB1 O (PD) 24/Q5 VOP 6 O AK7 DRGB4 O (PD) 24/Q5 VOP 3 O AK8 V SS GND --- AK9 DRGB31 I/O ( P D) 24/Q5 VID15 I AK10 DRGB26 I/O (PD) 24/Q5 VID10 I AK11 V SS GND --- AK12 VID7 I/O (PD) 24/Q7 AK13 VID5 I/O (PD) 24/Q7 AK14 V SS GND ---[...]

30 AMD Geode™ LX Processors Data Book Signal Definitions 33234H Signal Name Ball No. AD0 AJ19 AD1 AH19 AD2 AL20 AD3 AK20 AD4 AK19 AD5 AH21 AD6 AJ21 AD7 AL19 AD8 AK22 AD9 AL22 AD10 AK23 AD11 AH22 AD12 AL23 AD13 AL25 AD14 AH24 AD15 AJ24 AD16 AJ28 AD17 AK28 AD18 AL29 AD19 AJ30 AD20 AK29 AD21 AJ31 AD22 AH30 AD23 AH29 AD24 AG29 AD25 AG28 AD26 AF30 AD2[...]

AMD Geode™ LX Processors Data Book 31 Signal Definitions 33234H DRGB7 AJ8 DRGB8 AJ2 DRGB9 AK3 DRGB10 AL3 DRGB11 AH5 DRGB12 AJ4 DRGB13 AL4 DRGB14 AK4 DRGB15 AJ5 DRGB16 AF2 DRGB17 AF1 DRGB18 AG3 DRGB19 AG4 DRGB20 AH1 DRGB21 AH2 DRGB22 AH3 DRGB23 AJ1 DRGB24 AH11 DRGB25 AJ11 DRGB26 AK10 DRGB27 AL10 DRGB28 AJ10 DRGB29 AH10 DRGB30 AL9 DRGB31 AK9 DRSET [...]

32 AMD Geode™ LX Processors Data Book Signal Definitions 33234H VO P 13 A L 3 V OP14 AK3 VO P 15 A J 2 V OP_BLANK AE4 V OPCLK AE1 V OP_HSYNC AE3 V OP_VSYNC AD3 V MEM (T otal of 33) A2, A14, B1, B5, B8, B11, B21. B24, B27, B31, C3, C7, C14, C18, C25, C29, D4, D28, A18, E2, E30, G3, G29, H1, H31, K3, K29, L1, L31, A30, N4, N29, P29 Signal Name Ball[...]

AMD Geode™ LX Processors Data Book 33 Signal Definitions 33234H 3.4 Signal Descriptions 3.4.1 Sys tem Interfac e Signals Signal Name Ball No. T ype f V Description SYSREF Y31 I 33, 66 MHz 3.3 System Reference . PCI input clock; typical ly 33 or 66 MHz. DO TREF AB1 I 48 MHz 3.3 Dot Clock Reference. Input clock f or DOTCLK PLL. INT A# AD 28 I /O (P[...]

34 AMD Geode™ LX Processors Data Book Signal Definitions 33234H TDP AL17 A A nalog N/A Thermal Diode P ositive (TDP). TDP is the positive ter minal of the ther mal diode on the die. The diode is used to do ther mal characteri zation of the device in a system. This signal wor ks in conjunction with TDN. F or accurate die temperature measurements, [...]

AMD Geode™ LX Processors Data Book 35 Signal Definitions 33234H 3.4.3 Memor y Interfa ce Signals (DDR) Signal Name Ball No. Type f V Description SDCLK[5:0]P , SDCLK[5:0]N D20, D21, D23, D24, J28, H28, M28, L28, J4, H4, M4, L4 O up to 200 MHz 2.5 SDRAM Clock Differential P airs. The SDRAM de vices sample all the control, address, and data based on[...]

36 AMD Geode™ LX Processors Data Book Signal Definitions 33234H DQM[7:0] N30, H29, C24, A19, B10, A6, G2, M1 I/O 166-400 Mb/s 2.5 Da ta Mask Control Bits. During memor y read cycles, these outputs control whether the SDRAM output buff e rs are driven on the Mem- or y Data Bus or not. All DQM signals are asser ted during read cycles. During me mor[...]

AMD Geode™ LX Processors Data Book 37 Signal Definitions 33234H 3.4.5 PCI I nterface Signals Signal Name Ball No. Type f V Description AD[31:0] See T able 3-6 on page 30 I/O 33-66 Mb/s 3.3 Multiplexed Address and Data. Addresses and data are multiplex ed together on the same pi ns. A bus transaction consists of an address phase in the cycle in wh[...]

38 AMD Geode™ LX Processors Data Book Signal Definitions 33234H RESET# Y30 I 0-1 Mb/s 3.3 PCI Reset. RESET# abor ts all operations in progress and places the AMD Geode LX proces- sor into a reset state. RESET# f orces the CPU and peripheral functions to begi n e xecuting at a known state . All data in the on-chip cache is inv alidated upo n a res[...]

AMD Geode™ LX Processors Data Book 39 Signal Definitions 33234H DEVSEL# AK25 I/O 33-66 Mb/s 3.3 Device Select. DEVSEL# indicates that the driv- ing device has decoded its addre ss as the target of the current access . As an input, DEVSEL# indicates whether any device on the bus has been selected. DEVSEL# is also driven by an y agent that has the [...]

40 AMD Geode™ LX Processors Data Book Signal Definitions 33234H 3.4.6 TF T Display Interf ace Signals Signal Name Ball No. Type f V Description DRGB[31:24] DRGB[23:0] See T able 3-6 on page 30 I/O O (PD) 0-162 Mb/s 3.3 Display Data Bus. DO TCLK AE1 O (PD) 0-162 MHz 3.3 Dot Cloc k. Output clock from DO TCLK PLL. HSYNC AE3 O (PD) 0-162 Mb/s 3.3 (5v[...]

AMD Geode™ LX Processors Data Book 41 Signal Definitions 33234H 3.4.7 CRT Display Interface Sign als Signal Name Ball No. Type f V Description HSYNC AE3 I/O 0-350 Mb/s 3.3 (5vt) Horizontal Sync . Horiz ontal Sync es tablishes the line rate and horizontal retrace inter val f or an attached CRT . The polarity is programmable (See Section 6.8.3.2 on[...]

42 AMD Geode™ LX Processors Data Book Signal Definitions 33234H F or additional electr ical details on pins, refer to Section 7.0 "Electr ical Specifications" on page 59 7. 3.4.9 P ower a nd Ground Int e rface Signals Signal Name (Note 1) Ball No. Type f V Description V CORE See T able 3-6 on page 30 PWR N/A 1.2 Core P ower Connection ([...]

AMD Geode™ LX Processors Data Book 43 Signal Definitions 33234H T able 3-7. Signal Behavior During and Aft er Reset Signal Name T ype Behavior AD[31:0] PCI TRI-ST A TE during RESET# low INT A# PA R REQ# IRD Y# FRAME# GNT# DEVSEL# TRD Y# ST OP# BA[1:0] DDR CAS[1:0]# CBE[3:0]# CS[3:0]# DQ[63:0] DQM[7:0] DQS[7:0] MA[13:0] RAS[1:0]# SDCLK[5:0]P SDCLK[...]

44 AMD Geode™ LX Processors Data Book Signal Definitions 33234H[...]

AMD Geode™ LX Processors Data Book 45 4 GeodeLink™ Interface U nit 33234H 4.0 GeodeLink™ Interf ace Unit Many traditional architectures use buses to connect mod- ules together , which usuall y requires unique addressing for each register in ev er y module. This requires that some kind of house-keeping be done as new modules are designed and n[...]

46 AMD Geode™ LX Processors Data Book GeodeLink™ Interface Un it 33234H 4.1.1 P or t Addre ss Each GLIU has sev en channels with Ch annel 0 being the GLIU itself and therefore not considered a p h ysical p or t. Figure 4-1 illustrates the GeodeL ink architecture in a AMD Geode LX processor, sho wing how the modules are connected to the two GLIU[...]

AMD Geode™ LX Processors Data Book 47 GeodeLink™ Interface U nit 33234H 4.1.2 P ort Addressing Exceptions There are some e xceptions to the por t addressing ru les. If a module accesses an MSR fr om within its closest GLIU (e.g., CPU Core accessing a GLIU0 MSR), then, by con- vention, the por t address should be 0.0.0.0.0.0. But this por t addr[...]

48 AMD Geode™ LX Processors Data Book GeodeLink™ Interface Un it 33234H Each memor y request is compared against all the P2D descriptors. If the memor y request does not hit in any of the descripto rs, the request is sent to the subtractiv e por t. If the memor y requests hit mo re than one descriptor, the results are undefined. The soft ware m[...]

AMD Geode™ LX Processors Data Book 49 GeodeLink™ Interface U nit 33234H 4.1.3.2 I/O Routing and T ranslation I/O addresses are routed and are nev er translated . I/O request routing is performed wit h a choice of two descr iptor types. Each GLIU ma y have an y number of each descriptor type. The IOD types satisfy diff erent needs f or various s[...]

50 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2 GLIU Regist er Descriptions All GeodeLink™ Interface Unit (GLIU) registers are Model Specific Registers (MSRs) a nd are accessed through the RDMSR and WRMSR instru ctions. The registers associated wit h the GLIU are the Standard GeodeLink Device (GLD) MSRs, GLIU Specifi[...]

AMD Geode™ LX Processors Data Book 51 GLIU Register Descriptions 33234H GLIU0: 10000089h GLIU1: 40000089h RO SLA VE_O NL Y GLIU0: 00000000_000000 10h GLIU1: 00000000_000001 00h P age 67 GLIU0: 1000008Ah GLIU1: 4000008Ah RO Reserved --- --- GLIU0: 1000008Bh GLIU1: 4000008Bh RO WHO AM I (WHOAMI) Configuration Dependent P age 68 GLIU0: 1000008Ch GLI[...]

52 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H GLIU0: 100000C0h GLIU1: 400000C0h R/W Request Compare V alue (RQ_COMP ARE_V AL[0]) 001FFFFF_FFF FFFFFh P age 74 GLIU0: 100000C1h GLIU1: 400000C1h R/W Request Compare Mask (RQ_COMP ARE_MASK[0]) 00000000_0000000 0h P age 75 GLIU0: 100000C2h GLIU1: 400000C2h R/W Request Compare [...]

AMD Geode™ LX Processors Data Book 53 GLIU Register Descriptions 33234H GLIU0: 100000DEh GLIU1: 400000DEh R/W Data Compare Mask Low (D A_COMP ARE_MASK_LO[3]) 00000000_0000000 0h P age 78 GLIU0: 100000DFh GLIU1: 400000DFh R/W Data Compare Mask High (D A_COMP ARE_MASK_HI[3]) 00000000_0000000 0h P age 79 T able 4-7 . GLIU Statistic and Compa rator M[...]

54 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H T able 4-10 . GL IU IOD Descript or MSRs Summa ry MSR Address T ype Register Reset V alue Reference GLIU0 100000E0h- 100000E2h R/W IOD Base Mask Descri ptor s (IOD_BM) 000 000FF_FFF00000h P age 86 100000E3h- 100000E8h R/W IOD Swiss Cheese Descriptors (IOD_SC) 00000000 _000000[...]

AMD Geode™ LX Processors Data Book 55 GLIU Register Descriptions 33234H 4.2.1 Standar d GeodeLink™ Device (GLD) MSRs 4.2.1.1 GLD Capabilities MSR (GLD_MSR_CAP) 4.2.1.2 GLD Master Configur ation MSR (GLD_MSR_CONFIG) MSR Address GLIU0: 10002000h GLIU1: 400020 00h Ty p e R O Reset V alue 000 00000_000014xxh GLD _MSR_CAP Register Map 63 62 61 60 59[...]

56 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.1.3 GLD SMI MSR (GLD_MSR_SMI) The flags are set with inter nal condition s. The internal con ditio ns are alwa ys cap abl e of setting the flag, but if the mask is 1, the flagged condition will not trigger the SMI signal. Reads to t he flags retur n the value. Write = 1 t[...]

AMD Geode™ LX Processors Data Book 57 GLIU Register Descriptions 33234H 4.2.1.4 GLD Err or MSR (GLD_MSR_ ERROR) The flags are set with inter nal condition s. The internal con ditio ns are alwa ys cap abl e of setting the flag, but if the mask is 1, the flagged condi tion will not tr igger the ERR signal. Reads to the flag s return the value. Writ[...]

58 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 39 EFLAG7 Request Compar ator Error Flag 0. If high, records that an ERR was generated due to a Request Comparator 0 (RQ_COMP ARE_V AL0, GLIU0 MSR 100000C0h, GLIU1 MSR 400000C0h) e vent. Wr ite 1 to clear; writing 0 has no eff ect. EMASK7 (bit 7) must be lo w to generate ERR [...]

AMD Geode™ LX Processors Data Book 59 GLIU Register Descriptions 33234H 4.2.1.5 GLD P ower Management MSR (GLD_MSR_PM) 8 EMASK8 Request Comparator Error Mask 1 . Write 0 to enable EFLAG8 (bit 40) and to allo w a Request Comparator 1 (RQ_COMP ARE_V AL1, GLIU0 MSR 100000C2h, GLIU1 MSR 400000C2h) ev ent to generate an ERR 7 EMASK7 Request Comparator[...]

60 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.1.6 GLD Diagnostic MSR (GLD_MSR_DIA G) This register is reser ved for intern al use by AMD and should not be written to . 4.2.2 G LIU Specific Regi sters 4.2.2.1 Coherency (COH) GLD _MSR_PM Bit Descripti ons Bit Name Description 63:4 RSVD Reserved. 3:2 PMODE_1 Po wer Mode[...]

AMD Geode™ LX Processors Data Book 61 GLIU Register Descriptions 33234H 4.2.2.2 P or t Active Enable (P AE) P or ts that are not implemente d retur n 00 (RSVD). P or ts that are slav e only retur n 11. Master/Slav e por ts retur n the values as stated. GLIU0 will reset all P AE to 11 (ON) except that GLIU0 P AE3 re sets to 00 wh en the debug stal[...]

62 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.2.3 Arbitration (ARB) 4.2.2.4 Asynchr onous SMI (ASMI) ASMI is a condensed version of the por t ASMI signals. The MASK bits can be used to prev ent a device from issuing an ASMI. If the MASK = 1, the device’ s ASMI is disabled. MSR Address GLIU0: 10000082h GLIU1: 400000[...]

AMD Geode™ LX Processors Data Book 63 GLIU Register Descriptions 33234H 4.2.2.5 Asynchron ous ERR (AERR) AERR is a condensed version of the port ERR signal s. The MASK bits can be used to prev ent a de vice from issuing an AERR. If the MASK = 1, the device’ s AERR is disabled. ASMI Bit Descriptions Bit Name Description 63:16 RSVD Reserved. 15 A[...]

64 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H AERR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RSVD AERR_MASK7 AERR_MASK6 AERR_MASK5 AERR_MASK4 AERR_MASK[...]

AMD Geode™ LX Processors Data Book 65 GLIU Register Descriptions 33234H 4.2.2.6 GLIU Ph ysica l Capabilities (PHY_CAP) MSR Address GLIU0: 10000086h GLIU1: 400000 86h Ty p e R / W Reset V alue GL IU0: 20291830_010C1086h GLIU1: 20311030_0 100400Ah PHY_CAP Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 [...]

66 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.2.7 N Outstanding Response (NOUT_RESP) MSR Address GLIU0: 10000087h GLIU1: 400000 87h Ty p e R O Reset V alue 000 00000_00000000h NOUT_RESP Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 NOUT_RESP7 NOUT_RESP6 N[...]

AMD Geode™ LX Processors Data Book 67 GLIU Register Descriptions 33234H 4.2.2.8 N Outstanding Write Data (NOUT_WD A T A) 4.2.2.9 SLA VE_ONL Y MSR Address GLIU0: 10000088h GLIU1: 400000 88h Ty p e R O Reset V alue 000 00000_00000000h NOUT_WDA T A Regist er Map 63 62 61 60 59 58 57 56 55 54 53 52 5 1 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 [...]

68 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.2.10 WHO AM I (WHO AMI) 6 P6_SLA VE_ONL Y P or t 6 Slave Only . (GLIU0 = Not Used; GLIU1 = SB.) If high, indicates that P or t 6 is a slav e por t. If low , P or t 6 is a master/slav e por t. 5 P5_SLA VE_ONL Y P or t 5 Sla ve Only . (GLIU0 = GP; GLIU1 = VIP .) If high, in[...]

AMD Geode™ LX Processors Data Book 69 GLIU Register Descriptions 33234H 4.2.2.11 GLIU Slave Disable (GLIU_SL V) The slav e disable registers are av ail able f or the number of por ts on the GLIU . The unused por ts return 0. MSR Address GLIU0: 1000008Ch GLIU1: 400000 8Ch Ty p e R / W Reset V alue 000 00000_00000000h GLIU_SL V Register M ap 63 62 [...]

70 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.2.12 Arbitration2 (ARB2) MSR Address GLIU0: 1000008Dh GLIU1: 400000 8Dh Ty p e R / W Reset V alue 000 00000_00000000h ARB2 Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20[...]

AMD Geode™ LX Processors Data Book 71 GLIU Register Descriptions 33234H 4.2.3 GLIU Statistic and Comparator MSRs 4.2.3.1 Descriptor Statistic Counter (ST A TISTIC_CNT[0:3]) Descript or Statistic Co unter (ST A TISTIC_CNT[0]) Descript or Statistic Co unter (ST A TISTIC_CNT[1]) Descriptor Statistic Co unter (ST A TISTIC_CNT[2]) Descriptor Statistic[...]

72 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.3.2 Statistic Mask (ST A TISTIC_MASK[0:3] Descriptor Statistic M ask (ST A TISTIC_MASK[0]) Descriptor Statistic Mask (ST A TISTIC_MASK[1]) Descriptor Statistic Mask (ST A TISTIC_MASK[2]) Descriptor Statistic Mask (ST A TISTIC_MASK[3]) MSR Address GLIU0: 100000A1h GLIU1: 4[...]

AMD Geode™ LX Processors Data Book 73 GLIU Register Descriptions 33234H 4.2.3.3 Statistic Action (ST A TISTIC_A CTION[0:3] Descriptor Statistic A cti on (ST A T ISTIC_A CT ION[0]) Descriptor Statistic A cti on (ST A T ISTIC_A CT ION[1]) Descriptor Statistic Acti on (ST A TISTIC_A CTION[2]) Descriptor Statistic Acti on (ST A TISTIC_ACTION[3]) MSR [...]

74 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.3.4 Request Compare V a lue (RQ_COMP ARE_V AL[0:3] The RQ Compare V alue and the RQ Compa re Mask enable traps on specific t ransactions . A hit to the RQ Compare i s deter mined by hit = (RQ_IN & RQ_COM P ARE_MASK) == RQ_COMP ARE_V AL). A hit can trigger the RQ_CMP e[...]

AMD Geode™ LX Processors Data Book 75 GLIU Register Descriptions 33234H 4.2.3.5 Request Compare Ma sk (RQ_COMP ARE_MASK[0:3] The RQ Compare V alue and the RQ Compa re Mask enable traps on specific t ransactions . A hit to the RQ Compare i s deter mined by hit = (RQ_IN & RQ_COM P ARE_MASK) == RQ_COMP ARE_V AL). A hit can trigger the RQ_CMP err[...]

76 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.3.6 D A Compare V alue Lo w (D A_COMP ARE_V AL_LO[0:3 ] The D A Comp are V alue and the D A Compa re Mask enable traps on sp ecific transactions. A hit to the D A Compare is deter- mined by hit = (D A_IN & DA _COMP ARE_MASK) == DA_COM P A RE_V AL). A hit can trigger t[...]

AMD Geode™ LX Processors Data Book 77 GLIU Register Descriptions 33234H 4.2.3.7 D A Compare V alue High (DA_COMP AR E_V AL_HI[0 :3] The D A Comp are V alue and the D A Compa re Mask enable traps on sp ecific transactions. A hit to the D A Compare is deter- mined by hit = (D A_IN & DA _COMP ARE_MASK) == DA_COM P A RE_V AL). A hit can trigger t[...]

78 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.3.8 D A Compare Mask Low (DA_COMP ARE_MASK_LO[0:3]) Data Compare Mask Low (D A_COMP ARE_MASK_LO[0]) Data Compare Mask Low (D A_COMP ARE_MASK_LO[1]) Data Compare Mask Low (D A_COMP ARE_MASK_LO[2]) Data Compare Mask Low (D A_COMP ARE_MASK_LO[3]) The D A Comp are V alue and [...]

AMD Geode™ LX Processors Data Book 79 GLIU Register Descriptions 33234H 4.2.3.9 D A Compar e Mask High ( DA_COMP ARE_MASK_HI[0:3]) Data Compare Mask High (D A_COMP ARE_MASK_HI[0]) Data Compare Mask High (D A_COMP ARE_MASK_HI[1]) Data Compare Mask High (D A_COMP ARE_MASK_ HI[2]) Data Compare Mask High (D A_COMP ARE_MASK_HI[3 ]) MSR Address GLIU0: [...]

80 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.4 P2D Descri ptor Register s P2D descri ptors are ordered P2D_BM, P2D_BMO , P2D_R, P2D_RO , P2D_SC, P2 D_BMK. F or example if NP2D_BM=3 and NP2D_BM0=2, I MSR EO = P2D_BM[0 ], MSR E3 = P2D_SC[0]. 4.2.4.1 P2D Base Mask Descriptor (P2D_BM) See T able 4.1.3.1 "Memor y Ro[...]

AMD Geode™ LX Processors Data Book 81 GLIU Register Descriptions 33234H 4.2.4.2 P2D Base Mask Offset Descriptor (P2D_BMO) See T able 4.1.3.1 "Memor y Routing and T ranslatio n" on page 47 for details on the descrip tor usage. GLIU0 P2D_BMO[1:0] MSR Address 10000026h-10000 027h Ty p e R / W Reset V alue 000 00FF0_FFF00000h P2D_BMO Regist[...]

82 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.4.3 P2D Range Descriptor (P2D_R) See T able 4.1.3.1 "Memor y Routing and T ranslatio n" on page 47 for details on the descrip tor usage. GLIU0 P2D_R[0] MSR Address 10000028h Ty p e R / W Reset V alue 000 00000_000FFFFFh GLIU1 P2D_R[3:0] MSR Address 4000002Ah-400[...]

AMD Geode™ LX Processors Data Book 83 GLIU Register Descriptions 33234H 4.2.4.4 P2D Range Offset Descriptor (P2D_RO) See T able 4.1.3.1 "Memor y Routing and T ranslatio n" on page 47 for details on the descrip tor usage. GLIU0 P2D_RO[2:0] MSR Address 10000029h-10000 02Bh Ty p e R / W Reset V alue 000 00000_000FFFFFh P2D_RO Register Map [...]

84 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.4.5 P2D Swiss Chees e Descriptor (P2D_SC) See T able 4.1.3.1 "Memor y Routing and T ranslatio n" on page 47 for details on the descrip tor usage. GLIU0 P2D_SC[0] MSR Address 1000002Ch Ty p e R / W Reset V alue 000 00000_00000000h GLIU1 P2D_SC[0] MSR Address 4000[...]

AMD Geode™ LX Processors Data Book 85 GLIU Register Descriptions 33234H 4.2.5 SP ARE MSRs (SP ARE_MSR[0:9], A:F) MSR Address GLIU0: 10000040h-1000004Fh GLIU1: 40000040h-4 000004Fh Ty p e R / W Reset V alue 000 00000_00000000h SP ARE_MSR[x] Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 3[...]

86 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H 4.2.6 I/O Descri ptors I/O descriptors are ordered IOD_BM, IOD_SC. F or exampl e if NIOD_BM = 3 and NIOD_SC = 2, MSR 100000EOh = IOD_BM[0] and MSR 100000E3h = IOD_SC[0]. 4.2.6.1 IOD Base Mask Descriptors (IOD_BM) See T able 4.1.3.1 "Memor y Routing and T ranslatio n"[...]

AMD Geode™ LX Processors Data Book 87 GLIU Register Descriptions 33234H 4.2.6.2 IOD Swiss Chees e Descriptors (IOD_SC) See T able 4.1.3.1 "Memor y Routing and T ranslatio n" on page 47 for details on the descrip tor usage. GLIU0 IOD_SC[0:5] MSR Address 100000E3h-10 0000E8h Ty p e R / W Reset V alue 000 00000_00000000h GLIU1 IOD_SC[0:3] [...]

88 AMD Geode™ LX Processors Data Book GLIU Register Descriptions 33234H[...]

AMD Geode™ LX Processors Data Book 89 5 CPU Core 33234H 5.0 CPU Core This section descr ibes the inter nal o perations of the AMD Geode™ LX processo r’ s CPU Core from a pr ogram- mer’ s point of view . It includes a descr iption of the tradi- tional “core” processing and FPU operations. The integrated function registers are describe d [...]

90 AMD Geode™ LX Processors Data Book CPU Core 33234H 5.2 Instruction Set Overview The CPU Core instru ction set can be divided into nine types of oper ations: • Arithmetic • Bit Manipulation • Shift/Rotate • String Mani pulation • Control T ransfer • Data T ransf er • Floating P oin t • High-Lev el Langu age Suppor t • Operatin[...]

AMD Geode™ LX Processors Data Book 91 CPU Core 33234H 5.3 Application Register Set The Application Register Set c on s i st s of t he r eg i st e r s m os t often used by the applicati ons programmer . Th ese regis- ters are generally accessible, although some bits in th e EFLAGS registers are protected. The General Purpose register contents are [...]

92 AMD Geode™ LX Processors Data Book CPU Core 33234H 5.3.1 G eneral Purpose Register s The General Pu rpose registers are divided into f o ur dat a registers, two pointer registers, and two ind e x regi sters as shown in T ab le 5-2 on page 91. The Data re gisters are used by the applications program- mer to manipulate data str uctures and to ho[...]

AMD Geode™ LX Processors Data Book 93 CPU Core 33234H 5.3.4 EFLA GS R egister The EFLAGS register contains status information and con- trols cer tain ope rations on the Geode LX processor . Th e lower 16 bits of this register are used when e xecuting 8086 or 80286 code. T able 5-4 giv es the bit formats for the EFLA GS register. T able 5-4. EFLA [...]

94 AMD Geode™ LX Processors Data Book CPU Core 33234H 5.4 System Register Set The Syste m Regist er Se t, sho wn in T able 5-5, consi sts of registers not generally used by application programmers. These registers are ei ther initialized b y the system BIOS or emplo yed b y system lev el programmers who generate operating systems and memor y mana[...]

AMD Geode™ LX Processors Data Book 95 CPU Core 33234H 5.4.1 Cont rol Regist ers A map of the Control registe rs (CR0, CR1, CR2, CR3, and CR4) is shown in T able 5-6 and the bit descriptions are in the tables th at fo llow . (Thes e registers should not be con- fus ed wi th the C RRn regi sters .) CR0 c ontain s system con- trol bits that c onfi g[...]

96 AMD Geode™ LX Processors Data Book CPU Core 33234H T able 5-7. CR4 Bit Descriptions Bit Name Description 31:9 RSVD Reserved. Set to 0 (alwa ys retu rns 0 when read). 8P C E Perf or mance Counter Enable. Set PCE = 1 to make RDPMC av ai lable at nonz ero privi- lege lev els. 7P G E P age Global Enabl e. Set PGE = 1 to make global pa ges immune t[...]

AMD Geode™ LX Processors Data Book 97 CPU Core 33234H 30 CD Cache Disable/Not Write-Thr ough (Snoop). Cache behavior is based on the CR0 CD and NW bits. CD NW 0 0 Normal Cach e operation, coherency maintained. Read hits access the cache , Write hits up date the cache, Read/write mi sses may cause line allocations base d on memor y region configur[...]

98 AMD Geode™ LX Processors Data Book CPU Core 33234H T able 5-11. Effects of V arious Combi nations of EM, TS, and MP Bi ts CR0[3:1] Instruction T ype TS EM MP W AIT ESC 000 E x e c u t e E x e c u t e 001 E x e c u t e E x e c u t e 1 0 0 Execute F ault 7 101 F a u l t 7 F a u l t 7 0 1 0 Execute F ault 7 0 1 1 Execute F ault 7 1 1 0 Execute F [...]

AMD Geode™ LX Processors Data Book 99 CPU Core Register Descriptions 33234H 5.5 CPU Core Register Descriptions All CPU Core registe rs are Model Specific Registers (MSRs) and are accessed via the R DMSR and WRMSR instructions. Each module inside the processor is assigned a 256 regis- ter section of the address space. The module responds to any re[...]

100 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 00001110h RO IF Sequential Count MRS (IF_SEQCOUNT_MSR) 00000000_000000 00h Page 122 00001140h RO IF Bu ilt-In Self-T est MS R (IF_BIST_MSR) 00000000_00 000000h Page 123 00001210h R/W Exception Unit (XC) Configuration MSR (XC_CONFIG_MSR) 00000000_000000 00h Page 124 00001[...]

AMD Geode™ LX Processors Data Book 101 CPU Core Register Descriptions 33234H 00001335h R/W GS Segment Base/Limit MSR (GS_BASE_MSR) xxxxxxxx_xxxxxxxxh P age 134 00001336h R/W LDT Segment Base/Limit MSR (LDT_BASE_MSR) xxxxxxxx_xxxxxxxxh Page 134 00001337h R/W T emp Segment Base/Limit MSR (TEMP_BASE_MSR) xxxxxxxx_xxxxxxxxh Page 134 00001338h R/W TSS[...]

102 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 00001374h R/W Floating P oint Environment Opcode P ointer (FPENV_OP_MSR) 00000000_000000 00h Page 146 00001380h RO Address Calculatio n Un it Configuration MSR (AC_CONFIG_MSR) 00000000_000000 00h Page 147 00001408h R/W General Register EAX MSR (GR_EAX_MSR) 00000000_00 00[...]

AMD Geode™ LX Processors Data Book 103 CPU Core Register Descriptions 33234H 00001722h R/W ITB Entry MSR (ITB_ENTR Y_MSR) xxxxxxxx_xxxxxxxxh Page 157 00001723h R/W ITB Entry with Increment MSR (ITB_ENTR Y_I_MSR) xxxxxxxx_xxxxxxxxh Page 157 00001724h R/W ITB L0 Cache Entr y MSR (ITB_L0_ENTRY_MSR) x xxxxxxx_xxxxxxxxh Page 157 00001730h RO Instructi[...]

104 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 00001813h R/W Region Configuration Rang e 3 MSR (RCONF3_MSR) 00000000_000000 00h Page 169 W ar m Star t V alue: xxxxx000_xxxxx0xxh 00001814h R/W Region Configuration Rang e 4 MSR (RCONF4_MSR) 00000000_000000 00h Page 169 W ar m Star t V alue: xxxxx000_xxxxx0xxh 00001815h[...]

AMD Geode™ LX Processors Data Book 105 CPU Core Register Descriptions 33234H 00001901h R/W Bus Controller Configuration 1 MSR (BC_CONFIG1_MSR) 00000000_000000 00h Page 184 00001904h RO Reser ved Status MSR (RSVD_STS_MSR) 0 0000000_00000000h P age 185 00001908h R/W MSR Lock MSR (MSR_LOCK_MSR) 00000000_000000 00h Page 185 00001910h R/W Real Time St[...]

106 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 00001A03h R/W FPU Reser ved MSR (FPU_RSVD_MSR) 0000 0000_00000000h P age 202 00001A10h R/W FPU x87 Control Word MSR (FPU_CW_MSR) 00000000_00000040h P age 203 00001A11h R/W FPU x87 Status Word MSR (FPU_SW_MSR) 0000 0000_00000000h P age 203 00001A12h R/W FPU x87 T ag Word [...]

AMD Geode™ LX Processors Data Book 107 CPU Core Register Descriptions 33234H 00003000h R/W Standard Lev els and V endor ID String 1 (CPUID0_ MSR) 68747541_000000 01h Page 207 00003001h R/W V endo r ID Strings 2 and 3 (CPUID1_MSR) 69746E65 _444D4163h P age 207 00003002h R/W T ype/F amily/Model/Ste p (CPUID2_MSR) 00000 400_000005A2h Page 207 000030[...]

108 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.1 Standar d GeodeLink™ Device MSRs 5.5.1.1 GLD Capabilities MSR (GLD_MSR_CAP) 5.5.1.2 GLD Master Configur ation MSR (GLD_MSR_CONFIG) MSR Address 00002000h Ty p e R O Reset V alue 000 00000_000864xxh GLD_MSR_CAP Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50[...]

AMD Geode™ LX Processors Data Book 109 CPU Core Register Descriptions 33234H 5.5.1.3 GLD SMI MSR (GLD_MSR_SMI) This register is not used in the CPU Core modul e. 5.5.1.4 GLD Err or MSR (GLD_MSR_ ERROR) This register is not used in the CPU Core modul e. 5.5.1.5 GLD P ower Management MSR (GLD_MSR_PM) This register is not used in the CPU Core modul [...]

110 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2 CPU Core Specifi c MSRs 5.5.2.1 Time Stamp Counter MSR (TSC_MSR) 5.5.2.2 P erformance Event Co unter 0 MSR (PERF_CNT0_MSR) MSR Address 00000010h Ty p e R / W Reset V alue 000 00000_00000000h TSC_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46[...]

AMD Geode™ LX Processors Data Book 111 CPU Core Register Descriptions 33234H 5.5.2.3 P erformance Event Co unter 1 MSR (PERF_CNT1_MSR) MSR Address 000000C2h Ty p e R / W Reset V alue 000 00000_00000000h PERF_CNT1_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD PERF_CNT1 (High B[...]

112 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.4 SYSENTER/SYSEX IT Code Segment Select or MSR (SYS_CS_MSR) SYS_CS_MSR is used by the SYSENTER instruction (fast system call) as the selector of the most pr ivileged code seg- ment. SYS_CS plus 8 is use d by SYSENTE R as the selector of the most pr ivil eged stack [...]

AMD Geode™ LX Processors Data Book 113 CPU Core Register Descriptions 33234H 5.5.2.5 SYSENTER/SYSEX IT Stack P ointer MSR (SYS_SP_MSR) SYS_SP MSR is used b y the SYSENTER instruction (f ast system call) as the most privileged stack pointer . 5.5.2.6 SYSENTER/SYSEX IT Instruct ion P ointer MSR (SYS_IP_MSR) SYS_IP MSR is used b y the SYSENTER instr[...]

114 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.7 P erformance Event Counte r 0 Select MSR (PERF_SEL0_MSR 5.5.2.8 P erformance Event Counte r 1 Select MSR (PERF_SEL1_MSR) MSR Address 00000186h Ty p e R / W Reset V alue 000 00000_00000000h PERF_SEL0_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48[...]

AMD Geode™ LX Processors Data Book 115 CPU Core Register Descriptions 33234H 5.5.2.9 Instruction Fetch Configurati on MSR (IF_CONFIG_MSR) IF_CONFG_MSR controls the operation of the Instr uction Fetch (IF). The Le vel-0 COF cache (Change of Flow (COF) cache), L1 COF cache, return stack, and power saving mode ma y be tur ned on or off. The WRMSR in[...]

116 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 28 II_NS Instruction Pipeline (IP) Emp ty Mode . 0: IM Interf ace may m ake requests t o Instruct ion Memor y (IM) when the IP is not empty . (Def ault) 1: IM Interf ac e only makes requests to IM after the IP is empty . Note: Enabling this mode reduces performance. 27:2[...]

AMD Geode™ LX Processors Data Book 117 CPU Core Register Descriptions 33234H 6S T R O N G Stro ng Prediction. Allow the IF to make strong predictions . 0: Disable. 1: Enable. (Def ault) Note: Enabling strong predictions may improv e perf orm ance. 5 RSVD Reserved. 4R S Return Stack. 0: Disable. 1: Enable. (Def ault) Note: Enabling the return stac[...]

118 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.10 IF Inv alidate MSR (IF_INV ALID A TE_MSR) IF_INV ALIDA TE MSR ma y be used to inva lidate the contents of the T ag RAMs (L ev el-1 COF cache), Lev el-0 COF cache, and the retur n stack. De vices exter nal to the CPU should issue writes to IF_INV ALID A TE_MSR on[...]

AMD Geode™ LX Processors Data Book 119 CPU Core Register Descriptions 33234H 5.5.2.12 IF T est Data MSR (IF_TEST_D A T A_MSR) 12:8 BLOCK Block Identifier . 00h: T arget RAM 0 (W ay 0). (Def ault) 01h: T arget RAM 1 (W ay 0). 02h: T arget RAM 2 (W ay 0). 03h: T arget RAM 3 (W ay 0). 04h: T arget RAM 4 (W ay 1). 05h: T arget RAM 5 (W ay 1). 06h: T [...]

120 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H IF_TEST_DA T A_MSR Register Map for T ag RAMs 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 4 6 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 V LIP RSVD STRENGTH TYPE[...]

AMD Geode™ LX Processors Data Book 121 CPU Core Register Descriptions 33234H IF_TEST_D A T A_MSR Register Map for Le vel-0 COF Cache Addr ess 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 4 6 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 ADDR[[...]

122 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.13 IF Sequential Co unt MRS (IF_SEQCOUNT_MSR) IF SEQCOUNT MSR is a read only MSR cont aining the number of sequential instr uct ions ex ecuted sinc e the last change of flow . This is useful when the CPU is halted, since it help s de ter mine the instructions ex ec[...]

AMD Geode™ LX Processors Data Book 123 CPU Core Register Descriptions 33234H 5.5.2.14 IF Built-In Sel f-T est MSR (IF_BIST_MSR) IF_BIST_MSR may be used to run built-in self-test (BIST) on the IF T ag and T a rget RAMs, and to get an indi cation of whether the BIST run passed or failed. There are separate BI ST controllers for the T ag RAM and f o[...]

124 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.15 Exception Unit (XC) Co nfiguration MSR (XC_CONFIG_MSR) XC_CONFIG_MSR allows the processor to be configured so that when the proces sor is in it s HAL T state, it can r e quest that its clocks be turned off. It also allows the processor to be configured so that t[...]

AMD Geode™ LX Processors Data Book 125 CPU Core Register Descriptions 33234H 5.5.2.16 XC Mode MSR (XC_MODE_MSR) XC_MODE_MSR contains information about the current sta tus of the processor . MSR Address 00001211h Ty p e R / W Reset V alue 000 00000_00000000h XC_MODE_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42[...]

126 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.17 XC Histor y MSR (XC_HIST_MSR) MSR Address 00001212h Ty p e R O Reset V alue 000 00000_00000000h XC_HIST_MSR Register Ma p 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD TYPE11 TYPE10 TYPE9 TYPE8 TYPE7 TYPE6 3[...]

AMD Geode™ LX Processors Data Book 127 CPU Core Register Descriptions 33234H 5.5.2.18 XC Microcode Address MSR (XC_U ADDR_MSR) 5.5.2.19 ID Configura tio n MSR (ID_CONFIG_MSR) MSR Address 00001213h Ty p e R O Reset V alue 000 00000_00000000h XC_U ADDR_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37[...]

128 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.20 SMM Contro l MSR (SMM_CTL_MSR) MSR Address 00001301h Ty p e R / W Reset V alue 000 00000_00000000h SMM_CTL_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2[...]

AMD Geode™ LX Processors Data Book 129 CPU Core Register Descriptions 33234H 5.5.2.21 Debug Management Inte rrupt (DMI ) Control Register MSR Address 00001302h Ty p e R / W Reset V alue 0000 0000_00000000h DMI Control Re gister Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 3 1 3 0 2 9 2 8[...]

130 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.22 T emporar y MSRs T emporary 0 MSR (TEMP0_MSR) T emporary 1 MSR (TEMP1_MSR) T emporary 2 MSR (TEMP2_ MSR) T emporary 3 MSR (TEMP3_ MSR) 1D M I _ G P F DMI Gene ral Protection Faults. When enabled and not in DMM mode, allow general protection faults to generate DM[...]

AMD Geode™ LX Processors Data Book 131 CPU Core Register Descriptions 33234H 5.5.2.23 Segment Selector/Flags MSRs The Segment Selector/Flag s MSRs provide access to the segment sele ctor and segment flags par ts o f a segment register . The conten ts of segmen t registers should be accessed us ing MO V or SVDC/ RSDC. ES Segment Selector /Flags Re[...]

132 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.24 SMM Header MSR (SMM_HDR_MSR) The SMM_HDR_MSR provides access to the address r egister that contro ls w here SMI data is written. 19 X Executable Non-System Segment. 18 E/C Expand Down Data Segment / Co nfor ming Code Segment. 17 W/R Wr itable Data Segment / Read[...]

AMD Geode™ LX Processors Data Book 133 CPU Core Register Descriptions 33234H 5.5.2.25 DMM Header MSR (DMM_HDR_ MSR) DMM_HDR_MSR provides access to the address regist er that controls where DMI data is written. MSR Address 0000132Ch Ty p e R / W Reset V alue 000 00000_00000000h DMM_HDR_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 [...]

134 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.26 Segment Base/Limit MSRs The segment base/limit MS Rs provi de access to the segment lim it and segment b ase par ts of a segmen t register . The limit value is the true limit; it does not need to be altered based on the limit granularity bit. T he contents of se[...]

AMD Geode™ LX Processors Data Book 135 CPU Core Register Descriptions 33234H 5.5.2.27 Debug Registers 1 and 0 MSR (DR1_DR0_MSR) DR1_DR0_MSR provides access to Debug Register 1 (DR1 ) and Debug Register 0 (DR0). DR0 and DR1 each contain either an I/O por t number or a linear address f or use as a br eakp oint. The contents of debug registers are m[...]

136 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.29 Debug Registers 7 and 6 MSR (DR6_DR7_MSR) DR7_DR6_MSR provides access to Debug Register 7 (DR7) and Debug Register 6 (DR6). DR6 contains status information about debug conditions that hav e occu rred. DR7 contai ns debug condition enables , types, and lengths. T[...]

AMD Geode™ LX Processors Data Book 137 CPU Core Register Descriptions 33234H 5.5.2.30 Extended Debug Registers 1 and 0 MSR (XDR1_XDR0_MSR) XDR1/XDR0_MSR provides access to Exte nded Debug Regist er 1 (XDR1) and Extende d Debug Register 0 (XDR0). XDR0 and XDR1 each contain e ither an I/O por t number or a linear address for use as an e xtended bre[...]

138 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.32 Extended Debug Registers 5 and 4 MSR (XDR5_XDR4_MSR) XDR5/XDR4_MSR provides access to Exte nded Debug Regist er 5 (XDR5) and Extende d Debug Register 4 (XDR4). XDR4 contains an opcode ma tch value . XDR5 contains an op code match mask. 5.5.2.33 Extended Debug Re[...]

AMD Geode™ LX Processors Data Book 139 CPU Core Register Descriptions 33234H XDR7_XDR6_MSR Bit Descriptions Bit Name Des cription 63:62 LEN3 Exten ded Breakpoint 3 Le ngth. 61:60 TYPE3 Extended Breakpoint 3 T ype . 59:58 LEN2 Exten ded Breakpoint 2 Le ngth. 57:56 TYPE2 Extended Breakpoint 2 T ype . 55:54 LEN1 Exten ded Breakpoint 1 Le ngth. 53:52[...]

140 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.34 Extended Debug Registers 9 and 8 MSR (XDR9_XDR8_MSR) XDR9_XDR8_MSR provides access to Extended Debug Re gister 9 (XDR9) and Extended Debug Register 8 (XDR8). XDR8 contains an opcode match value. XDR9 contains an opcode match mask. MSR Address 00001354h Ty p e R [...]

AMD Geode™ LX Processors Data Book 141 CPU Core Register Descriptions 33234H 5.5.2.35 Extended Debug Registers 11 and 10 MSR (XDR11_XDR10_MSR) XDR11_XDR10_MSR provides access to the e xtended I/O breakpoint. 5.5.2.36 EX Stage Instruction Pointer MSR (EX_IP_MSR) EX_IP_MSR provides access to the EX stage instruction pointer (e ffectiv e address). M[...]

142 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.37 WB Stage Instructio n Pointer MSR (WB_IP_MSR) WB_IP_MSR provides access to the WB stag e instruction pointer (e ffectiv e addre ss). 5.5.2.38 EX Stage Linear Instruct ion Pointer MSR (EX_LIP_MSR) EX_LIP_MSR provides access to the EX stage linear instruction poin[...]

AMD Geode™ LX Processors Data Book 143 CPU Core Register Descriptions 33234H 5.5.2.39 WB Stage Line ar Instruction P ointer MSR (WB_LIP_MSR ) WB_LIP_MSR provides access to the WB stage linear instruction pointer. 5.5.2.40 C1/C0 Linear Instruc tio n P ointer MSR (C1_C0_LIP_ MSR) C1_C0_LIP_MSR provides access to linear instruct ion po inters when t[...]

144 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.41 C3/C2 Linear Instruc tio n P ointer MSR (C3_ C2_LIP_MSR) C3_C2_LIP_MSR provides access to linear instruct ion po inters when the code segment was loaded. 5.5.2.42 Floating Point Envir onm ent Code Se gmen t (FPENV_CS_MSR) FPENV_CS_MSR provides access to the floa[...]

AMD Geode™ LX Processors Data Book 145 CPU Core Register Descriptions 33234H 5.5.2.43 Floating Point Envir onment Instruction Po inter (FPENV_IP_MSR) FPENV_IP_MSR provides access to the floating point (FP) envi ronment instr uction pointer . Software better accesses the floating point environment data using the FLDE NV/FSTENV and FSA VE/FRST OR i[...]

146 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.45 Floating Point Envir onm ent Data Pointer (FPENV_DP_MSR) FPENV_DP_MSR p rovid es access to the f loating point (FP) en vironme nt data pointer . Software better accesses the float- ing point en vironment data usi ng the FLDE NV/FSTENV and FSA VE/FRST OR instruct[...]

AMD Geode™ LX Processors Data Book 147 CPU Core Register Descriptions 33234H 5.5.2.47 Address Calculation U nit Configuration MSR (A C_ CONFIG_MSR) MSR Address 00001380h Ty p e R O Reset V alue 000 00000_00000000h A C_CONFIG_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 3 1 3[...]

148 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.48 Gener al Register MSRs General Regi ster EA X MSR (GR_EAX_MSR) General Regi ster EC X MSR (GR_ECX_MSR) General Regi ster ED X MSR (GR_EDX_MSR) General Regi ster EB X MSR (GR_EBX_MSR) General Register ESP MSR (GR_ESP_MSR) General Regi ster EB P MSR (GR_EBP_MSR) G[...]

AMD Geode™ LX Processors Data Book 149 CPU Core Register Descriptions 33234H 5.5.2.49 Extended Flags MSR (EFLA G_MSR) 5.5.2.50 Control Register 0 MSR (CR0_MSR) This is the standard x86 Control Reg ister 0 (CR0). CR1 , CR2, CR3, and CR4 are lo cated at MSRs 00001881h-00001884h (see Section 5.5.2.74 on page 172). The co ntents of CR0-CR4 should onl[...]

150 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.51 Instruction Me mory Configuration MSR (IM_CONFIG_MSR) MSR Address 00001700h Ty p e R / W Reset V alue 000 00000_00000000h IM_CONFI G_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 3 1 3 0 2 9[...]

AMD Geode™ LX Processors Data Book 151 CPU Core Register Descriptions 33234H 8I C D Instruction Cache Disable. Completely disable L0 and L1 instruction caches. Contents of cache is not modified and no cache entr y is read. 0: Use standard x86 cache ability rules. (Default) 1: Instruction cach e will alwa ys generate a miss. 7T U S T r anslation L[...]

152 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.52 Instruction Cache Index MSR (IC_INDEX_MSR) 5.5.2.53 Instruction Cache Data MSR (IC_D A T A_MSR) MSR Address 00001710h Ty p e R / W Reset V alue 000 00000_00000000h IC_INDEX_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 [...]

AMD Geode™ LX Processors Data Book 153 CPU Core Register Descriptions 33234H 5.5.2.54 Instruction Cache T ag (IC_T A G_MSR) MSR Address 00001712h Ty p e R / W Reset V alue 000 00000_00000000h IC_T A G _MSR MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD LR U 3 1 3 0 2 9 2 8 2 7[...]

154 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.55 Instruction Cache T ag with Increment (IC_T A G_I_MSR) 5.5.2.56 L0 Ins truction Cach e Data MSR (L0_IC_DA T A_MSR) 5.5.2.57 L0 Instruc tion Cache T ag wi th Increment MSR (L0_IC_T A G_I_MSR) MSR Address 00001713h Ty p e R / W Reset V alue 000 00000_00000000h IC_[...]

AMD Geode™ LX Processors Data Book 155 CPU Core Register Descriptions 33234H 5.5.2.58 L1 Ins truction TL B Index (ITB_INDEX_MSR) The L1 Instruction TLB is accessible via an index/data mechanism. The index of the entry to access is se t via ITB_INDEX_MSR and an entr y is read or written via ITB_ ENTRY_MSR or ITB_ENTR Y_I_MSR. An autoincrement mech[...]

156 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.59 L1 Ins truction TLB Le ast Recently Used MSR (ITB_LR U_MSR) MSR Address 00001721h Ty p e R / W Reset V alue 000 00000_00000000h ITB_LRU_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 3 1 3 0 [...]

AMD Geode™ LX Processors Data Book 157 CPU Core Register Descriptions 33234H 5.5.2.60 L1 Ins truct ion TLB Entr y MSRs ITB Entry MSR (ITB_ENTR Y_MSR) ITB Entry with Incremen t MSR (ITB_ENTR Y_I_MSR) ITB L0 Cache Entry MSR (ITB_L0_ENTR Y_MSR) MSR Address 00001722h Ty p e R / W Reset V alue xxxxxxxx_xxxxxxxxh MSR Address 00001723h Ty p e R / W Rese[...]

158 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.61 Instruction Memor y Subsyste m BIST T ag MSR (IM_BIST_T A G_MSR) The Instruction Memor y s ubsystem suppor ts built-in self-test (BIST) f or the tag and data arra ys. Nor mally , BIST is run dur- ing manuf actu ring test. For con venience, BIST can be activ a te[...]

AMD Geode™ LX Processors Data Book 159 CPU Core Register Descriptions 33234H 5.5.2.63 Data Mem ory Subs ystem Configur ation 0 MSR ( DM_CONFIG0_ MSR) MSR Address 00001800h Ty p e R / W Reset V alue 000 00000_00000000h DM_CONFIG0_MSR Regis ter Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD [...]

160 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 32 WBDIS Write Buffer Disable. Disabling the write buff er f orces st ores to be sent directly from th e output of the store queue to the bus controller . Enabling the write buff e r allows memory stores to be buff ered, with or with out combining based on region proper [...]

AMD Geode™ LX Processors Data Book 161 CPU Core Register Descriptions 33234H 7 SPCDEC Decreas e Number of Speculative Reads of Data Cache. 0: Actively resync cache tag and data arrays so that loads can be speculatively handled in one clock if the MR U wa y is hit. (Default) 1: Do not attempt to resync cache tag and data arra ys. This is a perform[...]

162 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.64 Data Mem ory Subs ystem Configur ation 1 MSR ( DM_CONFIG1_ MSR) MSR Address 00001801h Ty p e R / W Reset V alue 000 00000_00000000h DM_CONFIG1_MSR Regis ter Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD [...]

AMD Geode™ LX Processors Data Book 163 CPU Core Register Descriptions 33234H 5.5.2.65 Data Memor y Subsystem Pr efetch Loc k MSR (DM_PFLOCK_MSR) 20 NOPFXEVCT No Prefetch Prefix Evictions. This bit disables clean line eviction in the case where a new allocation occurs on a load/store miss when a mov e str ing operation uses the REPNZ prefix instea[...]

164 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.66 Default Regi on Configur ation Pr oper ties MSR (RCONF_DEF AU L T_MSR) DM_PFLOCK_MSR Bit Descr iptions Bits Name Description 63:48 PFLOC KT2 Prefetch Lock out of PREFETCHT2. Bit mask of wa ys that cannot be allocated or replaced on a data prefetch miss on a PREF[...]

AMD Geode™ LX Processors Data Book 165 CPU Core Register Descriptions 33234H 5.5.2.67 Region Configuration By pass MSR (RCONF_BYP ASS_MSR) 5.5.2.68 Region Configuration A 0000-BFFFF MSR (RCONF_A0_BF_MSR) MSR Address 0000180Ah Ty p e R / W Reset V alue 000 00000_00000101h W ar m Star t V alue 00000000_0 0000219h RCONF_BYP ASS_MS R Register Map 63 [...]

166 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.69 Region Configuration C 0000-DFFFF MSR (RCONF_C0_DF_MSR) 5.5.2.70 Region Configuration E 0000-FFFFF MSR (RCONF_E0_FF_MSR) MSR Address 0000180Ch Ty p e R / W Reset V alue 010 10101_01010101h W ar m Star t V alue 19191919_1 9191919h RCONF_C0_DF_MSR Register Map 63 [...]

AMD Geode™ LX Processors Data Book 167 CPU Core Register Descriptions 33234H 5.5.2.71 Region Configuratio n SMM MSR (RCONF_SMM_MSR) RCONF_E0_FF_MSR Bit Descript ions Bit Name Description 63:56 RPFC Region Properties for 000FC000-000FFFFF . 55:48 RPF8 Region Properties for 000F8000-000FBFFF . 47:40 RPF4 Region Properties for 000F4000-000F AFFF . 3[...]

168 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.72 Region Configuratio n DMM MSR (RCONF_DMM_MSR) MSR Address 0000180Fh Ty p e R / W Reset V alue 000 00001_00000001h W ar m Star t V alue xxxxx001_xxxxx005h RCONF_DMM_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 [...]

AMD Geode™ LX Processors Data Book 169 CPU Core Register Descriptions 33234H 5.5.2.73 Region Configuratio n Rang e MSRs 0 through 7 Region Configuration Ra ng e 0 MSR (RCONF0_MSR) Region Configuration Ra ng e 1 MSR (RCONF1_MSR) Region Configuration Ra ng e 2 MSR (RCONF2_MSR) Region Configuration Ra ng e 3 MSR (RCONF3_MSR) Region Config uration Ra[...]

170 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H Region Pr oper ties The region proper ties consist of an 8-bit field a s shown in T able 5-15. T able 5-16 and T able 5-17 describe the various region proper ties effects on read and wri te operations. Note that the cache is always interrogated e ven in regions that are [...]

AMD Geode™ LX Processors Data Book 171 CPU Core Register Descriptions 33234H If paging is enabled, the region proper ties can be fur ther modified by the PCD and PWT flags in the page table entr y . The PCD flag is OR’ d with the CD bit of th e region proper ties, and the PWT bit is OR’ d with the WT bit of the region prope r ties. A similar [...]

172 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.74 x86 Control Register s MSRs (CR1, CR2, CR3, CR4) These are the standard x86 Con trol Registers CR1, CR2, CR 3, and C R4. CR0 is located at MSR 00001420h (see Se ction 5.5.2.50 on page 149). The content s of CR0-CR4 should only be accessed using the MO V instruct[...]

AMD Geode™ LX Processors Data Book 173 CPU Core Register Descriptions 33234H 5.5.2.76 Data Cache Data MSR (DC_DA T A_MSR) 5.5.2.77 Data Cache T ag MSR (DC_T A G_ MSR) MSR Address 00001891h Ty p e R / W Reset V alue 000 00000_00000000h DC_D A T A_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 3[...]

174 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.78 Data Cache T ag with Increment MSR (DC_T A G_I_MSR) Bit descriptions for this register are the same as f o r MSR 00001892h, except read/write of th is register causes an auto- increment on DC_IN DEX_MSR (MSR 00001890h). 49:32 LR U Least Recently Used V alue. (De[...]

AMD Geode™ LX Processors Data Book 175 CPU Core Register Descriptions 33234H 5.5.2.79 Data/Instruction Cache Snoop Register (SNOOP_MSR) The SNOOP_MSR provides a mechanism f or injecting a “snoop-f or-write” request in to the memor y subsystem. Both the I and D caches are snooped for the specified physical address. A hit to a dirty line in the[...]

176 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.81 L1 Da ta TLB Least Recen tly Used MSR (L1DTLB_LRU_MSR) MSR Address 00001899h Ty p e R / W Reset V alue 000 00000_00000000h L1DTLB_LR U_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 3 1 3 0 2[...]

AMD Geode™ LX Processors Data Book 177 CPU Core Register Descriptions 33234H 5.5.2.82 L1 Da ta TLB Entr y MSR (L1DTLB_ENTR Y_MSR) MSR Address 0000189Ah Ty p e R / W Reset V alue 000 00000_00000000h L1DTLB_ENTR Y_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 LINADDR RSVD WP WA _ W [...]

178 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.83 L1 Da ta TLB Entry with In crement MSR (L1DTLB_ENTR Y_I_MSR) Bit descriptions for this register are the same as for MSR 0 000189Ah, e xcept read /write of this register causes an auto- increment on the L1 TLB_INDEX_MSR (MSR 00001898h). 5.5.2.84 L2 TLB/DTE/PTE In[...]

AMD Geode™ LX Processors Data Book 179 CPU Core Register Descriptions 33234H 5.5.2.85 L2 TLB/DTE/PT E Least Recently Used MSR (L2TLB_LRU_MSR) 15:6 RSVD (RO) Reserved (Read Onl y). (Default = 0) 5:0 INDEX DTE/PT E Index. Increments on every access to L2TLB_ENTR Y_I_MSR (MSR 0000189Fh). MSR Address 0000189Dh Ty p e R / W Reset V alue 000 00000_0000[...]

180 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.86 L2 TLB/DTE/PTE En try MSR (L2TLB_ENTR Y_MSR) 21:16 PTE_ LR U 4M PTE Least Recently Used V alue. Bit 21: 4M PTE entry 0 more recent than entr y 1. Bit 20: 4M PTE entry 0 more recent than entr y 2. Bit 19: 4M PTE entry 0 more recent than entr y 3. Bit 18: 4M PTE e[...]

AMD Geode™ LX Processors Data Book 181 CPU Core Register Descriptions 33234H 7 RSVD (RO) Reserved (Read On ly). 6D I R T Y Dirty Flag. A 1 indicates that the page has be en written to . 5A C C Acc essed Flag. A 1 indicates an entr y in the TLB. 4C D Cache Disable Flag. A 1 indicates that the page is uncacheable. 3W T _ B R Write-Throug h/Write Bu[...]

182 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.87 L2 TLB/DTE/PTE Entr y with Increment MSR (L2T LB _ENTR Y_I_MSR) Bit descriptions for this register are the same as for MSR 0 000189Eh, e xcept read /write of this register causes an auto- increment on the L2TLB_IN DEX_MSR (MSR 0000189Ch). 5.5.2.88 Data Memor y S[...]

AMD Geode™ LX Processors Data Book 183 CPU Core Register Descriptions 33234H 5.5.2.89 Bus C ontr oller Configuration 0 MSR (BC_CONFIG0_MSR) 5 RETEN_TLB L2 TLB Retention Timer . Enable retention timer f or L2 TLB BIST . 0: Disable. 1: Enable . 4 R UN_TLB L2 TLB Run. Star t BIST test on L2 TLB arrays. Should read as 0 because BIST will ha ve comple[...]

184 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.90 Bus C ontr oller Configuration 1 MSR (BC_CONFIG1_MSR) This register is rese rved. Wr ite as read. 19:14 RSVD Reserved. Write as read. 13 CLK_ONS CPU Core Cloc ks On during Suspend. 0: All CPU Core clocks off during Suspend. (Def ault) 1: All CPU Core clocks on d[...]

AMD Geode™ LX Processors Data Book 185 CPU Core Register Descriptions 33234H 5.5.2.91 Reser ved Status MSR (RSVD_STS_MSR) 5.5.2.92 MSR Lock MSR (MSR_LOCK_MSR) MSR Address 00001904h Ty p e R O Reset V alue 000 00000_00000000h RSVD_STS_MSR Bit Descriptions Bit Name Description 63:0 RSVD (RO) Reserved (Read Onl y). Reads back as 0. MSR Address 00001[...]

186 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.93 Real Time Stamp Counter MSR (RTSC_MSR) 5.5.2.94 TSC and RTSC Low D WORDs MSR (RTSC_TSC_MSR) MSR Address 00001910h Ty p e R / W Reset V alue 000 00000_00000000h RTSC_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37[...]

AMD Geode™ LX Processors Data Book 187 CPU Core Register Descriptions 33234H 5.5.2.95 L2 Ca che Configur ation MSR (L2_CONFIG_MSR) L2_CONFIG_MSR controls the behavior of the L2 cache. MSR Address 00001920h Ty p e R / W Reset V alue 000 00000_0000000Eh L2_CONFIG_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 [...]

188 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.96 L2 Ca che Status MSR (L2_ST A TUS_MSR) L2_ST A T US_MSR returns the sta tus of the L2 cache controller . 5.5.2.97 L2 Ca che Inde x MSR (L2_INDEX_MSR) L2_INDEX_MSR ha s the L2 cache inde x, the wa y and the data QWORD select for diagnostic accesses. MSR Address 0[...]

AMD Geode™ LX Processors Data Book 189 CPU Core Register Descriptions 33234H 5.5.2.98 L2 Ca che Data MSR (L2_D A T A_MSR) L2_D A T A_MSR is used to access the L2 cache data for diagnostic accesses. 5.5.2.99 L2 Cache T ag MSR (L2_T A G_MSR) L2_T AG_MSR has the L2 cache tag, MR U and valid bits f or diagnostic accesses. MSR Address 00001923h Ty p e[...]

190 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.100 L2 Cache T ag with Increment MSR (L2_T A G _I_MSR) The L2_T AG_I_MSR has the auto incremented L2 cache tag, MRU and valid bits f or d iagnostic accesses. Bit descriptions for this register are the same as for L 2_T AG_MSR (MSR 00001924h), e xcept read/wr ite of[...]

AMD Geode™ LX Processors Data Book 191 CPU Core Register Descriptions 33234H 10 BIST_T AG_GO_ WA Y 3 ( R O ) L2 Cache T ag BIST W ay 3 Result (Read Only). 0: F ail. (D ef au lt) 1: P ass. 9 BIST_T AG_GO_ WA Y 2 ( R O ) L2 Cache T ag BIST W ay 2 Result (Read Only). 0: F ail. (D ef au lt) 1: P ass. 8 BIST_T AG_GO_ WA Y 1 ( R O ) L2 Cache T ag BIST [...]

192 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.102 L2 Cache T reatme nt Co ntrol MSR (L2_TR TMNT_CTL_MSR) MSR Address 00001927h Ty p e R / W Reset V alue 000 00000_00000000h L2_TR TMNT_CTL_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 3 1 3[...]

AMD Geode™ LX Processors Data Book 193 CPU Core Register Descriptions 33234H 5.5.2.103 P ower Mode MSR (PMODE_MSR) This MSR enables some modules to tur n their clocks off when they are idle to sav e power . Most of these bits a re off by default. It is recommended that they be set by BIOS. MSR Address 00001930h Ty p e R / W Reset V alue 000 00000[...]

194 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.104 Bus Controller Extended Debug Register s 1 and 0 MSR (BXDR1_ BXDR0_MSR) 5.5.2.105 Bus Controller Extended Debug Register s 3 and 2 MSR (BXDR3_ BXDR2_MSR) MSR Address 00001950h Ty p e R / W Reset V alue 000 00000_00000000h BXDR1_BXDR0_MSR Register Map 63 62 61 6[...]

AMD Geode™ LX Processors Data Book 195 CPU Core Register Descriptions 33234H 5.5.2.106 Bus Controller Extended Debug Register s 6 and 7 MSR (BXDR6_ BXDR7_MSR) BXDR6 (bits [31:0]) contains the status of the e xtended bus controller breakpoints. When a breakpoint occurs, the corre- sponding status bit is set in this register . The st atus bits re m[...]

196 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 41:40 LEN0 Exten ded Breakpoint 0 Le ngth. Selects the size of e x tende d breakpoint 1. See LEN3 (bits [47:46]) f or decode. 35 E3 Extended Breakpoint 3 Enable. Allows e xten ded breakpoint 3 to be enabled. 0: Disable. 1: Enable. 34 E2 Extended Breakpoint 2 Enable. Allo[...]

AMD Geode™ LX Processors Data Book 197 CPU Core Register Descriptions 33234H 5.5.2.107 Bus Controller Debu g Registers 0 through 3 MSR s Each of these registers specifies an address that must match the p h ysical address curr ently in the bus controller in order to trigge r the breakpoint. BDR7 is used to enable and specify th e type of BDR0-BDR3[...]

198 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.108 Bus Controller Debug Register 6 MSR (BDR6_MSR) This register contains the stat us of the bus controller breakpoints. When a breakpoint occurs, the corresponding status bit is set in this register . The status bits remain set until cleared by an MSR write. 5.5.2[...]

AMD Geode™ LX Processors Data Book 199 CPU Core Register Descriptions 33234H 31:28 TYPE3 Breakpoi nt 3 T ype. Selects the type of e xtended breakpoint 3. 0000: IM memor y read (Default). 0001: DM memory read. 0010: DM memory wr ite. 0011: DM memory read/write. 0100: DM I/O read. 0101: DM I/O wr ite. 0110: DM I/O read/wr ite. 0111: GLBus snoop for[...]

200 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.110 Memory Subsystem Ar ray Contr ol Enable MSR (MSS_ARRA Y_CTL_EN_MSR) The MSRs at addresses 00001980h -00001983h provide altern ate arra y delay control v alues fo r the MSS arra ys. After a reset, the MSS clock modules provide JT A G -accessible control values .[...]

AMD Geode™ LX Processors Data Book 201 CPU Core Register Descriptions 33234H 5.5.2.112 Memory Subsyst em Array Contr ol 1 MSR (MSS_ARRA Y_CTL1_MSR) 5.5.2.113 Memory Subsyst em Array Contr ol 2 MSR (MSS_ARRA Y_CTL2_MSR) L2 delay control settings . MSR Address 00001982h Ty p e R / W Reset V alue 000 00000_104823CFh MSS_ARRA Y_CTL1_MS R Register Map[...]

202 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.114 FPU Modes MSR (FP_MODE_MSR) 5.5.2.115 FPU Reserved MSR (FPU_RSVD_MSR) This register is reser ved for internal testing; do not write. 5.5.2.116 FPU Reserved MSR (FPU_RSVD_MSR) This register is reser ved for internal testing; do not write. MSR Address 00001A00h T[...]

AMD Geode™ LX Processors Data Book 203 CPU Core Register Descriptions 33234H 5.5.2.117 FPU x87 Control W ord MSR (FPU_CW_MSR) 5.5.2.118 FPU x87 Status W ord MSR (FPU_SW_MSR) 5.5.2.119 FPU x87 T ag W ord MSR (FPU_TW_MSR) MSR Address 00001A10h Ty p e R / W Reset V alue 000 00000_00000040h FPU_CW_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 [...]

204 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.120 FPU Busy MS R (FPU_BUSY_MSR) 5.5.2.121 FPU Register Map MSR (FPU_MAP_MSR) FPU_TW_MSR Bit Descriptions Bit Name Description 63:16 RSVD Reserved. Write as read. 15:0 FPU_TW FPU T ag W ord. MSR Address 00001A13h Ty p e R O Reset V alue 000 00000_00000000h FPU_BUSY[...]

AMD Geode™ LX Processors Data Book 205 CPU Core Register Descriptions 33234H 5.5.2.122 Mantissa of Rx MSRs Mantissa of R0 MSR (FPU _MR0_MSR) Mantissa of R1 MSR (FPU _MR1_MSR) Mantissa of R2 MSR (FPU _MR2_MSR) Mantissa of R3 MSR (FPU _MR3_MSR) Mantissa of R4 MSR (FPU _MR4_MSR) Mantissa of R5 MSR (FPU _MR5_MSR) Mantissa of R6 MSR (FPU _MR6_MSR) Man[...]

206 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H 5.5.2.123 Exponent of Rx MSRs Exponent of R0 MSR (FPU_ER0_MSR) Exponent of R1 MSR (FPU_ER1_MSR) Exponent of R2 MSR (FPU_ER2_MSR) Exponent of R3 MSR (FPU_ER3_MSR) Exponent of R4 MSR (FPU_ER4_MSR) Exponent of R5 MSR (FPU_ER5_MSR) Exponent of R6 MSR (FPU_ER6_MSR) Exponent o[...]

AMD Geode™ LX Processors Data Book 207 CPU Core Register Descriptions 33234H 5.5.2.124 FPU Reserved MSRs (FPU_RSVD_MSR) MSR addresses 00001A6 0h through 0000 1A6F are reser ved f or intern al storage pur poses and sh ould not be wr itten to . 5.5.2.125 CPU ID MSRs Standard Levels and V end or ID String 1 (CPUI D0_MSR) V endor ID Strings 2 and 3 ([...]

208 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions 33234H CPUIDx_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 CPUIDx 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 CPUIDx CPUIDx_MSR Bit Descript ions Bit Name [...]

AMD Geode™ LX Processors Data Book 209 6 Integrated Function s 33234H 6.0 Integr ated Functions The integrated functions of the AMD Geode™ LX proces- sor are: • GeodeLink™ Memor y Controller (GLMC) • Graphics Processor (GP) • Displa y Controller (DC) • Video Processor (VP) • GeodeLink Control Proce ssor (GLCP) • GeodeLink PCI Bri [...]

210 AMD Geode™ LX Processors Data Book GeodeLink™ Memor y Controller 33234H 6.1 GeodeLink™ Memory Controller The GeodeLink™ Memor y Controll er (GLMC) module sup- por ts the Unified Memor y Ar chitecture (UMA) of the AMD Geode™ L X processor and co ntrols a 64-bit DDR SDRAM interface without any e xter nal buffering. The inter- nal bloc k[...]

AMD Geode™ LX Processors Data Book 211 GeodeLink™ Memo ry Controller 33234H Features • Suppor ts up to 400 MT/S (millio n transf e rs per second) DDR SDRAMs • Suppor ts 64-b it data interface • Suppor ts unbuffered DIMMs and SODIMMs • Can maintain up to 16 open banks at a time • Can support up to three outstandin g requests at a time [...]

212 AMD Geode™ LX Processors Data Book GeodeLink™ Memor y Controller 33234H A u to Low Order Interleaving The GLMC requires that mo dule banks [0:1], if both installed, be identical an d module banks [2:3], if both installed, be identical. St andard DIMMs and SODIMMs are configured this way . Because of this requi rement, when module banks [0:1[...]

AMD Geode™ LX Processors Data Book 213 GeodeLink™ Memo ry Controller 33234H T able 6-1. LOI - 2 DIMMs, Same Size, 1 DIMM Bank 1 KB Pa g e Size 2 KB P ag e Size 4 KB P age Siz e 1 KB Page Size 2 K B P age Size 4 KB Page Size Row Col Row Col Row Col Row Col Row Col Row Col Address 2 Compo nent Banks 4 Component Banks MA13 A25 -- A26 -- A27 -- A26[...]

214 AMD Geode™ LX Processors Data Book GeodeLink™ Memor y Controller 33234H T able 6-3. Non-A uto LOI - 1 or 2 DIMMs, Differ ent Siz es, 1 DIMM Bank 1 KB Pa g e Size 2 KB Page Size 4 KB P age Size 1 KB P age Size 2 KB Page Size 4 KB P age Size Row Col Row Col Ro w Col Row Col Row Col Row Col Address 2 Component Banks 4 Com ponent Banks MA13 A24[...]

AMD Geode™ LX Processors Data Book 215 GeodeLink™ Memo ry Controller 33234H 6.1.1.2 Arbitration The pipelining of the GLMC mod ule requests consists of the GLIU0 interface request plus two request buff ers: the C (closed) and O (open) slots (see Figure 6-7). A request is accepted at the GLIU0 interfac e as long as there is a slot av ailable. Th[...]

216 AMD Geode™ LX Processors Data Book GeodeLink™ Memor y Controller 33234H 6.1.1.3 Data P ath The wri te datapath utilizes three write buff ers to gather write data within a burst, each one is 4 deep x 64 bits. Writes to the buff ers ar e alter nated between the three buff- ers or whichev er one is empty . The SID , PID , and implied BEX are a[...]

AMD Geode™ LX Processors Data Book 217 GeodeLink™ Memo ry Controller 33234H Figure 6-9. DDR Writes mph1 m_sd_data drdyrx rqin_ready dain rqin_take wrx0 wrx1 wrx2 wrx3 drdywx wry0 dain_ready dain_take rqin WRREQY WRREQX wrx0 wrx1 wrx2 wrx3 wr y0 w_databuf_out daout wrrespx wrrespy wrx1 m_sd_dqs wrx0 wrx2 wrx3 wry0 wrx1 wrx0 wrx2 wrx3 wry0 w_data[...]

218 AMD Geode™ LX Processors Data Book GeodeLink™ Memor y Controller 33234H 6.1.2 P ower Co ntrol The GLMC em ploys so me methods of power control for power sa vings. One method i s that it TRI-ST A TEs the GLMC address and control pin s when there is no valid address or control data being dr iven (i.e ., whe n all the chip selects are inactive[...]

AMD Geode™ LX Processors Data Book 219 GeodeLink™ Memor y Controller Register Descriptions 33234H 6.2 GeodeLink™ Memory Contro ller Register Descriptions All GLMC registe rs are Model Specific Registers (MSRs) and are accessed via the RDMSR and WRMSR instr uc- tions. The registers associated with the GLMC are the Standard GeodeLink Device (GL[...]

220 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Con troller Register Descriptions 33234H 6.2.1 Standar d GeodeLink™ Device (GLD) MSRs 6.2.1.1 GLD Capabilities MSR (GLD_MSR_CAP) 6.2.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG) - Not Used This register is not used in the GLMC module. 6.2.1.3 GLD SMI MSR (GLD_MSR_SMI) This register[...]

AMD Geode™ LX Processors Data Book 221 GeodeLink™ Memor y Controller Register Descriptions 33234H 6.2.1.4 GLD Err or MSR (GLD_MSR_ ERROR) MSR Address 20002003h Ty p e R / W Reset V alue 000 00000_00000000h GLD_MSR_ERROR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 3 1 3 0 2 9 [...]

222 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Con troller Register Descriptions 33234H 6.2.1.5 GLD P ower Management (GLD_MSR_PM) 6.2.1.6 GLD Diagnostic (GLD_MSR_DIA G) This register is reser ved f or intern al use by AMD and should not be written to . MSR Address 20002004h Ty p e R / W Reset V alue 000 00000_00000000h GLD_MSR_PM Reg[...]

AMD Geode™ LX Processors Data Book 223 GeodeLink™ Memor y Controller Register Descriptions 33234H 6.2.2 GLMC Spec ific MSRs 6.2.2.1 Ro w Addresses Bank0 DI MM0, Bank1 DIMM0 (MC_CF_BANK01) 6.2.2.2 Ro w Addresses Bank2 DI MM0, Bank3 DIMM0 (MC_CF_BANK23) MSR Address 20000010h Ty p e R O Reset V alue xxxxxxxx_xxxxxxxxh MC_CF_B ANK01 Register Map 63[...]

224 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Con troller Register Descriptions 33234H 6.2.2.3 Ro w Addresses Bank4 DI MM0, Bank5 DIMM0 (MC_CF_BANK45) 6.2.2.4 Ro w Addresses Bank6 DI MM0, Bank7 DIMM0 (MC_CF_BANK67) MSR Address 20000012h Ty p e R O Reset V alue xxxxxxxx_xxxxxxxxh MC_CF_BANK45 Register Map 63 62 61 60 59 58 57 56 55 54[...]

AMD Geode™ LX Processors Data Book 225 GeodeLink™ Memor y Controller Register Descriptions 33234H 6.2.2.5 Ro w Addresses Bank0 DI MM1, Bank1 DIMM0 (MC_CF_BANK89) 6.2.2.6 Ro w Addresses Bank2 DI MM1, Bank3 DIMM1 (MC_CF_BANKAB) MSR Address 20000014h Ty p e R O Reset V alue xxxxxxxx_xxxxxxxxh MC_CF_B ANK89 Register Map 63 62 61 60 59 58 57 56 55 5[...]

226 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Con troller Register Descriptions 33234H 6.2.2.7 Ro w Addresses Bank4 DI MM1, Bank5 DIMM1 (MC_CF_BANKCD) 6.2.2.8 Ro w Addresses Bank6 DI MM1, Bank7 DIMM1 (MC_CF_BANKEF) MSR Address 20000016h Ty p e R O Reset V alue xxxxxxxx_xxxxxxxxh MC_CF_B AN KCD Register Map 63 62 61 60 59 58 57 56 55 [...]

AMD Geode™ LX Processors Data Book 227 GeodeLink™ Memor y Controller Register Descriptions 33234H 6.2.2.9 Refresh and SDRAM Program (MC_CF07_D A T A) MSR Address 20000018h Ty p e R / W Reset V alue 100 71007_00000040h MC_CF07_D A T A Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 D1_[...]

228 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Con troller Register Descriptions 33234H 36 D0_CB DIMM0 Component Banks. Number of component banks per module bank for DIMM0. 0: 2 Component banks. (Default) 1: 4 Component banks. 35 RSVD Reserved. 34:32 D0_P SZ DIMM0 Pa g e Size . 000: 1 KB 100: 16 KB 001: 2 KB 101: 32 KB 010: 4 KB 110: [...]

AMD Geode™ LX Processors Data Book 229 GeodeLink™ Memor y Controller Register Descriptions 33234H 6.2.2.10 Timing and Mode Program (MC_CF8F_D A T A) 2 RSVD Reserved. 1S O F T _ R S T Software Re set. Puts the GLMC in a known state. Does not change configuration regi s- ters. The recommended sequence to use is: 1) Make sure SDRAM interf ace has [...]

230 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Con troller Register Descriptions 33234H MC_CF8F_D A T A Bit Descriptions Bit Name Description 63:56 ST ALE_REQ GLIU Max Stale Request Count. Non-high priority req uests (PRI = 0) are made high -pri- ority reque sts when the request is not ser viced within ma x stale request count clocks.[...]

AMD Geode™ LX Processors Data Book 231 GeodeLink™ Memor y Controller Register Descriptions 33234H 6.2.2.11 Featur e Enab les (MC_CF1017_D A T A) 11:8 ACT2A CT AC T(0) to A CT(1) P e riod. tRRD . Minimum number of SDRAM cloc ks between A CT and A CT comman d to two diff erent component banks within the same module bank. (Default = 7h) 7:6 DPL WR[...]

232 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Con troller Register Descriptions 33234H 6.2.2.12 Performance Counters (MC_CFPERF_CNT1) 2:0 WR2D A T Write Command T o Data Latency . Number of cloc ks between the write command and the first data beat. V alid values are: [2,1 ,0], and must correspond to the installed DIMMs as f ollows: 0[...]

AMD Geode™ LX Processors Data Book 233 GeodeLink™ Memor y Controller Register Descriptions 33234H 6.2.2.13 Counter and CAS Control (MC_PERCNT2) 6.2.2.14 Clocking and Debug (MC_CFCLK_DBUG) MSR Address 2000001Ch Ty p e R / W Reset V alue 000 00000_00FF00FFh MC_PERFCNT2 Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42[...]

234 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Con troller Register Descriptions 33234H MC_CFCLK_DBUG Bit Descript ions Bit Name Description 63:35 RSVD Reserved. 34 B2B_DIS Back-to-Back Command Disab le. Setting this bit disables the issuing of DRAM com- mands within back-to-back cycles in both MTEST and normal fu nctional mode. T o m[...]

AMD Geode™ LX Processors Data Book 235 GeodeLink™ Memor y Controller Register Descriptions 33234H 6.2.2.15 Page Open Status (MC_CFPG_OPEN) 6.2.2.16 Reser ved Register This register is reser ved and should not be written to . MSR Address 2000001Eh Ty p e R O Reset V alue 000 00000_0000FFFFh MC_CFPG_OPEN Register Map 63 62 61 60 59 58 57 56 55 54[...]

236 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Con troller Register Descriptions 33234H 6.2.2.17 PM Sensitivity Counters (MC_CF_PMCTR) MSR Address 20000020h Ty p e R / W Reset V alue 000 00000_00000006h MC_CF_PMCTR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 PM1_SENS 3 1[...]

AMD Geode™ LX Processors Data Book 237 Graphics Processor 33234H 6.3 Graphics Processor The Graphics Processor is based on the graphics proces- sor used in the AMD Geode™ GX pro cessor with se veral f eatures added to enhance performa nce and functionality . Like its predecessor , the AMD Geode LX processor’s Graphics Processor is a BitBL T/v[...]

238 AMD Geode™ LX Processors Data Book Graphics Processor 33234H T able 6-7. Graphics Pr ocessor Feature Comparison Feature AMD Geode™ GX Processor AMD Geode™ LX Processor Color Depth 8, 16, 32-bpp 8, 16, 32-bpp (A) RGB 4 and 8-bit index ed ROPs 256 (src, dest, pattern) 256 (2-src, dest and pattern) BL T Bu ff e rs FIFOs in Graphics Proc esso[...]

AMD Geode™ LX Processors Data Book 239 Graphics Processor 33234H 6.3.1 Command Buffer The AMD Geode LX pr ocessor suppor ts a command buff er interf ace in addition to the nor mal two-deep pipelined regis- ter interf ace. It is advised that software use either the com- mand buff er inte rface or the register interface. It is possib l e to use bot[...]

240 AMD Geode™ LX Processors Data Book Graphics Processor 33234H T able 6-9. V ector Command Buffer Struct ure 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W 0 1 S RSVD Write Enables GP_RASTER_MODE Data GP_DST_OFFSET Data GP_VEC_ERR Data GP_STRIDE Data GP_VEC_LEN Data GP_SRC_COLOR_FG Data GP_P A T_COLOR_0 [...]

AMD Geode™ LX Processors Data Book 241 Graphics Processor 33234H Where: 6.3.2 Channel 3 Channel 3 is an additio nal DMA channel (in addition to the first two channels: source and destination) that can fetch data from memor y or receive it through host source writes. This channel has al l of the data conversion f e atures built in to perform rotat[...]

242 AMD Geode™ LX Processors Data Book Graphics Processor 33234H 6.3.2.1 Rotating BL Ts This feature of the GP allows bitmaps to be rotated 90°, 180° or 270°. The 90° and 270 ° modes work by reading vertical str ips of the source bitmap that are on e cache line (32 bytes) wide star ting at either the top r ight or bottom left cor ner of the [...]

AMD Geode™ LX Processors Data Book 243 Graphics Processor 33234H 6.3.2.4 P alletized Color Suppor t If the Preser ve LUT Data bit is set i n the GP_CH3_MODE_STR register (GP Memor y Offset 64h[20]) then 1K o f the 2K buffer space will be allocated to be a LUT . As long as this bit remains set, the LUT data is preser ved as written. Setting th is [...]

244 AMD Geode™ LX Processors Data Book Graphics Processor 33234H 6.3.2.5 Anti-Aliased T ext Support Channel 3 can be setup to fetch 4-bpp alpha channel data that can be combined with either 16 o r 32-bpp color or monochrome source data using th e alpha unit in the GP . The depth and typ e in the GP_CH3_MODE_STR re gister should be setup to indica[...]

AMD Geode™ LX Processors Data Book 245 Graphics Processor 33234H 6.3.2.8 Channel 3 Host Source Channel 3 also su ppor ts host source data wr ites. When the HS bit is set in the GP_CH3_MODE_STR register (GP Memor y Offset 64h[18]), the channel 3 fetch engine is dis- abled and the FIFOs are filled via register wr ites to th e GP_CH3_HSRC register ([...]

246 AMD Geode™ LX Processors Data Book Graphics Processor 33234H 6.3.4 V ector O peration Generating a vector requires a similar setup to a BL T . Reg- isters must be written to spec ify the X and Y offsets of the star ting position of the v ector within the frame buff er , the vector length, and the three error ter ms required by the Bresenham a[...]

AMD Geode™ LX Processors Data Book 247 Graphics Processor 33234H 6.3.6.2 Color P atterns Color patter ns are enabled b y selecting the color patter n mode in the GP_RASTER_MODE register (GP Me mor y Offset 38h). In this mode, both of the GP_P A T_D A T A reg- isters and all six of the GP_ P A T_C OLOR registers are combined to provide a total of [...]

248 AMD Geode™ LX Processors Data Book Graphics Processor 33234H In 16-bpp mode, there is a total of two lin es of patter n, each line with eight pixels as illustrated in T ab le 6-18. In 32-bpp mode, there is only one line of patte rn with eight pixels . The orderi ng of the reg isters in the line from l eft to ri ght is as f ol- lows: 1) GP_P A[...]

AMD Geode™ LX Processors Data Book 249 Graphics Processor 33234H 6.3.7 8x8 Col or P atterns The new channel 3 hardware provides the capability of per- f or ming BL Ts with 64 pi x el color patter ns at all color depths. T o setup this mode, software first loads the pattern data into the LUT beginn ing at address 100h The least sig- nificant byte [...]

250 AMD Geode™ LX Processors Data Book Graphics Processor 33234H 6.3.8.2 Host Source F or source data that is not already in the frame buff er region of memor y , so ftware can use the GP_HST_SRC register (GP Memor y Offset 48h) for loading the data i nto the Graphics Processor . This is achiev ed by selecting host source as the or igination of t[...]

AMD Geode™ LX Processors Data Book 251 Graphics Processor 33234H 6.3.8.3 Sour ce Expansion The Graphics Processor contains hardware suppor t for color e xpansion of mo nochrome sour ce data. Those pix els corresponding to a clear bit in the source data are rendered using the color specified in the GP_SRC_COLOR_BG reg- ister (GP Memor y Offset 14h[...]

252 AMD Geode™ LX Processors Data Book Graphics Processor 33234H 6.3.11 Image Compositing Using Alpha Whereas the raster operation allows different streams of data to be logically combined, alpha chann el composition allows two streams of data to be mathematically combined based on the contents of t hei r alpha channel, which is an additional cha[...]

AMD Geode™ LX Processors Data Book 253 Graphics Processor 33234H A ov er B 1 1- α Α Displa y image A on top of image B. Where ver image A is transpar- ent, display image B. 000 10 A in B α B 0 Use image B to mask image A. Wherev er image B is non-trans- parent, display image A. 001 00 B held out by A 01 - α A Use image A to mask image B. Wher[...]

254 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H 6.4 Graphics Processor Register Definitions The registers associa ted with the Graphics Processor (GP) are the Standard GeodeLink™ Device (GLD) MSRs and Graphics Processor Configuration registers. T able 6-28 and T able 6-29 are register summar y tables that i[...]

AMD Geode™ LX Processors Data Book 255 Graphics Processor Register Definitions 33234H 10h R/W Color Config Source Co lor F oreground (GP_SRC_COLOR_FG) 00000000h P age 262 14h R/W Color Config Source Co lor Backg ro und (GP_SRC_COLOR_BG) 00000000h P age 263 18h-2Ch R/W P attern Config P atter n Color (GP_P A T_COLOR_x) 00000000h P age 265 30h-34h [...]

256 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H 6.4.1 Standard GeodeLink™ De vice (GLD) MSRs 6.4.1.1 GLD Capabilities MSR (GLD_MSR_CAP) This MSR contains the revision and de vice IDs f or the par ticu lar implementation of the Graph ics Processor . This register is read only . 6.4.1.2 GLD Master Configur at[...]

AMD Geode™ LX Processors Data Book 257 Graphics Processor Register Definitions 33234H 6.4.1.3 GLD SMI MSR (GLD_MSR_SMI) This MSR contains the SMI and Mask bits for the GP . An SMI is asser t ed whenev er an i llegal address or an i llegal type is detected on the GLIU and the mask bit is not set. This also causes th e mb_p_asmi output to be asser [...]

258 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H 6.4.1.5 GLD P ower Management MSR (GLD_MSR_PM) This MSR contains the power management controls for the GP . Since there is only one clock domain within the GP , most bits in this register a re unused. This register allows the GP to be switched off b y di sabling[...]

AMD Geode™ LX Processors Data Book 259 Graphics Processor Register Definitions 33234H 6.4.2 Graphics Proc essor Configuration Register s 6.4.2.1 Destination Of fset (GP_DST_ OFFSET) GP_DST_OFFSET is used to give a star ting location for the des tination of a BL T or vector in the destination region of mem- or y . It consists of three fields, the [...]

260 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H 6.4.2.3 V ector Erro r (GP_VEC_ERR) This register specifies the axial and di agonal error ter ms us ed by the Bresenham vector algorithm. GP_VEC_ERR shares the same storage space as GP_SRC_OFFSET and thus a wri te to one of these registers will be reflected in b[...]

AMD Geode™ LX Processors Data Book 261 Graphics Processor Register Definitions 33234H 6.4.2.5 BL T W idth/Heig ht (GP_WID_HEIGHT) This register is used to specify the width and the height of the BL T in pixels. Note that operations that extend bey ond the bounds of the frame buffer space “wrap” into the other end of the frame buffer . 6.4.2.6[...]

262 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H 6.4.2.7 Sour ce Color Foreground (GP_SRC_COLO R_FG) When source data is monoch rome, the contents of this regist er are used for e xpanding pix e ls that are set in the mono- chrome bitmap , thus replacin g the monochrome bit with a color that is appropr iatel y[...]

AMD Geode™ LX Processors Data Book 263 Graphics Processor Register Definitions 33234H 6.4.2.8 Sour ce Color Backgr ound (GP_SRC_COLOR_BG) When source data is monochrome, the contents of this regi ster are used for e xp anding pixels that are clear in the mono- chrome bitmap , thus replacin g the monochrome bit with a color that is appropr iatel y[...]

264 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H 6.4.2.9 P a ttern Color (GP_P A T_COLOR_x) In solid patter n mode, the pattern hardware is disab led and GP_P A T_COLOR_0 is selected as the input to the raster oper- ation. In monochrome patter n mo de, GP_P A T_COLOR_0 a nd GP_P A T _COLOR_1 are used for e xpa[...]

AMD Geode™ LX Processors Data Book 265 Graphics Processor Register Definitions 33234H 6.4.2.10 Pattern Data (GP_P A T_DA T A_x) In solid patter n mo de, these registers are not used. In monochrome patter n mode, GP_P A T_DA T A_0 and GP_P A T _D A T A_1 comb ine to hold the entire 8x8 patter n (64 bits). GP_P A T _D A T A_0[7:0] is the first lin [...]

266 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H GP_RASTER_MODE Bit Descriptions Bit Name Description 31:28 BPP/FMT Color Dept h and Format. 0000: 8-bpp , 3:3:2 f ormat. 0100: 16-bpp, 4:4:4:4 f ormat. 0101: 16-bpp, 1:5:5:5 f ormat. 0110: 16-bpp, 0:5:6:5 f ormat. 1000: 32-bpp, 8:8:8:8 f ormat. All Others: Unde [...]

AMD Geode™ LX Processors Data Book 267 Graphics Processor Register Definitions 33234H 6.4.2.12 V e ctor Mode (GP_VECT OR_MODE) Writing to this re gister configures the vector mode and initiates the render ing of the vector . If a BL T or vector operation is already in progress when this register is wr itten, the BL T pendin g bit in GP_BL T_ST A [...]

268 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H 6.4.2.13 BL T Mode (GP_BL T_MODE) Writing to this register configu res the BL T mode and initiates t he re ndering of the BL T . If a BL T o r vector oper ation is alread y in progress when this register is writte n, the BL T pending bit in GP_BL T_ST A TUS (GP [...]

AMD Geode™ LX Processors Data Book 269 Graphics Processor Register Definitions 33234H 6.4.2.14 Status and Reset (GP_BL T_ST A TUS, GP_RESET) This register is us ed to provide softw are with the current st atus of the GP in regards to operations pending and currently e x ecuting. A write to this registe r has no eff ect unless byte 3 is 69h, which[...]

270 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H 6.4.2.16 Base Offset (GP_B ASE_OFFSET) This register is used to define the physical base addresses of the regio ns used f o r all GP read and write operations to mem- or y . Each base de fines a 16 MB region that begins on a 4 MB boundar y . Thus the top two bit[...]

AMD Geode™ LX Processors Data Book 271 Graphics Processor Register Definitions 33234H 6.4.2.18 Command Bo ttom (GP_CMD_ BO T) This register defines the ending address of the co mmand buff er wit hin the command buff er re gion. Bits [23:0] of this register are combined with the CBASE in GLD_MSR_CONFIG (MSR A 0002001h) to form t he 32 bit address.[...]

272 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H 6.4.2.20 Command Wr ite (GP_CMD_WRITE) This register points to the next location to be wri tten wit h command buffer data from the processor . After the processor writes out a compl ete command buff er star ting at this address, it should write to this register [...]

AMD Geode™ LX Processors Data Book 273 Graphics Processor Register Definitions 33234H 6.4.2.22 Stride (GP_CH3_MODE_STR) The GP_ CH3_MODE_STR register has multiple uses. The STRIDE field is used to indicate th e byte width of the channel 3 bitmaps. Whene ver the Y coordinate is incremented, this value is added (o r subtracted if the Y bit is set) [...]

274 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H 29 X X Direction for Fetch. Data is re versed if f etch directi on does not match destination direction. 0: Left to r ight direction. 1: Right to left direction. 28 Y Y Direction for Fetch. Data is re versed if f etch directi on does not match destination direct[...]

AMD Geode™ LX Processors Data Book 275 Graphics Processor Register Definitions 33234H 6.4.2.23 Width/Heig ht (GP_CH3_WIDHI) This register is used to specify the wi dth and th e height of the bi tmap to be f e tched on channel 3 in pi x els. This need not match the destination width and height, as in the case o f a rotation BL T where the width an[...]

276 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions 33234H 6.4.2.25 LUT Inde x (GP_LUT_INDEX) This register is used to initialize the LUT_INDEX pointer t hat is used for subsequent LUT operations. All LUT accesses are D WORD accesses so only the 9 LSBs of the pointer are used to index into the 2 KB LUT . Addresses 0 00h[...]

AMD Geode™ LX Processors Data Book 277 Graphics Processor Register Definitions 33234H 6.4.2.27 Interrupt Co ntrol (GP_INT_CNTRL) This register is used to co ntrol the inte rru pt signal from the GP . It contains a 16-b it mask and a 16-bit interr upt detect. The mask por tion is read/wr ite. A bit set in the mask register disabl es the correspond[...]

278 AMD Geode™ LX Processors Data Book Display Controller 33234H 6.5 Display Contr oller The Display Controller (DC) module retriev es graphics, video , and overlay streams from the frame b uffer , serial- izes the streams, perf or ms any necessar y color loo kups and output formatting, and interfaces to the VP f or dr iving the displa y device. [...]

AMD Geode™ LX Processors Data Book 279 Display Controller 33234H The GUI bloc k, shown in Figure 6-13, provides sophisti- cated graphics functionality suitab l e f or a GUI environment such as Windows ® XP , Windows CE, or Linux ® operating systems. The GUI is optimiz ed f or high resolution and high color depth display modes . Figure 6-13. GUI[...]

280 AMD Geode™ LX Processors Data Book Display Controller 33234H The V GA block, shown in Figure 6-14, provides hardware suppor t for a compatib le VGA solution. It consists of an independent CRT controller and pixel f or matting units. It also provides the standard V GA host me mory data man ip- ulation functions such as colo r compare, set, res[...]

AMD Geode™ LX Processors Data Book 281 Display Controller 33234H 6.5.1 GUI Functional Overview 6.5.1.1 Display Mode Su pport The display modes listed in T able 6-32 are suppor ted by the GUI block. 32- and 24-bpp display suppor t is provided across all resolutions. The Dot Clock source (DO TCLK) is provided by a PLL. A vailab le memor y bandwidth[...]

282 AMD Geode™ LX Processors Data Book Display Controller 33234H 1280 x 1024 8, 16, or 24/32 60 108.000 200 8, 16, or 24/32 70 129.600 200 8, 16, or 24/32 72 133.500 200 8, 16, or 24/32 75 135.000 200 8, 16, or 24/32 85 157.500 200 8, 16, or 24/32 90 172.800 400 8, 16, or 24/32 100 192.000 400 1600 x 1200 8, 16, or 24/32 60 162.000 200 8, 16, or [...]

AMD Geode™ LX Processors Data Book 283 Display Controller 33234H 6.5.1.2 Display FIFO The DC module incor porates a 512-entr y x 64-bit display FIFO that queues up all disp lay data, including graphics frame buff er data, compressed display b uffer data, cursor and icon overla y da ta, and video overlay YUV data. When the video output por t is en[...]

284 AMD Geode™ LX Processors Data Book Display Controller 33234H Cursor/Icon Buffer Formats In 2-bpp mode, the cursor buff e r is stored as a linear dis- pla y buff er containing i nterlaced AND and XOR QWORDs (8-byte segments). Each QWORD contains the appropriate mask f or 64 pixels. Ev en QWORDs contain the AND masks and odd QWOR Ds contain the[...]

AMD Geode™ LX Processors Data Book 285 Display Controller 33234H 6.5.1.4 Display Re fresh Compression T o reduce the system memor y contention caused by the display refresh, the GUI block contains compression and decompression logic for compressing the fr a me bu ff er image in real time as it is sent to the display . Th e DC does not modify the [...]

286 AMD Geode™ LX Processors Data Book Display Controller 33234H 6.5.1.9 Video O verlay Support The GUI block also suppor ts a video overla y function. The DC has flexib le addressing capab ility f or YUV 4:2:2 and YUV 4:2:0 display surf aces. Video data is stored in a sepa- rate bu ff er within the off-screen frame buffer . Independent surf ace [...]

AMD Geode™ LX Processors Data Book 287 Display Controller 33234H 6.5.1.10 Output Formats Video Output Data Sequ encing The order that vi deo data is transmitted from the DC to th e VP depends on the format of the video data. For YUV 4:2:0 mode, the entire stream of Y data is transmitted for a source line, f oll ow e d by the entire stream of U da[...]

288 AMD Geode™ LX Processors Data Book Display Controller 33234H 6.5.4 V GA Block Functional Overvie w The V GA bloc k provides full hardware suppor t for a V GA graphics subsystem. It is comp atib le with the IBM V GA as defined in the IBM Video Sub system T echnical Ref erence manual. This section provides an o ver view of V GA f eatures and fu[...]

AMD Geode™ LX Processors Data Book 289 Display Controller 33234H 6.5.5.2 Graphi cs Controller The graphics controller mana ges the CPU interaction with video memor y , and contains the vi deo serializers that feed the front end of the attr ibute controller . Sev e ral memor y read and wr ite modes are suppor ted that provide various f or ms of ac[...]

290 AMD Geode™ LX Processors Data Book Display Controller 33234H 6.5.5.3 Write Modes There are four write modes suppo r ted by the graphics con- troller (mode 0, 1, 2, and 3). These wr ite modes provide assistance to the CPU when the frame buff er is in a planar graphics f or mat. Figure 6-17 shows the data flow logic that suppor ts these modes. [...]

AMD Geode™ LX Processors Data Book 291 Display Controller 33234H 6.5.5.4 Read Modes There are two read modes provided to assist the CPU with graphics operations in planar modes. Read mode 0 simply retur ns the frame b uffer data. Read mode 1 allows the CPU to do a single col or compare across eight pix els. Figure 6- 18 shows the data flow f or r[...]

292 AMD Geode™ LX Processors Data Book Display Controller 33234H Figure 6-19. Color Compare Operation 8x4 Input AND Compare Result [7:0] CC3 CC2 CC1 CC0 Memor y Data [31:0] 31:24 23:16 15:8 7:0 Color Compare [3:0] 3210 Color Don’t Care [3:0] 3210 D[7:0] C XOR OR CCx[7:0] E Color Compare Block Detail EC D ECD E C D E CD[...]

AMD Geode™ LX Processors Data Book 293 Display Controller 33234H 6.5.6 Graphics Scaler/F ilter The DC incor porate s a 3x5 tap filter to be used for up/ downscaling of the graphics image. In order to suppor t the filter , three lines of buff er ing are also included . These three line buff ers suppo r t a frame buff er resolution of up to 1024 pi[...]

294 AMD Geode™ LX Processors Data Book Display Controller 33234H Figure 6-20. Graphics Filter Bloc k Diagram (Continue d) 2 Pixel Latch x x x + x x x + 2 Pixel Latch H. Coefficient RAM X X X X X + Addresses for H. C oefficient RAM from H Phase Adder The entire structure is r epl icated f or each pixel component (red, green, blue, an d alpha).[...]

AMD Geode™ LX Processors Data Book 295 Display Controller 33234H T o suppor t the flicker filter , the scaling filter then f eeds two additional line buffers . The se buff ers are 1024 pixels wide . The scaling filte r directly feeds a tap of the 3x1-tap flick er filter . (The other two taps are fed b y the two line buffers .) Al l filterin g is [...]

296 AMD Geode™ LX Processors Data Book Display Controller 33234H 6.5.7 Color Key Elimination Additional logic, not shown in the diagrams, i s used to pre- ser ve the color k ey color . This logic, when enabled, adjusts the alpha value f or ea ch filter input pi x el i n which a color ke y match is detected. The filt er then uses the al pha value [...]

AMD Geode™ LX Processors Data Book 297 Display Controller 33234H 6.5.9 Interlaced Modes F or interlaced mode s, the V_A CTIVE and V_TO T AL fields are configured for the odd field. The Ev e n Field V er ti cal Timing registers (DC Me mor y Offsets 0E4h-0EC h) are configured for the corresponding e ven field. Figure 6-22 on page 298 shows a repres[...]

298 AMD Geode™ LX Processors Data Book Display Controller 33234H 6.5.10 Interlaced Timing Examples Figure 6-22 shows how the DC's timing registers are used to control timings for interlaced display modes. The SMTPE standards define the ev e n and odd fields as star ting at VSYNC , while the register se ttings define the timings based on the [...]

AMD Geode™ LX Processors Data Book 299 Display Controller 33234H T able 6-44 . Tim ing Regist er Settings for Interlaced Modes Timing Set Pa rameter Odd Regi ster Eve n Regist er Fo r m u l a V_Active_End (odd _active-1) (e ven_activ e-1) V_T otal (odd_active + odd_fp + ev en_bp - 1) (ev en_ active + e ven_fp + odd_bp - 1) V_Sync_Star t (odd _act[...]

300 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6 Display Contr oller Register Descriptions This section provides information on the regi sters associ- ated with the Display Controller (DC) (i.e., GUI and V GA bloc ks), in cluding the Standard Geod eLink™ Device (GLD) MSRs and the Display Controller Spec[...]

AMD Geode™ LX Processors Data Book 301 Display Contr oller Register Descriptions 33234H 020h R/W DC Video Y Buffer Start Addre ss Offset (DC_VID_Y_ST_OFFSET) xxxxxxxxh Page 323 024h R/W DC Video U Buff er Star t Address Offset (DC_VID_U_ST_OFFSET) xxxxxxxxh Page 323 028h R/W DC Video V Buffer Start Addre ss Offset (DC_VID_V_ST_OFFSET) xxxxxxxxh P[...]

302 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 08Ch R/W DC Dir ty/V alid RAM Access (DC_D V_ACCESS) 0000000xh P a ge 340 Graphics Scaling Control Registers 090h R/W DC Graphics Filter Scal e (DC_GFX_SCALE) 40004000 h P age 341 094h R/W DC IRQ/Filter Control (DC_IRQ_FIL T_CTL ) 00000000h Page 342 098h R/W DC[...]

AMD Geode™ LX Processors Data Book 303 Display Contr oller Register Descriptions 33234H T able 6-48. V GA Block Configuration Register Summary DC Memory Offset T ype Regis ter Name Reset V alue Reference 100h R/W V GA Con figuration (V GA_CONFIG) 00000000 h P age 355 104h RO V GA Status (VGA_ST A TUS) 00000000h Page 355 T able 6-49. V GA Block St[...]

304 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H T able 6-50. V GA Block Extend ed Register S ummar y VG A C RT C Index T ype Register Name Reset V alue Re ference 0030h R/W ExtendedRegisterL ock FFh P age 3 85 043h R/W ExtendedModeC ontrol 00h Page 385 044h R/W ExtendedSta r tAddress 00h Page 385 047h R/W Wr[...]

AMD Geode™ LX Processors Data Book 305 Display Contr oller Register Descriptions 33234H 6.6.1 Standard GeodeLink™ De vice (GLD) Registers (MSRs) 6.6.1.1 GLD Capabilities MSR (GLD_MSR_CAP) 6.6.1.2 GLD Master Configur ation MSR (GLD_MSR_CONFIG) MSR Address 80002000h Ty p e R O Reset V alue 000 00000_0003E4xxh GLD_MSR_CAP Register Map 63 62 61 60 [...]

306 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.1.3 GLIU0 Device SMI MSR (GLD_MSR_SMI) MSR Address 80002002h Ty p e R / W Reset V alue 000 00000_00000000h GLD_MSR_SMI Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD V GA_RES_CHANGE_SMI RSVD[...]

AMD Geode™ LX Processors Data Book 307 Display Contr oller Register Descriptions 33234H 40 SEQIOR_SMI Sequencer Registe r Read SMI. Reading a 1 indicates that one or more of the VGA’ s Sequencer registers has been read; wr iting a 1 to this bit clears it. 39 SEQIO W_SMI Sequencer Register Write SMI. Re ading a 1 indicates that one or more of th[...]

308 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.1.4 GLD Err or MSR (GLD_MSR_ ERROR) 9G F X I O W _ M S K Graphics Contr oller Re gister Write SMI. When set to 1, disables generation of the SMI that indicates that one or more of the V G A’ s Graphics Controller registers h as been writte n. 8 SEQIOR_MSK[...]

AMD Geode™ LX Processors Data Book 309 Display Contr oller Register Descriptions 33234H GLD_MSR_ERROR Bit Descriptions Bit Name Description 63:38 RSVD Res erved. Set to 0. 37 CWD _CHECK_ERR Co nt ro l Word Ch eck E rro r. Reading a 1 indicates that an invalid control word w as read from the Display FIFO , which is indica ti ve of a FIFO underrun.[...]

310 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.1.5 GLD P ower Management MSR (GLD_MSR_PM) 6.6.1.6 GLIU0 De vice Diagno stic MSR (GLD_MSR_DIA G) This register is reser ved for intern al use by AMD and should not be written to . MSR Address 80002004h Ty p e R / W Reset V alue 000 00000_00000015h GLD_MSR_P[...]

AMD Geode™ LX Processors Data Book 311 Display Contr oller Register Descriptions 33234H 6.6.2 Display Controller Specific MSRs 6.6.2.1 SP ARE MSR 6.6.2.2 DC RAM Contr ol MSR (DC_RAM_CTL_MSR) MSR Address 80000011h Ty p e R / W Reset V alue 000 00000_00000000h SP ARE_MS R Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 4[...]

312 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.3 Configuration and Status Register s All DC registers are D WORD accessible only . 6.6.3.1 DC Unloc k (DC_UNLOCK) This register is provided to lock the most cr itical memo r y-ma pped DC registers to prev ent unwanted modification (wr ite operations). Read[...]

AMD Geode™ LX Processors Data Book 313 Display Contr oller Register Descriptions 33234H DC_UNLOCK Bit Descriptions Bit Name Description 31:16 RSVD Reserved. 15:0 DC_UNLOCK Unlock Code. This register must be writ ten with th e value 4758h in order to write to the protected registers. The f o llowing registers are protect ed by the loc king mechani[...]

314 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.3.2 DC General Config uration (DC_GENERAL_CFG) This register contains general control bits f or the DC . Unless otherwise noted in th e bit descriptio ns table , setting s writte n to this register do not take eff ect until the star t of the fo llowing fr a[...]

AMD Geode™ LX Processors Data Book 315 Display Contr oller Register Descriptions 33234H 24 SIGE Signature Enable. Eff ective immedi ately . 0: CRC Signa ture is reset to 000001h and h eld (no capture). 1: CRC Logic captu res the pixel data signature with each pixe l clock beginning with th e next le ading edge of ver tical blank. Note that the CR[...]

316 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 11:8 DFHPSL Display-FIFO High Priority Start Level. This field speci fies the depth of the display FIFO (in multiples of 256 b ytes) at which a high-pr iority request is sent to the memor y controller to fill up the FIFO. The v alue is d ependent upon disp lay [...]

AMD Geode™ LX Processors Data Book 317 Display Contr oller Register Descriptions 33234H 6.6.3.3 DC Displa y Config uration (DC_DISPLA Y_CFG) This register contains config uration bits for co ntrolling the various display functions of the DC. Unless othe rwise noted, settings wr itten to th is register do not tak e eff ect until t h e start of the[...]

318 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 9:8 DISP_MODE Displa y Mode . Bits per pix el. 00: 8-bpp (also used in V G A emulation) 01: 16-bpp 10: 24-bpp (RGB 8:8:8) 11: 32-bpp 7 RSVD Reserved. 6T R U P Timi ng Register Update . Effe ctive immedia tely . 0: Pre vent update of working timing registers. Th[...]

AMD Geode™ LX Processors Data Book 319 Display Contr oller Register Descriptions 33234H 6.6.3.4 DC Arbitration Co nfiguration (DC_ARB_CFG) This register contains con figura tion bits f or controlling the pr iority lev el of GLIU req uests by the DC. It allo ws high pr ior it y to be enabled under se veral conditions (see bits [8:1]). These c ondi[...]

320 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 3 HPEN_2LB_INV High Pr iority Enable when Any T wo Line Buffer s Inv alid. This bit enab les the DC to arbitrate at high prio rity if the scaler filter is enabled and any tw o of the three lin e buff ers that feed this filter are inv al id. (The state of this b[...]

AMD Geode™ LX Processors Data Book 321 Display Contr oller Register Descriptions 33234H 6.6.4 Memor y Organization Registers The graphics memor y regio n is up to 16 MB in size. The gr aphics memor y is made up of the no rmal uncompressed frame buff er , compressed displa y buff er , cu rsor buff er , cursor color bu ff e r (f or 16 -bit color cu[...]

322 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.4.2 DC Compression Buffer Start Address (DC_CB_ST_OFFSET) This register speci fies the offset at which the compressed displ a y b uffer starts. Settings written to this register do not tak e eff ect until the star t of the foll owing frame or interlaced fie[...]

AMD Geode™ LX Processors Data Book 323 Display Contr oller Register Descriptions 33234H 6.6.4.4 DC Video Y Buffer Start Addr ess Offset (DC_ VID_Y_ST_OFFSET) This register specifies th e offset at which the video Y (YUV 4:2: 0) or YUV (YUV 4:2:2) buff er star ts . The upper 4 bits of thi s register are for the field count mechanism. This mechanis[...]

324 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.4.6 DC Video V Buffer Start Addr ess Offset (DC_ VID_V_ST_OFFSET) This register specifies th e offset at which the video V buff er star ts. Settings written to this register do not take eff ect until th e star t of the f ollowing frame or interlaced field .[...]

AMD Geode™ LX Processors Data Book 325 Display Contr oller Register Descriptions 33234H 6.6.4.8 DC Line Si ze (DC_LINE_SIZE) This register specifies the number of bytes to transf er for a line of frame b uffer , compression buff er , an d video buff er data. The compressed line buff er is invalidated if it e xceeds the CB_LINE_SIZE (bits [18:12])[...]

326 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.4.9 DC Graphics Pi tch (DC_GFX_PITCH) This register stores the pitch f or th e graphics displa y buff ers. 6.6.4.10 DC Video YUV Pi tch (DC_VID_YUV_PITCH) This register stores the pitch f or th e video buff ers. DC Memor y Offset 034h Ty p e R / W Reset V a[...]

AMD Geode™ LX Processors Data Book 327 Display Contr oller Register Descriptions 33234H 6.6.5 Timing Registers The DC timing registers control the generat ion of sync, blanking, and activ e displa y regions. These registers are generally programmed b y the BIOS from an INT 10h call or b y the extended mode driver from a displa y timing file. Exam[...]

328 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.5.1 DC Horizontal and T ota l Timing (DC_H_A CTIVE_TIMING) This register contains ho rizontal ac tive and t otal timing inf or mation. DC Memor y Offset 040h Ty p e R / W Reset V alue xxxxxxxxh DC_H_A CTIVE_TIMING Register Map 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 [...]

AMD Geode™ LX Processors Data Book 329 Display Contr oller Register Descriptions 33234H 6.6.5.2 DC CR T Horizo ntal Blanking Timing (DC_H_BLANK_TIMING) This register contains CRT hori zontal b la nk timing information. Note: A minimum of 32 pixel cloc ks is required f or th e horizontal blanking por tion of a line in order for the timing generato[...]

330 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.5.4 DC V ertical and T otal Timing (DC_V_ACTIVE_TIMING) This register contains ver tical active and total timing inf or m ation. The parameters per tain to both CRT and flat panel displa y . All values are specified in lines. 15:12 RSVD Reserved. These bits[...]

AMD Geode™ LX Processors Data Book 331 Display Contr oller Register Descriptions 33234H 6.6.5.5 DC CR T V ertical Blan k Timing (DC_V_ BLANK_TIMING) This register contains ver tical blank timi ng information. All values are specified in lines. For interlaced display , no border is suppor ted, so blank timing is implied by the total/active timing.[...]

332 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.5.7 DC Frame Buffer Active Region Register (DC_FB_A CTIVE) 6.6.6 Cursor P osition and Line Count/Status Register s The cursor registers contai n pixel coordinate inf or mation for t he cursor . These values are not latched b y the timing genera- tor until t[...]

AMD Geode™ LX Processors Data Book 333 Display Contr oller Register Descriptions 33234H 6.6.6.2 DC Cur sor Y P o sition (DC_CURSOR_Y) This register contains the Y position information of the hardware cursor . Settings written to this register will not take eff ect until the star t of the f ollowi ng frame or interlaced field. 6.6.6.3 DC Line Coun[...]

334 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H DC_LINE_CNT/ST A TUS Register Map 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 DNA VNA VSA RSVD FLIP V_LINE_CNT VFLIP SIGC EVEN_FIELD RSVD DO T_LINE_C NT DC_LINE_CNT/ST A TUS Bit Descriptions Bit Name Descri[...]

AMD Geode™ LX Processors Data Book 335 Display Contr oller Register Descriptions 33234H 6.6.7 Palett e Access FIFO Diagnostic Regist ers The P alette Acce ss registers are used for accessing the internal palette RAM and e xte nsions. In addition to the standard 256 entries for color translation, the palette has extensions f or cursor colors and o[...]

336 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.7.2 DC P alette Data (DC_P AL_ D A T A) This register contains the dat a f o r a palette access cycle. When a read or write to the palette RAM occurs, the pre vious out- put value is held f or one additional Do t clock period. This eff ect should go unnotic[...]

AMD Geode™ LX Processors Data Book 337 Display Contr oller Register Descriptions 33234H 6.6.7.4 DC Compression FIFO D iagnostic (DC_CF IFO_DIA G ) This register is provided to en able testability of the compress ed line buff er (FIFO) RAM. Before it is accessed, the DIAG bit should be set high (DC Memor y Offset 004 h[28] = 1) and the DFLE bi t s[...]

338 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.8 Video Downscalin g 6.6.8.1 DC Video Do wnsca ling Delta (DC_VID_DS_DEL T A) This register is provided to allow downscaling of the vid eo ov er lay image by selective skipping of source lines. A DD A engine is used to identify lines to be skipped according[...]

AMD Geode™ LX Processors Data Book 339 Display Contr oller Register Descriptions 33234H 6.6.9 GLIU Control Register s 6.6.9.1 DC GLIU0 Memory Of fset (DC_GLIU0_MEM_OFFSET) This register is used to set a base address for the graphics memo ry regio n. The value in this register is added to all outgo- ing memor y addresses. Because the base address [...]

340 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.9.3 DC Dirty/V alid RAM Access (DC_DV_A CCESS) 11:10 D V_LINE_SIZE DV L in e S i z e . This field determ ines how many b ytes of frame buff e r space correspond to an entry in the D V RAM. The value select ed by this field must be greater than or equal to t[...]

AMD Geode™ LX Processors Data Book 341 Display Contr oller Register Descriptions 33234H 6.6.10 Grap hics Scaling Control Registers 6.6.10.1 DC Graphics Filte r Scale (DC_GFX_SCALE) DC Memor y Offset 090h Ty p e R / W Reset V alue 400 04000h DC_GFX_SCALE Register Map 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1[...]

342 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.10.2 DC IRQ/Filte r Co ntrol (DC_IRQ_FIL T_CTL) DC Memor y Offset 094h Ty p e R / W Reset V alue 000 00000h DC_IRQ_F IL T_CTL Regi ster Map 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RSVD LINEBUF_SEL I[...]

AMD Geode™ LX Processors Data Book 343 Display Contr oller Register Descriptions 33234H 6.6.10.3 DC Filter Coef ficient Da ta Register 1 (DC_FIL T_COEFF1) Any read or write of this register causes a read or write of th e horizontal or filter coeffi cient RAM. If this occurs while the dis- pla y is activ e, improper filtering of an output pixel ca[...]

344 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.10.4 DC Filter Coef ficient Da ta Register 2 (DC_FIL T_COEFF2) Any read or write of this register causes a read or write of th e horizontal or filter coeffi cient RAM. If this occurs while the dis- pla y is activ e, improper filtering of an output pixel can[...]

AMD Geode™ LX Processors Data Book 345 Display Contr oller Register Descriptions 33234H 6.6.11.2 DC VBI Odd Cont rol (DC_VBI_ODD_ CTL) Settings written to this register do not take eff ect until the sta r t of the f o llowing frame or interlaced field. 6.6.11.3 DC VBI Horizontal Control (DC_VBI_HOR) Settings written to this register do not take e[...]

346 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.11.4 DC VBI Odd Line Enable (DC_VBI_LN_ODD) Settings written to this register do not take eff ect until the sta r t of the f o llowing frame or interlaced field. 6.6.11.5 DC VBI Even Line Enable (DC_VBI_LN_EVEN) Settings written to this register do not take[...]

AMD Geode™ LX Processors Data Book 347 Display Contr oller Register Descriptions 33234H 6.6.11.6 DC VBI Pitch and Size (DC_VBI_PITCH) 6.6.12 Color Key Control Registers 6.6.12.1 DC Color Key (DC_CLR_KEY) DC Memor y Offset 0B4h Ty p e R / W Reset V alue xxxxxxxxh DC_VBI_PITCH Register Map 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7[...]

348 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.12.2 DC Color Key Mask (DC_CLR_KEY_MASK) 6.6.12.3 DC Color Key Horizont al P osition (DC_CLR_KEY_X) Settings written to this register do not take eff ect until the sta r t of the f o llowing frame or interlaced field. 6.6.12.4 DC Color Key V ertical Positio[...]

AMD Geode™ LX Processors Data Book 349 Display Contr oller Register Descriptions 33234H 6.6.12.5 DC Interrupt (DC_IRQ) DC_CLR_KEY_Y Bit Descriptions Bit Name Description 31:27 RSVD Reserved. Set to 0. 26:16 CLR_KEY _Y_ END Color Ke y V ertical End. This field represents the ver tical end position of the color ke y region minus 1. This represents [...]

350 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.13 Interrupt an d GenLoc k Registers 6.6.13.1 DC GenLock Co ntrol (DC_GENLK_CTL) Settings written to this reg ister do not take eff ect until the star t of the frame or inter laced field after the timing register update bit (DC Memor y Offset 008h[6]) is se[...]

AMD Geode™ LX Processors Data Book 351 Display Contr oller Register Descriptions 33234H 6.6.14 Even Field Video Ad dress Registers 6.6.14.1 DC Even Field Video Y Start Ad dress Offset (DC_VID_EVEN_Y_ST_OFFSET) Settings writte n to this register do not take eff e ct until the sta r t of the ne xt ev en inter laced field. 20 VIP_VSYNC_ W AIT (RO) V[...]

352 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.14.2 DC Even Field Vide o U Start Address Offset (DC_VID_EVEN_U _ST_OFFSET) Settings writte n to this register do not take eff e ct until the sta r t of the ne xt ev en inter laced field. 6.6.14.3 DC Even Field Video V Start Ad dress Offset (DC_VID_EVEN_V_S[...]

AMD Geode™ LX Processors Data Book 353 Display Contr oller Register Descriptions 33234H 6.6.15 Even Field V ertical Timing Registers 6.6.15.1 DC V er tical and T o tal Timing for Even Fiel ds (DC_V_A CTIVE_EVEN_TIMING) This register contains vertical active and total timing inform atio n. These parameters per tain ONL Y to e ven fields in inter- [...]

354 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.15.2 DC CRT V ertical Blank Timing for Even Fields (DC_V_BLANK_EVEN_TIMING) This register contains ver tical blank timing informati on. All va lues are specified in lines. This register is used ONL Y f or e ve n fields in inter laced display modes . Setti n[...]

AMD Geode™ LX Processors Data Book 355 Display Contr oller Register Descriptions 33234H 6.6.16 V GA Blo ck Configuration Re gisters 6.6.16.1 V GA Configur ation (V GA_CONFIG) This register controls palette wr ite operations. 6.6.16.2 V GA Sta tus (V GA_ST A TUS) This register provides status information for the individual SMI ev ents enabled in t[...]

356 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.17 V GA Bloc k Standard Regi sters 6.6.17.1 V GA Misc ellaneous Output 2 VBLANK_SMI VBLANK SMI. If = 1, an SMI was generated due to leading edge ver tical blank. 1 ISR0_SMI Input Status Register 0 SMI. If = 1, an SMI was generated fr om an I/O IN to Input S[...]

AMD Geode™ LX Processors Data Book 357 Display Contr oller Register Descriptions 33234H 6.6.17.2 V GA Input Status Register 0 6.6.17.3 V GA Input Status Register 1 6.6.17.4 V GA Fea ture Control Read Address 3C2h Write Address -- Ty p e R / W Reset V alue 00h V GA Input Status Re gister 0 Bit Descr iptions Bit Name Description 7 RSVD Not Implemen[...]

358 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.18 V GA Se quencer Regi sters The Sequencer register s are accessed by writing an index v a lue to the Sequencer Index register (3C4h) and reading or writing the register using the Sequencer Data regi ster (3C5h). 6.6.18.1 V GA Se quencer Index 6.6.18.2 V G[...]

AMD Geode™ LX Processors Data Book 359 Display Contr oller Register Descriptions 33234H 6.6.18.4 V GA Clocking Mode 6.6.18.5 V GA Ma p Mask These bits enable (bit = 1) writing to their corresponding bytes in each DW ORD of the frame buff er (i.e., EM3 enables b y te 3, EM2 enables b y te 2, etc.). The four maps or planes correspond to the fo ur b[...]

360 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.18.6 V GA Cha racter Map Select Character Map A (bits [5,3 :2]) and Character Map B (bits [4,1:0]) deter mi ne which font tables are used when displa ying a character in text mode. When bit 3 of t he character's attribute = 1, Character Map A is used; [...]

AMD Geode™ LX Processors Data Book 361 Display Contr oller Register Descriptions 33234H 6.6.19 V GA CRT Contr oller Registers The CRTC registers are accessed by writing an index v a lue to the CRTC Inde x reg ister (3B4h or 3D4h) an d reading or wr it- ing the register using the CRTC Data register (3B5h or 3D5h). See the descr iption of the I/O A[...]

362 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.19.1 CRTC Index T able 6-54. CRTC Registers Summar y Index T ype Regis ter Reset V alue Reference -- R/W CR TC Index 00h P age 362 -- R/W CR TC Data 00h P age 363 00h R/W Horizontal T otal 00h P age 363 01h R/W Horizontal Displa y Enable End 00h P age 363 0[...]

AMD Geode™ LX Processors Data Book 363 Display Contr oller Register Descriptions 33234H 6.6.19.2 CRTC Data 6.6.19.3 Horizonta l T otal 6.6.19.4 Horizonta l Display Enab le End 6.6.19.5 Horizonta l Blank Start Data Address 3B5h or 3D5h Ty p e R / W Reset V alue 00h CRT C Data Regist er Bit Descript ions Bit Name Description 7 RSVD Reserved. 6:0 D [...]

364 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.19.6 Horizon tal Blank End 6.6.19.7 Horizonta l Sync Start 6.6.19.8 Horizonta l Sync End Index 03h Ty p e R / W Reset V alue 00h Horizontal Blan k End Register Bit Descrip tions Bit Name Description 7 RSVD Reserved. Set to 1. 6:5 DISPEN_SKEW Disp lay Enable[...]

AMD Geode™ LX Processors Data Book 365 Display Contr oller Register Descriptions 33234H 6.6.19.9 V er tical T otal 6.6.19.10 Overflow These are the high-o rder bits for se veral of the vertical prog ramming values. See the description s of the respective v er tical registers for descriptions of these fields. 6.6.19.11 Preset Row Scan Index 06h Ty[...]

366 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.19.12 Maximum Scan Line 6.6.19.13 Cursor Start 6:5 BYPE_P AN Byte Panning. This v alue causes the pixel data stream to be f etched zero , one, two , or three character positions early for use with pel panning in the attribute controller . This field is used[...]

AMD Geode™ LX Processors Data Book 367 Display Contr oller Register Descriptions 33234H 6.6.19.14 Cursor End 6.6.19.15 Start Address High 6.6.19.16 Start Address Low 6.6.19.17 Cursor Location High Index 0Bh Ty p e R / W Reset V alue 00h Cursor End Re gister Bit Descriptions Bit Name Description 7 RSVD Reserved. 6:5 CURS_SKEW Cursor Skew . This fi[...]

368 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.19.18 Cursor Location Low 6.6.19.19 V er tical Sync Star t 6.6.19.20 V er tical Sync End Index 0Fh Ty p e R / W Reset V alue 00h Cursor Location Low Register Bit Descriptions Bit Name Description 7:0 CURS_LOW Cursor Location Register Bits [7:0]. T ogether w[...]

AMD Geode™ LX Processors Data Book 369 Display Contr oller Register Descriptions 33234H 6.6.19.21 V er tical Di splay Enable End 6.6.19.22 Offset 6.6.19.23 Underline Location Index 12h Ty p e R / W Reset V alue 00h V ertical Display Enab le End Register Bit Descriptions Bit Name Des cription 7:0 V_DISP_EN_ END V er tical Display Enable End Regist[...]

370 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.19.24 V er tical Blank Star t 6.6.19.25 V er tic al Blank End 6.6.19.26 CRTC Mode Contr ol Index 15h Ty p e R / W Reset V alue 00h V ertical Blank Start Register Bit Descriptions Bit Name Description 7:0 V_BL_ST V er tical Blank Start Registe r Bits [7:0]. [...]

AMD Geode™ LX Processors Data Book 371 Display Contr oller Register Descriptions 33234H T able 6-55 illustrates the various frame buff er addressing schemes. In the table, MAx represents the frame b uffer memor y address signals, Ax represents the CRTC address counter si gnals, RSx represents row sc an counter output bits. The binar y value in th[...]

372 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.19.27 Line Compare 6.6.19.28 CPU Data Latch State 6.6.19.29 Attribute Inde x /Data FF State Index 18h Ty p e R / W Reset V alue 00h Line Compare Regi ster Bit Desc riptions Bit Name Description 7:0 LINE_COMP[7:0] Line Compare Register Bits [7:0]. This value[...]

AMD Geode™ LX Processors Data Book 373 Display Contr oller Register Descriptions 33234H 6.6.19.30 Attribute Inde x State 6.6.20 V GA Graphics Cont roller Registers The graphics controller registers are accessed by writing an index v alue to the Graphics Contro ller Index register (Inde x Address 3CEh) and reading or wr iting the register using th[...]

374 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.20.2 V GA Gra phics Contro ller Data 6.6.20.3 V GA Se t/Reset Bits [3:0] allow bits in their respectiv e maps to be set or reset through wr ite modes 0 or 3. See Section 6.5.5.3 "Wr ite Modes" on page 29 0 for more inf or mation . 6.6.20.4 V GA En[...]

AMD Geode™ LX Processors Data Book 375 Display Contr oller Register Descriptions 33234H 6.6.20.5 V GA Color Compare Bits [3:0] specify a compare value that allows the CPU to co mpare pixels in planar modes. Read mode 1 performs a com- parison b ased on these bits combined with the Co lor Don’t Care bits. Data returned will contain a 1 in each o[...]

376 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.20.7 V GA Read Map Select 6.6.20.8 V GA Gra phics Mode Index 04h Ty p e R / W Reset V alue xxh V GA Read Map Select Regi ster Bit Descriptions Bit Name Description 7:2 RSVD Reserved. 1:0 R_MP_SL Read Map Select. This field specifies which map CPU read data [...]

AMD Geode™ LX Processors Data Book 377 Display Contr oller Register Descriptions 33234H 6.6.20.9 V GA Misc ellaneous 1:0 WR_MD Wr ite Mode. This field specifies how CPU data is written to the frame b uffer . Note that the Write Operation field in the V GA Data Rota te register (Index 03h[4:3]) specifie s how CPU data is combined with data in the [...]

378 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.20.10 V GA Color Don’t Care 6.6.20.11 V GA Bit Mask 6.6.21 Attribute Controller Regi sters The attribute controller registers are accessed by writing an inde x value to the Attribute Controller Inde x register (3C0h) and reading or wr iting the register u[...]

AMD Geode™ LX Processors Data Book 379 Display Contr oller Register Descriptions 33234H 6.6.21.1 Attribute Contr oller Index/Data The attribute control ler registers do not have a separate addr ess for wr iting index and data inf or mation. Instead, an inter nal flip-flop alter nates between index and data registers. Reading In put Status Regi st[...]

380 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.21.3 Attribute Mode Control 6.6.21.4 Overscan Color Index 10h Ty p e R / W Reset V alue xxh Attrib ute Mode Control Register Bit Descriptions Bit Name Description 7 P5:4_SEL P5:4 Select. When this bit is a 1, bits [5:4] of the 8-bit VGA pix el value are tak[...]

AMD Geode™ LX Processors Data Book 381 Display Contr oller Register Descriptions 33234H 6.6.21.5 Color Plane Enable 6.6.21.6 Horizontal Pel P ann ing Index 12h Ty p e R / W Reset V alue xxh Color Plane En able Re gister Bit Descr iptions Bit Name Description 7:4 RSVD Reserved. 3 EN_CO_PN3 Enable C olor Plane 3. This bit enables color plane 3. It [...]

382 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.21.7 Color Sele ct 6.6.22 Vide o D AC Registers Video D AC palette registers are accessed by writing the Palette Address register at the read or wr ite address, then perform- ing three reads or writes, one fo r each of the red, green, and blue color v a lue[...]

AMD Geode™ LX Processors Data Book 383 Display Contr oller Register Descriptions 33234H 6.6.22.1 Video DA C Palette Address 6.6.22.2 Video DA C State 6.6.22.3 Video DA C Palette Data Read Address 3C8h Write Add ress 3C7h (P a lette Read Mode) 3C8h (P a lette Write Mode) Ty p e R O Reset V alue 00h Video D A C Palette Ad dress Register Bit Descrip[...]

384 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.22.4 Video DA C Palette Mask 6.6.23 V GA Bloc k Extended Registers The Extended registers are accessed by writing an index v al ue to the CRTC Index register (3B4h or 3D4h) and reading or writing the register using th e CR TC Data re gister (3B5h or 3D 5h).[...]

AMD Geode™ LX Processors Data Book 385 Display Contr oller Register Descriptions 33234H 6.6.23.1 Extende dRegisterLock 6.6.23.2 Extende dModeControl 6.6.23.3 ExtendedStar tAddress CRTC Inde x 030h Ty p e R / W Reset V al ue FFh ExtendedRegisterLoc k Register Bit Description s Bit Name Description 7:0 LOCK Lock. A value of 4Ch unlocks the e xtende[...]

386 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.23.4 WriteMemor yAperture 6.6.23.5 ReadMemor yAperture 6.6.23.6 BlinkCounterCtl This register is for simulation and test only . CRTC Inde x 047h Ty p e R / W Reset V alue 00h WriteMemoryAperture Register Bit De scriptions Bit Name Description 7:0 WR_BASE Wr[...]

AMD Geode™ LX Processors Data Book 387 Display Contr oller Register Descriptions 33234H 6.6.23.7 BlinkCounter This register is for simulation and test only . 6.6.23.8 V GALa tchSa vRe s 6.6.23.9 DA CIFSavRes CRTC Inde x 061h Ty p e R O Reset V alue 00h BlinkCounter Register Bit Descriptions Bit Name Description 7:5 RSVD Reserved. 4:0 BLNK_CNT Bli[...]

388 AMD Geode™ LX Processors Data Book Video Processor 33234H 6.7 Video Processor The Video Processor (VP) module provides a high-perfor- mance, low-po wer CRT/TFT disp la y or video output inter- f ace. There are three ma in functions co ntained withi n the VP: the Video Processor , the TFT controller, and the video output por t (VOP). The scali[...]

AMD Geode™ LX Processors Data Book 389 Video Processor 33234H Figure 6-23. Video Process or Bloc k Diagram Video Data Interf ace (YUV) Control Registers Interf ace Graphics Data Interf ace (RGB) Video Formatter X and Y Scaler Mixer/Blender (Overly with Alpha Blending, CSC and Gamma RAM) Dela y Video Output Po r t Output Fo r m a t (MUX) Output De[...]

390 AMD Geode™ LX Processors Data Book Video Processor 33234H 6.7.2 Functional Description The VP receives the input video stream in either YUV (4:2:2 or 4:2:0) or RGB (5:6:5) format. The VP has an inte- grated color space conv er ter to convert YUV d ata to RGB data. The video clock must a lwa ys be active (regardless of the source of video inpu[...]

AMD Geode™ LX Processors Data Book 391 Video Processor 33234H 6.7.2.1 Video Formatter The Video Processor mo dule accepts video d ata at a rate asynchronous to the GLIU clock rate . The byte order of video input data can be configured using the VID_FMT bits in the Video Configuration register (VP Memor y Offset 000h[3:2]). Video input data can be[...]

392 AMD Geode™ LX Processors Data Book Video Processor 33234H 6.7.2.3 Horizontal Downscaling The Video Processor module suppor ts horizontal down- scaling (see Figure 6-25). Th e downscaler can be imple- mented in the Video Processor module to shrink the video windo w by a f actor of up to 8: 1, in one-pix el increments . The Downscaler F actor S[...]

AMD Geode™ LX Processors Data Book 393 Video Processor 33234H 6.7.3 X and Y Upscaler After the video data has been buff e red, the upscaling algo- rithm is applied. The Vi deo Processor module employs a Digital Differential Analyzer-style (DD A) algor ithm for both horizontal and ver tical upscaling. The scaling parameters are programmed via the [...]

394 AMD Geode™ LX Processors Data Book Video Processor 33234H 6.7.5 Video Overla y Video data is mixed with gr aphics data accordi ng to the video window position. The video win dow position is pro- grammab le via the Video X P ositi on (VP Memor y Offset 010h) and Video Y P o sition (VP Memor y Offset 018h) reg- isters. A color-k eying and alpha[...]

AMD Geode™ LX Processors Data Book 395 Video Processor 33234H Figure 6-27 . Mi xer Block Diagram CSC_VIDEO Video YUV Graphics GV_P AL_BP RGB/YUV VSYNC Current Pix el Color K ey and Blending Logic P alette Alpha Color Registers and Cursor Color V alues Cursor_Color_K ey VID_CLR_KEY Location RAM CUR_COLOR_MASK Compare Compare VID_CLR_MASK 1 0 0 1 0[...]

396 AMD Geode™ LX Processors Data Book Video Processor 33234H Figure 6-28. Color Key and Alpha-Blending Logic No Ye s Ye s No Ye s No No Ye s No Ye s Notes: 1) V G_CK: Video/Graphics color ke y select (VP Memor y Offset 008h[20]). Selects whether graphic data is used f or color ke yin g or video data is used for chroma k eying. 2) GFX_INS_VIDEO: [...]

AMD Geode™ LX Processors Data Book 397 Video Processor 33234H T able 6-60 represents the same logic that is display ed in Fig ure 6-28 on page 396. 6.7.5.2 Gamma RAM Either the graphics or video stream can be routed through an integrated palette RAM f or gamma-correction of the data stream or (f or video data) contrast/brightn ess adjust- ments. [...]

398 AMD Geode™ LX Processors Data Book Video Processor 33234H 6.7.6 Video Output P or t 6.7.6.1 Functio nal Over view The Video Output P or t (VOP) receiv es YUV 4:4:4 encoded data from the VP and formats t he data into a video-stream that is BT .656) or BT .601 co mpliant. Output from the VOP goes to either a VIP or a TV enco der . The VOP m ust[...]

AMD Geode™ LX Processors Data Book 399 Video Processor 33234H 6.7.6.3 HBLANK and VBLANK Signals HBLANK and VBLANK signals are different from HSYNC and VSYNC. The HSYNC and VSYNC signals are only active f or a por tion of the blanking time, while the HBLANK and VBLANK signals are active through the en tire time. HBLANK is a function of hor i zonta[...]

400 AMD Geode™ LX Processors Data Book Video Processor 33234H Figure 6-32. HBLANK and VBLANK for Lines 263, 525 Figure 6-33. HBLANK and VBLANK for Lines 1- 18, 264-281 Figure 6-34. HBLANK and VBLANK for Lines 19, 282 Pix el Po sition Line Number HBLANK VBLANK 720 721 858 001 244 245 Pix el Po sition Line Number HBLANK VBLANK 720 721 858 001 L# L#[...]

AMD Geode™ LX Processors Data Book 401 Video Processor 33234H 6.7.6.4 Interface to Video Pr ocessor The output from the Video Processor is connected via a 24-bit bus. Bytes on this b us are aligned as shown below: [23:16] Y [15:8] Cr (V) [7:0] Cb (U) The V OP takes this 24-bit 4:4:4 data bus and conv er ts it to a 16-bit 4:2:2 data bus (the Y com[...]

402 AMD Geode™ LX Processors Data Book Video Processor 33234H 6.7.6.5 Operating Modes BT .656 Mode BT .656 is the basic standard that specifies the encoding of the control lines into the data bus. In this mode the sepa- rate control lines are encoded into the data bus as speci- fied by Recommendation ITU-R BT .656. Each line begins with a Star t [...]

AMD Geode™ LX Processors Data Book 403 Video Processor 33234H VIP 2.0 Modes (8 or 16 bits) VIP 2.0 mode builds on VIP 1.1 with the following changes/ additions: — Video Flags T , F , and V are v alid in the EA V and SA V code, valid values must appear no later then the SA V of the first scan line of the ne xt active region (see Figure 6-35). ?[...]

404 AMD Geode™ LX Processors Data Book Video Processor 33234H 6.7.6.6 New VIP 2.0 Video Flags F our bits are defin ed (shown in T able 6-64) b y the VIP specification that allow the VIP slave to comm un icate field/ frame-specific informati on to the graphics chip during th e video stream output. These flag s are embedded in the lower nibb le of [...]

AMD Geode™ LX Processors Data Book 405 Video Processor 33234H 6.7.7 Flat Panel Display Controller 6.7.7.1 FP Functional Overview The flat panel (FP) display controller conv er ts the digital RGB output of the Video Mixer b lock to digital output suit- able f or dr iving a TFT flat panel LCD . F eatures include: • 24-bit color suppor t for digit[...]

406 AMD Geode™ LX Processors Data Book Video Processor 33234H 6.7.7.3 FP Functional Description The FP connects to the RGB por t of the video mixer . LCD Interface The FP interfaces directly to industry stand ard 18-bit or 24- bit activ e matr ix thin-film-tran sistor (TFT). The digital RGB or video data that is supplied by the video logic is con[...]

AMD Geode™ LX Processors Data Book 407 Video Processor 33234H Maximum Frequency The FP will operate at a DO TCLK frequency of up to 170 MHz. There is no minimum frequency; howe ver , many flat panels hav e signal ti mings that require minimum frequen- cies. Ref er to the flat panel display manuf acturer’ s specifi- cations as appropriate. CRC S[...]

408 AMD Geode™ LX Processors Data Book Video Processor 33234H Figure 6-37. Dithered 8x8 Pix e l P attern All discussions to this point hav e referred to a 6-bit dither- ing scheme. A 6-bit ditherin g scheme is one in which the least significa nt six bits of the input intensity value f or each pixel color component are truncated and these least si[...]

AMD Geode™ LX Processors Data Book 409 Video Processor 33234H Figure 6-38. N-Bit Dithering P attern Sch e mes 15 13 14 12 000 001 010 011 100 111 101 110 000 001 010 011 100 111 101 110 75 31 11 9 46 82 1 0 15 13 14 12 75 31 11 9 46 82 1 0 15 13 14 12 75 46 82 1 0 15 13 14 12 75 46 82 1 0 3 1 1 193 1 1 19 X-Count[3:0] Y-Count [3:0] 12 1 2 000 001[...]

410 AMD Geode™ LX Processors Data Book Video Processor 33234H CRC Signature The FP contains hardware/logic that performs Cyclical Redundancy Checks (CRCs) on the panel data digital pipe- line. This feature is used f or error detecti on and makes it possible to capture a unique 24- or 32-bit signature f or any given mode setup . An error in the di[...]

AMD Geode™ LX Processors Data Book 411 Video Processor 33234H 6.7.8 VP Resolu tion T able Suppor ted CRT and flat panel resolutions of the VP are provided in T able 6-32 on page 281. All resolutions can be up to 8 bits per color , or 2 4 bits per pixel. In general, all dis- pla y resolutions contained in VESA Monitor Timing Specifi- cations V e r[...]

412 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8 Video Processor Re gister Descriptions This section provides information on the regi sters associ- ated with the Video Processor : Stand ard GeodeLink De vice (GLD) and Video Processor Specific MSRs (accessed via the RDMSR and WRMSR instr uctions), and two b l[...]

AMD Geode™ LX Processors Data Book 413 Video Processor Register Descriptions 33234H 050h R/W Miscellaneous (MISC) 00000000_ 00000C00h Page 430 058h R/W CRT Cloc k Sele ct (CCS) 00000000_00 000000h Page 431 060h R/W Video Y Scale (VYS) 00000000_00000000h P age 431 068h R/W Video X Scale (VXS) 00000000_00000000h P age 431 070h -- Reser ved (RSVD) -[...]

414 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H Flat Panel 400h R/W Panel Timing Register 1 (PT1) 0000 0000_00000000h P a ge 451 408h R/W Panel Timing Register 2 (PT2) 0000 0000_00000000h P a ge 453 410h R/W P ower Management (PM) 00000000_000000 02h Page 454 418h R/W Dither and Fr ame Rate Control (DFC) 000000[...]

AMD Geode™ LX Processors Data Book 415 Video Processor Register Descriptions 33234H 6.8.1 Standard GeodeLink™ De vice MSRs 6.8.1.1 GLD Capabilities MSR (GLD_MSR_CAP) 6.8.1.2 GLD Master Configur ation MSR (GLD_MSR_CONFIG) MSR Address 48002000h Ty p e R O Reset V alue 000 00000_0013F0xxh GLD_MSR_CAP Register Map 63 62 61 60 59 58 57 56 55 54 53 5[...]

416 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 15 FPC Simultaneous Flat P anel (or V OP) and CRT . Pri mar y displa y is fl at panel. Setting this bit activates the CR T D AC interf ac e to allow simultaneous displa y of both pane l and CRT . Lea vi ng this bit reset f orces the CR T D AC signals to zero . Thi[...]

AMD Geode™ LX Processors Data Book 417 Video Processor Register Descriptions 33234H 6.8.1.3 GLD SMI MSR (GLD_MSR_SMI) The Video Processo r does not produce SMI interrupts, therefore this register is not used. Alwa ys wr ite 0. 6.8.1.4 GLD Err or MSR (GLD_MSR_ ERROR) MSR Address 48002002h Ty p e R / W Reset V alue 000 00000_00000000h MSR Address 4[...]

418 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.1.5 GLD P ower Management MSR (GLD_MSR_PM) 6.8.1.6 GLD Diagnostic MSR (GLD_MSR_DIA G) This register is reser ved for intern al use by AMD and should not be written to . MSR Address 48002004h Ty p e R / W Reset V alue 000 00000_00000555h GLD_MSR_PM Register Map[...]

AMD Geode™ LX Processors Data Book 419 Video Processor Register Descriptions 33234H 6.8.2 Video Processor Module Specific MSRs 6.8.2.1 VP Diag nostic MSR (MSR_DIA G_VP) MSR Address 48002010h Ty p e R / W Reset V alue 000 00000_00000000h MSR_DIA G_VP Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 3[...]

420 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.2.2 P ad Select MSR (MSR_P ADSEL) MSR Address 48002011h Ty p e R / W Reset V alue 000 00000_00000000h MSR_P ADSEL Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 RSVD VO P C I N V RSVD DF_DRGB[31:26[...]

AMD Geode™ LX Processors Data Book 421 Video Processor Register Descriptions 33234H 6.8.3 Video Processo r Module C ontr ol/Configuration Register s 6.8.3.1 Video Conf iguration (VCFG) VP Memor y Offset 000h Ty p e R / W Reset V alue 000 00000_00000000h VCFG Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 3[...]

422 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.2 Display Configuratio n (DCFG) 5 SC_BYP Scaler Bypass. Bypass scaling math functi ons. Should only be used f o r non-scaled video outputs. Scale f actors set to 10000h. 0: Scaler enabled. 1: Scaler disabled. 4 RSVD (RO) Reserved (Read Only). Reads bac k as [...]

AMD Geode™ LX Processors Data Book 423 Video Processor Register Descriptions 33234H DCFG Bit Descriptions Bit Name Description 63:32 RSVD (RO) Reserved (Read Only). Reads back as 0. 31:28 SP Spa res. Bits are read/write, but hav e no function. 27 RSVD (RO) Reserved (Rea d Only). Reads back as 0. 26 D AC_VREF Select CRT D AC VREF . Allows use of a[...]

424 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.3 Video X P osition (VX) 2 VSYNC_EN CRT V ertical Sync Enable. Enables/disab les CR T vertical sync (used for VESA DPMS suppor t). 0: Disable. 1: Enable. 1 HSYNC_EN CRT Horizontal Sync Enab le . Enables/disab les CRT horizontal sync (used f or VESA DPMS supp[...]

AMD Geode™ LX Processors Data Book 425 Video Processor Register Descriptions 33234H 6.8.3.4 Video Y P osition (VY) 6.8.3.5 Video Scale (SCL) VP Memor y Offset 018h Ty p e R / W Reset V alue 000 00000_00000000h VY Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 RSVD 3 1 3 0 2 9 2 8 2 7 [...]

426 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.6 Video Color Ke y Register (VCK) 30 GB (RO) GLIU Behind (Read Only). This bit set indicates the GLIU line buff er fill is falling behind the Dot displa y . This bit clears on read. This bit is typically set if during ver tical downscale, the 2nd line b uff [...]

AMD Geode™ LX Processors Data Book 427 Video Processor Register Descriptions 33234H 6.8.3.7 Video Co lor Mask (VCM) 23:0 VID_CLR_KEY Video Color Ke y . The video color ke y is a 24-bit RGB or YUV value . • If V G_CK (VP Memory Offset 008h[20]) is se t to 0, the video pix e l is selected within the target window if the corresponding graphics pix[...]

428 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.8 P alette Address (P AR) 6.8.3.9 P alette Data (PDR) VP Memor y Offset 038h Ty p e R / W Reset V alue 000 00000_000000xxh P AR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 RSVD 3 1 3 0 2 9 2 8[...]

AMD Geode™ LX Processors Data Book 429 Video Processor Register Descriptions 33234H 6.8.3.10 Saturation Scale (SLR) VP Memor y Offset 048h Ty p e R / W Reset V alue 000 00000_00000000h SLR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 RSVD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 [...]

430 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.11 Miscella neous (MISC) VP Memor y Offset 050h Ty p e R / W Reset V alue 000 00000_00000C00h MISC Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2[...]

AMD Geode™ LX Processors Data Book 431 Video Processor Register Descriptions 33234H 6.8.3.12 CRT Cloc k Select (CCS) This register is made up of read only reser v ed bits and spare bits w ith no functi ons. 6.8.3.13 Video Y Scale (VYS) 6.8.3.14 Video X Scale (VXS) VP Memor y Offset 058h Ty p e R / W Reset V alue 000 00000_00000000h VP Memor y Off[...]

432 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.15 Video Downscaler Control (VDC) VXS Bit Descriptions Bit Name Description 63:32 RSVD (RO) Reserved (Read Only). Reads back as 0. 31:20 X_ACC_INIT X Accumulator Initial V alue . Load this value bef ore each video line. Works with hori- zontal scaling, in ca[...]

AMD Geode™ LX Processors Data Book 433 Video Processor Register Descriptions 33234H 6.8.3.16 CRC Signature (CRC) VP Memor y Offset 088h Ty p e R / W Reset V alue 000 00000_00000000h CRC Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 RSVD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0[...]

434 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.17 32-Bit CRC Signature (CRC32) 6.8.3.18 Video De-Interlacing and Alpha Control (VDE) VP Memor y Offset 090h Ty p e R O Reset V alue 000 00000_00000001h CRC32 Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35[...]

AMD Geode™ LX Processors Data Book 435 Video Processor Register Descriptions 33234H 17:16 A1P Alpha Window 1 Priority . Indicates the prio rity of alpha wind ow 1. A higher number indi- cates a higher prior ity . Prior ity is used to deter mine display order f or overlapping alpha windows. This field is reset b y hardware to 00. 15 ALPHA_DRGB Ena[...]

436 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.19 Cursor Color Key (CCK) 8G F X _ I N S _ VIDEO Graphics Wind ow inside Video Window . 0: Disable . The video window is assumed to be inside the graphics window . Outside the alpha window , graphics or video is displa yed, depending on the result of color k[...]

AMD Geode™ LX Processors Data Book 437 Video Processor Register Descriptions 33234H 6.8.3.20 Cursor Co lor Mask (CCM) 6.8.3.21 Cursor Color 1 (CC1) VP Memor y Offset 0A8h Ty p e R / W Reset V alue 000 00000_00000000h CCM Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 RSVD 3 1 3 0 2 9 [...]

438 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.22 Cursor Color 2 (CC2) 6.8.3.23 Alpha Window 1 X P osition (A1X) VP Memor y Offset 0B8h Ty p e R / W Reset V alue 000 00000_00000000h CC2 Regist er Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 RSVD 3 1[...]

AMD Geode™ LX Processors Data Book 439 Video Processor Register Descriptions 33234H 6.8.3.24 Alpha Window 1 Y P osition (A1Y) 6.8.3.25 Alph a Window 1 Color (A1C) VP Memor y Offset 0C8h Ty p e R / W Reset V alue 000 00000_00000000h A1Y Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 RS[...]

440 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.26 Alpha Wi ndow 1 Control (A1T) A1C Bit Descriptions Bit Name Description 63:25 RSVD (RO) Reserved (Read Only). Reads back as 0. 24 ALPHA1_ COLOR_REG_ EN Alpha Window 1 Color Register Enable. Enable bit for the color key matching in alpha window 1. 0: Disab[...]

AMD Geode™ LX Processors Data Book 441 Video Processor Register Descriptions 33234H 6.8.3.27 Alpha Window 2 X P osition (A2X) A1T Bit Descriptions Bit Name Description 63:19 RSVD (RO) Reserved (Read Only). Reads back as 0. 18 PP A1_EN P er-Pixel Al pha Windo w 1 Enable. Enable per-pix el alpha functio nality for alpha win- dow 1. 0: Single alpha [...]

442 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.28 Alpha Window 2 Y P osition (A2Y) 6.8.3.29 Alph a Window 2 Color (A C2) VP Memor y Offset 0E8h Ty p e R / W Reset V alue 000 00000_00000000h A2Y Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 R[...]

AMD Geode™ LX Processors Data Book 443 Video Processor Register Descriptions 33234H 6.8.3.30 Alpha Wi ndow 2 Control (A2T) A2C Bit Descriptions Bit Name Description 63:25 RSVD (RO) Reserved (Read Only). Reads back as 0. 24 ALPHA2_ COLOR_REG_ EN Alpha Window 2 Color Register Enable. Enable bit for the color key matching in alpha window 2. 0: Disab[...]

444 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.31 Alpha Window 3 X P osition (A3X) 16 ALPHA2_WIN_ EN Alpha Window 2 En able. Enable bit for alpha window 2. 0: Disable alpha window 2. 1: Enable alpha window 2. 15:8 ALPHA2_INC Alpha Windo w 2 Increment. Specifies the alpha va lue increment/decrement. This [...]

AMD Geode™ LX Processors Data Book 445 Video Processor Register Descriptions 33234H 6.8.3.32 Alpha Window 3 Y P osition (A3Y) 6.8.3.33 Alph a Window 3 Color (A3C) VP Memor y Offset 108h Ty p e R / W Reset V alue 000 00000_00000000h A3Y Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 RS[...]

446 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.34 Alpha Wi ndow 3 Control (A3T) A3C Bit Descriptions Bit Name Description 63:25 RSVD (RO) Reserved (Read Only). Reads back as 0. 24 ALPHA3_ COLOR_REG_ EN Alpha Window 3 Color Register Enable. Enable bit for the color key matching in alpha window 3. 0: Disab[...]

AMD Geode™ LX Processors Data Book 447 Video Processor Register Descriptions 33234H 6.8.3.35 Video Request (VRR) 16 ALPHA3_WIN_ EN Alpha Window 3 En able. Enable bit for alpha window 3. 0: Disable alpha window 3. 1: Enable alpha window 3. 15:8 ALPHA3_INC Alpha Windo w 3 Increment. Specifies the alpha va lue increment/decrement. This is a signed 8[...]

448 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.36 Alpha Watc h (A WT) Alpha values ma y b e automatically incr emented/decrem ented f or successiv e frames. T his register can be used to read alpha values that are being used in the current frame. 6.8.3.37 Video Processor T est Mode (VTM) VP Memor y Offse[...]

AMD Geode™ LX Processors Data Book 449 Video Processor Register Descriptions 33234H 6.8.3.38 Even Video Y P osition (VYE) 6.8.3.39 Even Alpha W indow 1 Y P osition (A1YE) VP Memor y Offset 138h Ty p e R / W Reset V alue 000 00000_00000000h VYE Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3[...]

450 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.40 Even Alpha W indow 2 Y P osition (A2YE) 6.8.3.41 Even Alpha W indow 3 Y P osition (A3YE) VP Memor y Offset 148h Ty p e R / W Reset V alue 000 00000_00000000h A2YE Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 3[...]

AMD Geode™ LX Processors Data Book 451 Video Processor Register Descriptions 33234H 6.8.3.42 Video Coefficient RAM (VCR) 6.8.3.43 Panel Timing Register 1 (PT1) VP Memor y Offset 1000h-1FFFh Ty p e R / W Reset V alue xxxxxxxx_xxxxxxxxh VCR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32[...]

452 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 29 FP_HSYNC_ POL FP_HSYNC Input P olarity . Selects p ositive or negativ e po larity of th e FP_HSYNC input. Program t his bit to match the polarity of the incoming FP_HSYNC signal. Note that FP Memor y Offset 408h[22] controls the polarity of the ou tput HSYNC . [...]

AMD Geode™ LX Processors Data Book 453 Video Processor Register Descriptions 33234H 6.8.3.44 Panel Timing Register 2 (PT2) VP Memor y Offset 408h Ty p e R / W Reset V alue 000 00000_00000000h PT2 Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 RSVD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2[...]

454 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.45 Po wer Management (PM) 19 MCS Colo r/Mono Select. Selects color or monochrome LCD panel. 0: Color . 1: Monochrome. 18:16 PIXF Pixe l Output Format . These bits define the pixel output f or mat. The selection of the pixel output f or mat deter mines how th[...]

AMD Geode™ LX Processors Data Book 455 Video Processor Register Descriptions 33234H 25 D Display Off Control Sour ce . Selects how DISPEN is controlled. Independent contro l ma y be used to disable the bac k light to sav e power e ven if the panel is otherwise ON. 0: DISPEN is controlled by with the pow e r up/down sequence. 1: DISPEN is controll[...]

456 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.46 Dither a nd Frame Rate Control (DFC) VP Memor y Offset 418h Ty p e R / W Reset V alue 000 00000_00000000h DFC Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 RSVD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 [...]

AMD Geode™ LX Processors Data Book 457 Video Processor Register Descriptions 33234H 6.8.3.47 Dither RA M Control and Address (DCA) 0D E N B Dithering Enable . Enable/disable dithering. The dither bit must be enabled in order for dither RAM reads or writes to occur . When this bit is cleared , the inter nal dither RAM is powered down, which sav es[...]

458 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 6.8.3.48 Dither Memor y Data (DMD) 6.8.3.49 Panel CRC Signature (CRC) VP Memor y Offset 450h Ty p e R / W Reset V alue 000 00000_00000000h DMD Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 RSVD 3 1 3 [...]

AMD Geode™ LX Processors Data Book 459 Video Processor Register Descriptions 33234H 6.8.3.50 32-Bit Panel CRC (CRC32) 6.8.3.51 Video Output Port Configuration (V OP_CONFIG ) VP Memor y Offset 468h Ty p e R O Reset V alue 000 00000_00000001h CRC32 Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 3[...]

460 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions 33234H 18 INV VS POL Invert VSYNC Polarity . Set to 1 to inv er t polar ity of VSYNC (for 6 01 mode only). 17 INV HS POL In ver t HSYNC Polarity . Set to 1 to inv er t polar ity of HSYNC (for 601 mode only). 16 UV SWAP UV Swap. 0: No sw ap. 1: Swap lo west byte with ne x[...]

AMD Geode™ LX Processors Data Book 461 Video Processor Register Descriptions 33234H 6.8.3.52 Video Output Po rt Signature (V OP_ SIG) 6 SC120X_MODE SC120X Compatible Mode . Creates EA V/SA V codes consistent with the AMD Geode™ SC1200 and SC1201 processor’ s VOP . 0: Nor mal mode. 1: SC1200/SC1201 compatible mode. Set to 1 f or BT .601 mode. [...]

462 AMD Geode™ LX Processors Data Book Video Input Port 33234H 6.9 Video Input P or t 6.9.1 Featu res • VESA 1.1, 2.0 and BT .601, BT .656 compliant, 150 MHz (e xcl udes host interf ace). — Standard 9 or 17 pin interf ace (8/16 data + clock) — 8/16-bit BT .656 video — T ASK A/B video and VBI (two video streams) — 8/16-bit ancilla ry dat[...]

AMD Geode™ LX Processors Data Book 463 Video Inpu t P or t 33234H 6.9.2 VIP Block Desc riptions Figure 6-39. VIP Block Diagra m 8/16 Address address F ormatter Generator Memor y Registers VIP Data VIP Clock VIP Clock Control GLIU Clock GLIU Clock Control VIPCLK GLIU_CLK Input Control QWORD = 64 bits take req reg write reg read Mapped GLIU Interfa[...]

464 AMD Geode™ LX Processors Data Book Video Input Port 33234H 6.9.2.1 Input Formatter The Input Formatter rece ives 8- or 16-bit VIP input data, It does a 4:2:2 to 4:2:0 translation (if enabled) and f or mats it into either linear data or planar data for storage in the Cap- ture RAM. 6.9.2.2 Input Contr ol The Input Control block operates in eit[...]

AMD Geode™ LX Processors Data Book 465 Video Inpu t P or t 33234H 6.9.3 Functi onal Descript ion The Video Input Po r t (VIP) receives 8- or 16-bit video or ancillar y data, 8-bit message data, or 8-bit raw video , and passes it to data buff ers lo cated in system memor y . The primar y operational mode is as a compliant VIP 2.0 slav e. The VIP 2[...]

466 AMD Geode™ LX Processors Data Book Video Input Port 33234H 6.9.5 Mode 1a,b,c - VI P Input Data (simplified BT .656) The VIP 2.0 specific ation descri bes an 8- or 16-bit data stream incor porating both con trol and data. The data/co n- trol is delivered in pack e ts. There are two diff erent packet types, SA V/EA V and ancil lar y pack ets. T[...]

AMD Geode™ LX Processors Data Book 467 Video Inpu t P or t 33234H VIP 2.0 Video Flags T wo new video flags are defined in the VIP 2.0 specification to decode whether the input video is interlaced or noninter- laced and whether the data i s merely a repeated field. These flags are meant to enable VIP to handle Bob and W eav e, as well as 3:2 pull [...]

468 AMD Geode™ LX Processors Data Book Video Input Port 33234H Figure 6-41. 525 line, 60 Hz D igital V er tical Timing Line 1 (V = 1) Line 20(V = 0) Line 264 (V = 1) Line 283 (V = 0) Line 525 (V = 0) Blanking Field 1 Active Video Blanking Field 2 Active Video Line 4 Line 266 Line 3 Field 1 (F = 0) Odd Field 2 (F = 1) Ev en H = 1 EA V H = 0 SA V L[...]

AMD Geode™ LX Processors Data Book 469 Video Inpu t P or t 33234H 6.9.5.2 Ancillary P ackets Ancillar y pack e ts are receiv ed during ver tical and/or hor i- zontal b l anking. The ancillar y pack e t has a 6-byte header of 00-FF-FF-DID-SDID-NN. T he first three bytes are the pre-amble . The DID and SDID bytes are the data identifier and the sec[...]

470 AMD Geode™ LX Processors Data Book Video Input Port 33234H 6.9.6 Messag e P assing Mod e The Message Passing mode (MSG) allows an e xter nal device to pass ra w d ata pack ets to the AMD Ge ode LX pro- cessor system memory (see Figure 6-43). In Message P assing mode, VID8 is redefined as a star t message indi- cation and VID9 is rede fined as[...]

AMD Geode™ LX Processors Data Book 471 Video Inpu t P or t 33234H 6.9.8 BT .601 Mode BT .601 mode all ows reception of 8- or 16-bit vi deo input which consists of HSYNC, VSYNC , and 8/16 bit data. V er ti- cal and hor izontal star t/stop registers provide th e informa- tion for data capture in each field/fr a me. The BT .656 SA V/ EA V codes (if [...]

472 AMD Geode™ LX Processors Data Book Video Input Port 33234H . Figure 6-46. BT .601 Mode Progr ammable Field Detectio n Figure 6-47. BT .601 Mode Horizontal Timing HSYNC VSYNC odd_field_detect_star t field_detect_duration A CTIVE LO W HSYNC/VSYNC (HSYNC Polarit y = 0 / VSYNC P olarity = 0) A CTIVE HIGH HSYNC/VSYNC (HSYNC P ola rity = 1 / VSYNC [...]

AMD Geode™ LX Processors Data Book 473 Video Inpu t P or t 33234H Figure 6-48. BT .601 Mode V ert ical Timing 6.9.9 YUV 4:2:2 to YUV 4:2:0 T ransl ation The VIP provides the option to translate incoming 4:2:2 co- sited video to YUV 4:2:0. The U and V values of e ven lines are simply discarded. No filter ing is performed. VIP stores the 4:2:0 data[...]

474 AMD Geode™ LX Processors Data Book Video Input Port 33234H Figure 6-49. YUV 4:2:2 to YUV 4:2:0 T ranslation 1 2 4 6 3 5 7 1 2 4 6 3 5 7 YUV 4:2:2 YUV 4:2:0 12 3 45 6 12 3 45 6 1 2 4 3 1 [1] [2] [3] 2 3 4 Y SAMPLE CB,CR SAMPLE YUV 4:2:2 YUV 4:2:0 12 3 45 6 12 3 45 6 [1] [2] [3] 12 3 45 6 1 2 4 3 1 [1] [2] [3] 2 3 4 YUV 4:2:2 YUV 4:2:0 12 3 45 [...]

AMD Geode™ LX Processors Data Book 475 Video Inpu t P or t 33234H 6.9.10 Soft ware Model The VIP receives data and st ores it into system memory . The VIP input modes with associated data types are shown in T able 6-74. VIP 2.0 is the VESA VIP 2.0 Lev el I (8-bit) standard or the VESA VIP 2.0 Le v el II (16-b it) standard. VIP 1.1 is the VESA (8-[...]

476 AMD Geode™ LX Processors Data Book Video Input Port 33234H 6.9.10.1 Video Data Buffers Video data buff ers can be organized in linear or plan ar f or- mats. Linear b uffers pack YUV v alues contiguous in mem- or y . Planar buff ers hav e separate subb uffers f or each set of YUV values in a field or frame . Th e VIP Control 1 register (VIP Me[...]

AMD Geode™ LX Processors Data Book 477 Video Inpu t P or t 33234H Figure 6-51 . E xample VIP YUV 4:2: 2 SA V/EA V P ackets Stored in Syst em Memory in a Linea r Buffer 0 1 2 3 vid_base (buff er star t) Cb Y Cr Y line 1 star t line 2 star t line 3 start * line is 00 fil led if not QWORD aligned Cb Y Cr Y Cb Y Cr Y Cb Y Cr Y Cb Y Cr Y 00* 00* 00* 0[...]

478 AMD Geode™ LX Processors Data Book Video Input Port 33234H Figure 6-52. Example VIP YUV 4:2:0 Pl anar Buffer (all base registers are 8-byte aligned) U Buff er V Buff er line #1 Y values Y pitch = task_A_vi d_pitch Y Buffer task_A_UV_pitch + U_buff er_ev en_o ffset +V_buff er_ev en_offset line #1 U values line #1 V values vid_base vid_base vid[...]

AMD Geode™ LX Processors Data Book 479 Video Inpu t P or t 33234H Figure 6-53. Example VIP 8/16- and 10-bit Ancillary Pac kets Stored in Syste m Memory 0 1 2 3 (8-byte aligned) 00 FF FF DID SDID NN=4 data data data data data data data data data data data data data data pack et 1 star t - buff er star t pack et 2 star t 00 FF FF DID SDID NN=6 data[...]

480 AMD Geode™ LX Processors Data Book Video Input Port 33234H 6.9.11 Bob and Wea ve Bob and Wea ve are two methods of outputting interlaced video , capture d by the VIP , in a progressive scan format. An example of this is when VIP receives 30 Hz interlaced (NTSC f or mat) and the data is to be display ed on a TFT panel that requires pro gressiv[...]

AMD Geode™ LX Processors Data Book 481 Video Inpu t P or t 33234H V er tical Timing Error (Frame or Address Err or) /Me s- sage Missed Error - This error indicate s a frame error or an address error . A frame error occurs when the time between VSYNCs exceeds the window defined b y the VIP_SYNC_ERR_COUNT regist er (VIP Memor y Offset 78h). The VIP[...]

482 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10 Video Input P or t Register Descriptions The registers associated with the VIP are the Standard GeodeLink Device (GLD) MSRs (accessed via the RDMSR and WRMSR instr uctions) and VIP Co nfiguration/Control Register s. T ab le 6-75 and T ab le 6-76 a re registe[...]

AMD Geode™ LX Processors Data Book 483 Video Input Port Register Descriptions 33234H 44h R/W VIP T ask B VBI Odd Base/VBI Start (VIP_T ASK_B_VBI_ODD_BASE_VBI_ST ART) 00000000h Page 502 48h R/W V IP T ask B Data Pitch/V er tical Star t Even (VIP_T ASK_B_D A T A_PITCH_VERT_ST AR T_EVEN) 00000000h Page 502 4Ch -- Reserved -- -- 50h R/W VIP T ask B V[...]

484 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.1 Standar d GeodeLink™ Device (GLD) MSRs 6.10.1.1 GLD Capabilities MSR (GLD_MSR_CAP) 6.10.1.2 GLD Configuratio n MSR (GLD_MSR_CONFIG) MSR Address 54002000h Ty p e R O Reset V alue 000 00000_ 0003C4xxh GLD_MSR_CAP Register Map 63 62 61 60 59 58 57 56 5 5 54[...]

AMD Geode™ LX Processors Data Book 485 Video Input Port Register Descriptions 33234H 6.10.1.3 GLD SMI MSR (GLD_MSR_SMI) MSR Address 54002002h Ty p e R / W Reset V alue 000000 000_ xxxx7FFFh GLD_MSR_SMI Register Map 63 62 61 60 59 58 57 56 5 5 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 3 5 34 33 32 RSVD 31 30 29 28 27 26 25 24 2 3 22[...]

486 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.1.4 GLD Error MSR (GLD_MSR_ERROR) MSR Address 54002003h Ty p e R / W Reset V alue 000 000000_ 00000000h GLD_MSR_ERROR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 RSVD 3 1 3 0 2 9 2 8 2 7 2 6 2[...]

AMD Geode™ LX Processors Data Book 487 Video Input Port Register Descriptions 33234H 6.10.1.5 GLD Po wer Ma nagement Register (GLD_MSR_PM) 6.10.1.6 GLD Diagnostic MSR (GLD_MSR_DIA G) This register is reser ved for intern al use by AMD and should not be written to . MSR Address 54002004h Ty p e R / W Reset V alue 000 000000_ 00000005h GLD_MSR_PM R[...]

488 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.2 VIP Contr o l/Configuration Register s 6.10.2.1 VIP Control Regi ster 1 (VIP_CTL_REG1) VIP Memory Offset 00h Ty p e R / W Reset V alue 420 00001h VIP_CTL_REG1 Register Map 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 [...]

AMD Geode™ LX Processors Data Book 489 Video Input Port Register Descriptions 33234H 19 NI No n-Interlaced Vide o Input. This bit deter mines if the star t/end-of-frame ev ent occurs each field (for non-interlace d video) or at the end of the odd field (for interlaced video). The star t/end-of-frame i ndication is used as the star t/end-of-frame [...]

490 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.2.2 VIP Control Regi ster 2 (VIP_CTL_REG2) 3:1 VIP_MODE VIP Operating Mode . 000: IDLE. This mode forces VID[ 15:0] to 0 from pads to VIP . 001: VIP 2.0 8-bit mode. 010: VIP 2.0 16-bit. 011: VIP 1.1 8-bit. 100: Message P a ssing. 101: Data Streaming. 110: 60[...]

AMD Geode™ LX Processors Data Book 491 Video Input Port Register Descriptions 33234H 26 ANCPEN Ancillary P arity Check Enab le. Wh en set to 1, ancillar y DID , SDID , NN, and check sum bytes are chec ked for e ven parity . The error is repor ted on MSR 4002002h[23]. When this bit is 0, the Ancillar y Checksum or P arity Error bit only indicates [...]

492 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.2.3 VIP Status (VIP_ST A TUS) VIP Memory Offset 08h Ty p e R / W Reset V alue xxxxxxxxh VIP_ST A TUS Register Map 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 APC RSVD FPE RSVD DPC SO BRNU RSVD MSG_BERR B[...]

AMD Geode™ LX Processors Data Book 493 Video Input Port Register Descriptions 33234H 14 MSG_BERR Message Buffer Error . 0: No error . 1: Message buff er was ov erwri tten. This occurs when both msg buff ers are full and a msg/dstrm packet is receiv ed. Writing a 1 to the bit resets it to 0. 13 B2_FULL MSG Buffer 2 Full. 0: Buff er 2 empty . 1: Bu[...]

494 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.2.4 VIP Interrupt (VIP_INT) VIP Memory Offset 0Ch Ty p e R / W Reset V alue xxxxFFFEh VIP_INT Register Map 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 INT_ST A TUS INT_MASK VIP_INT Bit Descriptions Bit N[...]

AMD Geode™ LX Processors Data Book 495 Video Input Port Register Descriptions 33234H 6.10.2.5 VIP Current/T arget (VIP_CUR_T AR) 6.10.2.6 VIP Max Address (VIP_MAX_ADDR) VIP Memory Offset 10h Ty p e R / W Reset V alue 000 00000h VIP_CUR_T AR Register Map 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654[...]

496 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.2.7 VIP T ask A Video Even Base Address (VIP_T ASK_A_VID_EVEN_BASE) 6.10.2.8 VIP T ask A Video Odd Base Address (VIP_T ASK_A _VID_ODD_BASE) VIP Memory Offset 18h Ty p e R / W Reset V alue 000 00000h VIP_T ASK_A_VID_EVEN_BASE Register Map 3 1 3 0 2 9 2 8 2 7 [...]

AMD Geode™ LX Processors Data Book 497 Video Input Port Register Descriptions 33234H 6.10.2.9 VIP T ask A VBI Even Base Address (VIP_T ASK_A_VBI_EVEN_BASE) 6.10.2.10 VIP T ask A VBI Odd Base Address (VIP_T ASK_A_VBI_ODD_BASE) VIP Memory Offset 20h Ty p e R / W Reset V alue 000 00000h VIP_T ASK_A_VBI_EVEN_BASE Register Map 31 30 29 28 27 26 25 24 [...]

498 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.2.11 VIP T ask A Video Pi tch (VIP_T A SK_A_VID_PITCH) 6.10.2.12 VIP Contro l Register 3 (VIP_CONTRL_REG3) VIP Memory Offset 28h Ty p e R / W Reset V alue 000 00000h VIP_T ASK_A_VID_PITCH Register Map 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1[...]

AMD Geode™ LX Processors Data Book 499 Video Input Port Register Descriptions 33234H 6.10.2.13 VIP T ask A V Offset (VIP_T ASK_A_V_OFFSET) 7E F D Even Field UV Decimation. When set to 1, the U and V values of the e ven frame will be discarded. Note: The DD bit (VIP Memor y Offset 00h[16]) should be set to 1 or e ven lines will also be decimated. [...]

500 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.2.14 VIP T ask A U Offset (VIP_T ASK_A_U_OFFSET) 6.10.2.15 VIP T ask B Video Even Base/Horizon tal End (VIP_T ASK_B_VI D_EVEN_BASE_HORIZ_END) VIP Memory Offset 34h Ty p e R / W Reset V alue 000 00000h VIP_T ASK_A _U_OFFS ET Register Map 3 1 3 0 2 9 2 8 2 7 2[...]

AMD Geode™ LX Processors Data Book 501 Video Input Port Register Descriptions 33234H 6.10.2.16 VIP T ask B Video Odd Base/Horizontal Star t (VIP_T ASK_B_VID_ ODD_BASE_HORIZ_ST ART) 6.10.2.17 VIP T ask B VBI Even Base/VBI End (VIP_T ASK_B_VBI_EVEN_B ASE_VBI_END) VIP Memory Offset 3Ch Ty p e R / W Reset V alue 000 00000h VIP_T ASK_B_VID_ODD_BASE_HO[...]

502 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.2.18 VIP T ask B VBI Odd Base/VBI St ar t (VIP_T ASK_B_VBI_ODD_BASE_VBI_ST ART) 6.10.2.19 VIP T ask B Data Pitch/V er tical Start Even (VIP_T ASK_B_D A T A_PITCH_VER T_ST ART_EVEN) 11:0 VBI_END VBI End. This registe r is redefined in BT .6 01 mode. In BT .60[...]

AMD Geode™ LX Processors Data Book 503 Video Input Port Register Descriptions 33234H 6.10.2.20 VIP T ask B V Offset (VIP_T ASK_B_V_Offset) 27:16 VER TICAL_ END_EVEN (e ven/second field) V er tical End Even. This register is redefined in BT .601 mode. In BT .601 type input modes timing is derived from the e xter nal HSYNC and VSYNC inputs. This va[...]

504 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.2.21 VIP T ask B U Offset (VIP_ T ASK_B_U_OFFSET ) 6.10.2.22 VIP Ancillar y Data/Message Passing/Data Streaming Buffer1 Base Address (VIP_ANC_MSG_1_BASE) VIP Memory Offset 54h Ty p e R / W Reset V alue 000 00000h VIP_T ASK_B _U_OFFS ET Register Map 3 1 3 0 2[...]

AMD Geode™ LX Processors Data Book 505 Video Input Port Register Descriptions 33234H 6.10.2.23 VIP Ancill ary Data/Message Passing/Data Streaming Buffer 2 Base Address (VIP_AN C_MSG_2_BASE) 6.10.2.24 VIP Ancill ary Data/Message Passing/Data Streaming Buffer Size (VIP_ANC _MSG_SIZE) VIP Memory Offset 5Ch Ty p e R / W Reset V alue 000 00000h VIP_AN[...]

506 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.2.25 VIP P age Offset/ P age Count (VIP_P AGE_OFFSET ) 6.10.2.26 VIP V er tical Start/ Stop (VIP_VER T_ST ART_ST OP ) VIP Memory Offset 68h Ty p e R / W Reset V alue 000 00000h VIP_P AGE_OFFSET Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 [...]

AMD Geode™ LX Processors Data Book 507 Video Input Port Register Descriptions 33234H 6.10.2.27 VIP FIFO Address (VIP_FIFO_R_W_ADDR) 6.10.2.28 VIP FIFO Da ta (VIP_FIFO_D A T A) VIP Memory Offset 70h Ty p e R / W Reset V alue 000 00000h VIP_FIFO_R_W_ADDR Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 [...]

508 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H 6.10.2.29 VIP VSYNC Error Co unt (VIP_SYNC_ERR_COUNT) 6.10.2.30 VIP T ask A U Ev en Off set (VIP_T ASK_A_U_EVEN _OFFSET) VIP Memory Offset 78h Ty p e R / W Reset V alue 000 00000h VIP_SYNC_ERR_COUNT Register Map 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9[...]

AMD Geode™ LX Processors Data Book 509 Video Input Port Register Descriptions 33234H 6.10.2.31 VIP T ask A V Even Offs et (VIP_T ASK_A_V_EVEN_OFFSET) VIP Memory Offset 80h Ty p e R / W Reset V alue 000 00000h VIP_T ASK_A_V_EVEN_OFFSET Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T ASK_A_V_EVEN[...]

510 AMD Geode™ LX Processors Data Book Security Block 33234H 6.11 Security Block The Secur ity Block provides a hardware Advanced Encr yp- tion Standard (AES) encr yption/decr yption engine and interf ace for accessing EEPR OM memor y for storing unique IDs and/or security keys. The AES and EEPR OM sections hav e separate co ntro l registers but [...]

AMD Geode™ LX Processors Data Book 511 Security Block 33234H 6.11.2 Functiona l Description The AES engine provides ECB a nd CBC 128-bit hardware encr yption and decr yption for the AMD Geode LX proces- sor using the Advanced Encrypti on Standard algor ithm. The Security Block has two ke y sources. One is a hidden 128-bit ke y stored in non-volat[...]

512 AMD Geode™ LX Processors Data Book Security Block 33234H 6.11.2.1 EEPROM ID Interface The EEPROM ID interf ace provides an interf ace to an EEPROM non-v olatile memor y av ailable f or storing ID numbers, k eys, or other securi ty related inform ation. The EEPROM ID interf ace consists of a 2K (256-byte) arr ay with 2 bytes reserved f or EEPR[...]

AMD Geode™ LX Processors Data Book 513 Security Block Register Descriptions 33234H 6.12 Security Bloc k Register Descriptions This section provides information on the regi sters associ- ated with the Secur ity Block (SB), including the Standard GeodeLink Device (GLD) MSRs, the Security Block Spe- cific MSRs (accessed via the RDMSR and WRMSR i ns [...]

514 AMD Geode™ LX Processors Data Book Security Block Register Descriptions 33234H 048h R/W SB CBC Initializa tion V ector 2 (SB_CBC_IV _2) 00000000h Page 528 04Ch R/W SB CBC Initiali zation V ector 3 (SB_CBC_IV _3) 00000000h Page 528 050h RO SB Random Number (SB_RANDOM_ N UM) 00000000h Page 529 054h RO SB Random Number Statu s (SB_RANDOM_NUM_ST [...]

AMD Geode™ LX Processors Data Book 515 Security Block Register Descriptions 33234H 6.12.1 Standar d GeodeLink™ (GLD) Device MSRs 6.12.1.1 GLD Capabilities MSR (GLD_MSR_CAP) 6.12.1.2 GLD Master Configur ation MSR (GLD_MSR_CONFIG) MSR Address 58002000h Ty p e R O Reset V alue 000 00000_001304xxh GLD_MSR_CAP Register Map 63 62 61 60 59 58 57 56 55[...]

516 AMD Geode™ LX Processors Data Book Security Block Register Descriptions 33234H 6.12.1.3 GLD SMI MSR (GLD_MSR_SMI) 6.12.1.4 GLD Error MSR (GLD_MSR_ERROR) MSR Address 58002002h Ty p e R / W Reset V alue 000 00000_00000007h GLD_MSR_SMI Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RS[...]

AMD Geode™ LX Processors Data Book 517 Security Block Register Descriptions 33234H GLD_MSR_ERROR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD RB_ERR_ST A TUS RA_ERR_ST A TUS RSVD AES_ERR_ST A TUS 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1[...]

518 AMD Geode™ LX Processors Data Book Security Block Register Descriptions 33234H 6.12.1.5 GLD Po wer Ma nagement MSR (GLD_MSR_PM) 6.12.1.6 GLD Diagnostic MSR (GLD_MSR_DIA G) This register is reser ved for intern al use by AMD and should not be written to . MSR Address 58002004h Ty p e R / W Reset V alue 000 00000_00000015h GLD_MSR_PM Register M[...]

AMD Geode™ LX Processors Data Book 519 Security Block Register Descriptions 33234H 6.12.2 Security Block Specific MSRs 6.12.2.1 GLD Control MSR (GLD_MSR_CTRL) MSR Address 58002006h Ty p e R / W Reset V alue 000 00000_00000003h GLD_MSR_CTRL Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32[...]

520 AMD Geode™ LX Processors Data Book Security Block Register Descriptions 33234H 6.12.3 Securit y Block Config uration/Contr ol Registers 6.12.3.1 SB Control A (SB_CTL_A) 2 SBI Swap Bits. This bit con trols a bit-sw appi ng f eature within the AES module. When set, the bits within each byte are s wapped on both AES DMA reads and wr ites. Bit 7 [...]

AMD Geode™ LX Processors Data Book 521 Security Block Register Descriptions 33234H 6.12.3.2 SB Control B (SB_CTL_B) 0S T A Start for A P ointer . When set, this bit commands t he AES to start a new operation based on the current control re gister setting and the settin gs in SB Memor y Offset 010h and 014h. This b it is reset automatically wh en [...]

522 AMD Geode™ LX Processors Data Book Security Block Register Descriptions 33234H 6.12.3.3 SB AES Interrupt (SB_AES_INT) 6.12.3.4 SB Source A (SB_SOURCE_A) SB Memor y Offset 008h Ty p e R / W Reset V alue 000 00007h SB_AES_INT Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD INT_ST A TUS RSV[...]

AMD Geode™ LX Processors Data Book 523 Security Block Register Descriptions 33234H 6.12.3.5 SB Destination A (SB_DEST_ A) 6.12.3.6 SB Length A (SB_LENGTH_A) SB Memor y Offset 014h Ty p e R / W Reset V alue 000 00000h SB_DEST_A Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Destination A R SVD SB[...]

524 AMD Geode™ LX Processors Data Book Security Block Register Descriptions 33234H 6.12.3.7 SB Source B (SB_SOURCE_B) 6.12.3.8 SB Destination B (SB_DEST_ B) SB Memor y Offset 020h Ty p e R / W Reset V alue 000 00000h SB_SOURCE_B Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOURCE_B RSVD SB_SOU[...]

AMD Geode™ LX Processors Data Book 525 Security Block Register Descriptions 33234H 6.12.3.9 SB Length B (SB_LENGTH_B) 6.12.3.10 SB Writable Ke y 0 (SB_WKEY_0) SB Memor y Offset 028h Ty p e R / W Reset V alue 000 00000h SB_LENGTH_B Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LENGTH_B RSVD SB_L[...]

526 AMD Geode™ LX Processors Data Book Security Block Register Descriptions 33234H 6.12.3.11 SB Writable Ke y 1 (SB_WKEY_1) 6.12.3.12 SB Writable Ke y 2 (SB_WKEY_2) SB Memor y Offset 034h Ty p e W O Reset V alue 000 00000h SB_WKEY_1 Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WKEY_1[63:32] SB[...]

AMD Geode™ LX Processors Data Book 527 Security Block Register Descriptions 33234H 6.12.3.13 SB Writable Ke y 3 (SB_WKEY_3) 6.12.3.14 SB CBC Initializatio n V ector 0 (SB_CBC_IV_0) SB Memor y Offset 03Ch Ty p e W O Reset V alue 000 00000h SB_WKEY_3 Regi ster Map 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1[...]

528 AMD Geode™ LX Processors Data Book Security Block Register Descriptions 33234H 6.12.3.15 SB CBC Initializatio n V ector 1 (SB_CBC_IV_1) 6.12.3.16 SB CBC Initializatio n V ector 2 (SB_CBC_IV_2) 6.12.3.17 SB CBC Initializatio n V ector 3 (SB_CBC_IV_3) SB Memor y Offset 044h Ty p e R / W Reset V alue 000 00000h SB_CBC_IV_1 Registe r Map 31 30 29[...]

AMD Geode™ LX Processors Data Book 529 Security Block Register Descriptions 33234H 6.12.3.18 SB Random Number (SB_RANDOM_NUM) 6.12.3.19 SB Random Number Status (SB_RANDOM_NUM_ST A TUS) SB Memor y Offset 050h Ty p e R O Reset V alue 000 00000h SB_RANDOM_NUM Register Map 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 [...]

530 AMD Geode™ LX Processors Data Book Security Block Register Descriptions 33234H 6.12.3.20 SB EEPROM Co mmand (SB_EE PROM_COMM) SB Memor y Offset 800h Ty p e R / W Reset V alue 000 00000h SB_EEPROM_COMM Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD RSVD HKD SL KV EX WR ST SB_EEPROM_COMM [...]

AMD Geode™ LX Processors Data Book 531 Security Block Register Descriptions 33234H 6.12.3.21 SB EEPROM A ddress (SB_EEPROM _ ADDR) 6.12.3.22 SB EEPROM Data (SB_EEPROM_D A T A) This register co ntains the Data bits for writing to or reading from the EEPR OM. SB Memor y Offset 804h Ty p e R / W Reset V alue 000 000FFh SB_EEPROM_ADDR Register Map 31[...]

532 AMD Geode™ LX Processors Data Book Security Block Register Descriptions 33234H 6.12.3.23 SB EEPROM Security State (SB_EEPROM_SEC_ST A TE) This read only register contains th e curr ent state of the access control bits for controlling reads and wr ites from/to the EEPROM. It is reloaded from the EEPR OM arra y after e very reset. The initial s[...]

AMD Geode™ LX Processors Data Book 533 GeodeLink™ Con trol Pr oc essor 33234H 6.13 GeodeLink™ Contr ol Pr ocessor The GeodeLink Contro l Processor (GLCP) functionality cov ers these areas (see Fi gure 6-55): • Scan chain control • JT AG interf ace to boundar y scan, BIST , GLIU1, and debug logic • P ower (cloc k) control • Reset logic[...]

534 AMD Geode™ LX Processors Data Book GeodeLink™ Con trol Pr oc essor 33234H T able 6-81. T AP Contr ol Instructio ns (25-Bit IR) Instruction DR Length IR Name Description 123FFF Ah 8 BYP ASS_MODES This register is read/write. 127FFF Ah 8 REVID Should be 10h for initial AMD Geode™ LX processor (upper nibble is major re v , low er nibble is m[...]

AMD Geode™ LX Processors Data Book 535 GeodeLink™ Con trol Pr oc essor 33234H EXTEST JT A G Instruction The EXTEST instructi on a ccesses the boundary scan chain around the chip and controls the pin logic such that the boundar y scan data control s the data and enable sig- nals for the pins. IEEE 1149.1 requires that an all-zero instruction acc[...]

536 AMD Geode™ LX Processors Data Book GeodeLink™ Con trol Pr oc essor 33234H Figure 6-56. Processor Cloc k Generation 6.13.4 Compan ion Device Interfac e The AMD Geod e companion device interf ace for I/O con- nections (GIO) provides the system interf ace between the AMD Geode CS55 36 companion device and the AMD Geode LX processor . The GIO s[...]

AMD Geode™ LX Processors Data Book 537 GeodeLink™ Con trol Pr oc essor 33234H Figure 6-57. GIO Interface Bloc k Diagram GIO_GLIU GIO_SYNC GIO_PCI GIO_A20M GIO_NMI GIO_SUSP GIO_IN IT GIO_INPUT _DIS GIO_OUTPUT_DIS GIO_INTR GLCP_SUSP A RQ13 SUSP A# GLIU Slav e I/F IGNNE# FERR IRQ13_GL SMI_GL LGCY_G L GL Clock PCI_RA W_CLK CLK Control SUSP# / CIS T[...]

538 AMD Geode™ LX Processors Data Book GeodeLink™ Con trol Pr oc essor 33234H GIO_PCI Serial Pr otocol The GIO can override the func tionality of its SUSP# pin to create a serial bus called CPU Interface Serial (CIS). The reset mode for this pin is the SUSP# function. T o proper ly operate as the CIS interface , the CISM bit in MSR 51000010h[4:[...]

AMD Geode™ LX Processors Data Book 539 GeodeLink™ Control Processor Register Descriptions 33234H 6.14 GeodeLink™ Contr ol Pr ocessor Register Descriptions All GeodeLink Control Processor registers are Model Spe- c if i c R e g i st e r s ( M S Rs ) and are ac c es s e d v i a th e R D M S R and WRMSR instr uctions. The registers associated wi[...]

540 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H 4C000015h R/W GLC P Dot Clock PLL Control (GLCP_DO TPLL) 000000D7_02000000 h Page 557 4C000016h R/W GLC P Debug Cloc k Control (GLCP_DBGCLKCTL) 00000000_000000 02h P age 559 4C000017h RO Chip Re visio n ID (GLCP_CHIP_REVID) 00000000_000000xxh Page 5[...]

AMD Geode™ LX Processors Data Book 541 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.1 Standar d GeodeLink™ Device MSRs 6.14.1.1 GLD Capabilities MSR (GLD_MSR_CAP) 6.14.1.2 GLD Master Configur ation MSR (GLD_MSR_CONFIG) MSR Address 4C002000h Ty p e R O Reset V alue 000 00000_00002400h GLD_MSR_CAP Register Map 63 62 61 60 59 5[...]

542 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H 6.14.1.3 GLD SMI MSR (GLD_MSR_SMI) MSR Address 4C002002h Ty p e R / W Reset V alue 000 00000_0000001Fh GLD_MSR_SMI Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 RSVD 3 1 3 0 2 9 2 8 2 7[...]

AMD Geode™ LX Processors Data Book 543 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.1.4 GLD Error MSR (GLD_MSR_ERROR) MSR Address 4C002003h Ty p e R / W Reset V alue 000 00000_00000000h GLD_MSR_ERROR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 RSVD ERR_SYSPLL ER[...]

544 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H 6.14.1.5 GLD Po wer Ma nagement MSR (GLD_MSR_PM) The debug logic powers up selecting GLIU1 for its cloc k. Deb ug cl ock select is in GLCP_DBGCLKCTL (MSR 4C000016h[2:0]). 6.14.1.6 GLD Diagnostic MSR (GLD_MSR_DIA G) This register is reser ved for int[...]

AMD Geode™ LX Processors Data Book 545 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2 GLCP Specif ic MSRs - GLC P Control MSRs 6.14.2.1 GLCP Clock Disable Dela y V alue (GLCP_CLK_DIS_DELA Y) 6.14.2.2 GLCP Clock Mask for Sl eep Request (GLCP_PMCLKDISABLE) MSR Address 4C000008h Ty p e R / W Reset V alue 000 00000_00000000h GLCP_[...]

546 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H 28 GLCPDBG GLCP Debug Clock Off. When set, disables GLCP DBG logic clock. 27 GLCPGLIU GLCP GLIU Clock Off. When set, disables GLCP GLIU clock. 26 GLCPPCI GLCP GIO PCI Cl ock Off. When set, disab les GLCP’ s GIO PCI clock. 25 VPV OP VP V OP Clock O[...]

AMD Geode™ LX Processors Data Book 547 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.3 Chip Fabrication Inf o rmation (GLCP_F AB) This read only register i s used to track v ar ious fab , process, and product family parameters. It is meant f or AMD inter nal use only . Reads return reset value . 6.14.2.4 GLCP Global Po wer Ma[...]

548 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.5 GLCP Debug Output fr om Chip (GLCP_DBGOUT) This register is reser ved for intern al use by AMD and should not be written to . 6.14.2.6 GLCP Processor Status (GLCP_PROCST A T) Note that the names o f these bits hav e the read stat us data be[...]

AMD Geode™ LX Processors Data Book 549 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.7 GLCP DO WSER (GLCP_DOWSER) 6.14.2.8 GLCP I/O Delay Controls (GLCP_DELA Y_CONTROLS ) MSR Address 4C00000Eh Ty p e R / W Reset V alue 000 00000_00000000h GLCP_DO WSER Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43[...]

550 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H 59 SDCLK_SET SDCLK Setup . 0: Full SDCLK set up . 1: Half SDCLK setup for control signals. 58:56 DDR_RLE DDR read latch enable position. 55 SDCLK_DIS SDCLK disa ble [1,3,5]. 0: All SDCLK output. 1: SDCLK[4,2,0] output only . 54:52 TLA1_OA TL A hint [...]

AMD Geode™ LX Processors Data Book 551 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.9 GLCP Clock Control (GLCP_ CLK OFF) This register has bits that, when set, force clocks off usin g GeodeLink™ Clock Control (GLCC) logic in the system. This is f or debugging only , and should not be used for po wer manag ement. MSR Addres[...]

552 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.10 GLCP Clock Ac tive (GLCP_CLKA CTIVE) See "GLCP_CLK OFF Bi t Descripti ons" on page 55 1 fo r bit description s. 11 DCDO T_ 0 DC Dot Clock Off. When set, disables DC Dot Clock 0 (DC). 10 GLIU0_1 GL IU0Clock Off. When set, disables[...]

AMD Geode™ LX Processors Data Book 553 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.11 GLCP Clock Mask f or Debug Cloc k Stop Action (GLCP_CLKDISABLE) See "GLCP_CLK OFF Bi t Descripti ons" on page 55 1 fo r bit description s. 6.14.2.12 GLCP Clock Active Mask f or Suspend Acknowledge (GLCP_CLK4A CK) See "GLCP_C[...]

554 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.13 GLCP System Reset an d PLL Control (GLCP_SYS_RSTPLL) This register is initiali zed during POR, bu t otherwise is not itself reset by any “sof t-reset” f eatures. Note that writing this reg- ister alwa ys has immediate effect, so read-m[...]

AMD Geode™ LX Processors Data Book 555 GeodeLink™ Control Processor Register Descriptions 33234H 23:16 HOLD_COUNT Hold Count. The number of PLL ref erence clock cycl es (divided by 16 ) that the PLL is powered down for , and also the nu mber bef ore releasing CHIP_RESET . 0: W ait 0 cycles. (Default) 1: W ait 16 clock cycles, etc. 15 RSVD Reser[...]

556 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H The PW1 pin (66 MHz PCI) is wired directly to the COREDI V and GL DIV signals dur ing rese t. The IRQ13 pin (stall after reset) has no effect on the PLL controls but is still st ored in the BOOTSTRAP bits (MSR 4C000018h[7:1]). T able 6-87 shows e xa[...]

AMD Geode™ LX Processors Data Book 557 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.14 GLCP Dot Cloc k PLL Co ntrol (GLCP_DO TPLL) This register does not include hardware hand shake controls lik e the GLCP_SYS_RSTPLL register (MSR 4C0 00014h), so care should be taken when changing the settings. For e xample, to chang e the D[...]

558 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H GLCP_DO TPLL Bit Descriptions Bit Name Description 63:49 RSVD Res erved. Wr ite as read. 48 DIV4 Divide by 4. When set, the PLL output is divided b y 4 before cloc king the logic. Thi s bit is intended for gener a ting frequencies below the PLL spec[...]

AMD Geode™ LX Processors Data Book 559 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.15 GLCP Debug Cloc k Control (GLCP_DBGCLKCTL) Note that after the mux to select the clock, a standard cloc k control gate e xists. This regi ster should nev e r be changed from one non-zero value to another . Always write this registe r to 0 [...]

560 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.17 GLCP Control (GLCP_CNT) This register is used in conju nction wit h GLIU1 P ower Management. I/O writes, which include the lowest byte of this regis- ter , may trigger an SMI if GLD_MSR_SMI (MSR 4C002002h ) is configured appropri ately . M[...]

AMD Geode™ LX Processors Data Book 561 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.19 GLCP Thro ttle or C2 Start Delay (GLCP_TH_ SD) 6.14.2.20 GLCP Scale Factor (GLCP_TH_SF) MSR Address 4C00001Ch T ype R/W - I/O Offs et 10h Reset V alue 000 00000_00000000h GLCP_TH_ SD Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 4[...]

562 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H 6.14.2.21 GLCP Proc essor Thr o ttle Off Delay (GLCP_TH_OD) 6.14.3 GLCP IG NNE I/Os The GLCP’ s GLIU is re sponsible f o r all the GLIU functional it y . The GLCP’ s GL IU implements a large MSR space consisting of the required standard GLIU dev[...]

AMD Geode™ LX Processors Data Book 563 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.4 GLCP Specific MSRs - GLCP Debug Interface MSRs 6.14.4.1 GLCP DA C (GLCP_D A C) This register has D AC diagnostic controls and status. It ties directly to inputs and outputs on the D AC module. Bits [13:11] of this re gister are only v alid af[...]

564 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions 33234H 6.14.5 GLCP Specif ic MSRs - GLC P Companion Device Interf ace MSRs 6.14.5.1 CPU A20M Signal (MSR_A20M) 6.14.5.2 CPU INIT Signal (MSR_INIT) MSR Address 4C000031h Ty p e R / W Reset V alue 000 00000_00000000h MSR_A20M Register Map 63 62 61 60 59 58 5[...]

AMD Geode™ LX Processors Data Book 565 GeodeLink™ Control Processor Register Descriptions 33234H 6.14.5.3 GLIU Device Inte rrupt Status (MSR_INT AX) This is a read only MSR with the status of interr upt signals fr om the various bloc ks. This register is intended for deb ug pur- poses. F or fu nctional interr upt handler s, t he bloc k-specific[...]

566 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge 33234H 6.15 GeodeLink™ PCI Bridge The GeodeLink™ PCI Br idge (GLPCI) module provides a PCI interface f or GeodeLink Interface Unit-based designs. The GLPCI module is composed of five major blocks: • GeodeLink Interface • FIFO/Synchronization • T ransaction Forw arding • PC[...]

AMD Geode™ LX Processors Data Book 567 GeodeLink™ PCI Brid ge 33234H 6.15.1 GeodeLink™ Interface Bloc k The Geod eLink Inte rface b lock pro vides a thin p rotocol conv ersi on la yer between the T ransaction Forw arding bloc k and GeodeLink Interface Unit 1 (GLIU1). It is responsible f or multiple xing in-bound w rite request data with out-b[...]

568 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge 33234H Figure 6-59. Atomic MSR Accesses Acr oss the PCI Bus GLIU1 De vice-A Device-B De vice-C PCI-de vice = 1 PCI-de vice = 15 PCI-de vi ce = 25 PCI-device = 30 2 4 3 6 5 1 2 7 3 AMD Geode™ LX Pr ocessor 2.4.1. 3.6.x 2.4.2.5.1.x 2.4.3.2.7.3 GLPCI_EXT (MSR 5000201Eh) config uration:[...]

AMD Geode™ LX Processors Data Book 569 GeodeLink™ PCI Brid ge 33234H 6.15.4 PCI Bus Interface B lock The PCI Bus Interface block is compliant to the PCI 2.2 specification, except in t he handling of SERR#/PERR# sig- nals. These signals are not available . The PCI Bus Interface bloc k provides a protocol conversion lay er between the T ransactio[...]

570 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge 33234H 6.15.5 PCI Arbite r The PCI arbiter implements a fa ir arbitration scheme with special suppor t for the companion device. By de f ault it operates as a simple round-robin arbiter that rotates p rior- ity in circular fashion (see Figure 6-60). There are three ex ter nal REQ#/GNT[...]

AMD Geode™ LX Processors Data Book 571 GeodeLink™ PCI Brid ge 33234H 6.15.6 Exception Handling 6.15.6.1 Out-Bound Write Exceptions When performing an out-bound wr ite on the PCI bus, two errors may occur: target abor t and PERR# asser tion. When a target abor t occurs, the PCI Bus Interface b lock must flush any stored write data. It must then [...]

572 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 6.16 GeodeLink™ PCI Bridge Register Descriptions All GeodeLink™ PCI Br idge (G LPCI) registers are Model Specific Registers (MSRs) and are accessed via the RDMSR and WRMSR instru ctions. The registers associated w ith the GLPCI are the Standard GeodeL[...]

AMD Geode™ LX Processors Data Book 573 GeodeLink™ PCI Bridg e Register Descriptions 33234H 5000201Dh R/W GLPCI Memor y Regio n 5 Configuration (GLPCI_R5) 00000000_00000000h Page 593 5000201Eh R/W G LPCI External MSR Access Con figuration (GLPCI EXT_MSR) 00000000_00000000h Page 594 5000201Fh R/W GLPCI Spare 00000000_00000000h Page 595 50002020h [...]

574 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 6.16.1 Standar d GeodeLink™ Device (GLD) MSRs 6.16.1.1 GLD Capabilities MSR (GLD_MSR_CAP) 6.16.1.2 GLD Master Configur ation MSR (GLD_MSR_CONFIG) MSR Address 50002000h Ty p e R O Reset V alue 000 00000_001054xxh GLD_MSR_CAP Register Map 63 62 61 60 59 5[...]

AMD Geode™ LX Processors Data Book 575 GeodeLink™ PCI Bridg e Register Descriptions 33234H 6.16.1.3 GLD SMI MSR (GLD_MSR_SMI) MSR Address 50002002h Ty p e R / W Reset V alue 000 00000_0000003Fh GLD_MSR_SMI Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 3 1 3 0 2 9 2 8 2 7 2 6 2 [...]

576 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 6.16.1.4 GLD Error MSR (GLD_MSR_ERROR) MSR Address 50002003h Ty p e R / W Reset V alue 000 00000_0000003Fh GLD_MSR_ERROR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 3 1 3 0 2 9 2 8 2 7 [...]

AMD Geode™ LX Processors Data Book 577 GeodeLink™ PCI Bridg e Register Descriptions 33234H 6.16.1.5 GLD Po wer Ma nagement MSR (GLD_MSR_PM) 6.16.1.6 GLD Diagnostic MSR (GLD_MSR_DIA G) This register is for AMD use only and shoul d not be written to. MSR Address 50002004h Ty p e R / W Reset V alue 000 00000_00000015h GLD_MSR_PM Register Map 63 62[...]

578 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 6.16.2 GLPCI Speci fic Registers 6.16.2.1 GLPCI Global Control (GLPCI_CTRL) MSR Address 50002010h Ty p e R / W Reset V alue 440 00000_00000000h GLPCI_CTRL Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 [...]

AMD Geode™ LX Processors Data Book 579 GeodeLink™ PCI Bridg e Register Descriptions 33234H 42 SL TO Subseque nt Latency Timeout Select. Specifie s the subsequent target latency timeout limit. If within a burst, the GLPCI module does not respond with the configured number of clock tic ks, the PCI interface will terminate the PCI bu s cycle. 0: 8[...]

580 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 24 MARS Master Abort Re ceive ASMI. Allow reception of a PCI bu s master abor t to be repor ted in the T ARE bit (MSR 50002002h[17]). 0: Disable. 1: Enable. 23:21 SUS Busy Sustain. Controls the sustain ti me f or keeping the clocks running after the inter[...]

AMD Geode™ LX Processors Data Book 581 GeodeLink™ PCI Bridg e Register Descriptions 33234H 6.16.2.2 GLPCI Arbite r Control (GLPCI_ARB) 9L D E Latency Disconnect Enable. Wr iting 1, causes the PCI interface to disconnect from a PCI bus master when a latency timer expirati on occurs . Thi s enf orces the configured min- imum latency upon PCI bus [...]

582 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H GLPCI_ARB Bit Definitions Bit Name Description 63:60 CR CPU Repeat. Controls the number of consecutive gr an ts given to the CPU before rotat- ing to the ne xt requestor . This is only valid if there is a non-zero v al ue f or the CPU Hold - Grant control[...]

AMD Geode™ LX Processors Data Book 583 GeodeLink™ PCI Bridg e Register Descriptions 33234H 20 O V0 Override 0. Enab les requester0 to ov err ide the repeat-count and grant-hold f o r other requestors. When O V0 is set and REQ0# is asser ted, repea t-count and grant-hold mech- anisms for other masters are temporarily disabled. This bit does not [...]

584 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 6.16.2.3 GLPCI VPH / PCI Configur ation Cycle Control (GLPCI_PBUS) The PBUS model specific register is us ed to control the way that the GLPCI module generates (or does not gene rate) PCI configuration cycles onto the PCI b us. SEC (bits [39:32]) should b[...]

AMD Geode™ LX Processors Data Book 585 GeodeLink™ PCI Bridg e Register Descriptions 33234H 6.16.2.6 GLPCI Fixed Region Con figuration A0-BF (GLPCI_A0) GLPCI_REN Bit Descriptions Bit Name Description 63:32 Spare Spare Bits. Extra bits a vailable f or future use. These bits ma y be set an d cleared, but do not control anything. 31:24 RSVD (RO) Re[...]

586 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 6.16.2.7 GLPCI Fixed Region Con figuration C0-DF (GLPCI_C0) GLPCI_A0 Bit Descriptions Bit Name Description (Note 1) 63:56 BC BC Properties. Region proper ties for BC000 through BFFFF . 55:48 B8 B8 Pr oper ties. Region proper ties for B8000 through BBFFF .[...]

AMD Geode™ LX Processors Data Book 587 GeodeLink™ PCI Bridg e Register Descriptions 33234H 6.16.2.8 GLPCI Fixed Region Con figuration E0-FF (GL PCI_E0) 39:32 D0 D0 Properties. Region proper ties for D0000 through D3FFF . 31:24 CC CC Properties. Region proper ties for CC000 through CFFFF . 23:16 C8 C4 Properties. Region Proper ties for C8000 thr[...]

588 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 6.16.2.9 GLPCI Memory Region 0 Configuration (GLPCI_R0) MSR Address 50002018h Ty p e R / W Reset V alue 000 00000_00000000h GLPCI_R0 Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 T OP RSVD 31[...]

AMD Geode™ LX Processors Data Book 589 GeodeLink™ PCI Bridg e Register Descriptions 33234H 6.16.2.10 GLPCI Memory Region 1 Configuration (GLPCI_R1) MSR Address 50002019h Ty p e R / W Reset V alue 000 00000_00000000h GLPCI_R1 Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 T OP RSVD 3[...]

590 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 6.16.2.11 GLPCI Memory Region 2 Configuration (GLPCI_R2) MSR Address 5000201Ah Ty p e R / W Reset V alue 000 00000_00000000h GLPCI_R2 Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 T OP RSVD 3[...]

AMD Geode™ LX Processors Data Book 591 GeodeLink™ PCI Bridg e Register Descriptions 33234H 6.16.2.12 GLCPI Memory Region 3 Configuration (GLPCI_R3) MSR Address 5000201Bh Ty p e R / W Reset V alue 000 00000_00000000h GLPCI_R3 Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 T OP RSVD 3[...]

592 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 6.16.2.13 GLCPI Memory Region 4 Configuration (GLPCI_R4) MSR Address 5000201Ch Ty p e R / W Reset V alue 000 00000_00000000h GLPCI_R4 Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 T OP RSVD 3[...]

AMD Geode™ LX Processors Data Book 593 GeodeLink™ PCI Bridg e Register Descriptions 33234H 6.16.2.14 GLPCI Memory Region 5 Configuration (GLPCI_R5) MSR Address 5000201Dh Ty p e R / W Reset V alue 000 00000_00000000h GLPCI_R5 Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 T OP RSVD 3[...]

594 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 6.16.2.15 GLPCI External MSR Access Configuration (GLPCI EXT_MSR) Note: MSR accesses addressed to P or t 0 are handled directly by the GLPCI module. MSR Address 5000201Eh Ty p e R / W Reset V alue 000 00000_00000000h GLPCI_EXT_MSR Register Map 63 62 61 60[...]

AMD Geode™ LX Processors Data Book 595 GeodeLink™ PCI Bridg e Register Descriptions 33234H 6.16.2.16 GLPCI Spare MSR Address 5000201Fh Ty p e R / W Reset V alue 000 00000_00000003h GLPCI Spare 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 3 7 36 35 34 33 32 Spare 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 [...]

596 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Regis ter Descriptions 33234H 6.16.2.17 GLPCI General Pu rpose I/O (GLPCI_GPIO) MSR Address 50002020h Ty p e R / W Reset V alue 000 00000_00000000h GLPCI_GPIO Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 3 3 32 MSW RSVD SAMPDIV[...]

AMD Geode™ LX Processors Data Book 597 7 Electrical Specifications 33234H 7.0 Electr ical Specifications This section provides information on electr ical connections, absolute maximum ratings, operating conditions, and DC/A C ch aracteristic s f or the AMD Geode™ LX processor . All voltage v alues in the ele c trical specifications are with res[...]

598 AMD Geode™ LX Processors Data Book Electrical Specifications 33234H 7.3 Operating Conditions T able 7-2 lists the operating conditions for the AMD Geode LX processor . T able 7-2. Operating Conditions Symbol P arameter (Note 1) Note 1. The AMD Geode LX 900@ 1.5W processor operates at 600 MH z, the AMD Geode LX 800@0.9W processor o per- ates a[...]

AMD Geode™ LX Processors Data Book 599 Electrical Specifications 33234H 7.4 DC Current DC current is not a simple measuremen t. Three of the AMD Geode LX proc essor’ s power states (ON, Active Idle , and Sleep) were selected for measurement. For the ON power state measured, two functional characteristi cs (T ypi- cal A verage and Absolute Maxim[...]

600 AMD Geode™ LX Processors Data Book Electrical Specifications 33234H The data bus on the DDR SDRAM has a low voltage s win g when actively terminated (ter minate d topology). The ter mi- nated topology suppor ts higher data transf e r rates and is less constrained, but it consumes more pow er . Many designs should be able to ope rate reliably [...]

AMD Geode™ LX Processors Data Book 601 Electrical Specifications 33234H T able 7-4. AMD Geode LX 800@0.9W Pr ocessor DC Currents LX 800@0.9W (500 MHz), No EEPROM, V CORE = 1.25V , TDP T = 3.8W , TDP U = 3.6W (Note 1) Symbol Parameter T yp A vg Max Unit Comments I CC3ON - CR T Display P ower State: On (S0/C0) 85 100 mA I CC3ON - TFT Displa y 37 45[...]

602 AMD Geode™ LX Processors Data Book Electrical Specifications 33234H T able 7-5. AMD Geode LX 700@0.8W Pr ocessor DC Currents LX 700@0.8W (433 MHz), No EEPROM or EEPROM, V CORE = 1.20V , TDP T = 3.2W , TDP U = 3.1W (Note 1) Symbol Parameter T yp A vg Max Unit Comments I CC3ON - CR T Display P ower State: On (S0/C0) 85 100 mA I CC3ON - TFT Disp[...]

AMD Geode™ LX Processors Data Book 603 Electrical Specifications 33234H T able 7-6. AMD Geode LX 600@0.7W Pr ocessor DC Currents LX 600@0.7W (366 MHz), No EEPROM, V CORE = 1.20V , TDP T = 2.9W , TDP U = 2.8W (Note 1) Symbol Parameter T yp A vg Max Unit Comments I CC3ON - CR T Display P ower State: On (S0/C0) 85 100 mA I CC3ON - TFT Displa y 37 45[...]

604 AMD Geode™ LX Processors Data Book Electrical Specifications 33234H 7.5 DC Characteristics All DC parameters and current measurements in th is section were measured under t he operating co nditions listed in T able 7-2 "Operating Conditions", unless otherw ise noted. The sig nals associated with the sev en signal buff e r types on t[...]

AMD Geode™ LX Processors Data Book 605 Electrical Specifications 33234H I LEAK Input Leakage Current Includi ng Hi-Z Output Leakage, Note 1 PCI -3.0 3.0 µA 24/Q3 -3.0 3.0 µA 24/Q5 -3.0 3.0 µA 24/Q7 -3.0 3.0 µA 5V -3.0 3.0 µA If V IH > V IO , I LEAK max = 20 µA DDR -3.0 3.0 µA DDRCLK -5.0 5.0 µA I PU/PD W e ak Pull-Up/Down Current, Note[...]

606 AMD Geode™ LX Processors Data Book Electrical Specifications 33234H I OL Output Low Current , Note 1 V O = V OL (Max) PCI 1500 µA 24/Q3 24.0 mA 24/Q5 24.0 mA 24/Q7 24.0 mA 5V 16.0 mA DDR (BA[1:0], MA[13:0]) 15.2 mA I OL min = 11 mA with half- drive set f or pad DDR (DQ[63:0], CKE[1:0], CS[3:0]#, RAS[1:0]#, CAS[1: 0]#, WE[1:0]# , DQS[7:0], DQ[...]

AMD Geode™ LX Processors Data Book 607 Electrical Specifications 33234H 7.6 A C Characteristics The follo win g tables list the A C character istics including output delays , in put setup requirements, input hold require- ments, and output float dela ys. The r ising-clock-edge refer- ence lev el V REF , and other reference le vels are shown in F [...]

608 AMD Geode™ LX Processors Data Book Electrical Specifications 33234H Figure 7-3. Drive Level and Measurement P oints f or Switching Characteristics T able 7-8. System Interface Signals Symbol P a rameter Min Max Unit Comments t CK SYSREF Cycle time 15.0 INF ns 66 MHz t CH SYSREF High time 6.0 ns 40% t CK t CL SYSREF Low time 6.0 ns 40% t CK t [...]

AMD Geode™ LX Processors Data Book 609 Electrical Specifications 33234H Figure 7-4. P ower Up Sequencing Figure 7-5. Drive Level and Measurement P oints f or Switching Characteristics V CORE V IO ,V MEM RESET# SYSREF SYSREF cycle time not to scale with other delays in this figure. Outputs t ON t RSTX t Z MVREF t MV ON T able 7-9. PCI Interface Si[...]

610 AMD Geode™ LX Processors Data Book Electrical Specifications 33234H Figure 7-6. Drive Level and Measurement P oints f or Switching Characteristics T able 7- 10. VIP Interface Si gnals Symbol P a rameter Min Max Unit Comments t CK VIPCLK period 12.5 ns 80 MHz t CH VIPCLK High time 3.0 ns 45% t CK t CL VIPCLK Lo w time 3.0 ns 45% t CK t VA L VI[...]

AMD Geode™ LX Processors Data Book 611 Electrical Specifications 33234H Figure 7-7. Drive Level and Measurement P oints f or Switching Characteristics T able 7-11. Flat Panel I nterface Signals Symbol P a rameter Min Max Unit Comments t CK DO TCLK per iod 6.0 ns 166 MH z t CH DO TCLK High ti me 2.7 ns 45% t CK t CL DO TCLK Low time 2.7 ns 45% t C[...]

612 AMD Geode™ LX Processors Data Book Electrical Specifications 33234H T able 7-12. C RT Interface Sign als Symbol P a rameter Min Max Unit Comments t CK DO TCLK P e riod 2.8 ns 350 MHz t CH DO TCLK High ti me 1.2 ns 45% t CK t CL DO TCLK Low time 1.2 ns 45% t CK DO TCLK lo ng term outpu t jitter 15% t CK Note 1 t SKEW Ske w between RED , GREEN,[...]

AMD Geode™ LX Processors Data Book 613 Electrical Specifications 33234H T able 7- 14. CR T Di splay Analog (DA C) Characte ristics Symbol Parameter Min T yp Max Units Comments (Note 1) V OS Ou tput V oltage Saturation Limit 1.25 V I OV A R Ou tput Current 18.67 mA Achiev e s 700 mV on 3 7.5 Ω INL Integral Linearity Error +/-1 LSB DNL Differentia[...]

614 AMD Geode™ LX Processors Data Book Electrical Specifications 33234H T able 7- 15. Memory (DDR ) Interface Signals Symbol (Note 1) Parameter Min Max Unit Comments t CK SDCLK[5:0]P , SDCLK[5: 0]N period 5.0 ns Note 2 t CH SDCLK[5:0]P , SDCLK[5:0] N High time 2.4 ns 48% t CK t CL SDCLK[5:0]P , SDCLK[5:0] N Low time 2.4 ns 48% t CK t SKEW1 SDCLK[[...]

AMD Geode™ LX Processors Data Book 615 Electrical Specifications 33234H Figure 7-8. DDR Write Timing Measurement Poi nts SDCLK[5:1]P Non-DQ Outputs V REF V alid Output n+1 V alid Output n V REF t VA L 2 Min t VA L 2 Max V IHD V ILD V REF DQS Outputs DQS V IHD V ILD V REF DQ Outputs DQ n+1 DQ n V REF DQ n+2 SDCLK[5:0]N V REF t SKEW1 t SKEW1 t DEL2[...]

616 AMD Geode™ LX Processors Data Book Electrical Specifications 33234H Figure 7-9. DDR Read Timing Measurement P oints DQ Inputs V REF DQ t V REF DQ t-1 SDCLK0 DQS ‘Late’ Input V REF other DQS Inpu t V REF DQ t+1 DQ t+2 DQS[n] Input V REF t SKEW2 t DQSCK Max DQS ‘Early’ Input V REF t DQSCK Min t SKEW2 -t DQSQs t DQSQh associated with DQS[...]

AMD Geode™ LX Processors Data Book 617 Electrical Specifications 33234H T able 7-16. JT A G Interface Signal s Symbol P a rameter Min Max Unit Comments TCLK per iod 15 ns No te 1 TCLK High time 4 ns 40% period TCLK Lo w time 4 ns 40% period TDI, TMS Setup time to TCLK rising edge 1.5 ns TMS Hold time from TCLK rising edge 3.0 ns TDI Hold time fro[...]

618 AMD Geode™ LX Processors Data Book Electrical Specifications 33234H[...]

AMD Geode™ LX Processors Data Book 619 8 Instruction Set 33234H 8.0 Instr uction Set This chapt er provide s the gener al instruction set f ormat and detailed inf ormation on th e AMD Geo de™ LX proc essor’s instruc tions/ instru ction encodings. The instr uction set is divided into three categor ies: • CPUID Instruction Set - listed in Sec[...]

620 AMD Geode™ LX Processors Data Book Instruction Set 33234H 8.1.1 Prefix (Op tional) Prefix bytes can be placed in front of any instruction to mo di fy the operation of that instr uction. Wh en more than one prefix is used, the order is not impor tant. There are five types of prefix es that can be used: 1) Segment Override explicitly specifies [...]

AMD Geode™ LX Processors Data Book 621 Instruction Set 33234H 8.1.2 Opc ode The opcode field specifies the operation to be perf or med by the instr uction. The opcode field is either one or two bytes in length and may be fur ther defined by additional bits in th e mod r/m byte. Some operations hav e more than o ne opcode, each specifying a differ[...]

622 AMD Geode™ LX Processors Data Book Instruction Set 33234H 8.1.2.4 eee Field (MO V -Instr uction Register Selection) The eee field (bits [5:3]) is used to sel ect the control, debug, and test registers in the MO V instructions. The type of regist er and bas e re gis ters sel ecte d by the eee fie ld are lis ted in T able 8-7. The v alues shown[...]

AMD Geode™ LX Processors Data Book 623 Instruction Set 33234H 01 000 DS:[BX+SI+d8] DS:[EAX+d8] 01 001 DS:[BX+DI+d8] DS:[ECX+d8] 01 010 SS:[BP+SI+d 8] DS:[EDX+d8] 01 011 SS:[BP+DI+d8] DS:[EBX+d8] 01 100 DS:[SI+d8] s-i-b is present (See T a ble 8-15 on page 626) 01 101 DS:[D I+d8] SS:[EBP+d8] 01 110 SS:[BP+d8] DS:[ESI+d8] 01 111 DS:[BX+d8] DS:[EDI+[...]

624 AMD Geode™ LX Processors Data Book Instruction Set 33234H 8.1.4 reg Fie ld The reg field (T able 8-10) determines w hich general regist ers are to be used. The selected register is depe ndent on whether a 16-bit or 3 2-bit operation is current and on the status of the w bit. 8.1.4.1 sreg2 Field (ES, CS, SS, DS Register Selection) The sreg2 fi[...]

AMD Geode™ LX Processors Data Book 625 Instruction Set 33234H 8.1.5 s-i-b Byte (Scale, Inde xing, Base) The s-i- b fie lds pro vide sc ale f actor , i nde xing, and a base f ield f or addr ess sele ctio n. The ss, ind e x, and base fields are described next. 8.1.5.1 ss Field (Scale Selection) The ss field (T able 8-13) specifies the sca le factor[...]

626 AMD Geode™ LX Processors Data Book Instruction Set 33234H 8.1.5.3 Base Field (s-i-b Present) In T ab le 8-8 on page 622, the note “s-i-b is present” f o r cer tain e ntr ies forces t he us e of th e mo d and base fiel d as l iste d in T able 8-15. The first two digits in the first column of T able 8- 15 identify the mod bits in the mod r/[...]

AMD Geode™ LX Processors Data Book 627 Instruction Set 33234H 8.2 CPUID Inst ruction Set The CPUID instru ction (opcode 0F A2) allows softw are to mak e processor inquir ies as to the vendor , f amil y , model, step- ping, f ea tures, and specific cache organization inf or mation. Th e presence of suppor t for the CPUID instruction is indicated b[...]

628 AMD Geode™ LX Processors Data Book Instruction Set 33234H T able 8-18. CPUID Instruction Codes with EAX = 00000000 Register Reset V alue Description Comment EAX[31:28] 0x0 Reser ved EAX[27:20] 0x00 Extended F amily EAX[19:16] 0x00 Extended Mod el EAX[15:12] 0x0 Reser ved EAX[11:8] 0x5 Processor/ Instruction F amily EAX[7:4] 0xA Processor Mode[...]

AMD Geode™ LX Processors Data Book 629 Instruction Set 33234H 8.2.2 Extended CPUID Level s T esting for e xtended CPUID inst r uction suppor t can be accomp lished by e xec uting a CPUID instruction with the EAX regis- ter initialized to 80000000h. If a value greater than or eq ual to 80000000h is re turn ed to the EAX register by the CPUID instr[...]

630 AMD Geode™ LX Processors Data Book Instruction Set 33234H T able 8-21. CPUID Instruct ion Codes with EAX = 80000001h Register Reset V alue Description Comment EAX[31:28] 0x0 Reser ved EAX[27:20] 0x00 Extended F amily EAX[19:16] 0x00 Extended Mod el EAX[15:12] 0x0 Reser ved EAX[11:8] 0x5 Processor/ Instruction F amily EAX[7:4] 0x5 Processor Mo[...]

AMD Geode™ LX Processors Data Book 631 Instruction Set 33234H 8.2.2.3 CPUID Instruct ion with EAX = 80000002h, 80000003h, or 80000004h Extended functions 80 000002h through 8000 0004h (EAX = 80000002h, EAX = 80 000003h, and EAX = 80000004h) of the CPUID instructi on return s an ASCII string contai ning the CP U marketing name, as shown in T able [...]

632 AMD Geode™ LX Processors Data Book Instruction Set 33234H 8.2.2.4 CPUID Instruct ion with EAX = 80000005h Extended function 80000005h (EAX = 80000005h) of the CPUID in str uction returns informatio n on the inter nal L1 cache and TLB structures. They are used f or repor ting purp oses only . See T able 8-23 f or retur ned contents. 8.2.2.5 CP[...]

AMD Geode™ LX Processors Data Book 633 Instruction Set 33234H 8.3 Processor Core Instruction Set The instruction set for the AMD Geode LX processor core is summarized in T able 8-26. The table uses se veral symbols and abbre viation s that are descr ibed next and listed in T able 8-25. 8.3.1 Opc odes Opcodes are given as he x values e xcept when [...]

634 AMD Geode™ LX Processors Data Book Instruction Set 33234H T able 8-26 . P r ocessor Core Instruction Se t Instruction Opcode Clock Count (Reg/Cache Hit) Flags Notes Real Mode Prot’d Mode OD I T S Z AP C FFFFFFFFF Real Mode Prot’d Mode AAA ASCII Adjust AL after Add ition 3 7 3 3 u - - - uux ux AAD ASCII Adjust AX before Divide D 5 0 A 4 4 [...]

AMD Geode™ LX Processors Data Book 635 Instruction Set 33234H BTS T est Bit and S et --------x b h Register/Memory , Immediate 0F BA [mod 101 r/m] # 2 2 Register , Register 0F AB [mod reg r/m] 2 2 Memory , Register 0F AB [mod reg r/m] 8 8 CALL Subroutine Call --------- b h , j , k , r Direct Within Segment E8 +++ 2 2 Register/Memory Indirect With[...]

636 AMD Geode™ LX Processors Data Book Instruction Set 33234H CMO VNS Move if Not Sign 0 F 4 9 [ m o d r e g r / m ] 1 1 --------- r Register , Register/Memory CMP Comp are Integers x- - - xxxxx b h Register to Register 3 [10dw] [11 reg r/ m] 1 1 Register to Memory 3 [101w] [mo d reg r/m] 1 1 Memory to Register 3 [100w] [mod reg r/m] 1 1 Immediat[...]

AMD Geode™ LX Processors Data Book 637 Instruction Set 33234H IMUL Integer (Signed) Multiply x ---x x u u x b h Accumulator b y Register/Memor y Multiplier: Byte Wor d Doubleword F [011w] [mod 101 r/m] 3 4 4 3 4 4 Register with Regi ster/Memor y Multiplier: Word Doubleword 0F AF [mod reg r/m] 4 4 4 4 Register/Memory with Immediate to Register2 Mu[...]

638 AMD Geode™ LX Processors Data Book Instruction Set 33234H JNBE/JA J ump on Not Below or Equal /Abov e -------- r 8-bit Displacement 77 + 1 1 Full Displacement 0F 87 +++ 1 1 JNE/JNZ J ump on Not Equal/Not Zero -------- r 8-bit Displacement 75 + 1 1 Full Displacement 0F 85 +++ 1 1 JNL/JGE J ump on Not Less/Greater or Equal -------- r 8-bit Disp[...]

AMD Geode™ LX Processors Data Book 639 Instruction Set 33234H LOOPNZ/LOOPNE Offset E 0 + 2 2 --------- r LOOPZ/LOOP E Offset E 1 + 2 2 --------- r LSL Load Segme nt Limit -----x --- F rom Register/Memor y 0F 03 [mod reg r/m] 9 a g,h,j,p LSS Load P ointer to SS 0 F B 2 [ m o d r e g r / m ] 4 9 / 1 5 --------- a h , i , j LT R Load T ask Register [...]

640 AMD Geode™ LX Processors Data Book Instruction Set 33234H OUT Output to P or t --------- m Fixed P ort E [011w] # 8 8/23 V ariable P or t E [111 w] 8 8/23 OUTS Output String 6 [ 1 1 1 w ] 1 2 1 2 / 2 6 --------- b h , m PA U S E 7 POP P op V alue off St ack --------- b h , i , j Register 8F [mod 000 r/m] 1 1 Memory 8F [mod 000 r/m] 3 3 Regist[...]

AMD Geode™ LX Processors Data Book 641 Instruction Set 33234H REP CMPS CX==0 66 CX==1 13 13 CX>1 10+3C 10+3C REP INS I nput String F 3 6 [ 1 1 0 w ] --------- b h , m CX==0 99 / 2 4 CX==1 CX>1 15+6C 1 5+6C/ 30+6C REP LODS Load S t ring F 3 A [ 1 1 0 w ] --------- b h CX==0 55 CX==1 10 10 CX>1 8+2C 8+2C REP MO VS Mov e String F 3 A [ 0 1 [...]

642 AMD Geode™ LX Processors Data Book Instruction Set 33234H SAL Shift Left Arithmetic bh Register/Memory by 1 D[000w] [mod 100 r/m] 1 1 x - - - x x u x x Register/Memory by CL D[001w] [mod 100 r/m] 1 1 u - - - x x u x x Register/Memory by Immediate C[000w] [mod 100 r/m] # 1 1 u - - - x x u x x SAR Shift Right Arithmetic bh Register/Memory by 1 [...]

AMD Geode™ LX Processors Data Book 643 Instruction Set 33234H SFENCE 11 SGDT Store GDT Register b, c h T o R e g i s t e r / M e m o r y 0 F 0 1 [ m o d 0 0 0 r / m ] 6 6 --------- SIDT Store IDT Regist er b, c h T o R e g i s t e r / M e m o r y 0 F 0 1 [ m o d 0 0 1 r / m ] 6 6 --------- SLDT Store LDT Register ah T o R e g i s t e r / M e m o [...]

644 AMD Geode™ LX Processors Data Book Instruction Set 33234H WRMSR Write to Model S pecific Register 0 F 3 0 1 0 1 0 --------- XADD Exchange and Add x- - - xxxxx Register1, Register2 0F C[000w] [11 re g2 reg1] 2 2 Memory , Register 0F C[000w] [mod re g r/m] 2 2 XCHG Exchange --------- b , f f , h Register/Memory with Register 8[011w] [mod reg r/[...]

AMD Geode™ LX Processors Data Book 645 Instruction Set 33234H Instruction Notes for Instruction Set Summary Notes a through c apply to real address mode only: a. This is a protec ted mode instruction. Attempted e xecut i on in real mode results in ex ce ption 6 (inv alid opcode ). b . Exception 13 fault (general protection) oc curs in real mode i[...]

646 AMD Geode™ LX Processors Data Book Instruction Set 33234H 8.3.4 Non-Stand ard Pr oce ssor Core Instruc tions 8.3.4.1 DMINT - Enter Deb ug Management Mode Operation Opcode Instruction C locks Description 0F 39 DMINT 50-52 Enter DMM and call the DMI handl er IF (CPL<>0 OR (DMM_INST_EN=0 AND SMM=0 AND DMM=0)) #UD; ELSE DMM_HEADER[A C_TEMP0[...]

AMD Geode™ LX Processors Data Book 647 Instruction Set 33234H Description The DMINT instru ction sav es por tions of the processors stat e to the Debug Management Mode (DMM) he ader , alters the processors state for DMM, enters DMM, and then call s the DMM mode hand ler . Below is the f or mat of the DMM header . Flags Affected All EFlags are ret[...]

648 AMD Geode™ LX Processors Data Book Instruction Set 33234H 8.3.4.3 MO V - Move to /fr om T est Registers Operation IF (CPL <> 0) THEN #GP(0); ELSE DEST <= SRC; Description The abov e f or ms of the MO V instr uction store the contents of a test register (eithe r TR0, TR 1, TR2, TR3, TR4, TR5, TR6, or TR7) to a general purpose registe [...]

AMD Geode™ LX Processors Data Book 649 Instruction Set 33234H 8.3.4.4 RDM - Lea ve Debug Management Mode Operation Description The RDM instru ction restores the state of the pro cessor from the DMM header, and then jumps to the address in dicated in the NEXT_IP field of the DMM header. Be lo w is the f or mat of the DMM header. Flags Affected All[...]

650 AMD Geode™ LX Processors Data Book Instruction Set 33234H Exceptions #UD If current privilege le vel is not 0, or the DMM_INST_ EN = 0 and if the processor is not in SMM an d if the processor is not in DMM. Notes Data address breakpoints o n DMM header addresses a re i gnored dur ing the ex ecution of the RSM instruction. The RDM instru ction[...]

AMD Geode™ LX Processors Data Book 651 Instruction Set 33234H 8.3.4.6 RSLDT - Restore Local Descri ptor T able Register and Descriptor Operation Description Restore the Local De scriptor T able register and descriptor from memor y . Be low is the f orm at of the descri ptor contents in memor y . Flags Affected None. Exceptions #UD If current priv[...]

652 AMD Geode™ LX Processors Data Book Instruction Set 33234H 8.3.4.7 RSM - Lea ve S ystem Management Mode Operation Description The RSM instruction restores the state of the pr ocessor from the System Managem ent Mode (S MM) header , and then jumps to the address indicated by the NEXT_IP field of the SMM header . Below is the format of the SMM h[...]

AMD Geode™ LX Processors Data Book 653 Instruction Set 33234H Notes The RSM instr uction does not check the values th at it reads from the SMM header f or validity . The RSM instr uction set the curr ent pr ivilege lev e l to the SS DPL value read from the SMM header . If a RSM restores the processor to real mode, the VM bit o f t he EFlags regis[...]

654 AMD Geode™ LX Processors Data Book Instruction Set 33234H Exceptions None. Notes None. 8.3.4.10 SMINT - Enter System Management Mode Operation Opcode Instruction C locks Description 0F 38 SMINT 55 E nter SMM and call the SMI handler IF (CPL<>0 OR (SMM_INST_EN =0 AND SMM=0 AND DMM=0)) #UD; ELSE SMM_HEADER[SMM_CTL] <= SMM_CTL; SMM_HEAD[...]

AMD Geode™ LX Processors Data Book 655 Instruction Set 33234H Description The SMINT instruction sav es por tions of the processors state to the System Management Mode (SMM) h eader , alters the processors state for SMM, enters SMM, and then calls the SMM handler . Below is the f or mat of the SMM header. Flags Affected All EFlags are retur ned to[...]

656 AMD Geode™ LX Processors Data Book Instruction Set 33234H 8.3.4.12 SVDC - Save Segmen t Register and Descriptor Operation Description Write the specified segmen t descriptor (either DS, ES, FS , GS, SS , or CS) to memory . Below is the f or mat of the descriptor contents in memor y . Flags Affected None. Exceptions #UD If current privilege le[...]

AMD Geode™ LX Processors Data Book 657 Instruction Set 33234H Exceptions #UD If current privilege lev el is not 0, or the SMM_INST_EN = 0 and if the processor is not in SMM and if the processor is not in DMM. Notes The reg field within the mod r/m byte must be zero f or the SVLDT instr uction to be recognized. 8.3.4.14 SVTS - Save T ask Register [...]

658 AMD Geode™ LX Processors Data Book Instruction Set 33234H 8.4 MMX™, FPU , and AMD 3DNo w!™ T echnology In structions Sets The CPU is functional ly divided into the Flo ating P oint Uni t (FPU) unit and the Integer Unit. The FPU has b een extended to process MMX, AMD 3DNow!, and floating point instr uctions in parallel with the Integer Uni[...]

AMD Geode™ LX Processors Data Book 659 Instruction Set 33234H windex 1 (imm8) The range given b y [in de x1 (imm8) + 15: index1 (imm8)]. windex 2 (imm8) The range given b y [in de x2 (imm8) + 15: index2 (imm8)]. windex 3 (imm8) The range given b y [i ndex3 ( imm8) r15: indes3 (imm8)]. windexall (imm8) The four diff erent index # (imm8) ordered in[...]

660 AMD Geode™ LX Processors Data Book Instruction Set 33234H T able 8-28. MMX™ Instruction Set MMX™ Instructions Opcode Operation Clock Ct Notes EMMS Empty MMX Stat e 0F77 T ag Word <--- FFFFh (empties the floating point tag word) 1 1 MASKMO VQ Streaming (Cache Bypass) Store Usin g Byte Mask (Using EDI Regist er) 2 MMX Register1with MMX R[...]

AMD Geode™ LX Processors Data Book 661 Instruction Set 33234H P ADDUSW Add Unsi gned Word with Saturation MMX Register 2 to MMX Register 1 0FDD [11 mm1 mm2] MMX reg 1 [word] <--- sat --- (MMX reg 1 [word] + MMX reg 2 [word]) 2 Memory to Register 0FDD [mod mm r/m] MMX reg [ word] <--- sat --- (memory [word] + MMX reg [wor d]) 2 P ADD W Pac k[...]

662 AMD Geode™ LX Processors Data Book Instruction Set 33234H PCMPGTD P ack Compare Greater Than Dword MMX Register 2 to MMX Registe r 1 0F66 [11 mm1 mm2] MMX reg 1 [dwo rd] <--- FFFF FFFFh --- if MMX reg 1 [dword] > MMX reg 2 [dword] MMX reg 1 [dw ord]<--- 0000 0 000h ---if MMX reg 1 [dword]NO T > MMX reg 2 [dword] 2 Memory with MMX [...]

AMD Geode™ LX Processors Data Book 663 Instruction Set 33234H PMINSW P acked Minimum Signed Word MMX Register 1with MMX Register 2 0FEA [11 mm1 mm2] MMX reg 1 [word] <--- MMX reg 1 [w ord] --- if (MMX reg 1 [sign word] < MMX reg 2 [sign word]) MMX reg 1 [word] <--- MMX reg 2 [w ord] --- if (MMX reg 1 [sign word] NO T < MMX reg 2 [sign[...]

664 AMD Geode™ LX Processors Data Book Instruction Set 33234H PSHUFW P acked Shuff le Word MMX Register1, MMX Regi ster2, imm8 0F70 [11 mm1 mm2] # MMX reg 1 [w ord] <--- MMX re g 2 [windexall (imm8)] 2 MMX Register , Memory64, imm8 0F70 [mod mm r/m] # MMX reg [wor d] <--- Memory 64 [winde xall (imm8)] 2 PSLLD P acked Shift Left Logical Dwor[...]

AMD Geode™ LX Processors Data Book 665 Instruction Set 33234H PSUBB Subtract Byte With Wrap-Around MMX Regist er 2 to MMX Reg ister 1 0FF 8 [11 mm1 mm2] MMX reg 1 [byt e] <--- MMX reg 1 [byte] - MMX reg 2 [byte] 2 Memory to MMX Register 0FF8 [mod mm r/m] MMX reg [b y te] <--- MMX reg [b yte] - memor y [byte] 2 PSUBD Subtract Dword With Wr a[...]

666 AMD Geode™ LX Processors Data Book Instruction Set 33234H 1) This instruction must wait f or the FPU pipeline to flush. Cycle count depends on what inst ructions are in the pipe line. PXOR Bitwise XOR MMX Register 2 to MMX R egister 1 0FEF [11 mm1 mm2] MMX reg 1 [qword] --- MMX reg 1 [qw ord], <--- logic exclusive OR MMX reg 2 [ qword] 2 M[...]

AMD Geode™ LX Processors Data Book 667 Instruction Set 33234H T able 8-29. FPU Instruction Set FPU Instruction Opcode Operation Clock Ct Single/Dbl (or extended) Notes F2XM1 Functi on Evaluation 2x-1 D9 F0 TO S <--- 2 TO S -1 145 - 166 2 FA B S Floating Absolute V alue D9 E1 T OS <--- | T OS | 1 3 FA D D Floating P oint Add T op of Stack DC[...]

668 AMD Geode™ LX Processors Data Book Instruction Set 33234H FDECSTP Decrement Stack pointer D9 F6 Decrement top of stack pointer 1 3 FDIV Float ing P oint Divide T op of Stack DC [1111 1 n] ST(n) <--- ST(n) / T OS 12/47 80-bit Register D8 [1111 0 n] TOS <--- T OS / ST(n) 12/47 64-bit Real DC [mod 110 r/m] T OS <--- TOS / M.DR 12/47 32-[...]

AMD Geode™ LX Processors Data Book 669 Instruction Set 33234H FP A T AN Function Eval: T an-1(y/ x) D9 F3 ST(1) <--- A T AN[ST(1) / TOS]; t hen pop TOS 269 - 354 3 FPREM Floating P oint Remainder D9 F8 T OS <--- Rem[TOS / ST(1)] 53 - 208 FPREM1 Floating Poi nt Remainder IEEE D9 F5 TOS <--- Rem[T OS / ST(1)] 53 - 208 FPT AN Function Ev al[...]

670 AMD Geode™ LX Processors Data Book Instruction Set 33234H All ref erences to T OS and ST(n) refer to stac k lay out prior to ex ecu tion. V alues popped off the stack are discarded. A POP from the stack increments the top of stac k poi nter . A PUSH to the stac k decremen ts the top of stack pointer . Issues: 1) For FCOS , FSIN, FSINCOS, and [...]

AMD Geode™ LX Processors Data Book 671 Instruction Set 33234H T able 8- 30. AMD 3DNow!™ T echnology Instruction Set AMD 3DNow!™ Instructions Opcode/imm8 Operation Clk Cnt Notes FEMMS F aster Exit of the MMX or 3DNow! State 0F0E T ag Word <-- - FFFFh (empties the floating point tag w ord) MMX registers <--- u ndefined v alue 11 PAV G U S[...]

672 AMD Geode™ LX Processors Data Book Instruction Set 33234H PFMAX P ack ed Floating-P oint MAXimum 2 MMX Register1 with MMX Register2 0F0F [11 mm1 mm2] A4 MMX reg 1[dword] <--- MMX reg 1 [d word] --- if (MMX reg 1 [dword] > MMX reg 2 [dw ord]) MMX reg 1 [dw ord] <--- MMX reg 2 [dwo rd] --- if (MMX reg 1 [dword] NO T > MMX reg 2 [dwo[...]

AMD Geode™ LX Processors Data Book 673 Instruction Set 33234H 1) These instructions must w a it f or the FPU pipeline to flus h. Cycle count dep ends on what instructions are in the pi pe- line. 2) The AMD Geode LX processor perf or ms PFRCP and PFRSQRT to 24- bit accuracy in one cycle , so these instructions are unnecessar y . They are treated a[...]

674 AMD Geode™ LX Processors Data Book Instruction Set 33234H 8.4.1 Non-Standard AMD 3DNo w!™ T echnology Instruction s 8.4.1.1 PFRCPV - Floating-Point Reciprocal Appr o x imation Operation DEST[31:0] <= reciprocal(SR C[31:0]); DEST[63:32] <= RECI PROCAL(SRC[63:32]); Description PFRCPV performs the same operation as the PFRCP i nstruction[...]

AMD Geode™ LX Processors Data Book 675 9 Pac kage Specifications 33234H 9.0 P ac kage Specifications 9.1 Physical Dimensions The figures in this section provide the mechanical package outline for the BGU481 (481-ter minal Ball Grid Array Ca vi ty Up) Figure 9-1. BGU481 T op/Side Vie w /Dimension s[...]

676 AMD Geode™ LX Processors Data Book Pac kage Specificatio ns 33234H Figure 9-2. BGU481 Bottom Vie w /Dimensions[...]

A AMD Geode™ LX Processors Data Book 677 Appendix A: Suppor t Document ation 33234H Appendix A Suppor t Documentation A.1 Or der Information Ordering information for the AMD Geode™ LX proce ssors is c ontained i n this section. The order ing par t number (OPN) is f orm ed by a combination of elements. An e xample of the OPN is sh own in Figure [...]

678 AMD Geode™ LX Processors Data Book Appendix A: Order Information 33234H T able A-1. V alid OP N Combinations Fam ily Architecture MTDP Per fo r m an c e Indicator Pac k ag e Ty p e Operating Vo l t a g e System Bus Speed EEPROM Indicator Display Ty p e Case T emperature/ Solder T ype (Note) ALX G 900 EE Y J 2 V H ALX D 800 EE X J 2 V C D F CC[...]

AMD Geode™ LX Processors Data Book 679 Appendix A: Data Book Revision Histor y 33234H A.2 Data Book Revision History This document is a repor t of the revi sion/creation process of the data book fo r the AMD Geode™ LX processors. Any re vi- sion (i.e., additions, deletions, parameter corrections, etc.) are recorded in the table(s) below . T abl[...]

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