Analog Devices TigerSHARC ADSP-TS201S manuale d’uso

• a TigerSHARC and the TigerSHARC logo are registered trademar ks of Analog Devices, Inc. TigerSHARC ® Embedded Processor ADSP-TS201S Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, n or for any infringements of patents or other right s o[...]

Rev. C | Page 2 of 48 | December 2006 ADSP-TS201S T ABLE OF CONTENTS G e n e r a l D e s c r i p t i o n ......................... ..................... ... 3 D u a l C o m p u t e B l o c k s .......... .......................... ........ 4 D a t a A l i g n m e n t B u f f e r ( D A B ) ..... .......................... ... 4 D u a l I n t e g e r[...]

ADSP-TS201S Rev. C | Page 3 of 48 | December 2006 GENERAL DESCRIPTION The ADSP-TS201S TigerSHARC pr ocessor is an ultrahigh per- formance, static superscalar processor optimized for large sign al processing tasks and communications infrastructure. The DSP combines very wide mem ory widths with dual computa tion blocks—supporting floating-poi nt ([...]

Rev. C | Page 4 of 48 | December 2006 ADSP-TS201S The TigerSHARC DSP uses a Static Superscalar TM † architecture. This architecture is superscala r in that the ADSP-TS201S pro- cessor’s core can execute simultan eously from one to four 32-bit instructions enco ded in a very lar ge instruction word (VLIW) instruction line using the DSP’s dual [...]

ADSP-TS201S Rev. C | Page 5 of 48 | December 2006 The IALUs have hardware support for circular buffers, bit reverse, and zero-overhead loopin g. Circular buffers facilitate efficient programming of delay li nes and other data str uctures required in digital signal proc essing, and they are commonly used in digital filters and Four ier transforms. E[...]

Rev. C | Page 6 of 48 | December 2006 ADSP-TS201S 33.6G bytes per second, enabling the core and I/O to access eight 32-bit data-words and four 32-bit instructions each cycle. The DSP’s flexible memo ry structure enables: • DSP core and I/O acc esses to different memo ry blocks in the same cycle • DSP core access to three memory blocks in para[...]

ADSP-TS201S Rev. C | Page 7 of 48 | December 2006 The ADSP-TS201S processor prov ides programmable memory, pipeline depth, and idle cycl e for synchronous accesses; and external acknowledge cont rols to support interfacing to pipe- lined or slow devices, host processors, and other memory- mapped peripherals with variable access, hold, and disable t[...]

Rev. C | Page 8 of 48 | December 2006 ADSP-TS201S external memory. T hese tran sfers only use handshake mode protocol. DMA priority rotat es between the four receive channels. • AutoDMA transfers. Two de dicated unidirecti onal DMA channels transfer data received from an external bus master to internal memory or to link port I/O. These transfers [...]

ADSP-TS201S Rev. C | Page 9 of 48 | December 2006 LINK P OR TS (L VDS) The DSP’s four full-duplex link ports each prov ide addi tional four-bit receive a nd four-bit transmit I/ O capability, using low voltage, differential-signal (L VD S) technology. With the ability to operate at a double data rate—l a tching data on both the rising and falli[...]

Rev. C | Page 10 of 48 | December 2006 ADSP-TS201S POWE R DO M A I N S The ADSP-TS201S processor ha s separate power supply con- nections for int ernal logic (V DD ), analog circuits (V DD_A ), I/O buffer (V DD_IO ), and internal DRA M (V DD_DRA M ) power supply. Note that the analog (V DD_A ) supply powers the clock generator PLLs. To produce a st[...]

ADSP-TS201S Rev. C | Page 11 of 48 | December 2006 eliminating the need to start from th e very beginning when developing new applicatio n code. The VDK fe atures include threads, cri tical and unsched ule d regions, semaphores, events, and device fla gs. The VDK also supports priority-based, pre- emptive, cooper ative, and time -sliced scheduling [...]

Rev. C | Page 12 of 48 | December 2006 ADSP-TS201S PIN FUNCTION DESCRIPTIONS While most of the ADSP-TS201S processor’s input pins are nor- mally synchronous —tied to a specific clock—a few are asynchronous. For t hese asynchronous signa ls, an on-chip syn- chronization circuit prevents metastability proble ms. Use the ac specification for asy[...]

ADSP-TS201S Rev. C | Page 13 of 48 | December 2006 Table 5. Pin Definition s—External Port Bus Con trols Signal T ype T e rm Descrip tion ADDR31–0 I/O/T (pu_ad) nc Address Bus . The DSP issues addresses f or accessing memor y and peripherals on these pins. In a multipr ocessor sy stem, the bus master drives addresses for accessing internal memo[...]

Rev. C | Page 14 of 48 | December 2006 ADSP-TS201S Table 6. Pin Defini tions—External P ort Arbitration Signal T ype T e rm Descrip tion BR7–0 I/O V DD_IO 1 Multiprocessing Bus Request P ins. Used by the DSP s in a multiprocessor syst em to arbitrate for bus mastership . Each DSP drives its own BRx line (corresponding to the value of its ID2–[...]

ADSP-TS201S Rev. C | Page 15 of 48 | December 2006 Table 7. Pin Defini tions—Ext ernal Port DMA/Flyby Signal T ype T e rm Descrip tion DMAR3–0 I/A epu DMA Request Pins. Enable external I/O devices to request DM A services from the DSP . In response to DMARx , the DSP per forms DMA transfers according to the DMA channel’ s initialization. The [...]

Rev. C | Page 16 of 48 | December 2006 ADSP-TS201S Table 8. Pin D efinitio ns—Exter nal Port SDRAM C ontrolle r Signal T ype T e rm Descrip tion MSSD3–0 I/O/T (pu_0) nc Memory Select SDRAM. MS SD0 , MSSD1 , MSSD2 , or MSSD3 is asserted whenever the DSP accesses SDRAM memory space. MSSD3–0 are decoded memory address pins that are asser ted whe[...]

ADSP-TS201S Rev. C | Page 17 of 48 | December 2006 Table 9. Pin Definitions—JTAG Port Signal T ype T e rm Descrip tion EMU O/OD nc 1 Emulation. Connected to the DSP’ s JT AG emulator target boar d connector only . TC K I ep d o r e p u 1 T est Clock (JT AG). P rovides an asynchr onous clock for JT AG scan. TDI I (pu_ad) nc 1 T est Data Input ( [...]

Rev. C | Page 18 of 48 | December 2006 ADSP-TS201S Table 11. Pin Definitions—Li nk Ports Signal T ype T e rm Descrip tion LxDA TO3–0P O nc Link P orts 3–0 Data 3–0 T ransmit L VDS P LxDA TO3–0N O nc Link P orts 3–0 Data 3–0 T ransmit L VDS N LxCLKOUTP O nc Link Ports 3–0 T ransmit Clock L VDS P LxCLKOUTN O nc Link Ports 3–0 T rans[...]

ADSP-TS201S Rev. C | Page 19 of 48 | December 2006 Table 13. Impedance Control Selection C ONTROLIMP1-0 Driver M ode 00 (recommended) Normal 01 Reser ved 10 (default) A/D Mode 11 Reser ved Table 14. Drive Strength/Output Impedance Selection DS2–0 Pin s Drive Strength 1 Output Impedance 2 000 Strength 0 (11.1%) 26 Ω 001 Strength 1 (23.8%) 32 Ω 0[...]

Rev. C | Page 20 of 48 | December 2006 ADSP-TS201S STRAP PIN FUNCTION DESCRIPTIONS Some pins have alternate func ti ons at reset. Strap options set DSP operating modes. During re set, the DSP samples the strap option pins. Strap pins have an internal pull-up or pull-down for the default value. If a strap pin is not c onnected to an over- driving ex[...]

ADSP-TS201S Rev. C | Page 21 of 48 | December 2006 ADSP-TS201S—SPECIFICATIONS Note that component specifications are subject to change with- out notice. For information on link port electrical characteristics, see Link Port Low Voltage, Differential-Signal (LVDS) Electrical Characteristics, and Timing on Page 30 . OPERAT ING C ONDITIO NS Par amet[...]

Rev. C | Page 22 of 48 | December 2006 ADSP-TS201S ELECTRICAL CHARAC TERISTICS Table 18. Maximum Duty Cycle for Input Transient Voltage V IN Max (V ) 1 V IN Min (V) 1 Maximum Duty Cyc l e 2 +3.63 –0.33 100% +3.64 –0.34 90% +3.70 –0.40 50% +3.78 –0.48 30% +3.86 –0.56 17% +3.93 –0.63 10% 1 The individual value s cannot be combined for ana[...]

ADSP-TS201S Rev. C | Page 23 of 48 | December 2006 PACKAGE INF ORMATION The informat ion presented in Figure 8 provide detai ls about the package branding for the ADSP -TS201S processors. For a com- plete listing of prod uct availability, see Ordering Guide on Page 46 . ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed below may cause per[...]

Rev. C | Page 24 of 48 | December 2006 ADSP-TS201S T IMING SPECIFICATIONS With the exception of DMAR3–0 , IRQ3–0 , TMR0E, and FLAG3–0 (input only) pins, all ac timing for the ADSP-TS201S processor is relative to a refe rence clock edge. Because input setup/hold, output valid/hold, an d output enable/disable times are relativ e to a clock ed g[...]

ADSP-TS201S Rev. C | Page 25 of 48 | December 2006 Table 23. R eference Clocks—System Clock (SCLK) Cycle Time Par am et e r De s cr i pt io n SCLKRA T = 4 × , 6 × , 8 × , 10 × , 12 × SCLKRA T = 5 × , 7 × Unit Min Max Min Max t SCLK 1, 2, 3 System Clock C ycle Time 8 50 8 50 ns t SCLKH System Clock C ycle High Time 0.40 × t SCLK 0.60 × t [...]

Rev. C | Page 26 of 48 | December 2006 ADSP-TS201S Table 25. Power-U p Timing 1 Parameter Min Max Unit Timing Require ment t VDD_DRAM V DD_DRAM Sta ble Aft er V DD , V DD_A , V DD_IO Stable >0 ms 1 For information about power supply sequencing and monitoring solutions, pl ease visit www.analog.com/seq uencing . Figure 12. Power-Up Timing Table 2[...]

ADSP-TS201S Rev. C | Page 27 of 48 | December 2006 Table 27. Norm al Reset Timing Parameter Min Max Unit Timing Requ irements t RST_IN RST_IN Asserted 2 ms t STRAP RST_IN Deasserted After Strap Pins Stable 1.5 ms Switching Char acteristic t RST_OUT RST_OUT Dea sser t ed Af ter R ST_ IN D easserted 1.5 ms Figure 14. Norma l Reset Timing Table 28. On[...]

Rev. C | Page 28 of 48 | December 2006 ADSP-TS201S Table 29. AC Signal Specifications (A ll values in this table are in nanosec onds.) Name Descrip tion Input Setup (Min) Input Hold (Min) Output V alid (Max) Output Ho ld (Min) Output Enab le (Min) 1 Output Disable (Max) 1 Reference Clock ADDR31–0 External Address Bus 1.5 0.5 4.0 1.0 1.15 2.0 SCLK[...]

ADSP-TS201S Rev. C | Page 29 of 48 | December 2006 DS2–0 8 Static Pins—Must Be C onstant — — — — — — — SCLKRA T2–0 8 Static Pins—Must Be C onstant — — — — — — — ENEDREG Static P ins—Must Be Connected to V SS ——————— STRAP S YS 9, 10 S t r a p P i n s 1 . 5 0 . 5 ————S C L K JT AG S YS 11, [...]

Rev. C | Page 30 of 48 | December 2006 ADSP-TS201S Link Port Low V oltage, Differential-Signal (L VDS) Electrical Char acteristics , and T iming Table 30 and Table 31 with Figure 16 provide the elect rical characteristics fo r the LVDS link ports. The LV DS link port sig- nal definitions represent all differential signals with a V OD =0V level and [...]

ADSP-TS201S Rev. C | Page 31 of 48 | December 2006 Link P ort —Da ta Ou t T imi ng Table 32 with Fi gure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , and Figure 23 provide the data out timing for the LVDS link ports. Table 32. Link Port—Data Out Timing Parameter Descripti on Min Max Unit Outputs t REO Ris in g Edg e ( Fi g u re 1 9 )3 5[...]

Rev. C | Page 32 of 48 | December 2006 ADSP-TS201S Figure 18. Link Ports—Output Clock Figure 19. Link Ports—Di fferential Output Signals Transition Time LxCLKOUT V OD =0 V t COJT t LCLKOL t LCLK OH t LCLK OP + | V OD | MIN - | V OD | MIN V OD =0 V t REO t FEO V O_N V O_P R L C L C L_P C L_ N R L =1 0 0 ⍀ C L =0 . 1 p F C L_P =5 p F C L_N =5 p[...]

ADSP-TS201S Rev. C | Page 33 of 48 | December 2006 Figure 22. Link Ports—Transmissi on End and Stops Figure 23. Link Port s—Back to Back Transmission LxCLKO UT LxDAT O V OD =0 V V OD =0 V FIRST EDGE OF 5TH SHOR T WORD IN A QUAD WORD t LAC K IS t BCMPO H LxACKI LxBCMPO t LACKIH L A S TE D G EI NAQ U A DW O R D LxCLKO UT LxDAT O V OD =0 V V OD =0[...]

Rev. C | Page 34 of 48 | December 2006 ADSP-TS201S Link P ort —Da ta I n T imin g Table 33 with Figure 24 and Figure 25 provide the data in timing for the LVDS link ports. Table 33. Link Port—Data In Timing Par ameter Description Min Max Unit Inputs t LC LK I P LxCLKIN Period ( Fi g u r e 2 5 )G r e a t e r o f 1 . 8 or 0.9 × t CCLK 1 12.5 ns [...]

ADSP-TS201S Rev. C | Page 35 of 48 | December 2006 Figure 25. Link Ports— Da ta Input Setup and Hold 1 1 These parame ters are valid fo r both clock ed ges. LxCLKIN LxDATI V OD =0 V V OD =0 V t LDIS t LDI H t LD IS t LDIH t LCLKI P[...]

Rev. C | Page 36 of 48 | December 2006 ADSP-TS201S OUTPUT DRIV E CURR ENTS Figure 26 through Figure 33 show typical I–V characteristics for the output drivers of the ADSP-T S201S processor. The curves in these diagrams represent the current driv e capability of the out- put drivers as a function of output voltage ove r the range of drive strength[...]

ADSP-TS201S Rev. C | Page 37 of 48 | December 2006 T EST CONDITIONS The ac signal specific ations (timing p arameters) appear in Table 29 on Page 28 . These include output disable time, output enable time, and ca pacitive loading. The t iming specifications for the DSP apply for the voltage reference levels in Figure 34 . Output Disabl e Ti me Outp[...]

Rev. C | Page 38 of 48 | December 2006 ADSP-TS201S Output Enable Time Output pins are consid ered to be enabled wh en they hav e made a transition from a high impedance state to when the y start driv- ing. The time for the voltag e on the bus to ramp by Δ V is dependent on the capacitive loa d, C L , and the drive current, I D . This ramp time can[...]

ADSP-TS201S Rev. C | Page 39 of 48 | December 2006 Figure 41. Typical Outp ut Rise and Fall Time (10% to 90%, V DD_IO =2 . 5V ) vs. Load Capacitance at Stre ngth 4 Figure 42. Typical Outp ut Rise and Fall Time (10% to 90%, V DD_IO =2 . 5V ) vs. Load Capacitance at Stre ngth 5 Figure 43. Typical Outp ut Rise and Fall Time (10% to 90%, V DD_IO =2 . 5[...]

Rev. C | Page 40 of 48 | December 2006 ADSP-TS201S EN VIRONMENTAL C ONDITIONS The ADSP-TS201S processor is rated for performance under T CASE environmental conditions specified in the Operating Con- ditions on Page 21 . Thermal Characteristic s The ADSP-TS201S processor is packaged in a 25 mm × 25 mm, thermally enhanced ball gr id array (BGA_ED). [...]

ADSP-TS201S Rev. C | Page 41 of 48 | December 2006 576-BALL BGA_ED PIN CONFIGURATIONS Figure 46 shows a summary of pin configurations for the 576-ball BGA_ED package and Table 35 lists the signal-to-ball assignments. Figure 46. 576-Ball BGA_ED Pin Configura tions 1 (Top View, Summary) 1 For a more detailed pin summary diagram, see the EE-179: ADSP-[...]

Rev. C | Page 42 of 48 | December 2006 ADSP-TS201S Table 35. 576 -Ball (25 mm × 25 mm) BGA_ED Ball Assignments Ball No . Signal Name Ball No. Signal Name Ball No . Signal Name Ball No . Signal Name A1 V SS B1 DA T A53 C1 V SS D1 DA T A55 A2 DA T A51 B2 V SS C2 V SS D2 DA T A56 A3 V SS B3 V SS C3 V SS D3 DA T A54 A4 DA T A4 9 B4 DA T A5 0 C4 DA T A[...]

ADSP-TS201S Rev. C | Page 43 of 48 | December 2006 J1 RAS K1 SDA10 L1 SDWE M1 BR3 J2 CAS K2 SDCKE L2 BR0 M2 SCLKRA T1 J3 V SS K3 LDQM L3 BR1 M3 BR5 J4 V REF K4 HDQM L4 BR2 M4 BR6 J5 V SS K5 V DD_IO L5 V DD_IO M5 V DD_IO J6 V DD K6 V DD L6 V DD M6 V DD J7 V DD K7 V DD L7 V DD M7 V DD J8 V SS K8 V SS L8 V SS M8 V SS J9 V SS K9 V SS L9 V SS M9 V SS J1[...]

Rev. C | Page 44 of 48 | December 2006 ADSP-TS201S U1 MSSD0 V1 MSSD2 W1 CONTROLIMP0 Y1 EMU U2 RST_OUT V2 DS2 W2 ENEDREG Y2 TCK U3 ID2 V3 POR_IN W3 TDI Y3 TMR0E U4 DS1 V4 CONTROLIMP1 W4 TDO Y4 FLAG3 U5 V DD_IO V5 V SS W5 V DD_IO Y5 V SS U6 V DD V6 V DD W6 V DD Y6 V DD_IO U7 V DD V7 V DD W7 V DD Y7 V SS U8 V SS V8 V DD W8 V DD Y8 V DD_IO U9 V SS V9 V[...]

ADSP-TS201S Rev. C | Page 45 of 48 | December 2006 OUTLINE DIMENSIONS The ADSP-TS201S processor is available in a 25 mm × 25 mm, 576-ball metric thermally enhanced ball grid array (BGA_ED) package with 24 rows of balls (BP-576). SUR FACE MOUNT DESIGN Table 36 is provided as an ai d to PCB design. For industry- standard design recommendations, refe[...]

Rev. C | Page 46 of 48 | December 2006 ADSP-TS201S ORDERING GUIDE Model T emperature Range 1 1 Represents case tem perature. Instruct ion Rat e 2 2 The instruction rate is the same as the internal processor core clock (CCLK) rate. On-Chip DRAM Operating V oltage Package Opti on Package Description ADSP- TS201SABP -060 –40°C to +85°C 600 MHz 24M[...]

ADSP-TS201S Rev. C | Page 47 of 48 | December 2006[...]

Rev. C | Page 48 of 48 | December 2006 ADSP-TS201S © 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D 04324-0-11/06(C)[...]