Compaq EV68A manuale d’uso

Compaq Computer Cor poration Sh rewsbur y , Massach use tt s 212 64/ EV68A Microp rocessor Hardw are Refere nce Man ual Part Number: DS–0038B–T E This man ual i s directly de rived from the internal 2126 4/EV68A Specif ications, Revi- sion 1.1. Y ou can access this hardware reference manual in PDF format from the follo win g sit e: ftp: //ftp. [...]

Mar ch 2002 The i nfor ma tion in t hi s pub lica tion i s sub j e ct to cha nge withou t not ice . COMP AQ COMPUTER C ORPORA TION SHALL NOT BE L IABLE F OR TECHNICA L OR EDITORIAL ERRORS OR OMISSIONS CONT AINE D HEREIN, NOR FOR INCIDENT AL OR CONSEQUENTIAL DAM- AGES RESUL TING FROM THE FURNISHING , PE RFORMANCE, OR USE OF THIS MA TERIAL. THIS INFO[...]

21264/EV 68A Hardware Refere nce Manu al iii T able of Content s Pre face 1 Int ro duc tio n 1 . 1 T h eA r c h i t e c t u r e ... ..... ...... ...... ........... ........... ...... ..... ..... 1 – 1 1 . 1 . 1 A d d r e s s i n g .... ..... ............ ........... ..... ...... ........... ..... 1 – 2 1.1. 2 Int eger Dat a Types. . . ...... ..[...]

iv 21264/ EV68A Har dware R eferenc e Man ual 2 . 3 . 1 I n s t r u c t i o nG r o u pD e f i n i t i o n s ....... ..... ........... ............ ..... ..... 2 – 1 7 2 . 3 . 2 E b o x S l o t t i n g .. ..... ...... ........... ........... ...... ........... ..... 2 – 1 8 2 . 3 . 3 I n s t r u c t i o nL a t e n c i e s ............. .........[...]

21264/EV 68A Hardware Refere nce Manu al v 4 . 4 V i c t i mD a t aB u f f e r.. ..... ...... ...... ..... ...... ........... ........... ..... 4 – 8 4.5 Cac he Coherency . . ........... ...... ..... ...... ..... ............ .......... 4 – 8 4.5. 1 Cac he Coherency Bas i cs .......... ........... ..... ............ .......... 4 – 8 4 . 5 . 2[...]

vi 21264/ EV68A Har dware R eferenc e Man ual 5 . 1 . 4 V i r t u a l A d d r e s sC o n t r o lR e g i s t e r–V A _ C T L ........... ...... ...... .......... 5 – 4 5 . 1 . 5 V i r t u a l A d d r e s sF o r m a tR e g i s t e r–V A _ F O R M .......... ............ .......... 5 – 5 5 . 2 I b o xI P R s ......... ..... ...... ...... .....[...]

21264/EV 68A Hardware Refere nce Manu al vii 6 . 5 . 3 H a r d w a r eS t r u c t u r eo fI m p l i c i t l yW r i t t e nI P R s .......... ...... ...... ..... ..... 6 – 9 6 . 5 . 4 I P R A c c e s sO r d e r i n g ....... ...... ..... ...... ..... ............ .......... 6 – 9 6 . 5 . 5 C o r r e c tO r d e r i n go fE x p l i c i tW r i t e [...]

vi ii 21264/ EV68A Har dware R eferenc e Man ual 7 . 1 1 . 2 . 1 G C L K ......... ............ ........... ........... ...... .......... 7 – 1 9 7.11. 2.2 D iffer ential 2126 4/EV68A Clock s ........... ........... ........... ..... 7 – 1 9 7.11. 2. 3 Nomi nal Op er ati ng Frequency . . ........... ..... ...... ...... ..... ..... 7 – 1 9 7 .[...]

21264/EV 68A Hardware Refere nce Manu al ix 1 1 . 5 . 2 S R O MI n i t i a l i z a t i o n ... ...... ........... ........... ...... ...... .......... 1 1 – 5 1 1 . 5 . 2 . 1 S e r i a lI n s t r u c t i o nC a c h eL o a dO p e r a t i o n .......... ...... ...... ..... ..... 1 1 – 6 11.6 Notes on IEEE 1149. 1 Operati on and Compli ance ......[...]

x 21264/ EV68A Har dware R eferenc e Man ual D . 2 6 R e s t r i c t i o n3 0:H W _ M T P R a n d H W _ M F P Rt ot h eC b o xC S R ....... ........... ..... D – 1 5 D.27 Restr icti on 31 : I _CTL[VA_48] Up date . . . ..... ...... ..... ...... ...... .......... D – 1 7 D . 2 8 R e s t r i c t i o n3 2:P C T R _ C T LU p d a t e .......... .....[...]

21264/EV 68A Hardware Refere nce Manu al xi Fig ur es 2–1 21264/EV68A Blo ck Diagram .......... ........... ........... ...... ..... ..... 2 – 3 2 – 2 B r a n c hP r e d i c t o r ... ........... ........... ...... ..... ............ .......... 2 – 4 2 – 3 L o c a lP r e d i c t o r ......... ...... ...... ..... ...... ........... .......[...]

xi i 21264/ EV68A Har dware R eferenc e Man ual 5 – 3 4 D c a c h eS t a t u sR e g i s t e r ......... ...... ........... ........... ...... ..... ..... 5 – 3 2 5 – 3 5 C b o xD a t aR e g i s t e r ...... ............ ........... ........... ...... ..... ..... 5 – 3 3 5 – 3 6 C b o xS h i f tR e g i s t e r...... ............ ..........[...]

21264/EV 68A Hardware Refere nce Manu al xiii Tab l es 1–1 Integer Data Types . ..... ............ ........... ..... ...... ........... ..... 1 – 2 2 – 1 P i p e l i n eA b o r tD e l a y( G C L KC y c l e s ) .......... ........... ...... ........... ..... 2 – 1 6 2 – 2 I n s t r u c t i o nN a m e ,P i p e l i n e ,a n d T y p e s .....[...]

xi v 21264/ EV68A Har dware R eferenc e Man ual 4–34 Rul es f or System Cont rol of Cach e Status Updat e O rder ........... ...... ..... ..... 4 – 4 2 4 – 3 5 R a n g eo fM a x i m u mB c a c h eC l o c kR a t i o s . ........... ........... ...... ..... ..... 4 – 4 3 4 – 3 6 B c a c h eP o r tP i n s ........ ...... ...... ........... .[...]

21264/EV 68A Hardware Refere nce Manu al xv 7–6 Effect on IPRs Aft er Transi tion Thr ough Sleep M ode . . . ..... ...... ........... ..... 7 – 1 0 7–7 Signals and Cons t rai nts for t he Sleep Mo de Sequence . ..... ................. ..... 7 – 1 1 7 – 8 E f f e c to nI P R sA f t e rW a r mR e s e t . ...... ..... ........... ...........[...]

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21264/EV 68A Hardware Refere nce Manu al xvi i Pref ac e Au dience This man ual is f or s ystem de signer s and progr ammers who use the Alpha 21264/ EV68A microproc essor (r e ferred to a s t he 21264/ EV68A). Content This m anual conta ins the followi ng chapters a nd append ixes: Chapte r 1, Introduc tion, int r oduces the 21 264/EV68A and provi[...]

xvi i i 21264/ EV68A Har dware R eferenc e Man ual Appendi x C, Seri al Ic ache Load Predecode V al ues, pr ovides a pointer to the Alp ha Motherb oards Soft ware Developer’ s Kit (SDK), which contains this inf ormati on. Appendi x D, P ALcode Restric ti ons and Guidelines , lists restr icti ons a nd guidel ines that must be adhe red to when gene[...]

21264/EV 68A Hardware Refere nce Manu al xix T ermino logy and Co nven t io ns This sectio n defines the abbr evia tions , terminol ogy , and other conve ntions use d throu ghout thi s document. Abbreviations • Binar y Multip le s The abbreviati ons K, M , and G (kilo, mega, a nd giga) repres ent binary multiples and have the fol lowing value s. [...]

xx 21264/ EV68A Har dware R eferenc e Man ual • Sign exte nsion SEXT(x) mea ns x is sign-exte nded to the re quired si ze. Addresses Unless ot herwis e noted, all addr esses and of fsets a re hexadec imal. Al igne d and U n al ig n ed The terms aligned and nat urally aligned are interchangeable a nd r efer to data obj e cts that are powers of two[...]

21264/EV 68A Hardware Refere nce Manu al xxi Dat a Unit s The following da ta unit te rminology is used th roughout this m anual. Do Not Care (X) A capi tal X repres ents any va lid val ue. Exte rn al Unless ot herwis e stated, exte rnal means not co ntained in the chip. Fiel d Notatio n The names of singl e-bit and mult iple-bit f ields c an be us[...]

xxi i 21264/ EV68A Har dware R eferenc e Man ual Alpha S igna l[n:n ] Boldfa ce, mixed-ca se type denotes signa l names that ar e assi gned int e rnal a nd e xter nal t o the 21264/ EV68A (th a t is, the signa l tr averse s a c hip i nter face pin). AlphaSig nal_ x [n:n ] When a signal has high and low asse rtion state s, a lower- case ita lic x re[...]

21264/EV 68A Hardware Refere nce Manu al xx iii X Do not care . A ca pital X repres ent s a ny valid val ue.[...]

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21264/EV 68A Hardware Refere nce Manu al Introduc tion 1–1 1 Introduction This cha pter pr ovi des a brie f intr oductio n to the Alpha architect ure , Com paq ’ s RIS C (red uced instruc ti on set computing) a rc hitectur e designed f or high perfo rmance. The chapte r then summarize s the specif ic featur es of the Alpha 21264/EV68A micropr o[...]

1–2 I ntroduction 21264/ EV68A Har dware R eferenc e Man ual Th e Arc hit ect u re The Alpha a rchi tect ure pe rforms byt e shifti ng and maski ng with n ormal 64-bi t, r egis- ter -to-regi ster ins truct ions. Th e 21264/ EV68A p erform s single-byt e and si ngle- word load and stor e instr uctions. 1. 1.1 Add ressin g The bas ic addr essab le [...]

21264/EV 68A Hardware Refere nce Manu al Introduc tion 1–3 2 1264/EV 68A Mi cropr oc essor F eatur es 1.2 2126 4/EV 68A M icr opr oces so r Fe atur es The 21264/EV6 8A micropr ocessor i s a superscalar pi pelined processor . It i s packa ged in a 587-pin PGA carri er and has removabl e application - specif ic heat sinks . A number of con figur at[...]

1–4 I ntroduction 21264/ EV68A Har dware R eferenc e Man ual 21264/E V68A M icr opr ocesso r Feat ures • An onchip, du plica te tag a rray u sed t o mai nta in lev el 2 cac h e cohe rency . • A 64-bit data bu s with onch ip parity and error corr ec tion code (ECC) su ppor t. • Support for an exter nal s econd-le vel (Bc ache) c ache. The si[...]

21264/EV 68A Hardware Refere nce Manu al Intern al A rchit ecture 2–1 2 Intern al Architec ture This chapt er provi des both an overv iew of the 2 1264/EV68A micro architect ure and a sys- tem des ign er ’ s view of th e 21 264 /EV6 8A im p leme ntat ion of th e Alp ha ar chitec tu re. The comb ina tion of th e 212 64 /EV 68A m icroa rch itectu[...]

2–2 Inte rn al A r ch it ec tu re 21264/ EV68A Har dware R eferenc e Man ual 21 264/EV 68A Mi croar chit ectur e • Floating - point ex ecuti on unit (Fbox) • Onchip cache s (Icache and Dc ache) • Memory refer ence unit ( Mbox) • Externa l cache and syste m interface un it (Cbox) • Pipeline ope rati on sequence 2. 1.1 Instr uct ion Fe tc[...]

21264/EV 68A Hardware Refere nce Manu al Intern al A rchit ecture 2–3 21264 /EV68A M icroar ch itec ture Figure 2–1 2126 4/EV68A Block Diagram 2.1.1.2 B ranch Pred ictor The branc h predi c tor is composed of t hree units: the local , global, and choice pr edic - tors . Figure 2–2 shows how the bra nch predictor gene rat es the predi cted bra[...]

2–4 Inte rn al A r ch it ec tu re 21264/ EV68A Har dware R eferenc e Man ual 21 264/EV 68A Mi croar chit ectur e Figure 2–2 Bran ch Predictor Local Pred ictor The local pre dictor u ses a 2-level table t hat holds the hi story of individua l bran ches. The 2-l evel ta ble de sign a pproac hes t he predict ion acc uracy of a l ar ger sin gle-l e[...]

21264/EV 68A Hardware Refere nce Manu al Intern al A rchit ecture 2–5 21264 /EV68A M icroar ch itec ture Figure 2–4 Glob al Pred ictor Choice Predictor The choic e predic tor m onitors t he histor y of the local and globa l predic tors a nd choose s the be st of th e two predict ors for a particula r bran ch. Figu re 2–5 shows how the c hoice[...]

2–6 Inte rn al A r ch it ec tu re 21264/ EV68A Har dware R eferenc e Man ual 21 264/EV 68A Mi croar chit ectur e 2.1.1.4 Instruction Fetch Log ic The instructi on p refe tch er (prede cod e) reads an octa word , contai ning up to four natu- rally a ligned inst r ucti ons per cycle, fr om the Icache. Bra nch predicti on and line predi c- tion bits[...]

21264/EV 68A Hardware Refere nce Manu al Intern al A rchit ecture 2–7 21264 /EV68A M icroar ch itec ture • Intege r oper ate • Intege r condit ional br anch • Uncondi tional br anch – both displ acement and memory for mat • Intege r and float ing-poin t load and store • P AL-rese rve d instruc tions : HW_MTPR, HW_MFPR, HW_LD, HW_ST , [...]

2–8 Inte rn al A r ch it ec tu re 21264/ EV68A Har dware R eferenc e Man ual 21 264/EV 68A Mi croar chit ectur e The FQ arbite rs pick b etween si multan eous request ers of a pipe line b ased on the age of the reque st—older re quests ar e given priority over newer reque st s. Floating -point st ore instr uctions a nd FTOI x inst ructions in e[...]

21264/EV 68A Hardware Refere nce Manu al Intern al A rchit ecture 2–9 21264 /EV68A M icroar ch itec ture Figu re 2– 6 In tege r Exe cut ion U nit— C lust ers 0 and 1 Most inst ructi ons have 1-cycle lat ency for consum ers that execute wi thin the sa me clus- ter . Also, there is anothe r 1-cycle de l ay associate d with produ c ing a value i[...]

2–10 Inte rn al A r ch it ec tu re 21264/ EV68A Har dware R eferenc e Man ual 21 264/EV 68A Mi croar chit ectur e The Ebox has 80 register -file entri es that contain sto rage for the values of the 31 Alpha inte ger regis ters (the v alue of R31 is not store d), the va lues of 8 P ALshadow re gisters, and 41 result s writte n by instructions tha [...]

21264/EV 68A Hardware Refere nce Manu al Intern al A rchit ecture 2–11 21264 /EV68A M icroar ch itec ture The Fbox registe r fil e contains six reads por ts and four wri te ports. Four r ead ports are used to sourc e operands to th e add and multiply pipeli ne s, and two read ports are use d to sour ce data for store instr uctio ns. T wo write po[...]

2–12 Inte rn al A r ch it ec tu re 21264/ EV68A Har dware R eferenc e Man ual 21 264/EV 68A Mi croar chit ectur e • V irtua l tag bits [ 47:15] • 8-bit addr ess spa ce number (ASN) field • 1-bit addr ess spa ce match (ASM) bit • 1-bit P ALcode bit to indicate physi cal addr essing • V alid bit • Data a nd tag p a rit y bi ts • Four [...]

21264/EV 68A Hardware Refere nce Manu al Intern al A rchit ecture 2–13 Pipe line Organiz ation • Miss address f ile (MAF) • Dstrea m translation buf fer ( DTB) 2.1.6.1 Lo ad Queue The load queue ( LQ) is a reorder buffer for load instructi ons. It conta ins 32 ent ries and mainta ins the sta te assoc iate d with load instr uctions t hat have [...]

2–14 Inte rn al A r ch it ec tu re 21264/ EV68A Har dware R eferenc e Man ual Pipe line Organizatio n Figu re 2–8 P ipeli ne Or ganiz ati on Stage 0 — Instru ction Fetch The branch predic tor uses a bra nch history algor it hm to predict a branch instruc tio n tar- get address . Up to four align ed instru ctions are fe tched from the Icach e,[...]

21264/EV 68A Hardware Refere nce Manu al Intern al A rchit ecture 2–15 Pipe line Organiz ation In the slot stage, the bra nch predictor compar es the next Icache index that it gene rates to the inde x tha t was ge nerate d by the lin e predictor . If there i s a mismatch , the bra nch predic tor w ins—the inst r uct ions f etched during that cy[...]

2–16 Inte rn al A r ch it ec tu re 21264/ EV68A Har dware R eferenc e Man ual Instr uctio n Issue Rules Stage 4 — Reg ister Read Inst ructi ons issue d from the issue que ues re ad their operands from the in teger and floa t- ing-p oint regi ster file s and receiv e bypass data. St age 5 — Execute The Ebox and Fbox pipeline s begin exec ution[...]

21264/EV 68A Hardware Refere nce Manu al Intern al A rchit ecture 2–17 Instr uction Issu e Rul es 2. 3.1 Instructi on Group Definit ions T abl e 2–2 lists the ins truction cl ass, t he pipeli ne assig nm ents, a nd the i nstruc tion s incl uded in the class . Tab le 2–2 Ins tr ucti on Nam e , Pipe line, a nd Ty pes Class Name Pipel ine Ins tr[...]

2–18 Inte rn al A r ch it ec tu re 21264/ EV68A Har dware R eferenc e Man ual Instr uctio n Issue Rules 2. 3.2 Ebox S lot ting Inst ructi ons tha t are is sued fr om the IQ, and could exec ute i n eith er upper or l owe r Ebox sub cluste rs, are s lotted to one pa ir or th e other durin g the pipe li ne mapping st age based on the ins truct ion m[...]

21264/EV 68A Hardware Refere nce Manu al Intern al A rchit ecture 2–19 Instr uction Issu e Rul es ELUU LLUU UE LE U LLU EUEE LULU UELL UULL EUEL LUUL UELU ULLU EUE U LULU UE UE ULU L EUL E LULU UE UL ULU L EUL L UULL UE UU ULU U EULU LULU UL EE U LUL EUUE LUUL ULEL ULUL EUUL LUUL ULEU ULLU EUUU LUUU ULLE ULLU LEEE LULU UL LL U LL L LEEL LUUL ULLU[...]

2–20 Inte rn al A r ch it ec tu re 21264/ EV68A Har dware R eferenc e Man ual Instr uctio n Issue Rules 2. 3.3 Instr uct ion La tencies After an instructio n is pl a ced i n the I Q or F Q, it s i ssue p oint is determine d by t he avai l- abil ity of its regist e r operands, functiona l unit(s) , and relatio nship to other instruc tions in th e [...]

21264/EV 68A Hardware Refere nce Manu al Intern al A rchit ecture 2–21 Instr uction Retire Ru les 2. 4 Ins truc tion Re tir e Rule s An instru ction is reti r ed when it has been execute d to completion , and all prev ious instr uctions have been re tire d. The exe cution pipeline stage i n which an i nstruc tion becomes el igibl e to be retire d[...]

2–22 Inte rn al A r ch it ec tu re 21264/ EV68A Har dware R eferenc e Man ual Ret ire of O perat e Instr uct ion s in to R3 1/F3 1 2.4.1 Float ing-Point D ivide/Sq uare Root E arly Ret ire The float ing-poin t divider and squa re root unit can dete ct that, for many combina tio ns of s ource op erand v alues , no exce p tion can be generated. Ins[...]

21264/EV 68A Hardware Refere nce Manu al Intern al A rchit ecture 2–23 Load Inst r uctio ns to R 3 1 and F31 2.6 Loa d Ins tr uc tio n s to R3 1 an d F3 1 This s e ctio n desc ribe s h ow the 21264/ EV68A proc esse s sof twa re-di re cted pre fetch transa ctions and loa d i nstructions with a de stina tio n of R 31 a nd F31. Prefe tches allocat e[...]

2–24 Inte rn al A r ch it ec tu re 21264/ EV68A Har dware R eferenc e Man ual Spec i al Ca ses of A lph a In str uc ti on Ex ecu t ion 2. 6.3 Prefetc h, Evict Next : LD Q and HW _LDQ Inst ructio ns The 21264/EV6 8A proc esses t his inst ructi on l ike a n or mal p refetch t ransac tio n (Rea d - BlkSpec c ommand), with one exception — if t he l[...]

21264/EV 68A Hardware Refere nce Manu al Intern al A rchit ecture 2–25 Speci al Case s o f A lpha In str uction Executio n For example, in F igure 2–9 , instructi on 1 and instr uctio n 2 are issue d within th e specu- lati ve window of the loa d instruc ti on. If the load ins truction hits, the n both ins tructions will be deleted fr om the q [...]

2–26 Inte rn al A r ch it ec tu re 21264/ EV68A Har dware R eferenc e Man ual Spec i al Ca ses of A lph a In str uc ti on Ex ecu t ion If instr uction 1 is dep endent on the loa d instruc tion data and the load ins truct ion hits , instr uction 1 is removed f rom the que ue one c ycle la ter ( at t he start of cycle 8). If the load ins truct ion [...]

21264/EV 68A Hardware Refere nce Manu al Intern al A rchit ecture 2–27 Me mory a nd I/O Ad dr ess Spa ce Instr uc tion s The Ebox execute s inte ger CMOV ins tructions as two di stinct 1- cycle late ncy op era- tions. The Fbox ad d pipelin e exec utes f loating- point C MOV instr uctions a s t wo distinc t 4-cyc le late ncy o perations . 2.8 Mem [...]

2–28 Inte rn al A r ch it ec tu re 21264/ EV68A Har dware R eferenc e Man ual Memo ry and I/O Addr ess Space Inst ructio ns The Mbox alloca tes a new MAF entry to a n I/O load inst r ucti on and increases I /O band- width by a ttempt ing to mer ge I / O load instruc tio ns in a mer ge r egister . T able 2–7 shows the rule s for mergi ng data. T[...]

21264/EV 68A Hardware Refere nce Manu al Intern al A rchit ecture 2–29 Me mory a nd I/O Ad dr ess Spa ce Instr uc tion s SQ entr y data that has not be en t ransfe rred to the Dcache m ay sourc e data to newer load instr uctions . The M bo x compares t he virtu a l Dcache i ndex bits of inc oming load instr uctions to que ued SQ entri es, and sou[...]

2–30 Inte rn al A r ch it ec tu re 21264/ EV68A Har dware R eferenc e Man ual MA F Memory Addr ess Space Mer ging Rul es 2.9 MAF Mem or y Add ress Space Mer ging Ru les Because all memo ry transa ctions are to 64-byt e blocks, ef ficiency is improved by merg- ing seve ral sm all da ta tr ansa ctions into a si ngle lar ger data t r ansac tion. T a[...]

21264/EV 68A Hardware Refere nce Manu al Intern al A rchit ecture 2–31 Re pla y Tr aps The 21264/EV6 8A maintains the def ault I/O instr uction or deri ng as shown in T able 2– 1 1 ( assum e addres s X an d addres s Y are di f fe rent). 2.1 1 Repl ay T raps There ar e some situat ions in which a load or stor e instr uction cannot be e xecute d [...]

2–32 Inte rn al A r ch it ec tu re 21264/ EV68A Har dware R eferenc e Man ual I/O W rit e Buf fer an d the W MB I nst ructio n The Ibox contains extra hardware to reduce the f re quency of the stor e-loa d trap. T here is a 1-bit by 1024-entr y VP C-inde xed table in the Ibox calle d the stW ait table. When an Icache i nstruc tion is fe tched, th[...]

21264/EV 68A Hardware Refere nce Manu al Intern al A rchit ecture 2–33 I/O Write Buffer and the WMB Instru ction 2.12.1.1 M B Ins truction Pro cessing When an MB instruction is fetched in the predic ted instr uctio n execution pa th, it st alls in th e map sta ge of t he pip eline. This also sta lls all instructi ons afte r the MB, and con- trol [...]

2–34 Inte rn al A r ch it ec tu re 21264/ EV68A Har dware R eferenc e Man ual I/O W rit e Buf fer an d the W MB I nst ructio n c. Whe n a probe response ha s been sent to th e system for the marked prob e queue entry , t he Cbox consi ders the WM B to be sa tisfie d. • If Cbox C SR SYSBUS_MB_ENABLE is set, the Cbox p erforms the f ol lowing act[...]

21264/EV 68A Hardware Refere nce Manu al Intern al A rchit ecture 2–35 Perf orman ce M easure m ent S uppo r t—P erfor mance C oun ters 2. The integer queue issues a HW _MTPR instr uction wit h a D TB_P TE0, that is data- depende nt on t he HW_LD i nstruc tion wit h a VP TE, a nd i s re quire d in or der t o fil l the DTBs. The HW_MTPR instruc [...]

2–36 Inte rn al A r ch it ec tu re 21264/ EV68A Har dware R eferenc e Man ual Fl oat ing -Poi n t Co nt rol R egi ster Figure 2–11 Flo ating-Point Control Reg ister The floating- poin t control regist er fields are described in T able 2–14. Table 2–1 4 Floati ng-Point Co ntrol Register Fields Name Extent Type Descriptio n SUM [63] R W Summa[...]

21264/EV 68A Hardware Refere nce Manu al Intern al A rchit ecture 2–37 AMA SK a nd IMPL VE R I nstr uct i on Va lue s 2. 15 AMAS K an d IMPL VER I nstru ct io n V alue s The AMASK and IMPL VER instructions return the suppo rted archit ecture exte nsi ons and processor type , respective ly . DYN [59:58] R W Dyna mic r ounding mo de. Indic ates the[...]

2–38 Inte rn al A r ch it ec tu re 21264/ EV68A Har dware R eferenc e Man ual Des ign Ex ampl es 2. 15.1 AM ASK The 2 1264/EV68A return s the AMAS K instructi on value s provided i n T able 2–15. The I_CTL registe r repor ts the 21264/EV68 A pass level (see I_CT L[CHIP_ID] , Section 5.2. 15). The AMASK bit definit ions provide d in T a ble 2–[...]

21264/EV 68A Hardware Refere nce Manu al Intern al A rchit ecture 2–39 Desig n Exa mples Figure 2–12 Typical Un iproce ssor Confi guration Figure 2–13 shows a typic al multiproc essor s ystem, each process or with a second-le vel cache. Each interfa ce con trolle r must employ a dupl icate tag s tore to maint a in ca che coher ency . Thi s sy[...]

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21264/EV 68A Hardware Refere nce Manu al Hardware Interface 3–1 3 Hard ware In te rfac e This c hapte r c ontains the 21264/ EV68A mic ropro cessor logic sym bol a nd provide s inform ation abo ut signa l names, the ir functi on, and thei r location . This chapter also descr ibes the mecha nical spec ificat ions of the 21264/EV68A. It is or ganiz[...]

3–2 Hardware I n terface 21264/ EV68A Har dware R eferenc e Man ual 21264/E V68A M icr opr ocesso r Logic S ymbo l Figure 3–1 2126 4/EV68A Micro process or Lo gic Sym bol 2126 4 Sy ste m Inte r fac e Bc ache I nte rfac e Sy sA ddIn _L [14 :0 ] SysA ddI nCl k_ L Sy sA ddO ut_ L[ 14: 0] Sy sA ddO utCl k _L SysV ref Sy sD ata_ L[ 63: 0] Sy sC he c[...]

21264/EV 68A Hardware Refere nce Manu al Hardware Interface 3–3 2 1264/ EV68A Sig nal Names and Fu nc tions 3. 2 2 12 64 /E V6 8A Si gna l Name s and Fun ctio ns T abl e 3–1 defines the 21264/EV6 8A signal types re f erred t o in this section . T abl e 3–2 list s all signal pi ns in alphabeti c or der a nd provi des a ful l f uncti onal de sc[...]

3–4 Hardware I n terface 21264/ EV68A Har dware R eferenc e Man ual 21 264/EV 68A Sign al Names and Fu nct ions BcDataOutClk_H[ 3:0] BcDataOutClk_L[3: 0] O_PP 8 Bca che dat a output c locks . These fre e-r unnin g clocks are dif- ferent ial copi es of the Bca che clock and are der ived from t he 21264/E V68A GCLK. T heir period i s a mul tiple o [...]

21264/EV 68A Hardware Refere nce Manu al Hardware Interface 3–5 2 1264/ EV68A Sig nal Names and Fu nc tions FrameClk _H FrameClk _L I_ DA_CLK 2 A skew-con trol led dif ferentia l 50% duty cyc le copy of the s ys- tem clock . It is us ed by the 21264 /E V68A as a refer ence, or framing, clock. IR Q_H[5 :0] I_DA 6 These six interr upt signal line s[...]

3–6 Hardware I n terface 21264/ EV68A Har dware R eferenc e Man ual 21 264/EV 68A Sign al Names and Fu nct ions T abl e 3–3 lists signa ls by function and provide s an abbre viate d descripti on. SysV ref I_DC_REF 1 System interface reference voltage . Tc k _ H I_DA 1 IEEE 1 149.1 te st clo ck. Tdi_H I_ DA 1 IEEE 1 149.1 te st data-i n signal .[...]

21264/EV 68A Hardware Refere nce Manu al Hardware Interface 3–7 2 1264/ EV68A Sig nal Names and Fu nc tions BcV r ef I_ DC_REF 1 T ag data input refer e nce vol ta ge. SysV ref Do main SysA ddIn_L [14:0] I_DA 15 T ime-multi pl exed SysAdd In, sys tem- to-21 264/ EV68A. SysA ddInClk_ L I_ DA 1 Single -en ded forwarde d clock from syst em for SysAd[...]

3–8 Hardware I n terface 21264/ EV68A Har dware R eferenc e Man ual Pin A ssign men ts 3.3 Pi n Assi gn men ts The 21264/EV6 8A package has 587 pins ali gned in a pin grid array (PGA) desig n. There are 380 functiona l s ignal pins, 1 de dica ted 2. 5-V pi n for the PLL, 112 g r ound VSS pin s, and 94 VDD pins. T able 3–4 li sts the signal pin [...]

21264/EV 68A Hardware Refere nce Manu al Hardware Interface 3–9 P in As si gn ment s BcDat a_H_ 106 L4 5 BcDat a_H_ 107 N45 BcD a ta_H _10 8 T44 BcDat a_H_ 109 U45 BcData_H _ 1 1 M2 B c Da ta _H _110 W45 BcData_H _ 1 1 1 AA43 BcData_H _ 1 12 AC43 Bc D ata _H _113 AD44 BcData_H _ 1 14 AE41 BcDat a_H_ 1 15 AG45 B c Da ta _H _116 AK44 BcData_H _ 1 1[...]

3–10 Hardware I n terface 21264/ EV68A Har dware R eferenc e Man ual Pin A ssign men ts BcData_H _ 9 K2 BcData_H _ 90 BA3 Bc D ata _H _91 BC3 BcData_H _ 92 BD6 BcData_H _ 93 BA9 Bc D ata _H _94 BC9 BcData_H _ 95 AY 1 2 BcData_H _ 96 A39 Bc Da ta _H _9 7 D36 BcData_H _ 98 A41 BcData_H_ 99 B42 BcDataInClk_H_0 E7 BcDataInClk_H_1 R3 BcDataI nClk_H_2 [...]

21264/EV 68A Hardware Refere nce Manu al Hardware Interface 3–11 P in As si gn ment s SysA ddIn_L_5 BA27 Sys AddIn_L_6 BD2 8 SysA ddIn _L_7 BE27 SysA ddIn_L_8 AY 2 6 SysAddIn _L_9 BC25 SysAddIn Clk_L BB2 6 SysAddO ut_L_0 AW 3 3 Sys AddOut _L_1 BE39 Sys AddOut_L_10 BE3 3 SysAddO ut_L_1 1 AW 2 9 SysAddOut _L_12 BC31 SysAddO ut_L_13 AV 2 8 SysA ddOu[...]

3–12 Hardware I n terface 21264/ EV68A Har dware R eferenc e Man ual Pin A ssign men ts SysData OutClk_L_5 R4 1 Sys Data OutClk_L_ 6 AH4 0 SysD ataOutCl k_L_ 7 AW 3 9 SysD ataOutV alid_L BB2 2 Sys Fil lV al id _L BC23 SysVref BA2 5 Tc k _ H BE19 Tdi _H BA21 Tdo_ H BB20 T est S tat_H BA19 Tms_H BD18 Tr s t _ L AY 2 0 Table 3–5 P in List So rted [...]

21264/EV 68A Hardware Refere nce Manu al Hardware Interface 3–13 P in As si gn ment s AR1 BcD ata _H_22 AR3 Spare AR3 9 Sy sDat a_L_58 AR43 Bc Data OutC lk _H_3 AR45 BcDat a_H_ 1 19 AR7 SysDat a_L_ 25 AT 2 BcChec k_H_2 AT 3 8 Sy sD a ta_ L _ 59 AT 4 S p a r e AT 4 2 Bc Data OutClk_L _ 3 AT 4 4 BcCheck_ H_14 AT 8 SysData_L_ 26 AU3 Bc Data OutClk_H[...]

3–14 Hardware I n terface 21264/ EV68A Har dware R eferenc e Man ual Pin A ssign men ts BC25 SysAddI n_L_9 BC29 Sys AddIn_L_1 BC3 Bc Data _H_91 BC31 SysAddO u t_L_12 BC3 5 Sys AddOut _L_3 BC37 BcChec k_H_7 BC41 BcD ata _H_12 5 BC4 3 BcData_H _ 60 BC5 BcData InClk_H_3 BC9 BcD ata _H_94 BD10 BcCheck_ H_1 1 BD12 Pll Bypas s_H BD16 Reset_L BD18 Tms_H[...]

21264/EV 68A Hardware Refere nce Manu al Hardware Interface 3–15 P in As si gn ment s G39 SysDat a_L_37 G41 BcDat a_H_ 38 G45 BcD ata_H _10 4 G5 BcD ata _H_70 G7 Sys Data _L_5 H10 SysDat a_L_4 H12 SysDat a_L_3 H16 BcT ag_H_ 21 H18 Bc T a g _H_29 H22 BcT ag_H_42 H24 BcT agOE_L H28 Bc Add_H_13 H30 BcAdd_H_2 1 H34 Sy sD at a_ L _34 H3 6 SysDat aOutC[...]

3–16 Hardware I n terface 21264/ EV68A Har dware R eferenc e Man ual Pin A ssign men ts T abl e 3–6 lists the 21264 /EV68A ground and power ( VSS and VDD , respectiv ely) pin list. Tab le 3–6 G round a nd P ow er (VS S an d VDD ) Pin Li st Signal PGA Location VSS A15 A21 A25 A3 A3 1 A37 A43 A9 AA1 AA39 AA45 AA7 AC41 AC5 AE1 AE39 AE45 AE7 AG3 [...]

21264/EV 68A Hardware Refere nce Manu al Hardware Interface 3–17 Mech anic al Spec ifications 3.4 Me chan ica l Sp eci fic ation s This sectio n shows the 21264/EV68A mechanic al package di mensions wit hout a heat sink. F or heat sink inf ormation and dimension s, refer to Chapter 10. Figure 3–2 shows the pa ckage p hysical d imensio ns withou[...]

3–18 Hardware I n terface 21264/ EV68A Har dware R eferenc e Man ual 21264/E V68A P ack agin g 3.5 212 64 /EV68A P ac kagin g Figure 3–3 sho ws the 21264/ EV68A p inout from the to p view with pins fa cing do wn. Figure 3–3 2126 4/EV68A To p View (Pin Do wn)[...]

21264/EV 68A Hardware Refere nce Manu al Hardware Interface 3–19 21264/E V68A P acka gin g Figure 3–4 sho ws the 21264/EV68A pinout f rom the bottom view with pins f acing up. Figure 3–4 2126 4/EV68A Bottom Vie w (Pin Up)[...]

[...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4–1 4 Cache a nd Extern al Inter face s This c hapte r de scr ibes t he 21264 /EV68A cache and exte rna l i nter face, wh ich in c ludes the sec ond- le vel cach e (Bc ache ) interfa ce and th e system interface. It also describes locks , interr upt signals, and ECC/par ity ge[...]

4–2 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual In trod uction to th e Externa l Int er face s • The Bcache i nterface inc ludes a 128-bi t bidire ctiona l data bus, a 20-bit unidirec- tiona l address bus, a nd several con trol signa ls. – The BcDataOutClk_ x [3:0] clocks are fre e-runni ng and are derived f rom [...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4–3 In tr od uct i on to th e Exte r nal I nte rf ace s Figure 4–1 2126 4/EV68A System and Bcac he Interfaces 4. 1.1 System I n te rface This sectio n introduc es the system (e xternal) bus int erface. T he sy ste m inter face is made up of two unidirec tional 15- bit addres[...]

4–4 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Phy sical Addr ess Conside rations 4.1.1.1 Comm and s and Address es The syste m sends probe and dat a movement c ommands to t he 21264/ EV68A. The 21264/EV68A can hold up to ei ght probe commands fr om the system. The system c on- trol s the num ber of out standing pro[...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4–5 Ph ysica l Add res s Consid er ation s Prefe tches ( LDL, LDF , LDG , LDT , LDBU, LDWU) to R31 use the LDx f low , and prefe tch w ith m odify inte nt (LDS) use s the STx flow . If the pref etch tar get is addre ssed to I/O space, th e upper addres s bit is cleared, conver[...]

4–6 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Phy sical Addr ess Conside rations T abl e 4–1 notes: 1. Set Dirty Flow: Ba sed on the Cbox C SR SET_DIR TY_ENABLE[2:0], SetDir ty reque sts can be either i nter nally acknowle dged (calle d a SetModify) or se nt to the syste m environ ment for processing. Whe n exter[...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4–7 Bcac he S truc ture 4.3 Bcach e Struc tu re The 21264/EV6 8A Cbox p r ovide s cont rol si gnals and an i nter face for a sec ond-le vel cach e ( Bc ache) . The 21264/EV6 8A supports a Bcach e from 1MB to 16M B, with 64-byt e blocks. A 128- bit bidir ect ional dat a bus is [...]

4–8 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Vict im Da ta Bu ffer • Issui ng probes and SysDc fi ll commands to the 21264/EV68A out-of -or der with respe ct to their order at the system ser ializa tion point • Filt ering out all pr obe misses from t he 21264/EV68A cache syst em If a pr obe mis ses i n the 212[...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4–9 Cac he Coher ency Figure 4–3 Cache S ubset Hierarch y The following ta sks must be per formed to maint ain cache coheren cy: • Istream d ata fro m m em ory s pac es m ay be cac h ed in th e Icac he and Bcach e. Ic ache cohere n ce is not ma int ained b y har dw are— [...]

4–10 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Cac he Coher ency 4. 5.3 Cache Blo ck S tate T ran sition s Cache bl ock st ate tr ansiti ons are reflect ed by 21264/EV68A-gene rated commands to the syst e m. Cac he block state transi tions c an also be caused by sys tem-ge nerate d com- mands t o the 212 64/EV68A ([...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4–11 Cac he Coher ency 4. 5.4 Using SysDc Com mands Note the f ol lowing: • The conv entiona l respon se f or RdBlk comman ds is SysDc R eadData o r ReadD- ataS hared . • The conv entiona l respon se f or a RdBlkMod c ommand is S ysDc ReadDa taDirty . • The convent ional[...]

4–12 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Cac he Coher ency RdBlkModx Re adDat a Read DataS ha red Re a dDa ta Sh ar ed /D ir ty The cac he block i s fille d and mar ked with a nonwri ta ble st atus. If the sto re inst ruct ion t hat gene rated t he RdBl kModx comma nd is sti ll act ive (n ot kille d), t he 21[...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4 –13 Cac he Coher ency The 21264/ EV68A sends a W rV ictimBlk command to the syst em when it evicts a Dirty or Dirty/S hared c ache bloc k. The 21264/EV68A may be configur ed to send a CleanV i c- timBlk to the sys tem (by way of the Cbox CSR B C_CLEAN_VICT IM[0]) when evict-[...]

4–14 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Lock Mec hanism 1. When the Mbox request s a Dca che fil l, the Cbox uses th e CT AG array entry to f ind if the Dcach e already contai ns the reques ted physic al address in anot her virtua lly - index ed Dcache line. If it doe s, the Cbox invali dates th at cache lin[...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4 –15 Lock M echanism 4. 6.1 In-Order P rocess ing o f LDx_L /STx_ C Instru cti ons The 21264/EV6 8A uses the stW ait logic in the IQ to ensure that LDx_L/S Tx_C pairs are iss ued in order . The stW ait log ic treats an Ldx_L inst ructi on like S tx instruc ti ons. STx_C instr[...]

4–16 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Syst em Port If t he ChangeT oDirt y command s ucceeds, the STx_C enter s the writa ble state, and th e Mbox lock s the Dc ache l ine. The Mbo x does not release the Dc ache l ine unt il the STx_C data i s trans ferred t o the D cach e. This ensur es t hat no ot her ag[...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4 –17 System P ort Figure 4–4 System Interface S ignals 4. 7.1 System Port Pins T abl e 3–1 defines the 21264/EV6 8A signal types re f erre d to i n this sec tion. T able 4–6 lists the system port pin groups al ong with their type , number , and functional desc rip- tion[...]

4–18 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Syst em Port 4. 7.2 Progr ammin g the System Int er face Clock s The system forwarded clocks are free running and de ri ve d from the 21264/EV68A GCLK. The perio d of the system forwar ded clocks is co ntrolle d by three Cbox CSRs, based on the bit -rate r atio (simila[...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4 –19 System P ort T abl e 4–9 lists the pr ogra m values f or CSR SYS_FRAME_LD_VECT OR[4:0] th a t se t the r atio b etween the for warded c locks a nd the f rame cloc k. 4. 7.3 21264/E V68A-t o-System Com ma nds This s e ctio n desc ribe s t he 2126 4/EV68A-to- syst em com[...]

4–20 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Syst em Port 4.7.3.2 P age Hi t Mod e T abl e 4–11 s hows the c ommand for mat fo r page hit mode ( 21264/ EV68A-to- system). T abl e 4–12 describ es the field definit ions for T ables 4–10 and 4–1 1. C yc le 2 P A[ 2 7: 2 2] , P A [ 12: 6 ] P A [35 ] P A [37 ][...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4 –21 System P ort System designe rs can mini mize pin count for syste ms with a small memory by config- uring bot h t he ba nk inte rle ave on cache block bounda ry m ode and t he page hi t mode form ats i nto a short bus form at. T he p in SysAddOut_L [1] and/or SysAd dOut_L[...]

4–22 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Syst em Port ReadBl kMod 10001 Me mory rea d with modify i nte nt. ReadBl kI 10010 Memo ry r ead fo r I s trea m. FetchBl k 1001 1 Non cached me mory read. ReadBl kSpec 2 10100 Specul ative memor y re ad (opti onal ). ReadBl kModSpe c 2 10101 Specul ative m emor y re a[...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4 –23 System P ort T abl e 4–14 footnotes: 1. Systems c an opt ionally enable MB i nstruction s to t he extern al sys tem b y asse rting Cbox CSR SYSBUS_MB_ENABLE. This m ode is describe d i n Secti on 2 .12.1. 2. T o minimize load- to-use memor y latency , systems can opti [...]

4–24 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Syst em Port Systems th at requir e an explicit indic ation of Cha ngeT oDirty status c hanges initi- ated by STx_C instr uctions c an asser t Cbox CSR S TC_ENABLE[0]. Whe n this regist e r field = 000, CleanT oDirty and SharedT oDirty comman ds are used. The dis- tinc[...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4 –25 System P ort T abl e 4–18 describ es the ProbeRespons e command fields. The syste m uses the SysDc sign a l lines to retrie ve data for probes that re queste d a cache block fr om the 21264/EV68A. Se e Section 4.7.7. 2 for more info rmation about 2-cyc le data tr ansfe[...]

4–26 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Syst em Port • There is no mechanism f or the syste m to r eject a 21264/EV68A- to-syst em com- mand. Probe Respons e, VDBFlushR eq, NOP , NZNOP , and RdBlk x Spec (w ith a clea r R V bit) com mands do n ot requir e a respon se fro m the sys tem. Syste ms must provi [...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4 –27 System P ort T abl e 4–20 de s cribes the syste m-to-2126 4/EV68A pr obe commands fie lds desc riptions . The probe command fie ld Probe[ 4:0] has two sect ions, Probe [4:3] and Probe [2:0] . T abl e 4–21 lists the data move ment sele cted by Probe[4:3] . T abl e 4?[...]

4–28 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Syst em Port The 21264/EV68A hol ds pending pr obe commands in a 8-entry d eep probe queue . The syste m must count the number of probes th at have be en sent and e nsure that t he probes do not overru n the 21264/EV68A queue. The 21264/EV68 A removes probes fr om the [...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4 –29 System P ort T abl e 4–24 describes the SysDc[4:0] fiel d. The A bit in the fir st c ycle ind icate s tha t t he com mand is ack no wled ge d. Wh en A = 1, t he 21264/EV68A de crements its c ommand outsta nding counter , but the A bit is not neces- saril y re late d to[...]

4–30 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Syst em Port The Chan geT oDirtySucce ss and C hangeT oDirtyFai l commands cannot be issued in the shadow of S ysDc ca che fi ll c omm ands (ReadDataError , ReadData, ReadDa taDir ty , Read Dat aSh are d, and Re adDat aS hare d/Di rty). E ach ca che fill co mman d all [...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4 –31 System P ort If bo th the se nder a nd the r eceiver a re sa mpling a t th e same ra te, the se t hree prin ciple s are suf ficient t o s afely m ake poi nt-to-poin t trans fers usin g cloc k fo rwa rding . However , it is often de sira ble for syste ms to align cloc k-f[...]

4–32 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Syst em Port Figure 4–5 show a simpl e example of a fast transf er . The data ra te ra tio is 1. 5X with a 4:1 S YSCLK t o INT_F WD_CLK ratio . Figure 4–5 Fast T ransfer T iming Exam ple In fas t data mode , movement of d ata int o the 21264/EV68 A require s turnin[...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4 –33 System P ort T abl e 4–26 shows four e xample confi gurations and sho ws thei r use o f the SYSDC_DELA Y[4:0] . System 1 has si x GCLKs to eve ry S YSCLK and only sends 4-cycle commands to the 21264/EV68A. Thus, a per iod of thr ee S YSCLKs between t he SysDc c ommand [...]

4–34 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Syst em Port T abl e 4–27 lists infor mation f or the f our ti m ing example s. In T a b le 4–27 , note t he fol- lowing: • SysDc write commands are not a f fecte d by the SYSDC_DELA Y par ameter . • The SYS_RCV_MUX_PRESET adds de lay at t he rate of one INT_FW[...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4 –35 System P ort 1. The SysDataInV al id _L signa l must be a sserte d for both cycl es of a SysDc fill command, an d two quadwords of data must be deli vered to the 21264/EV68A in succe eding bi t-clock cyc les wi th the a ppropria te ti m ing in referen ce to t he SysDc fi[...]

4–36 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Syst em Port Fig ure 4–6 SysF illVa li d_L Timin g 4.7.8.6 Data W rapping All data movement between the 21264/EV68A and the system is composed of 64 bytes in e ight cyc les on the da ta bus. A ll 64 bytes of m emory data are valid. This appl ies to memory read tra ns[...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4 –37 System P ort point is the QW pointed t o by the 21264/EV 6 8A; h owever , some syst ems may find it more ben eficia l to be gin the transfer e lsewhere . The s ystem must a lways indicate t he starti ng point to the 21264/EV68A. The wrap order for subsequ ent QWs is inte[...]

4–38 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Syst em Port T abl e 4–31 defines the wrap or der for double-pum ped data trans fers. 4. 7.9 Nonexis tent Memory Proc essin g Like its pre decesso r s, the 21264/EV68A c an generate r efer ence s to n onex isten t (NX M) memory or I /O spac e. However , unli ke the e[...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4 –39 System P ort T abl e 4–32 shows each 21264/EV68 A command, with NXM a ddre sses, and the appr o- priate syste m response. Table 4–32 21264/E V68A Comm ands with NXM Add resses and System Response 21264/EV68 A Command NXM Address System/212 64/EV68A Response Probe Res[...]

4–40 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Syst em Port 4. 7.10 Orde ring of System Po rt T ransa ctio ns This s e ctio n desc ribe s o rdering of s ystem port tra ns actions. The two c lasses of transa c- tions are l isted he re: • 21264/EV68A co mmands and system probe s • System probe s and SysDc transf [...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4 –41 System P ort • Probes that invali date l ocked bl ocks do not g enerat e a ReadBlkMod com mand. The 21264/EV68A fails t he S Tx_C inst ruct ion as de fined i n the Alpha Ar chitec tur e Handbook , V e rsion 4 . • All read commands (Rd Blk, RdBlkMod, Fetc h, InvalT oD[...]

4–42 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Bcache P ort 4.7.10.2 System Probes and SysDc Co mmands Orderi ng of cache tr ansaction s at the system ser ializ ation poin t must be refl ect ed in the 21264/EV68A cac he syste m. T able 4–34 shows the rules tha t a system must follow to control the order of cache [...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4 –43 Bcach e Por t The Bcache suppor ts the fol lowing multipl es of the GCLK period: 1.5X (dual- data mode only), 2X, 2.5X, 3X, 3.5X, 4X, 5X, 6X, 7X, a nd 8X. However , the 2126 4/EV68A imposes a max imum B cach e cloc k period b ased on the SY SC LK rat io. T ab le 4–35 l[...]

4–44 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Bcache P ort 4. 8.2 Bcache C lo cking For cloc king , the Bcac he port pins can be d ivided into thr ee gr oups. 1. The B cache index pins (address and control) are ref erenc ed to I n t _Add_BcClk, a n inte rnal ve rsion of the Bcache forwa rded c lock. The i ndex pin[...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4 –45 Bcach e Por t BcT agS har ed_H BcT agV a lid_H 3. The B cache clock pins ( BcDataOutClk _ x [3:0] an d BcT a g Out Cl k _ x ) clock t he index and dat a pins at the SSRAMs. These clo cks can be d elayed from Int_Data _BcClk from 0 t o 2 G CLK p ha s e s (h a lf c ycl es [...]

4–46 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Bcache P ort 3. BC_FDBK_EN[7:0 ] T o prog ram thes e th ree CSRs , the pr ogr amme r mu st know t he bit-rat e of the Bc ache data, a nd whethe r only the ri sing edge o r both edges of the clock are us ed to latch da ta. For exam p le, a 200-M Hz l ate-w rite SS RA M [...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4 –47 Bcach e Por t In addition to pr ogra mming the clock CSRs, the data -sample /drive Cbox CSRs, at the pads, m ust be se t a ppropria tely . T able 4–41 l ists t hese CSRs a nd prov ides t heir pro- gram me d valu e. 4. 8.3 Bcache T ran sac tions The Cbox uses the progra[...]

4–48 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Bcache P ort have been pr ogrammed f or the Bcac he clock peri od, and with s atisf actory de lay pa ram- eter s for the SSRAM setup/hol d Bcache addr ess l atch r equirement s, a Bcac he re ad command pr oce eds thr oug h the 21264/ EV68A Cbox a s f oll ows: 1. When t[...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4 –49 Bcach e Por t priate programming o f the Bcac he cloc k per iod and delay pa rameters t o satisf y SSRAM setup /hold r equir ements of the B cache addr ess latch, a Bcac he write t r ansac tion pr o- ceeds throug h the Cbox as follows: 1. The Cbox transmits the i ndex an[...]

4–50 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Bcache P ort The Relationship Between Write-to-Read — BC_W R_RD_BUBBLE S and wr_rd The following f ormul as calcul ate the relation ship between the Cbox CSR BC_ WR_ RD _BU BB LES a nd w r_rd: wr_rd = ( BC_WR_RD_BUBB LES – 1) * b cfrm or BC_WR_RD_ BUBBLES = ((w r_r[...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4 –51 Bcach e Por t 4.8.4.1 BcAdd_H[23 :4] The BcAdd_H[23: 4] p ins ar e high dr ive outp uts t hat pro vides the in de x for th e Bcache. The 21264/EV6 8A supports Bcache s izes of 1MB, 2MB, 4MB, 8MB, and 16M B. T abl e 4–42 lists the value s to be progra mmed into Cbox CSR[...]

4–52 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Bcache P ort T abl e 4–45 lists the combi nation of contr ol pin asser tion for RAM_TYPE B. T abl e 4–46 lists the combi nation of contr ol pin asser tion for RAM_TYPE C. T abl e 4–47 lists the combi nation of contr ol pin asser tion for RAM_TYPE D. Notes: 1. The[...]

21264/EV 68A Hardware Refere nce Manu al Cache and External Interfaces 4 –53 Bcach e Por t 4.8.4.3 BcDataInClk_H and B cT agInClk_H The BcDataInClk_H[7 :0] and BcT agIn Clk_H pins are used to ca pture ta g dat a and data f rom the Bcache da ta and ta g RAMs respec tively . Dual- data ra te SSRAMs provide a clo ck outpu t with the data output pin [...]

4–54 Cache and Ex ternal Interfaces 21264/ EV68A Har dware R eferenc e Man ual Inter rupt s BC_CPU_LA TE_WRITE_NUM[ 1:0] = 0x1 BC_LATE_W RITE_NUM[2:0] = 0x0 BC_LATE_W RITE_UPPER = 0 DUP_TAG_E NABLE = 0 4.9 In te rru pts The sys tem may requ est inte rr upts by way of the IR Q_H [5:0 ] p ins. These six interrupt source s are ident ical. They may b[...]

21264/EV 68A Hardware Refere nce Manu al Internal Proc essor Regi sters 5–1 5 Internal Proces sor Re gister s This c hapte r de scr ibes 2 1264/EV68A int ernal processor registe rs (I PRs). They are se p- arat ed into t he followi ng circuit logic groups: Ebox , I box, Mbox , and Cbox. The gray a reas in re gist er figur es indicate reserved fiel[...]

5–2 I nternal Proces sor Reg isters 21264/ EV68A Har dware R eferenc e Man ual Inst ruction V A form at IV A_FORM 000 0 01 1 1 5 RO 0L 3 Curren t mode CM 000 0 1001 4 R W 0L 3 In terr upt enab le IER 0000 1 010 4 R W 0L 3 In terr upt enab le a nd cur r ent mo de IER_CM 000 0 1 0xx 4 R W 0L 3 Softwa re inter rup t reque st SIRR 0000 1 10 0 4 R W 0[...]

21264/EV 68A Hardware Refere nce Manu al Internal Proc essor Regi sters 5–3 Ebox I PRs 5.1 Ebo x IPR s This s e ctio n desc ribe s t he int ernal processor registe rs t ha t c ontrol Ebox func tions. 5. 1.1 Cycle C ount er Re gister – CC The cycle counter r egiste r (CC) is a r ead -writ e registe r . The lower half of C C is a count er that, w[...]

5–4 I nternal Proces sor Reg isters 21264/ EV68A Har dware R eferenc e Man ual Ebox I PRs T abl e 5–2 describes the C C_CTL regis ter fields. 5. 1.3 V irtual Addr ess Regis ter – V A The vir tual a ddress register ( V A) is a r ead-onl y regist e r . When a DTB miss or f ault occur s, t he associa ted effective vi rtu al addre ss is w ritte n[...]

21264/EV 68A Hardware Refere nce Manu al Internal Proc essor Regi sters 5–5 Ebox I PRs T abl e 5–3 describes the vir tual addre ss contr ol registe r fields. 5. 1.5 V irtual Addr ess Form at Regist er – V A_F ORM The virtua l address f ormat regist er (V A_FORM) is a read-onl y regist er . It contains th e virt ual page tabl e entry address d[...]

5–6 I nternal Proces sor Reg isters 21264/ EV68A Har dware R eferenc e Man ual Ibox IPRs Figure 5–6 Virtual Ad dress Forma t Register (VA_48 = 1, VA_F ORM_32 = 0) Figure 5–7 shows V A_FORM when V A_CTL(V A_4 8) equals 0 and V A_CTL(V A_FORM_32) equa ls 1. Figure 5–7 Virtual Ad dress Forma t Register (VA_48 = 0, VA_F ORM_32 = 1) 5.2 Ibox IPR[...]

21264/EV 68A Hardware Refere nce Manu al Internal Proc essor Regi sters 5–7 Ibox IPRs Figu re 5–9 ITB PT E Arr ay Wri te Regis ter 5. 2.3 ITB Inva lidate All Proces s (ASM= 0 ) Reg ister – I TB_IAP The ITB i nvalida te all process regist er (ITB_IAP) is a pseudo regis ter that, when wr i t- ten to, i nvalida tes all ITB entrie s whose ASM bit[...]

5–8 I nternal Proces sor Reg isters 21264/ EV68A Har dware R eferenc e Man ual Ibox IPRs 5. 2.6 Profile Me P C Reg ister – PMPC The Prof ileMe P C registe r (P MPC) is a r ead- only regis ter tha t co ntains the PC of the last prof iled inst r ucti on. Additiona l infor matio n is available in the I_ST A T a n d PCTR_CTL registe r descr ipti on[...]

21264/EV 68A Hardware Refere nce Manu al Internal Proc essor Regi sters 5–9 Ibox IPRs 5. 2.8 Instr ucti on V irtual Ad dress Fo rmat Regist er — IV A_F ORM The instruc ti on vi rtual a ddre ss format r egiste r ( IV A_F ORM) i s a r ea d-only regi ster . It contains th e virtual P TE a d dress derive d from the fault ing virtua l address store [...]

5–10 I nternal Proces sor Reg isters 21264/ EV68A Har dware R eferenc e Man ual Ibox IPRs Figure 5–16 Interru pt Enable an d Current Process or Mode Reg ister T abl e 5–5 describes the i nterrupt ena ble and curre nt pr ocess or mode regi ster f ields. 5. 2.10 Softwa re Inte rrup t Req ues t Reg ister – S IRR The soft ware inter rupt re que[...]

21264/EV 68A Hardware Refere nce Manu al Internal Proc essor Regi sters 5–11 Ibox IPRs Figure 5–17 Softwa re Interrup t Reque st Regis ter T abl e 5–6 describes the s oftware inte rrupt r equest r egis ter f ields. 5.2. 1 1 Int err up t S um mary Re gis t er – I S UM The inter rupt summary regis ter (ISUM) is a read- only regi ster that re [...]

5–12 I nternal Proces sor Reg isters 21264/ EV68A Har dware R eferenc e Man ual Ibox IPRs T abl e 5–7 describes the i nterrup t summary regis ter fiel ds. 5. 2.12 Hardw are Int errup t Clear Regist er – HW_IN T_ CLR The hardware interr upt clear regist er (HW_INT_CLR) i s a write -only register used to clea r edge-se nsit ive in terrupt r equ[...]

21264/EV 68A Hardware Refere nce Manu al Internal Proc essor Regi sters 5–13 Ibox IPRs T abl e 5–8 describes the h a rdware interrupt c lear r egist e r fi elds. 5. 2.13 Exce pti on Summ ary R eg ister – E XC _SU M The exception summary regist er (EXC_SUM) is a read-onl y re gist er that contains inform ation abo ut instruc tions that have t [...]

5–14 I nternal Proces sor Reg isters 21264/ EV68A Har dware R eferenc e Man ual Ibox IPRs Figure 5–20 Excep tion Summary Reg ister T abl e 5–9 describes the e xce ption sum mary re gister fie ld s. Table 5–9 Exce ption S ummary Re gister Fields D escription Name Extent Type Descripti on SEXT(SET_IOV) [63: 48] RO, 0 Sign-exte nded value of b[...]

21264/EV 68A Hardware Refere nce Manu al Internal Proc essor Regi sters 5–15 Ibox IPRs 5. 2.14 P AL Bas e Regi ster – P AL_B AS E The P AL base re gist er (P AL_BASE) is a read-wr ite re gister th a t conta ins the ba se phys- ical a ddres s for P ALc ode. Its c ontent s are cl eared by c hi p reset bu t are not c lea red after waking up from s[...]

5–16 I nternal Proces sor Reg isters 21264/ EV68A Har dware R eferenc e Man ual Ibox IPRs Figure 5–22 Ibox Co ntrol Reg ister T abl e 5–11 d escribe s the I box c ontrol regi ster f ields. Table 5–11 Ibox Control Register Fields Description Name Extent Type Descri ption SEXT(VP TB[47]) [63:48] RW , 0 Sig n extended VP T B[47]. VP TB[47:30] [...]

21264/EV 68A Hardware Refere nce Manu al Internal Proc essor Regi sters 5–17 Ibox IPRs ST_W AIT _64K [20] R W ,0 The stW ait t abl e is us ed to re duce loa d/st ore ord er tra ps. Wh en se t, th e stW a it t ab le is cl ea red af t er 64 K cycl es . Whe n clea r, the st W ait t ab le is clea re d af ter 1 6K c ycle s. S ee S ec - tion 2. 1 1 . P[...]

5–18 I nternal Proces sor Reg isters 21264/ EV68A Har dware R eferenc e Man ual Ibox IPRs 5. 2.16 Ibox St atus Reg ist er – I_ST A T The Ibo x stat us regis ter ( I_ST A T) is a read/ write -1-t o-clear r egiste r t hat contains Ibox stat us i nfor mation. Usage of I_ST A T in perf ormance monitor ing is describ e d in Section 6. 10. Figure 5?[...]

21264/EV 68A Hardware Refere nce Manu al Internal Proc essor Regi sters 5–19 Ibox IPRs Figure 5–23 Ibox Status Regis ter T abl e 5–12 describes the Ibox st atus regist er fields. Table 5–12 Ibox Status Register Fiel ds Description Name Extent Type Descriptio n Reserved [6 3:41] RO Re serve d fo r COMP AQ. MIS [40] R O ProfileMe Mi spred ict[...]

5–20 I nternal Proces sor Reg isters 21264/ EV68A Har dware R eferenc e Man ual Ibox IPRs TR AP TYP E[3 :0 ] [37:34] RO Profil eMe Tr ap T yp es. If the profi led instr uction c ause d a trap (i ndic ated b y I_ST A T[TR P]), th is fi el d i ndi ca te s th e tr a p typ e a s l is te d her e : Va l u e Tr a p Ty p e 0R e p l a y 1 Invalid (unus ed[...]

21264/EV 68A Hardware Refere nce Manu al Internal Proc essor Regi sters 5–21 Ibox IPRs 5. 2.17 Icach e Flush Register – IC_FLUS H The Icache fl ush regi ster (IC_FLUSH) is a pseudo regis te r . Wri ting to this register inval idate s all Icache bl ocks. The cache is flushe d when the next HW_RET/ST ALL instr uction is r etir ed. See Sectio n D.[...]

5–22 I nternal Proces sor Reg isters 21264/ EV68A Har dware R eferenc e Man ual Ibox IPRs Figure 5–24 Process Con text Register T abl e 5–14 describ es the process conte xt regis ter fields. Table 5–14 Process Context Register Fields Descr iption Name Extent Type Des cripti on Reserve d [63:47] — — ASN[7:0] [46:39] R W Address s pace n [...]

21264/EV 68A Hardware Refere nce Manu al Internal Proc essor Regi sters 5–23 Ibox IPRs 5. 2.22 Per fo rmanc e Count er Co ntro l Regis ter – P CTR _ CTL The perf ormanc e counte r contr ol reg ister ( PCTR_CTL) i s a rea d-write r egiste r t hat control s the func tion of t he performance counte rs f or ei ther a ggreg ate counting or Pro- fil [...]

5–24 I nternal Proces sor Reg isters 21264/ EV68A Har dware R eferenc e Man ual Ibox IPRs PCTR0[19: 0] [47:28] R W Performance counter 0. PCTR0 is en abled b y I_CTL[PCT0_EN] a nd eithe r I_C TL[SPCE] o r PCT X[PPCE]. In Ag gre gate mo de: W he n ena b led , PCT R 0 is i nc rem en ted a t ea ch cycl e b y the s e lect ed input. (Se e Section 6.10[...]

21264/EV 68A Hardware Refere nce Manu al Internal Proc essor Regi sters 5–25 Mbox IP Rs 5.3 Mbo x I PR s This s e ctio n desc ribe s t he int ernal processor registe rs t ha t c ontrol M box f uncti ons. 5. 3.1 DTB T ag Arr ay W rit e Reg iste r s 0 and 1 – DTB_T AG0 , DTB_T AG 1 The DTB ta g ar ray write r egiste rs 0 and 1 (DTB _T AG0 and DTB[...]

5–26 I nternal Proces sor Reg isters 21264/ EV68A Har dware R eferenc e Man ual Mb ox IPR s 5. 3.2 DTB P TE Ar ra y W rit e Reg iste rs 0 and 1 – D TB_PTE 0, DT B_P TE1 The DTB P TE array write regis te rs 0 and 1 (DTB_P TE0 and D T B_P TE1) are regis ters thro ugh w hich the D TB P TE arra ys are w rit ten. Th e ent ries to b e wr itten a re c[...]

21264/EV 68A Hardware Refere nce Manu al Internal Proc essor Regi sters 5–27 Mbox IP Rs 5.3 . 4 Ds tr e am TB I nva l id at e A ll Pr o ces s (A S M= 0) Re gi st e r – D T B _ I A P The D st ream t ra nslation bu ffer inva lidate all proc ess ( ASM=0) registe r (DTB_IAP) is a write- only pseud o registe r . W rite tran sacti ons to this registe[...]

5–28 I nternal Proces sor Reg isters 21264/ EV68A Har dware R eferenc e Man ual Mb ox IPR s 5. 3.7 Dst rea m TB Add ress S p a ce Numb er Re gister s 0 an d 1 – D T B_A SN0 , 1 The Dstream translati on bu ffer add res s sp ace nu mbe r reg ister s (DT B _ASN 0 a nd DTB_ASN1) are writ e-only re gister s that should be writ ten with the addr ess [...]

21264/EV 68A Hardware Refere nce Manu al Internal Proc essor Regi sters 5–29 Mbox IP Rs Note: The Ra field of the inst r ucti on that trig gered t he error c an be obta ined from the I box EXC_SUM regist e r . 5. 3.9 Mbox Con trol Registe r – M_CTL The Mbox control re gist er (M_CTL) is a writ e-only regi ster . Its contents are cle ared by chi[...]

5–30 I nternal Proces sor Reg isters 21264/ EV68A Har dware R eferenc e Man ual Mb ox IPR s T abl e 5–19 describ es the Mbox c o ntrol regis ter fie lds. Note: Supe rpage access es are only allowe d in kernel mode. Non-kerne l mode ref- erence s to superpage s resul t i n access violat ions. 5. 3.10 Dcache C ontro l Registe r – DC_CTL The Dca[...]

21264/EV 68A Hardware Refere nce Manu al Internal Proc essor Regi sters 5–31 Mbox IP Rs Figure 5–33 Dcac he Control Register T abl e 5–20 describes the Dcache contr ol r egister f ields. 5. 3.1 1 Dcac he St atus R eg iste r – DC_ ST A T The Dcac he status register ( DC_ST A T) is a rea d-write r egiste r . If a Dcache tag parit y erro r or [...]

5–32 I nternal Proces sor Reg isters 21264/ EV68A Har dware R eferenc e Man ual Cbox CSRs and IPRs Figure 5–34 Dcac he Status Register T abl e 5–21 describes the Dcache status register f ield s. 5 . 4 C b o xC S R sa n dI P R s This s e ctio n desc ribe s t he Cbox C SRs and I PRs. The Cbox configur ation r egiste rs are spl it into three shi[...]

21264/EV 68A Hardware Refere nce Manu al Internal Proc essor Regi sters 5–33 Cbox CSRs and IPRs 5. 4.1 Cbox Dat a Re gist er – C _DA T A Figure 5–3 5 sh ows t he Cbox da ta r egis ter . Figure 5–35 Cbox Data Register T abl e 5–22 describes the Cbox data re gister f i elds. 5. 4.2 Cbox Shi ft Regist er – C_SH FT Figure 5–3 6 sh ows t h[...]

5–34 I nternal Proces sor Reg isters 21264/ EV68A Har dware R eferenc e Man ual Cbox CSRs and IPRs • Only a brief des cript ion of each CSR is given. The funct ional des cription of these CSRs is contai ned in Chapter 4. • The order of multibi t ve ctors is [ MSB:LSB], so the LSB is first bit in the Cbox chain . T abl e 5–24 describ es the [...]

21264/EV 68A Hardware Refere nce Manu al Internal Proc essor Regi sters 5–35 Cbox CSRs and IPRs BC_WR_RD_BUBBL ES[0 :3] Wri te to read GCLK bubbl e s. DUP_T AG_EN ABLE Dupli c ate CSR . SKEWED_FILL_M ODE Duplicate CSR. BC_RDVICTIM Duplica t e CSR. SKEWED_FILL_M ODE Duplicate CSR. BC_RDVICTIM Duplica t e CSR. BC_CLEAN_V ICTIM Duplica te C SR. DUP_[...]

5–36 I nternal Proces sor Reg isters 21264/ EV68A Har dware R eferenc e Man ual Cbox CSRs and IPRs BC_T AG_DDM_F ALL_EN[0] Enables the upd a t e of the 21 264/ EV68A Bcac he tag outp uts based on the fall ing edge of th e forwarded cloc k. BC_T AG_DDM_RISE_EN[0] Enables t he upd ate of the 21 264/EV68A Bc ache ta g outp uts based on the ris ing e[...]

21264/EV 68A Hardware Refere nce Manu al Internal Proc essor Regi sters 5–37 Cbox CSRs and IPRs BC_CLKFWD_E NABLE Duplica te CSR. BC_RCV_M UX_CNT_PRESET [0:1] Duplicate CSR . SYS_DDM_F ALL_EN Duplicate CSR . SYS_DDM_RISE_E N Duplica te CSR. SYS_CLKFWD_E NABLE Duplicate CSR. SYS_RCV_ MUX_CNT_P RESET[ 0:1] Duplica te CSR. SYS_CLK_ DELA Y[0:1] Dupli[...]

5–38 I nternal Proces sor Reg isters 21264/ EV68A Har dware R eferenc e Man ual Cbox CSRs and IPRs 5. 4.4 Cbox WRIT E_MA NY Chain Descr ipt ion The WRITE_MANY chain order is c ontaine d in T able 5–25. No te the following: • Many CSRs are d uplica ted for e ase of ha rdware imple mentati on. These CSR names are indi cated in ita lics an d hav[...]

21264/EV 68A Hardware Refere nce Manu al Internal Proc essor Regi sters 5–39 Cbox CSRs and IPRs • The order of multibi t ve ctors is [ MSB:LSB], so the LSB is first bit in the Cbox chain . T abl e 5–25 describ es the Cbox WRITE_MANY c hai n order from LSB to MSB. Figure 5 –37 shows an examp le of P ALcod e used to write to the W RI TE_MANY [...]

5–40 I nternal Proces sor Reg isters 21264/ EV68A Har dware R eferenc e Man ual Cbox CSRs and IPRs ; INI T_MO DE = 0 ; BC_ SIZE = 0xF ; INVA LI D_ TO_DI RT Y_ EN ABLE = 3 ; ENA BLE_ EV ICT = 1 ; SET _DIR TY _EN ABLE = 6 ; BC_ BANK _E NAB LE = 1 ; BC_ WRT_ ST S = 0 ; ; The va lue f or t he w rite _ma ny c ha in is bas ed o n Ta ble 5– 25. ; ; Th[...]

21264/EV 68A Hardware Refere nce Manu al Internal Proc essor Regi sters 5–41 Cbox CSRs and IPRs 5. 4.5 Cbox Rea d Registe r (IPR) Descrip tion The Cbox r ead re gist er is r ead 6 bi ts at a time. T able 5–26 shows the orde ring f rom LSB to MS B. Table 5–26 Cbox Read IPR Fields Description Name Descr iptio n C_SYNDROME_1[7: 0] Syndrome for u[...]

C _S T A T [4 :0 ] A s f ol lo ws : C_STS[ 3:0] If C_ST A T equa ls xxx _MEM_E RR or xx x _BC_ER R, then C_STS conta ins the st a tus of th e b loc k as f oll o ws ; oth e rw ise , th e v alu e of C_ S T S is X : C_ADDR[6:42] Address of last repor ted ECC or parity error . If C_ST A T value is DSTREAM_DC_E RR, only bi ts 6:19 ar e valid. Table 5–[...]

21264/EV 68A Hardware Refere nce Manu al Privileged Architecture L ibrary Co de 6–1 6 Privi leged A rchitec ture Libra ry Code This cha pter de scr ibes t he 21264/EV68A pr i vileged ar chite ctur e librar y code ( P AL- code) . The chapter is or ga nized as foll ows: • P ALcode de scri ptio n • P ALmode en vironment • Requir ed P ALcode fu[...]

6–2 Pr ivileged Architecture Library Code 21264/ EV68A Har dware R eferenc e Man ual PA Lmod e Envi ronm ent • There are som e necessa ry su pport f uncti ons that a re to o complex to implement direc tly in a proces sor chip’ s hardwa re, but that ca nnot be handled by a normal opera ting syst em software routi ne . Routines to fill the tran[...]

21264/EV 68A Hardware Refere nce Manu al Privileged Architecture L ibrary Co de 6–3 Requ ired PALc ode Funct ion Cod es When exec uting in P ALmode, there a re cer tain re st rictions for using t he privi leged instr uctions because P ALm ode gi ves the pr ogrammer c omplet e access to many of the inte rnal deta ils of the 21264 /EV68A. Refer to [...]

6–4 Pr ivileged Architecture Library Code 21264/ EV68A Har dware R eferenc e Man ual Opcod es Reser ved for PALco de Figu re 6–1 HW _L D Ins tructi on Form a t T abl e 6–3 describes the HW_LD inst ruction fi elds. 6. 4.2 HW_ST Instr uc tion P ALcode use s the HW_S T instr uction to access memory outside the r ealm of no r mal Alpha memory man[...]

21264/EV 68A Hardware Refere nce Manu al Privileged Architecture L ibrary Co de 6–5 Opc odes Rese rved for PAL cod e T abl e 6–4 describes the HW_ST instr uction fie lds. 6. 4.3 HW_RE T In str uc tion The HW_RET instructio n is used to return ins truct ion flow to a specifi ed PC. The RB field of t he HW_RET instructi on specifie s an inte ger [...]

6–6 Pr ivileged Architecture Library Code 21264/ EV68A Har dware R eferenc e Man ual Opcod es Reser ved for PALco de Figure 6–3 HW_R ET Instruction F ormat T abl e 6–5 describes the HW_RET instr uction fie lds. 6. 4.4 HW_MF PR and HW_MT PR Instr uctio ns The HW_MFPR and HW_MTPR instruc tions ar e used to acc ess inte rnal p rocessor r eg- ist[...]

21264/EV 68A Hardware Refere nce Manu al Privileged Architecture L ibrary Co de 6–7 Intern al Proces sor Register A cce ss Mecha nisms T abl e 6–6 describes the HW_MFPR and HW_M TPR ins truct ions fields. 6.5 Inte rnal P roce ss or Re gis ter A ccess M echan is ms This s e ctio n desc ribe s t he har dware a nd softwa re acc ess m echanism s th[...]

6–8 Pr ivileged Architecture Library Code 21264/ EV68A Har dware R eferenc e Man ual Inter na l Processo r Register A ccess Mec hanism s 6. 5.1 IPR S corebo ar d Bit s In previ ous Alpha implementa ti ons, IPR regist ers were not scoreboa rded in har dware. Softwa re w as requ ired to schedule HW_M TPR and HW_MFPR instructi ons for each machine?[...]

21264/EV 68A Hardware Refere nce Manu al Privileged Architecture L ibrary Co de 6–9 Intern al Proces sor Register A cce ss Mecha nisms 6. 5.3 Hardwa re S truc ture o f Impli citly Wr itten IPRs Implic itl y written IPRs are phy sical ly built using only a sin gle level of re gister , how- ever the I PR ha s t wo har dware state s ass oc iat ed wi[...]

6–10 Pr ivileged Architecture Library Code 21264/ EV68A Har dware R eferenc e Man ual Inter na l Processo r Register A ccess Mec hanism s For convenie nce of imp lementa tion, the re is no IPR scoreboa rd bit chec king wit hin the same fetch bloc k (octawor d-al igned octaword) . • W ithin one fetch block, t here can be only one expl icit wri t[...]

21264/EV 68A Hardware Refere nce Manu al Privileged Architecture L ibrary Co de 6– 11 P ALsha d ow Re gis te rs 6. 5.6 Correct Orderi ng of Exp licit Readers Fo llowed by Implicit Wri ters Certain I PRs that are update d as a re sult of fault ing memory operati ons r equire P AL- code ass istanc e to maintai n ordering aga inst newer inst r uct i[...]

6–12 Pr ivileged Architecture Library Code 21264/ EV68A Har dware R eferenc e Man ual PAL cod e E ntry Po int s 3. Correct a ction s must occur when th e FPCR i s writ ten by wa y of a MT_FPCR instr uction. 6. 7.1 S ta tus Flags The FPCR st atus bits in the 21264/EV68A are set with P ALcode assistanc e. Floati ng- point exce ptio ns, for which th[...]

21264/EV 68A Hardware Refere nce Manu al Privileged Architecture L ibrary Co de 6 –13 PAL cod e E ntry Po int s Each CALL_P AL instruc tion inc ludes a functio n fie ld th at is us ed to c alcu late the P C of its ass ociat ed P ALcode entry point. The P ALcode OPCDEC exce ption flow will be invoke d i f the CALL_P AL functi on fie ld sa tis fies[...]

6–14 Pr ivileged Architecture Library Code 21264/ EV68A Har dware R eferenc e Man ual Tran slat ion Buf fer (TB ) Fill Flows 6. 9 T ransl a tio n Buffe r (TB) F ill Fl ows This s e ctio n sh ows t he e xpected P ALcode f lows f or DTB mis s and ITB miss. Familia r- ity with 21264/EV6 8A IPRs is assumed. 6. 9.1 DTB Fill Figure 6–5 sho ws single-[...]

21264/EV 68A Hardware Refere nce Manu al Privileged Architecture L ibrary Co de 6 –15 Translat io n Buffer (TB) Fill Flows ASSUME <tb_mb_en + pte_e co> ne 2 .if ne pte_eco bne p7, trap__d tbm_single_mb ; branch f or mb hw_ret (p23) ; return trap__dtbm_single_mb: mb hw_ret (p23 ) ; return .iff hw_ret(p23) ; return ; (assumes tb_mb_en on m ul[...]

6–16 Pr ivileged Architecture Library Code 21264/ EV68A Har dware R eferenc e Man ual Tran slat ion Buf fer (TB ) Fill Flows • The cond itio nal bra nch is pl aced i n the co de so tha t all o f the MTPR i nstruc tion s are issued and re tire d or non e of the m are issued and re tired. This allows t he TB fill hardware t o update the TB whenev[...]

21264/EV 68A Hardware Refere nce Manu al Privileged Architecture L ibrary Co de 6 –17 Perfo rman ce Co unt er Su pp ort srl r4, #OSF_PTE__PFN__S, r6 ; (xU) sh ift PFN to <0> sll r6, #EV6__ITB_PTE__PFN__S, r6 ; (xU) sh ift PFN into p lace and r4, #<1@OSF_PTE__FOE__S>, r7 ; (xL) get FOE bit blbc r4, trap__inval id_ipte ; (xU) inv alid =[...]

6–18 Pr ivileged Architecture Library Code 21264/ EV68A Har dware R eferenc e Man ual Pe rfor manc e Cou nter Su pport Profi leMe mode, supports a new way of statisti c all y sampling indi vidual instructi ons durin g program executi on. This mode counts e vents trigge red by a targe ted inf ligh t instr uction. Counter su pport uses t he hardwar[...]

21264/EV 68A Hardware Refere nce Manu al Privileged Architecture L ibrary Co de 6 –19 Perfo rman ce Co unt er Su pp ort The legal range for PCTR0 when writing the IPR is 0 : (2** 20-16). The legal range for PCTR1 when writing the IPR is 0 : (2** 20-4). 6.10.2.2 Op eration 1. Se tup The following I PRs need to be set up by P ALcode instr uctions. [...]

6–20 Pr ivileged Architecture Library Code 21264/ EV68A Har dware R eferenc e Man ual Pe rfor manc e Cou nter Su pport 6.10.2.3 Ag gregate Counting Mode Des cri pti on 6.10.2.3.1 Cycle cou nting Counts cyc les. PCTR0 i s i ncremente d by the number of cycles c ount ed, that i s, 1. 6.10.2.3.2 Retired instru ctions cycles PCTR0 i s i ncremente d b[...]

21264/EV 68A Hardware Refere nce Manu al Privileged Architecture L ibrary Co de 6 –21 Perfo rman ce Co unt er Su pp ort The CMOV instructi on is decompose d into two valid fetc hed instruc tions th at, in the absenc e of s talls, a re f etched in c o nsecutive c ycle s. See T able 6–12 for more inf orma- tion. 6.10.3.2 Op eration 1. Se tup The [...]

6–22 Pr ivileged Architecture Library Code 21264/ EV68A Har dware R eferenc e Man ual Pe rfor manc e Cou nter Su pport For inst ructi ons that c ause a trap, the la st cycle i n the window is t he 2nd cycle aft er the tra p. Mispredic ted branche s are incl uded in this cate gory . For non trappi ng instr uctio ns that r etir e, the l a st cyc le[...]

21264/EV 68A Hardware Refere nce Manu al Privileged Architecture L ibrary Co de 6 –23 Perfo rman ce Co unt er Su pp ort 6.10.3.3 Pro fileMe Counting Mode Descrip tion 6.10.3.3.1 Cycle cou nting In Prof ileMe m ode, e ither c ounter c ounts c ycle s during the window of the p r ofil ed instr uction. 6.10.3.3.2 Inum retire delay cycles This i nput [...]

6–24 Pr ivileged Architecture Library Code 21264/ EV68A Har dware R eferenc e Man ual Pe rfor manc e Cou nter Su pport 6.1 0.3.4 Co unte r Mod es for P rofi leMe M ode T abl e 6–14 shows the count er modes that are us ed with P rofile Me mode. Table 6–14 ProfileMe Mode PCTR_CT L Input Select Fields SL0[4] SL1[3: 2] PCTR0 PCTR1 1 00 Reti red i[...]

21264/EV 68A Hardware Refere nce Manu al Init ializ atio n and C on figu rati on 7–1 7 Initializa tion and Configuration This cha pter pr ovi des infor mation on 21264/EV68A-spe cif ic mic roprocessor system initia li zati on and configurat ion. It is or ga nized as foll ows: • Power-u p res et flow • Fault r es et flow • Ener gy star certi[...]

7–2 I nitialization and Configuration 21264/ EV68A Har dware R eferenc e Man ual Powe r-U p Reset Flow and the Reset _L and DCO K_H Pins 1. The clock forwarding a nd system cloc k ra tio configur ation inf ormati on is loaded onto the 21264/EV68A. See Section 7.1.2. 2. The internal PLL is ramped up to opera ting fr equency . 3. The interna l arra[...]

21264/EV 68A Hardware Refere nce Manu al Init ializ atio n and C on figu rati on 7–3 Powe r-Up Reset Flow and the Reset _L and DCOK_H Pins Figu re 7–1 P ow er-Up Ti min g Sequ enc e 7. 1.1 Powe r Seq uencin g an d Res et S t ate for Si gnal Pins Power seque ncing and avoidin g potentia l failure mechani sm s is descri bed in Section 9.3. The re[...]

7–4 I nitialization and Configuration 21264/ EV68A Har dware R eferenc e Man ual Powe r-U p Reset Flow and the Reset _L and DCO K_H Pins In addition , a s power is being ra mped, Reset_L must be asse rte d — this all ows the 21264/EV68A to rese t inter nal sta te. Once the tar get volt a ge leve ls are attaine d, sys- tems should as sert DCOK_H[...]

21264/EV 68A Hardware Refere nce Manu al Init ializ atio n and C on figu rati on 7–5 Powe r-Up Reset Flow and the Reset _L and DCOK_H Pins T abl e 7–3 summarize s the pi ns and the s uggested/re quire d initia li zati on st ate. M ost o f this inf ormation is supp lied by placing ( switch- sele ctable or hardwir ed) weak pul l-ups or pull-d own[...]

7–6 I nitialization and Configuration 21264/ EV68A Har dware R eferenc e Man ual Powe r-U p Reset Flow and the Reset _L and DCO K_H Pins 7. 1.3 PLL Ram p Up After th e c onfi gurat ion is loaded through t he IRQ_H pins, the next pha se in the power up f low is the i nternal PLL ramp up s equence. R amping u p of the P LL i s re quire d t o guara [...]

21264/EV 68A Hardware Refere nce Manu al Init ializ atio n and C on figu rati on 7–7 Powe r-Up Reset Flow and the Reset _L and DCOK_H Pins As BiST c ompletes, the T estS tat _H pi n is hel d low for 16 GCLK cycles. The n, if BiST succe eds, the pi n remains low . Otherwis e , it is asse rte d. After suc ces sfully c ompleti ng BiST , the 21264/ E[...]

7–8 I nitialization and Configuration 21264/ EV68A Har dware R eferenc e Man ual Fault R ese t F l ow 7.2 Fault R ese t F low The faul t reset se quenc e of operati on is trigge red by t he assertion of the ClkFwdRst_H signa l line . Figur e 7–2 shows the fault r eset se quenc e of opera tion . The res et st ate machine is init ially in RUN sta[...]

21264/EV 68A Hardware Refere nce Manu al Init ializ atio n and C on figu rati on 7–9 Ene rgy Star Certificatio n a nd Sleep M ode Fl ow Figure 7–2 Faul t Reset Sequ ence o f O peration 7.3 Ene rgy St a r Cer ti fic ati on and S le ep Mod e Flo w The 21264/EV68A i s Ener gy Star complia nt. Ene rg y St ar is a progr am administe red by the Envir[...]

7–10 I nitialization and Configuration 21264/ EV68A Har dware R eferenc e Man ual Ene rgy Star Certificatio n a nd Sleep M ode F low After th e P LL has fi nished ramping down, the reset state machin e enters the W AIT_INTERRUP T state . Note the effect s of t he ent ry into that state on the IPRs liste d in T a b le 7–6. Note that In terrupt e[...]

21264/EV 68A Hardware Refere nce Manu al Init ializ atio n and C on figu rati on 7– 11 Warm Rese t Flow Figu re 7–3 Slee p Mo de Sequ ence o f Opera tion T abl e 7–7 describes e ach signa l an d const raint for t he sleep mode seque nce . 7.4 W ar m Res et F low The warm reset seque nce of opera tion is trigg ered by the a sse rtion of the Re[...]

7–12 I nitialization and Configuration 21264/ EV68A Har dware R eferenc e Man ual Array Initializatio n The 21264/EV68A waits until R e set_L is deasserted befo re trans itioning from t he W AIT_RESET state. The 21264/EV68A ram ps up the PLL until the state machine enter s the W AIT_ClkFwdRst0 state. Note that the sys tem must a ssert Cl kFwdRst_[...]

21264/EV 68A Hardware Refere nce Manu al Init ializ atio n and C on figu rati on 7–13 Initializat ion Mode Processin g Except fo r INIT_MODE, all the CSR register s have been desc ribed in earli er sections. When ass e rted, INIT_MODE has the followin g be havior: • Cache bloc k updates to the Dcac he set the block to the Clea n state. • Upda[...]

7–14 I nitialization and Configuration 21264/ EV68A Har dware R eferenc e Man ual Exte rnal In ter face In itiali zation SweepMemo ry: ;Write good parity /ecc t o memor y by ; writing a all memory locations. This is ;done by WH64 of memor y addr esses turn_on_b cache: ;bc_enable_ a 0 ;bc_siz e_a Actual Bcache size ;zerobl k_enable_a 3 ;set_di rty[...]

21264/EV 68A Hardware Refere nce Manu al Init ializ atio n and C on figu rati on 7–15 Inter nal P roc essor Regist er Power-U p Res et S tate ITB_IAP ITB invalid ate-a ll (ASM=0) X — ITB_IA IT B inva lidate all X Must be written to in P ALcode. ITB_IS ITB invalid ate s ingl e X — PMP C ProfileMePC X — E XC _AD D R E x cept ion ad d ress X ?[...]

7–16 I nitialization and Configuration 21264/ EV68A Har dware R eferenc e Man ual IEE E 1149.1 Test P ort Res et 7.9 IE EE 1 1 49 .1 T es t Po rt R eset Signal T rst_L must b e asserted when powering up the 21264/EV68A. T rst_L must no t be deasser ted pri or to assert ion of DCOK_H . Tr s t _ L can remain asserte d during nor- mal oper ation of [...]

21264/EV 68A Hardware Refere nce Manu al Init ializ atio n and C on figu rati on 7–17 Res et Stat e Machine Figure 7–5 2126 4/EV68A Reset State Mach ine State Diagram Table 7–11 21264/E V68A Reset State Machi ne State Descriptions State Name Descr iptio n C OL D C hip c o ld . T ra n sit io ne d to W A IT _ S ET TL E w i th a sse rt io n of R[...]

7–18 I nitialization and Configuration 21264/ EV68A Har dware R eferenc e Man ual Res et S ta te Machi ne RAMP2 T riggere d by the du ration co unte r reach ing 4108 cycl es, the X div and Z div divi sors ar e change d to 1 and 2, res pecti ve ly , and the f requenc y is inc reas ed. The dura ti on counte r is reload ed to count 82 05-c ycles. W [...]

21264/EV 68A Hardware Refere nce Manu al Init ializ atio n and C on figu rati on 7–19 Phase- Lock Loo p (PLL) Funct ional Descrip tion 7. 1 1 Phase -Loc k L oop (PL L) Fun ct iona l Des crip ti on The PLL multipli es the clock fr equency of a di fferential i nput reference cloc k and aligns the ph ase of its output to that differe ntial i nput cl[...]

7–20 I nitialization and Configuration 21264/ EV68A Har dware R eferenc e Man ual Pha se-L oc k Loop (PLL) Fun ctio nal Descr ipt ion T abl e 7–12 shows the all owable Clk In_ x fre quencies f or a given operating f requenc y of the 21264 /EV68A and the Y div divider . For exa mple, to set the 21264/EV68A GCLK freq uency to 500 M Hz with a Clk [...]

21264/EV 68A Hardware Refere nce Manu al Error Det ection a nd Error Handling 8–1 8 Error Detec tion and Error Handling This c hapte r give s an ove rvie w of the 2126 4/EV68A error de t ectio n and error handli ng mechanism s, and i s o rga nize d as follows: • Data erro r cor rec tion code • Icach e dat a or tag pari ty error • Dcac he ta[...]

8–2 Er ror Det ection a nd Error Handling 21264/ EV68A Har dware R eferenc e Man ual Data Er ror Correction Code 8.1 Dat a Erro r Cor rec tio n Cod e The 21264/EV68A support s a quadword erro r correct ion code (E CC) for the system data bus. ECC is g enera ted by the 2 1264/EV68A for all memory write transacti ons (W rV i cti mB l k) e mitted f [...]

21264/EV 68A Hardware Refere nce Manu al Error Det ection a nd Error Handling 8–3 Dcache Data Single-Bit Correctable ECC Error 3. The virtual address associa ted with the er ror is avail able in the V A register . 4. The P ALcode flu shes the er ror bloc k by temporar ily disabling DC_CTL[DCT AG_P AR_EN] and evictin g the block using two HW_LD in[...]

8–4 Er ror Det ection a nd Error Handling 21264/ EV68A Har dware R eferenc e Man ual Dca che Stor e Seco nd Erro r – C_ADDR conta ins bits [19:6] of th e Dc ache a ddres s of the bl ock th at conta ins the e rror (bits [42:2 0] of the phys ical a ddress ar e not upda ted) . – DC_ST A T[ECC_ERR_LD] is set. – The load queue r etr ies the load[...]

21264/EV 68A Hardware Refere nce Manu al Error Det ection a nd Error Handling 8–5 B cache T ag Pari ty Err or • C_S T A T[D C_ PER R] i s set . • C_ADDR contains b its [42:6] of the Dcache dupl icate tag addr ess of the block that contains th e error . • When enabl ed, a m achi ne check (MCHK) is pos ted. The MCHK is taken whe n not in P AL[...]

8–6 Er ror Det ection a nd Error Handling 21264/ EV68A Har dware R eferenc e Man ual Bcache Data Single-Bit Correctable ECC Error • C_ADDR contains bits [ 42:6] of the Bcache fill address of t he block that co ntains the e rror . • C_SYNDROME_0[7:0] and C_SYNDROME_1[7:0] contain the syndrome of quadword 0 and 1, res pecti vely , of t he octaw[...]

21264/EV 68A Hardware Refere nce Manu al Error Det ection a nd Error Handling 8–7 Memor y/Syst em Port Single -Bit Data Corr ectable ECC Er ror Note: Err ors in specula ti ve load instructi ons c ause a CRD error to be posted but the data is not scrubbed by ha rdware . The P ALcode cannot perform a scrub opera tion because C_ST A T is zero and C_[...]

8–8 Er ror Det ection a nd Error Handling 21264/ EV68A Har dware R eferenc e Man ual Memo ry /System Port S ingl e-B it Dat a Cor rectab le ECC Err or • A machine c heck (MCHK) i s poste d and taken immediatel y . The P ALc ode mac hine check handle r p erfor ms a s cr u bbing operati on as descri bed in Sectio n D.36 to ensure t ha t th e orig[...]

21264/EV 68A Hardware Refere nce Manu al Error Det ection a nd Error Handling 8–9 Bc ache Data Sin gle-B it Correct abl e ECC Error on a P rob e 8.1 1 Bc ache Dat a Single -Bit Correct able E CC Error on a Pr obe The probed proc essor extr act s the block from its Bcache, si gna ling a corrected r ead data (C RD ) erro r a nd latc hin g err or in[...]

8–10 Er ror Det ection a nd Error Handling 21264/ EV68A Har dware R eferenc e Man ual Erro r Ca se S umm ary 8. 13 Error C ase Su mma ry T abl e 8–3 sum marize s the various error cases and their ramificati ons. T ab le 8–3 Err or Case Sum mary Error Exception St at u s Hardware Action PALcode Act i on Icach e data or tag par ity er ror CRD I[...]

21264/EV 68A Hardware Refere nce Manu al Error Det ection a nd Error Handling 8– 11 Er ror Cas e Sum mar y Memory singl e- bit e rror on I ca che f ill MCHK an d CRD 2 C_ST A T [ISTRE AM_MEM_E RR] C_ADDR[err or a ddres s] C_SYNDROME_0 C_SYNDROME_1 Icache flushed Scrub error as descri bed in Sect ion D.36 . Log as CR D Memory singl e- bit e rror o[...]

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21264/EV 68A Hardware Refere nce Manu al Elec trica l Data 9–1 9 Elect r ical Dat a This chapte r descr ibes the ele ctrical ch aract eristic s of the 21264/EV68 A and its inter- face pins. The chapter contains both ac and dc electr ical characte ristic s and power s up- ply c onsi deratio ns, and i s o rganiz ed a s follows: • Electr ica l cha[...]

9–2 Elect rical Data 21264/ EV68A Har dware R eferenc e Man ual DC Characteristics 9.2 DC Char a cte rist ics This s ectio n contains the dc cha racteri stics for the 21264/ EV68A. The 2126 4/EV68A pins c an b e divided into 10 di stinct e lectric al signal types. The m apping betwe en the se signa l t ypes a nd the p ackage pins is sh own in Cha[...]

21264/EV 68A Hardware Refere nce Manu al Elec trica l Data 9–3 DC Characteristics Note: Cur rent out of a 21264/EV6 8A pin is re presented by a – symbol while a + symbol i ndica tes cu rrent f lowing int o a 21264/EV68A pin. Table 9–3 VD D (I_DC_P OWER) Paramet er Symbol Descri ption Test Condition s M ini m um M axim um VDD Pr ocess or co re[...]

9–4 Elect rical Data 21264/ EV68A Har dware R eferenc e Man ual DC Characteristics Table 9–7 P in Type: O pen-Drain Ou tput Driver (O_O D) Parameter Symbol Des cripti on Tes t Condit ions Minimum M aximum V OL Low-le vel outp ut voltage I OL = 50 mA — 400 m V |I OZ | High im pedance outp ut current 0 < V < VDD — 150 µ A C OD Op en- d[...]

21264/EV 68A Hardware Refere nce Manu al Elec trica l Data 9–5 Power S upply Seq uencin g and Av o iding P ote ntia l Failure Me chanisms 9. 3 Po wer Sup ply Se qu en ci ng an d A vo idi ng Pote ntial Failu re Mec h- anism s Befo re the po wer-on seq uen cing can oc cur , syst e ms should ensure that D COK_ H is deass er ted and Re set_ L is asse[...]

9–6 Elect rical Data 21264/ EV68A Har dware R eferenc e Man ual AC Characteristics the teste r environm ent and does not need to be dis abled. EV6Clk_L and EV6Clk _H are outpu ts that are bot h generated and consu med by the 21264/EV68A; thus, VDD tracks for both the p roducer and consumer . On the push-pull int e rfac es: • Disabl ing all outp[...]

21264/EV 68A Hardware Refere nce Manu al Elec trica l Data 9–7 AC Characteristics • The AC specifi catio n values for TSU, TDH, and TSkew assume a ± 0.4 V input signa l amplitude, r elative to V r ef, one volt per nanose cond slew rates, no mismatc h in pin loa din g, and z ero time- off set be tween f orwa rded clocks a nd data . Any de vi a-[...]

9–8 Elect rical Data 21264/ EV68A Har dware R eferenc e Man ual AC Characteristics BcData InClk_H[7:0] I_DA NA NA NA NA 45-55% BcData OutClk_H[3: 0] O_PP EV6 Clk _ x NA NA ± 350 ps BcData OutClk_L[3 :0] O_P P EV6 Clk _ x NA NA ± 350 ps BcT ag_H[ 42:2 0] B _DA_PP BcT agIn Clk _H 400 p s 400 ps NA NA 1.0 V/ns BcT ag Dirty _H B_DA_PP Bc T agI nC l[...]

21264/EV 68A Hardware Refere nce Manu al Elec trica l Data 9–9 AC Characteristics 2 The TD H spec i fied for al l cl ock -f orwa rd ed s ign al g ro ups i s wi th res pe ct t o the a sso ci ated clo ck . 3 The TSk ew value a pplies only when the SYS_CL K_DELA Y[0:1 ] entr y in the Cbox WRI TE_ONCE chai n (T able 5 –24) is s et to zero pha ses o[...]

[...]

21264/EV 68A Hardware Refere nce Manu al Thermal Managem ent 10–1 10 Thermal Management This chapte r descr ibes the 21264 /EV68A thermal management a nd thermal design consi deration s, and i s or ganized as f o llows: • Operat ing temper ature • Heat sink spe cifi catio ns • Thermal des ign conside rat ions 10. 1 Op er at in g T emper atu[...]

10–2 T hermal M anagemen t 21264/ EV68A Har dware R eferenc e Man ual Oper atin g Tem peratu re T abl e 10–2 lists the value s fo r the c enter of heat-sink- to-ambie nt ( θ c a) f or the 212 64/ EV68A 587- pin PGA. T ables 10 –3 t hrough 1 0–6 s how t he a llowable T a (wit hout exce edi ng T c ) at various air flows. Table 10–2 θ ca a[...]

21264/EV 68A Hardware Refere nce Manu al Thermal Managem ent 10–3 Heat Sin k Spec ification s 10.2 Heat Sin k Sp ec ific atio ns Three he at sin k types a re specif ied. The m ounti ng holes for a ll thr ee are in lin e with the cooli ng fin s. Figure 10– 1 shows the he at si nk type 1, a lo ng with i ts ap proximate d imensio ns. Figure 10–1[...]

10–4 T hermal M anagemen t 21264/ EV68A Har dware R eferenc e Man ual Hea t Sink Specif icat ions Figure 10– 2 shows the he at si nk type 2, a lo ng with i ts ap proximate d imensio ns. Figure 10–2 T ype 2 Heat Sink 1.00 in 2.3 5 in 0. 25 in 1.3 75 in 1.0 15 in 1.8 75 in 3.75 in 3.75 i n 1.87 5 in 0.0 75 in 0 .055 in 0.0 4 in LK99-021 1a[...]

21264/EV 68A Hardware Refere nce Manu al Thermal Managem ent 10–5 Heat Sin k Spec ification s Figure 10– 3 shows heat sink type 3, a long with its appr oximate dimens ions. The cooling f ins of heat sink type 3 are cross - cut. Also, an 80 mm × 80 mm × 15 mm fan i s attache d t o heat sink type 3. Figure 10–3 Ty pe 3 Heat Sink 2.00 i n 0.30[...]

10–6 T hermal M anagemen t 21264/ EV68A Har dware R eferenc e Man ual Ther m al Desig n Co nsi derati ons 10. 3 Therma l Des ign Con side ratio ns Follo w these guideline s for print ed circui t board (PCB) compone nt placement: • Orient the 2 1264/EV68A on the PCB with the heat sink fi ns aligne d with the air- flow dire ction. • A void preh[...]

21264/EV 68A Hardware Refere nce Manu al Testability and Diagnostics 1 1–1 11 T est ability and Diagnostics This chapter describ e s the 21264/EV68A user -ori ented testa bility a nd diagnosti c fea- tures. These featur es i nclude a utomatic powe r - up self -te st, Ic ache i niti alizati on from exter nal seria l ROMs, and the serial di agnosti[...]

11– 2 Testability and Diagnostics 21264/ EV68A Har dware R eferenc e Man ual SROM/S erial Dia g nost ic Term inal P ort 1 1.2 SROM/ Ser ial Dia gn osti c T ermi na l Port This port sup ports two functi ons. During power -up, it supports autom atic in itiali zati on of the C box con figur ation regis te rs a nd the I cache f rom the s ystem seri a[...]

21264/EV 68A Hardware Refere nce Manu al Testability and Diagnostics 1 1–3 IEEE 1149.1 Por t On the rece ive side , while in native mode, any tra nsit ion on the Ibox I_CTL [SL_R CV ], dr iven fro m th e SromData_H pi n, results in a trap to t he P ALcode inte r- rupt handle r . When in P ALmode, all inte rrup ts are blocked. Th e interrupt ro ut[...]

11– 4 Testability and Diagnostics 21264/ EV68A Har dware R eferenc e Man ual TestS t at_H Pin Table 11– 3 TAP Contro ller State M achine 1 1 .4 T estS t at_H P in The T estS t at_H pi n serve s two p urposes. During power -up, it indic ates BiST pass/fa il stat us. Afte r power -up, it indica tes the 2126 4/EV68A timeou t eve nt. The system res[...]

21264/EV 68A Hardware Refere nce Manu al Testability and Diagnostics 1 1–5 Power-U p Self-T est and In itiali zatio n Figure 11–1 TestStat_H P in Timing During Po wer-Up Built-In Self-Test (BiST) Figure 11–2 TestStat_H P in Timing During Bu ilt-In Self-Initializati on (BiSI) 1 1. 5 Po wer- Up Se lf- T est and I nitia lizatio n Upon powering u[...]

11– 6 Testability and Diagnostics 21264/ EV68A Har dware R eferenc e Man ual Power- Up Self- Test an d I nitializat ion In the SROM represente d in Figure 1 1–3, the length for f ields Cbox Confi g Data( 0,n) plus MBZ(m,0) m ust equal 367 bits. (If Cbox C onfig Data(0 ,n) is (0, 366), MBZ woul d be zero.) For th e 21264/ EV68A, Cbox Conf ig Dat[...]

21264/EV 68A Hardware Refere nce Manu al Testability and Diagnostics 1 1–7 Notes on IEEE 1149.1 Op eratio n and C omp liance The instr ucti on cache line s are l oaded in the revers e orde r . If the f etc h_count(9, 0) is zero, then, no ins truct ion ca che lines are loa ded. S ince the va l id bit s are alr eady cle ared by the BiST operation ,[...]

[...]

21264/EV 68A Hardware Refere nce Manu al Alpha Instruction Set A–1 A Alpha Instruct ion Set This appe ndix pr ovid es a su mmary of the Al pha in struc tion se t and de scribes th e 21264/EV68A IEEE floating- poi nt conformanc e. It is or ganiz ed as follows: • Alpha inst ruct ion summary • Rese rved opc o des • IEEE float ing-poin t instru[...]

A–2 Alpha Instruction Set 21264/ EV68A Har dware R eferenc e Man ual Al pha I n str uc ti on Sum ma ry Quali fiers fo r operate inst ructi ons are shown in T abl e A–2. Qualifier s for IEEE and V AX floating- point i nstruc tions ar e shown in T ables A–5 and A–6, res pectivel y . Memory/ branch M br oo.h oo is the 6-bit opcode field. h is [...]

21264/EV 68A Hardware Refere nce Manu al Alpha Instruction Set A–3 Alph a Ins truct ion Summar y BSR M br 34 Branc h to subroutin e CALL_PAL P cd 00 Trap t o PALco de CMOVEQ Opr 11.24 CMOVE i f = ze ro CMOVGE Opr 11.46 CMOVE if ≥ zero CMOVGT Opr 11.66 CMOVE if > zero CMOVLBC Opr 11. 1 6 CMOVE if low bit cle ar CMOVLBS Opr 11.14 CMOVE if low [...]

A–4 Alpha Instruction Set 21264/ EV68A Har dware R eferenc e Man ual Al pha I n str uc ti on Sum ma ry CVTGQ F-P 15.0AF Conve rt G_f loati ng to quadword CVTLQ F -P 17.0 10 Convert l ongword t o qu adword CVTQF F-P 15.0BC Conve rt quadword to F_floa ting CVTQG F-P 15.0BE Conve rt quadword to G_f loating CVTQL F -P 17.0 30 Convert quadwor d to lon[...]

21264/EV 68A Hardware Refere nce Manu al Alpha Instruction Set A–5 Alph a Ins truct ion Summar y FCMOVGT F-P 17.02F FCMO VE if > zero FCMOVLE F-P 17.02E FCMO VE if ≤ ze ro FCMOVLT F-P 17.02C FCMOVE if < zero FCMOVNE F-P 17.02B FCMO VE if ≠ ze ro FETCH Mfc 18.8 000 Prefetch da ta FETCH_M M fc 18.A000 Prefe tch data , modify i ntent FTOIS[...]

A–6 Alpha Instruction Set 21264/ EV68A Har dware R eferenc e Man ual Al pha I n str uc ti on Sum ma ry LDS M em 22 Load S_floati ng LDT Mem 23 Load T_floating LDWU Mem 0C Load zero- extend ed word MAXSB8 Opr 1C.3E Vector si gned byt e maximum MAXSW4 Opr 1C.3F Vector signe d word maximum MAXUB8 Opr 1C.3C Vector uns igned b yte maximum MAXUW4 Opr 1[...]

21264/EV 68A Hardware Refere nce Manu al Alpha Instruction Set A–7 Alph a Ins truct ion Summar y PKWB Opr 1C .36 Pack words t o bytes RC Mfc 18.E 000 Read and clear RET M br 1A.2 Return from subrouti ne RPCC Mfc 18.C000 Read pr ocess cycle counte r RS M fc 1 8. F000 Re ad a nd set S4ADDL Opr 10.02 Scaled add lo ngword by 4 S4ADDQ Opr 10.22 Scale [...]

A–8 Alpha Instruction Set 21264/ EV68A Har dware R eferenc e Man ual Res erved Op co des A.2 Res erved O pc odes This secti on describes the opc o des that are res erved in the Al pha archite ctur e. They can be rese rved f or Compaq or for P ALcode. A.2. 1 Opc odes Rese rved for C omp aq T abl e A–3 lists opc odes r eserve d for Comp aq. STW M[...]

21264/EV 68A Hardware Refere nce Manu al Alpha Instruction Set A–9 IE EE Fl oat ing -Poi n t Instr uc tion s A.2. 2 Opc odes Rese rved for P ALc o de T abl e A–4 lists t he 21264/EV68A-speci fic inst r ucti ons. See C hapter 2 for more inform ation. A.3 IE EE Fl oa ti ng- P oi nt In st ru cti ons T abl e A–5 lists t he hexadecimal value o f t[...]

A–10 Alpha I nstruction Set 21264/ EV68A Har dware R eferenc e Man ual IEEE Fl o ating - Poin t I ns tr uct ion s SQRTS 08B 00B 04B 0CB 18B 10B 14B 1CB SQRTT 0AB 02B 06B 0EB 1AB 12B 16B 1EB SUBS 081 001 041 0C1 181 101 141 1C1 SUBT 0A1 021 061 0E1 1A1 121 161 1E1 Mn em on ic / S U /S UC /S UM /S UD /S UI /S UI C /S UIM /SUI D ADDS 580 500 540 5C0[...]

21264/EV 68A Hardware Refere nce Manu al Alpha Instruction Set A–1 1 VAX Float ing-P oint Instr uction s Prog ram ming N o te: In order to use CMPTxx with soft ware comple tion tra p handling, it is nec essary to specif y the /SU I EEE trap mode, even though an underflow trap is not possible . In o rder to use CVTQS or CVTQT with software complet[...]

A–12 Alpha I nstruction Set 21264/ EV68A Har dware R eferenc e Man ual Opc ode Su mmar y Tab le A– 7 I nd epe nde nt F loat ing-P o int I nstru ctio n Fu nct ion Co des A. 6 Opc od e Su mmar y T abl e A–8 lists a ll Alpha opc odes from 00 (CALL_P AL) through 3F (BG T). In the tabl e, t he column hea dings tha t a ppear o ver the i nstruc tion[...]

21264/EV 68A Hardware Refere nce Manu al Alpha Instruction Set A–13 Requ ired PALc ode Funct ion Cod es T abl e A–9 explai ns the symbols used in T able A–8. A. 7 Requ i r ed P ALc od e Func tion Co des T abl e A–10 lists opcodes r equired for all Alpha implementat ions. The notati on used is oo.ff ff , w here oo is the hexade cimal 6-bit o[...]

A–14 Alpha I nstruction Set 21264/ EV68A Har dware R eferenc e Man ual IE EE Floa ting-P oi nt Conf ormance A.8 IE E E Fl oa tin g- Poi nt Co nf or m an ce The 21264/EV6 8A supports the IEEE fl oating-point op e rations de fine d in the Alpha System Ref er ence Manual , Revision 8 and the refor e also from the Alpha Ar chitectur e Refer ence Manu[...]

21264/EV 68A Hardware Refere nce Manu al Alpha Instruction Set A–15 IE EE F loat ing -P oin t Co nfo rma nc e If one of these bits is se t, and an instr uction with the /S qualif ier s et generate s the associa ted exce ptio n, the 21264/EV68A produc es the IEEE nontr apping resul t and suppr esses the tr ap. These nontra pping response s include[...]

A–16 Alpha I nstruction Set 21264/ EV68A Har dware R eferenc e Man ual IE EE Floa ting-P oi nt Conf ormance Exponent overflow ±I nf o r ±MAX Overflow Exponen t underflo w +0 Under flow Inexac t resul t Result Inexac t Tab le A– 1 1 E xc ept ion al In put a nd Ou tput Con ditio ns ( Co nti nued) Alpha I nstruct i ons 21264/ EV68A Hardwar e Sup[...]

21264/EV 68A Hardware Refere nce Manu al Alpha Instruction Set A–17 IE EE F loat ing -P oin t Co nfo rma nc e MULx INPUT Inf operand ±In f (none) QNaN operand QNaN (none) SNaN operand QNa N Inva li d Op 0*I n f C Q N a N I n v a l i dO p MULx OUT PUT (same as ADDx) DIVx I NPUT QNaN operand QNaN (none) SNaN operand QNa N Inva li d Op 0/0 or Inf/I[...]

See Section 2. 14 for infor mation about the floa ti ng-point contr ol reg ister (F PCR). SNaN oper and 0 Invali d Op CVTf i OUTPU T Inexac t resul t Result Inexac t Intege r o verflow T ru ncate d r esult Invali d Op CVT if OUTPUT Inexac t resul t Result Inexac t CVTff INPUT Inf operand ±In f (none) QNaN operand QNaN (none) SNaN operand QNa N Inv[...]

21264/EV 68A Hardware Refere nce Manu al 21264/EV 68A Bound ary-Scan Regist er B–1 B 21264 /EV 68A Boundary -Sca n Register This appendix c ontains the BSDL descr ipti on of the 21264/EV68A boundar y-sc an reg- iste r . B. 1 Bo undar y- Sc an Re giste r The Boundary- Scan Registe r (BSR) on the 21264/EV68A is 367 bits lo ng. It is accesse d by t [...]

B–2 21264/EV 68A Boun dary-Scan Regi ster 21264/ EV68A Har dware R eferenc e Man ual Bo undar y-Scan Reg iste r SysDataInClk_H :in bit_vector (0 to 7) ; BcDataOutClk_L :out bit_vector (0 to 3) ; -- JWB corrected BcDataOutClk_H :out bit_vector (0 to 3) ; -- JWB corrected ClkIn_H :linkage bit ; -- Oscillator ClkIn_L :linkage bit ; -- Oscillator PLL[...]

21264/EV 68A Hardware Refere nce Manu al 21264/EV 68A Bound ary-Scan Regist er B–3 Bo undar y-Scan R egi ste r " AB38, AC39, AD38, AF40, AH38, AJ39, AL41, AK38, "& " AN39, AP38, AR39, AT38, AY38, AV36, AW35, AV34),"& "SysCheck_L : (L7 , AA5 , AK8 , BA13, L39 , AA41, AM40, AY34),"& "SysDataInClk_H : ([...]

B–4 21264/EV 68A Boun dary-Scan Regi ster 21264/ EV68A Har dware R eferenc e Man ual Bo undar y-Scan Reg iste r "NoConnect_0 : BB14, "& "NoConnect_1 : BD2 , "& "ClkFwdRst_H : BE11, "& "EV6Clk_H : AM6 , "& "EV6Clk_L : AL7 , "& "Spare_4 : AT4 , "& "Spare_5 : AR[...]

21264/EV 68A Hardware Refere nce Manu al 21264/EV 68A Bound ary-Scan Regist er B–5 Bo undar y-Scan R egi ste r "BcLoad_L : 124 , "& "BcDataWr_L : 79 , "& "BcData_H : (26 , 71 , 2 , 46 , 45 , 90 , 159 , 89 , "& " 1 7 9,1 8 6,1 9 5,2 0 2,2 3 4,2 4 2,2 5 0,2 6 7," & " 2 9 0,2 9 8,3 0 7,3 2[...]

B–6 21264/EV 68A Boun dary-Scan Regi ster 21264/ EV68A Har dware R eferenc e Man ual Bo undar y-Scan Reg iste r "VSS : (44 , 259 , 388 , 138 , 97 , 146 , 60 , 278 , "& " 4 9 7,2 3 3,1 7 8,3 2 3,4 7 9,4 3 6,4 8 5,4 4 4," & " 5 3 8,3 1 0,2 1 ,2 8 1,2 2 6,3 7 1,4 7 ,5 3 ," & " 5 7 8,1 0 6,3 5 8,1 5 5,3 [...]

21264/EV 68A Hardware Refere nce Manu al 21264/EV 68A Bound ary-Scan Regist er B–7 Bo undar y-Scan R egi ste r " 363 ( BC_2, SromData_H, INPUT, x ), "& -- " 362 ( BC_3, reset_L, INPUT, x ), "& -- " 361 ( BC_3, IRQ_H(5), INPUT, x ), "& -- " 360 ( BC_3, IRQ_H(4), INPUT, x ), "& -- " 359 ([...]

B–8 21264/EV 68A Boun dary-Scan Regi ster 21264/ EV68A Har dware R eferenc e Man ual Bo undar y-Scan Reg iste r " 298 ( BC_2, SysData_L(19), BIDIR, x, 302, 0, WEAK1 ), "& -- " 297 ( BC_2, BcData_H(18), BIDIR, x, 305, 0, Z ), "& -- " 296 ( BC_2, BcData_H(82), BIDIR, x, 305, 0, Z ), "& -- " 295 ( BC_2,[...]

21264/EV 68A Hardware Refere nce Manu al 21264/EV 68A Bound ary-Scan Regist er B–9 Bo undar y-Scan R egi ste r " 233 ( BC_2, BcData_H(67), BIDIR, x, 239, 0, Z ), "& -- " 232 ( BC_2, SysData_L(3), BIDIR, x, 236, 0, WEAK1 ), "& -- " 231 ( BC_2, BcData_H(2) , BIDIR, x, 239, 0, Z ), "& -- " 230 ( BC_2, B[...]

B–10 21264/EV68A Boun dary-Scan Regi ster 21264/ EV68A Har dware R eferenc e Man ual Bo undar y-Scan Reg iste r " 168 ( BC_2, BcAdd_H(22), OUTPUT2, x ), "& -- " 167 ( BC_2, BcAdd_H(23), OUTPUT2, x ), "& -- " 166 ( BC_2, SysData_L(32), BIDIR, x, 150, 0, WEAK1 ), "& -- " 165 ( BC_2, BcData_H(96), BIDIR[...]

21264/EV 68A Hardware Refere nce Manu al 21264/EV 68A Bound ary-Scan Regist er B–1 1 Bo undar y-Scan R egi ste r " 103 ( BC_2, SysCheck_L(5), BIDIR, x, 119, 0, WEAK1 ), "& -- " 102 ( BC_2, BcCheck_H(13), BIDIR, x, 116, 0, Z ), "& -- " 101 ( BC_2, BcCheck_H(5), BIDIR, x, 116, 0, Z ), "& -- " 100 ( BC_[...]

B–12 21264/EV68A Boun dary-Scan Regi ster 21264/ EV68A Har dware R eferenc e Man ual Bo undar y-Scan Reg iste r " 38 ( BC_2, BcData_H(63), BIDIR, x, 50, 0, Z ), "& -- " 37 ( BC_2, SysCheck_L(7), BIDIR, x, 53, 0, WEAK1 ), "& -- " 36 ( BC_2, BcCheck_H(15), BIDIR, x, 50, 0, Z ), "& -- " 35 ( BC_2, BcChe[...]

21264/EV 68A Hardware Refere nce Manu al Serial Icache Load Pred ecode Values C–1 C Ser ial Icache Load Predecode V alues See the Al pha M otherboa rds S oftwar e Devel oper’ s Kit (SDK) f or i nformat ion.[...]

[...]

21264/EV 68A Hardware Refere nce Manu al PALc ode Restrictions and Guideli nes D–1 D P ALcode Re strictions and G uidelines D. 1 Re str ic ti on 1 : Reset Seq uence Re quir ed by Reti re Log ic an d Ma pper For conve nienc e of im ple mentation, the Ibox r etir e l ogic done st a tus bits are not initial- ized duri ng reset. I nstead, a s shown i[...]

D–2 PALcod e Re strictions and G uide lines 21264/ EV68A Har dware R eferenc e Man ual Res trictio n 1 : Reset Sequ ence Requir ed by Retire Lo gic and Mapp er addt f31,f31, f2 /* initia lize F .P. Reg. 2*/ mult f31,f31, f3 /* initia lize F .P. Reg. 3*/ addq r31,r31, r4 /* initia lize I nt. Reg. 4*/ addq r31,r31, r5 /* initia lize I nt. Reg. 5*/ [...]

21264/EV 68A Hardware Refere nce Manu al PALc ode Restrictions and Guideli nes D–3 Rest ric tion 1 : Reset S eque nce R eq uired by Retire Logic and Mappe r addq r31,r31, r27 /* initia lize I nt. Reg. 27*/ addt f31,f31, f26 /* initia lize F .P. Reg. 26*/ mult f31,f31, f27 /* initia lize F .P. Reg. 27*/ addq r31,r31, r28 /* initia lize I nt. Reg. [...]

D–4 PALcod e Re strictions and G uide lines 21264/ EV68A Har dware R eferenc e Man ual Res trictio n 1 : Reset Sequ ence Requir ed by Retire Lo gic and Mapp er ** or the PALcode, but it must be done in the manner a nd order belo w. ** ** It assumes that the retirator has been initialized, that the ** non-sh adow register s are mapped , and t hat [...]

21264/EV 68A Hardware Refere nce Manu al PALc ode Restrictions and Guideli nes D–5 Rest ric tion 1 : Reset S eque nce R eq uired by Retire Logic and Mappe r addq r31,r31, r21 /* initia lize S hadow Reg. 5* / br r31, nxt 8 /* contin ue exe cuting in next block*/ tch7: br r31, tch 8 /* fetch in next block */ nxt8: addq r31,r31, r22 /* initia lize S[...]

D–6 PALcod e Re strictions and G uide lines 21264/ EV68A Har dware R eferenc e Man ual Res trictio n 1 : Reset Sequ ence Requir ed by Retire Lo gic and Mapp er br r31,bccs hf /* contin ue shifting*/ bccend: mtpr r31,EV6__E XC_ADDR + 16 /* dummy IPR wri te - sets SCB D bit 4 */ addq r31,r31, r0 /* nop*/ addq r31,r31, r1 /* nop*/ mtpr r31,EV6_ _EXC[...]

21264/EV 68A Hardware Refere nce Manu al PALc ode Restrictions and Guideli nes D–7 Rest ric tion 1 : Reset S eque nce R eq uired by Retire Logic and Mappe r mtpr r31,EV6_ _PCTR_CTL /* 2nd buffer fetch bl ock for above map-s tall /* and 2n d clear PCTR_ CTL (S CRBRD=4 )*/ bis r31,1,r0 /* set up value for demon write*/ bis r31,1,r0 /* set up value [...]

D–8 PALcod e Re strictions and G uide lines 21264/ EV68A Har dware R eferenc e Man ual Restri ction 2 : No Multiple Writer s to IPRs in Sam e Scoreboa rd Group br r31,palb ase_init palbase_i nit: br r0, br60 /* r0 <- current locat ion */ br60: lda r1 , (EntryPoint -br60)(r0) / * r1 <- locat ion of codeba se */ mtpr r1, EV6__PAL_BA SE /* set[...]

21264/EV 68A Hardware Refere nce Manu al PALc ode Restrictions and Guideli nes D–9 Guide line 6 : Avoid Consecu tive Read- Mo dify-Wr ite- Read- Modif y-Wri te D.4 Gu ide line 6 : A void C ons ec ut ive Rea d- Mo dify -Wri te-R e ad- Mod ify -Write A void consecutive r ead-modi fy-writ e -rea d-m odify -w rite se qu ences to IP Rs i n the same sc[...]

D–10 PALcode Re strictions a nd Guide lines 21264/ EV68A Har dware R eferenc e Man ual Res trictio n 9 : PALmode Ist r eam Ad d ress Ra nges Bad_inter rupt_flow_ent ry: ADDQ R31, R31,R0 STF Fa,(R b) ; This STF m ight not unde rgo a dirty s ource registe r ; check and might give w rong r esults ADDQ R31, R31,R0 ADDQ R31, R31,R0 ......... .........[...]

21264/EV 68A Hardware Refere nce Manu al PALc ode Restrictions and Guideli nes D–1 1 Rest rictio n 11: Ib ox IP R Up date S ynchro ni zatio n D. 8 Rest ric ti on 1 1: Ibo x IPR U p date Sy nc hr oniz ati on When updat ing any Ib ox IPR, a r eturn to native (virtu a l) mode s hould use the HW_R ET instr uction with the associa ted ST ALL bit set t[...]

D–12 PALcode Re strictions a nd Guide lines 21264/ EV68A Har dware R eferenc e Man ual Guide line 16 : JSR-BAD V A D.12 Guid eline 16 : JS R-B AD V A A JSR memo ry form at instruc tio n that ge n erates a b ad V A (IAC V) trap re quire s P A L- code as sist ance to det er mine the co r rect exce p tion address . If the EXC_SUM[BAD_IV A] is set, b[...]

21264/EV 68A Hardware Refere nce Manu al PALc ode Restrictions and Guideli nes D–13 Rest riction 22: H W_RET /STA LL Aft er HW_MTP R IS0/IS 1 BIS R31, R31, R31 HW_MTPR R 9, ASN0, SCBD <4> HW_MTPR R 9, ASN1, SCBD <7> This s e quence guar ante es, through the r egist e r dependenc y on R 0, that neithe r HW_MTPR are issue d be fore s co[...]

D–14 PALcode Re strictions a nd Guide lines 21264/ EV68A Har dware R eferenc e Man ual Restriction 24: HW_RET /STALL After HW_MTPR IC_FLUS H, IC_FLUSH_ASM , xxx HW_ST/C - > R0 Bxx R0, t ry_again STQ ; Force next S T/C to fail if no p recedi ng LDxL HW_RET D.20 Re striction 24 : HW_RET/ST AL L After HW_M TPR IC_FLU SH, IC_FLUSH_ ASM, CLEAR_MAP [...]

21264/EV 68A Hardware Refere nce Manu al PALc ode Restrictions and Guideli nes D–15 Rest riction 27: R eset of ‘Forc e-F ail Lock Flag’ Stat e in PALcod e D.23 Re stric tio n 27: R ese t o f ‘F orce -Fail Lo ck F la g’ St at e in P AL cod e A virtua l mode load or store i s require d in P ALcode be for e the exe cution of any load- locked[...]

D–16 PALcode Re strictions a nd Guide lines 21264/ EV68A Har dware R eferenc e Man ual Res trictio n 3 0 : HW _MTP R and HW _MF PR to the Cbox C SR ALIGN_FET CH_BLOCK sys__cbox : mb ; quiet t he dstream hw_mfpr p6, EV6__ I_CTL ; (4,0L) ge t i_ctl lda p4, ^xFCF F(r31) ; mask for clearing SBE bits and p6, p4, p 4 ; clear SBE bits sbe_off_o ffset = [...]

21264/EV 68A Hardware Refere nce Manu al PALc ode Restrictions and Guideli nes D–17 Res tri ctio n 31 : I_ CTL[ V A_ 48] Upda te sys__cbox _over6: ; block 6 beq p6, sys__cbox_o ver8 ; branch if done bis r31, r31, r31 ; nop br r31, sys_ _cbox_over7 ; go to b lock 7 sys__cbox _touch6: ; br r31, sys_ _cbox_touch7 ; touch b lock 7 sys__cbox _over7: ;[...]

D–18 PALcode Re strictions a nd Guide lines 21264/ EV68A Har dware R eferenc e Man ual Res trictio n 33 : HW_L D Physical/L ock Use D.29 Re stri ctio n 33 : HW _LD Phy sic al /Lo ck Us e The HW_LD physi cal/ lock i nstruc tion must be one of the fir st t hr ee i nstruc tions in a quad-ins truction aligne d fetch bloc k. A pipe line error ca n occ[...]

21264/EV 68A Hardware Refere nce Manu al PALc ode Restrictions and Guideli nes D–19 Guidelin e 39: W riting Mu ltip le DTB E ntr ies in the Same P AL Flow D.35 Guideli ne 39: Writin g M ultip le DT B Entries in the Sa me P AL Fl ow If a P ALcode flo w intends t o writ e multiple DTB entries ( as wou ld occur i n a double miss), it m ust take care[...]

D–20 PALcode Re strictions a nd Guide lines 21264/ EV68A Har dware R eferenc e Man ual Restri ction 4 0: Scrubbing a Single-Bit E rro r hw_mtpr r31, EV6__DTB_ IA ; (7,1L) flush dtb lda r20, ^x3301(r3 1) ; set WE, RE bis r31, r3 1, r31 bis r31, r3 1, r31 hw_mtpr r 31, <EV6__MM_ STAT ! ^x80> ; wait fo r retire srl r4, #13 , r6 ; shift byt e o[...]

21264/EV 68A Hardware Refere nce Manu al PALc ode Restrictions and Guideli nes D–21 Restri ction 4 1: MTPR IT B_TAG, MTPR IT B_PTE Must be in the Sam e Fetc h Block D.37 Rest ri ction 41 : MTPR ITB_T AG , MTPR I TB_PTE Must be in th e Same F etc h Block W rite t he I TB_T AG and I TB_P TE register s in the same f etch block. Thi s avoid s a mispr[...]

D–22 PALcode Re strictions a nd Guide lines 21264/ EV68A Har dware R eferenc e Man ual Res tri ction 46: Avo iding Live locks in Speculativ e Lo ad CRD Hand lers D. 42 Rest ricti on 4 6: A void ing Li velo ck s in S p ecul at ive Load CR D Ha ndle rs Specul ative lo ad CRD handl ers that relea se from the inte rrupt wit hout scrubbing a cache blo[...]

21264/EV 68A Hardware Refere nce Manu al PALc ode Restrictions and Guideli nes D–23 Rest riction 47: C ache Evicti on for Single- Bit Cach e Error s If " C BOX_ERR[C_ADDR]" has no t cha nged whe n the CRD_HANDLER i s re- enter ed, or "CBOX_ERR[C_ST A T] == 0x0", all cac he location s should to be evi cted to avoid the live loc[...]

D–24 PALcode Re strictions a nd Guide lines 21264/ EV68A Har dware R eferenc e Man ual Res tri ctio n 48: M B Bracket ing of D cac he Wr ite s to Forc e Bad Data ECC and For ce D.44 Re stric tio n 48: MB Br a cketin g of Dc ach e Writes to F orc e Bad Dat a ECC a nd Force Bad T ag Parity W rites to D C_CTL[F_BAD_DECC] and DC_CTL[DCDA T_ERR_EN] mu[...]

21264/EV 68A Hardware Refere nce Manu al 21264/EV 68A-to-Bcache Pin Interface E–1 E 21264/ EV 68A-t o-B cache Pi n Inte rfac e This appendix pr ovid es the pin int erface b etwee n t he21 2 64/EV68A and Bcache SSRA M s. E. 1 For war d in g C loc k Pin G rou ping s T abl e E–1 lists t he corr espondance be tween t he clock si gnals f or the 2 12[...]

E–2 21264/EV 68A-to-Bcache Pin Int erface 21264/ EV68A Har dware R eferenc e Man ual Late-Wri te Non-Bur sting SS RAMs E.2 Lat e-Wri te Non -Bu rst ing S SRA M s T abl e E–2 provides th e data pin co nnections be tween late -wr ite non- bursting SSRAMs and the 21 264/EV68A or the syst e m board. T able E–3 p rovide s the sa me informa tion fo[...]

21264/EV 68A Hardware Refere nce Manu al 21264/EV 68A-to-Bcache Pin Interface E–3 Dual- Data Rate SSR AMs E.3 D ual-Da t a Rate SSRAMs T abl e E–4 provide s t he da ta pi n conne ction s between du al-data rate SS RAMs and t he 21264/EV68A or the syst em board. T able E–5 provide s the sa me inf ormation f or the tag pins . Data Pin Usage Set[...]

E–4 21264/EV 68A-to-Bcache Pin Int erface 21264/ EV68A Har dware R eferenc e Man ual Du al-Dat a Rat e SSRA Ms Tag Pin Usag e Unused Bcach e ta g pins should be p ulled to g round t hr ough a 200-ohm r esiste r . From board, p ulled up to VDD TMS_H From board, p ulled up to VDD TDI_H Unconnec ted or pull ed down to VSS TRST_L BcDa taOE _L OE_L (G[...]

21264/EV 68A Hardware Refere nce Manu al 21264/EV 68A-to-Bcache Pin Interface E–5 Dual- Data Rate SSR AMs Unconnec ted TRST_L From board, p ull ed down to VSS OE _L (G_L) From board, p ull ed up to VDD SD/DD_L (B3) Table E–5 Dual-Data Rate SSRAM Tag Pin Usage (Continued) 21264/EV68 A Signal Name or Boar d Connecti on Dual-Dat a Rate SSRAM Tag P[...]

[...]

21264/EV 68A Hardware Refere nce Manu al Glos sary This glossa ry provi des definit ions for spec ific t erms and acronyms associa ted with the Alpha 21264/ EV68A mic roprocessor and chips in gene ral. abor t The unit stop s the operat ion it is performi ng, with out saving status, t o p erfo rm some other operati on. addr ess spa ce num ber (ASN )[...]

Glossa ry –2 21264/ EV68A Har dware R eferenc e Man ual as ync hron ous syst em trap (AST) A soft ware- sim ula ted inter ru pt to a use r-defined r ou tine. AST s enable a user proc ess to be notif ied asynchronously , with respect to that proc ess, of t he oc currenc e of a specific event. I f a use r proc ess has def ined an AS T routine for a[...]

21264/EV 68A Hardware Refere nce Manu al boot Short for boots trap. Loading an operati ng system into memory is ca lled booting. BSR Boundar y-scan regis ter . bu ffe r An interna l memory area used for te mporary st orage of data re cords during inpu t or output ope rati ons. bugc h eck A software condi tion , usually the response to software’ s[...]

Glossa ry –4 21264/ EV68A Har dware R eferenc e Man ual cache hit The status return ed when a logic unit probes a c ache memory and fin ds a va lid cache entry at th e probed addre ss. ca che int erfer ence The re sult o f an op eration t hat a dversely aff ects the mechanisms and proc edur es use d to keep fre quently use d items in a cache. Suc[...]

21264/EV 68A Hardware Refere nce Manu al cl ock offset (or clk off set) The delay int entiona lly adde d to the forwarded clock to meet t he setup and hold requir ements at t he Receive Flop. CMOS Complement ary metal- oxide se miconductor . A silic on devic e formed by a process that combine s PMOS and NMOS semicondu c tor mate ria l. cond itiona [...]

Glossa ry –6 21264/ EV68A Har dware R eferenc e Man ual dire ct-mappin g c ache A cache or ganiz ation in whic h only one address compar ison is needed to loca te any data in the cache , because a ny blo ck of ma i n memory data can be placed in only one possible position in the ca che. dire ct mem ory acc ess (DMA) Access to memory by an I/O dev[...]

21264/EV 68A Hardware Refere nce Manu al exter nal cach e See sec ond-le vel c ach e. FE PROM Flash- erasa ble progr ammabl e read-only m emory . FEPROMs ca n be bank - or bulk- erase d. Contrast wit h EEPROM. FE T Field -effec t tra nsistor . FE U The unit with in the 21264/EV68A micr oprocess or that perfor ms floatin g- point c alcula- tions. fi[...]

Glossa ry –8 21264/ EV68A Har dware R eferenc e Man ual of the clock fo rward logic . Additio na lly , the framing clock can ha ve a period that is less than, e qual to, or gr eater th an the time it takes to send a full four cyc le command/ addre ss. GCLK Global cloc k within th e 21264/EV68A. gran ul arity A characte ristic of stor age syste ms[...]

21264/EV 68A Hardware Refere nce Manu al inter fa ce reset A synchronousl y received r eset sign al that is used to preset an d start the clock for ward- ing circ uitry . Durin g this reset, a ll forwarde d clocks ar e stopped and the preset table count values are applied to the counters; then, some number of c ycles late r , the clocks are enabl e[...]

Glossa ry –10 21264/ EV68A Har dware R eferenc e Man ual mach ine chec k An operati ng system acti on trigge red by certain syste m hardware -det ected erro rs that can be fatal to system oper ation. Once triggere d, machine check handler software ana- lyzes t he erro r . MAF Miss address f ile. mai n m emor y The lar ge memory , extern al to the[...]

21264/EV 68A Hardware Refere nce Manu al MS I Medium-sc ale int e gration . mult iproc essin g A processi ng method that repli cates the s equenti al compute r and i nterconnec ts the col - lectio n so that each pr ocessor can execute the same or a di fferent p rogram at t he sa me time. must be on e (MBO ) A field that must be sup plied as one. mu[...]

Glossa ry –12 21264/ EV68A Har dware R eferenc e Man ual outp u t m ux cou nt er Counter us ed to select th e output mux that dri ves address and data . It is rese t with the Interfa ce Re set and increm en ted by a c opy of t he local ly genera ted for ward ed clock . PAL Privile ged arc hitec ture li brary . See also P ALc ode. See also Prog ra[...]

21264/EV 68A Hardware Refere nce Manu al PQF P Plastic qua d flat pack. prim ary cac he The cache that is the fastest and close st to the proce ssor . The fir st-leve l caches , located on the CPU chip, composed of the Dca che a nd Icache . pr ogra m co un ter That portio n of the CPU that contains the vi rtual addre ss of the next instr uction to [...]

Glossa ry –14 21264/ EV68A Har dware R eferenc e Man ual read str eam buff er s Arra nge me nt wh ereby eac h m em ory m od ule i ndep end ently p refetc hes D RA M d ata prio r to a n actua l rea d requ e st for th at da ta. Re duc es a verage m em ory l atency while improving tot a l memory bandwidt h. recei ve counter Counter used to enable th[...]

21264/EV 68A Hardware Refere nce Manu al SDRAM Synchr onous dynamic random -acc ess memory . secon d -level cach e A cache memory provid ed outside of the mic roprocessor chip, usually lo cated on the same modul e. Also calle d board -level, e xterna l, or m odule-le vel cache . se t-assoc iative A form of cache or ganiz ation in whic h the locatio[...]

Glossa ry –16 21264/ EV68A Har dware R eferenc e Man ual STRAM Self-t im ed random-ac cess memory . supe r pipel ined Descri bes a pipelined mach ine that ha s a la rge r n umber of pipe st ages a nd more c om- plex sche duling and cont rol. See als o pipeline . supe r sc alar Descri bes a m achine a rchit ecture t hat all ows multiple i nde pend[...]

21264/EV 68A Hardware Refere nce Manu al UNPREDICTABLE Results or occ urrenc es that do not disru pt the basic opera tion of the proce ssor; the pro- cessor c ont inues t o exec ute instr uctions in its no rmal manner . Privil eged or un privi- leged sof tware can tr igger UNPREDICT ABLE results or occ urrence s. (This mea ning only appl ies when t[...]

Glossa ry –18 21264/ EV68A Har dware R eferenc e Man ual WAR W rite-a fter-rea d. word T wo conti guous bytes (16 bits) star ting on an arbitr ary byt e boundary . The bits are num- bered fr om right to left , 0 through 15. write -ba ck A cache mana gement technique i n which write op e ration data is writ ten into cache but is not written in to [...]

21264/EV 68A Hardware Refere nce Manu al Index–1 Index Numerics 21264/ E V68A, fea tures of , 1–3 32_BYTE _IO Cbox CSR defin e d , 5–34 A Ab br e via ti o n s , xix bina ry multip les , xix re gis t er ac ce ss , xi x AC ch ara ct eri stics , 9– 6 Addr ess conve nt ions , xx Aggr egate mode , 6 –18 Aligne d con vention , xx Alpha in s tru[...]

Index– 2 21264/ EV68A Har dware R eferenc e Man ual BC_SJ_BANK_ENABLE Cbox CSR defin e d , 5–34 BC_TAG_DDM_FALL_EN Cbox CSR , 4–47 defin e d , 5–36 BC_TAG_DDM_R ISE_EN Cbox CSR , 4–47 defin e d , 5–36 BC_W R_RD_BUB BLES Cbox CSR , 4–49 defin e d , 5–35 BC_WR_WR_BUBB L E Cbox CSR , 4 –53 defin e d , 5–34 BC_WRT_ST S Cbox CSR , 5 [...]

21264/EV 68A Hardware Refere nce Manu al Index–3 Cb ox data r egi ster C_ DATA , 5 –33 des cribed , 2– 11 , 4–3 dup lic at e Dca ch e tag a rr ay , 2–11 dup lic at e D cach e t ag a rr ay wi th , 4–13 HW_MTPR and HW_MFPR to CSR , D–15 I/O write bu ffer , 2–11 inte rna l process or regis ters , 5–3 pr obe queue , 2–1 1 read regis[...]

Index– 4 21264/ EV68A Har dware R eferenc e Man ual Dcache des cribed , 2– 12 dupli cate tag pa rity errors , 8–4 du plica te tags with , 4–1 3 error cas e summary for , 8 –10 fill fro m Bcache error , 8–6 fill fro m m emory erro rs , 8–8 in it ializ ed by Bi ST , 7–12 pipe lined , 2–16 single -bit correct able ECC error , 8– 3 [...]

21264/EV 68A Hardware Refere nce Manu al Index–5 ECC 64- bi t da t a an d c he ck bi t co d e , 8–2 Dcache da ta sin gle-bit corre ctab le errors , 8–3 for sys tem da ta bus , 8–2 memory/ sys tem port sin gle-bit corre ctab le errors , 8–7 sto re inst ructio ns , 8–4 ENABLE_EVICT Cb ox CSR , 4– 23 , 5–3 9 ENA BLE_PROBE _CHE CK Cbox [...]

Index– 6 21264/ EV68A Har dware R eferenc e Man ual I_CTL Ibox con trol regi ster , 5–15 aft er f au lt r e set , 7–8 aft er w arm rese t , 7–11 at po wer -o n re set st a te , 7–15 PALsh adow registe rs , 6 –11 through s lee p mode , 7– 10 VA_48 fiel d upda te , D–17 I_DA pin type , 3– 3 , 9–2 valu e s f or , 9–3 I_DA_CLK pin[...]

21264/EV 68A Hardware Refere nce Manu al Index–7 2–16 Integ e r exec uti on unit. See Ebox Int e ge r i ss u e q ue u e , 2–6 pipe lined , 2–15 Inter na l proce ssor regi s ters , 5–1 acce ss in g , 6–7 expl icitly wr itten , 6–8 impl ic itly wr it ten , 6–9 or dering acce ss , 6–9 paired fet ch order , 6–9 sc oreboard bits for [...]

Index– 8 21264/ EV68A Har dware R eferenc e Man ual MB, 21264/EV6 8A c ommand , 4–13 , 4–21 MB_CNT Cbox CSR , operat ion , 2–32 MBDone, Sys Dc com mand , 4–13 Mbox Dc ac he co ntro l regi ste r DC_CTL , 5 –30 Dcache sta tus registe r DC_S TAT , 5–3 1 des cribed , 2– 12 Dstr eam trans lati on buffe r , 2– 13 DTB addr e ss spa ce nu[...]

21264/EV 68A Hardware Refere nce Manu al Index–9 PALcode condi ti onal branc hes in , D–14 des cribed , 6– 1 entri es poi nts for , 6–12 exce ption en try poi nts , 6–13 guide l ines for , D–1 HW_LD i nstruc ti on , 6– 3 HW_MFPR ins tru ction , 6–6 HW_MTPR ins tructi on , 6–6 HW_RET in s tr uctio n , 6–5 HW_ST in struc tion , 6?[...]

Index– 10 21264/ EV68A Har dware R eferenc e Man ual Read Blk, 21264 /EV6 8A com mand , 4–21 system p robe s, with , 4–41 Read BlkI , 21264 /EV68A c ommand , 4–22 Read BlkMo d, 212 64/EV68A comm and , 4–22 system p robe s, with , 4–41 Read BlkMo dSpec , 21264/E V68A comm and , 4–22 Read BlkMo dVic , 21264/E V68A command , 4–22 Read [...]

21264/EV 68A Hardware Refere nce Manu al Index –11 St ore in struc tio ns Dcache ECC erro rs with , 8–4 I/O a ddress s pace , 2–29 I/O r efer en ce o rde ring , 2–31 M box or d e r t ra ps , 2–31 memory address space , 2–28 memory referenc e ordering , 2–30 t rans l at ion to e xterna l interf a ce , 4–5 St ore queue , 2–1 3 St or[...]

Index– 12 21264/ EV68A Har dware R eferenc e Man ual The rm al d es ign c h ara cter i sti cs , 10–6 Tms_H signa l pin , 3– 6 Tra ps load -load orde r , 2–31 Mb ox or d e r , 2–31 replay , 2–31 sto re-l oad or de r , 2–31 Trs t_L si gnal pin , 3–6 U UNALIGN fa ult , 6–13 Unali gne d conve nti on , xx UNDEFINED , xxii UNPREDICTABLE[...]