Epson S1C63000 manuale d’uso

MF855-03 Core CPU Manual CMOS 4 - BIT SINGLE CHIP MICROCOMPUTER S1C63000[...]

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The information of the product number change Configuration of product number Devices Comparison table between new and previous number S1C63 Family processors Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales r[...]

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S1C63000 CORE CPU MANUAL EPSON i CONTENTS S1C63000 C ORE CPU M ANU AL PREF A CE This manual explains the architecture, operation and instruction of the core CPU S1C63 of the CMOS 4-bit single chip microcomputer S1C63 Family . Also, since the memory configuration and the peripheral cir cuit configuration is differ ent for each device of the S1C63 Fa[...]

ii EPSON S1C63000 CORE CPU MANUAL CONTENTS 3.5 Interrupts ...................................................................................................... 26 3.5.1 Interrupt vectors ........................................................................................ 26 3.5.2 Interrupt sequence .............................................[...]

S1C63000 CORE CPU MANUAL EPSON 1 CHAPTER 1: OUTLINE CHAPTER 1O UTLINE The S1C63000 is the core CPU of the 4-bit single chip micr ocomputer S1C63 Family that utilizes original EPSON architectur e. It has a lar ge and linear addressable space, maximum 64K wor ds (13 bits/ word) pr ogram memory (code ROM area) and maximum 64K wor ds (4 bits/wor d) dat[...]

2 EPSON S1C63000 CORE CPU MANUAL CHAPTER 1: OUTLINE 1.3 Bloc k Diagram Figure 1.3.1 shows the S1C63000 block diagram. F ig. 1.3.1 S1C63000 block diagr am 1.4 Input-Output Signals T ables 1.4.1 (a) and 1.4.1 (b) show the input/output signals between the S1C63000 and peripheral cir cuits. T able 1.4.1(a) Input/output signal list (1) Type I/O I I I O [...]

S1C63000 CORE CPU MANUAL EPSON 3 CHAPTER 1: OUTLINE T able 1.4.1(b) Input/output signal list (2) Type I/O I I/O I/O O O O I O I I O O O O O O O Function Terminal name Data bus Bus control signal System control signal Interrupt signal Status signal I00 – I12 M00 – M15 D0 – D3 RD WR RDIV SR USLP NMI IRQ IACK NACK FETCH STOP IF BS16 DBS0 DBS1 In[...]

4 EPSON S1C63000 CORE CPU MANUAL CHAPTER 2: ARCHITECTURE CHAPTER 2A RCHITECTURE This chapter explains the S1C63000 ALU, r egisters, configuration of the program memory ar ea and data memory area, and addr essing. 2.1 ALU and Registers 2.1.1 ALU The ALU (Arithmetic and Logic Unit) loads 4-bit data fr om a memory or a r egister and operates the data [...]

S1C63000 CORE CPU MANUAL EPSON 5 CHAPTER 2: ARCHITECTURE • A and B registers The A and B registers are r espective 4-bit data r egisters that are used for data transfer and operation with other registers, data memories or immediate data. They ar e used independently for 4-bit trans- fer/operations and used in a BA pair that makes the B register t[...]

6 EPSON S1C63000 CORE CPU MANUAL CHAPTER 2: ARCHITECTURE Shift/Rotate instructions that change the Z flag: SLL, SRL, RL, RR The Z flag is used for condition judgments when executing the conditional jump ("JRZ sign8" and "JRNZ sign8") instructions, thus it is possible to branch pr ocessing to a r outine according to the operation[...]

S1C63000 CORE CPU MANUAL EPSON 7 CHAPTER 2: ARCHITECTURE 2.1.4 Arithmetic operations with numbering system In the S1C63000, some instructions support a numbering system. These instr uctions ar e indicated with the following notations in the instruction list. ADC operand,n4 SBC operand,n4 INC operand,n4 DEC operand,n4 (See "Instruction List&quo[...]

8 EPSON S1C63000 CORE CPU MANUAL CHAPTER 2: ARCHITECTURE • Notes in numbering operations When performing a numbering operation, set operands in corr ect notation according to the radix before operation. For example, if a decimal operation is done for hexadecimal values (AH to FH), the corr ect operation result is not obtained as shown in the foll[...]

S1C63000 CORE CPU MANUAL EPSON 9 CHAPTER 2: ARCHITECTURE The EXT register maintains the data set pr eviously until new data is written or an initial r eset. In other words, the content of the EXT r egister becomes valid by only setting the E flag using an above instr uc- tion without the register writing and is used for an extended addr essing. How[...]

10 EPSON S1C63000 CORE CPU MANUAL CHAPTER 2: ARCHITECTURE • 16-bit data transf er/arithmetic for the index registers X and Y The following six instructions, which handle the X or Y register and have an 8-bit immediate data as the operand, permit the extended addressing. LDB %XL,imm8 LDB %YL,imm8 ADD %X,sign8 ADD %Y,sign8 CMP %X,imm8 CMP %Y,imm8 W[...]

S1C63000 CORE CPU MANUAL EPSON 11 CHAPTER 2: ARCHITECTURE 2.2 Program Memory 2.2.1 Configuration of program memory The S1C63000 can access a maximum 64K-word ( × 13 bits) pr ogram memory space. In the individual model of the S1C63 Family , the ROM of which size is decided depending on the model is connected to this space to write a program and sta[...]

12 EPSON S1C63000 CORE CPU MANUAL CHAPTER 2: ARCHITECTURE 2.2.3 Branch instructions V arious branch instructions ar e pr ovided for program r epeat and subroutine calls that change a sequen- tial program flow contr olled with the PC. The branch instruction modifies the PC to branch the pr ogram to an optional address. The types of the branch instr [...]

S1C63000 CORE CPU MANUAL EPSON 13 CHAPTER 2: ARCHITECTURE (2) Instruction with a 4-bit A register data that specifies a relativ e address JR %A This instruction branches the pr ogram sequence with the content of the A register as an unsigned 4-bit relative addr ess. The range that can be branched is fr om the next instruction addr ess +0 to +15 (ab[...]

14 EPSON S1C63000 CORE CPU MANUAL CHAPTER 2: ARCHITECTURE PC relative jump instructions Program memory 0000H FFFFH xxxxH xxxxH-127 JR sign8 xxxxH+128 0000H FFFFH xxxxH-1 xxxxH xxxxH-32767 LDB %EXT,imm8 JR sign8 xxxxH+32768 0000H FFFFH xxxxH JR %A xxxxH+16 A=0 → xxxxH+1 : A=15 → xxxxH+16 0000H FFFFH xxxxH JR %BA xxxxH+256 BA=0 → xxxxH+1 : BA=2[...]

S1C63000 CORE CPU MANUAL EPSON 15 CHAPTER 2: ARCHITECTURE This instruction permits the extended addr essing with the E flag, and the 8-bit relative addr ess can be extended into 16 bits (the contents of the EXT r egister becomes the high-order 8 bits). In this case, the range that can be branched is fr om the next instruction address -32768 to +327[...]

16 EPSON S1C63000 CORE CPU MANUAL CHAPTER 2: ARCHITECTURE • Return instructions (RET , RETS, RETD , RETI) A r eturn instruction is used to r eturn fr om a subroutine called by the call instr uction to the r outine that called the subroutine. Return operation is done by loading the PC value (addr ess next to the call instruction) that was stor ed [...]

S1C63000 CORE CPU MANUAL EPSON 17 CHAPTER 2: ARCHITECTURE TOASCII: ;BCD to ASCII conversion LDB %EXT,0x00 ;Sets address 0040H LDB %XL,0x40 JR %A RETD 0x30 ;"0" RETD 0x31 ;"1" RETD 0x32 ;"2" RETD 0x33 ;"3" RETD 0x34 ;"4" RETD 0x35 ;"5" RETD 0x36 ;"6" RETD 0x37 ;"7" RETD [...]

18 EPSON S1C63000 CORE CPU MANUAL CHAPTER 2: ARCHITECTURE 2.3.2 Addressing f or data memory For addressing to access the data memory , the index registers X and Y , and stack pointers SP1 and SP2 are used. (The next section will explain the stack pointers.) Index registers X and Y ar e both 16-bit r egisters and cover the entir e 64K data memory sp[...]

S1C63000 CORE CPU MANUAL EPSON 19 CHAPTER 2: ARCHITECTURE • Accessing f or addresses 0000H to 003FH Data in this ar ea is used for a relative addr ess by the "JR [addr6]" and "CALR [addr6]" explained in Section 2.2.3. This area is suitable for setting up various flags and counters since the bit operation instructions (CLR, SET[...]

20 EPSON S1C63000 CORE CPU MANUAL CHAPTER 2: ARCHITECTURE The SP1 increment/decr ement af fects only the 8-bit field shown in Figur e 2.3.3.1, and its operation is performed cyclically . In other words, if the SP1 is decremented by the PUSH instr uction or other conditions when the SP1 is 00H (indicating the memory addr ess 0000H), the SP1 becomes [...]

S1C63000 CORE CPU MANUAL EPSON 21 CHAPTER 2: ARCHITECTURE F ig . 2.3.3.4 4-bit stack oper ation The SP2 increment/decr ement af fects only the 8-bit field shown in Figure 2.3.3.3, and its operation is performed cyclically . In other words, if the SP2 is decremented by the PUSH instr uction or other conditions when the SP2 is 00H (indicating the mem[...]

22 EPSON S1C63000 CORE CPU MANUAL CHAPTER 3: CPU OPERATION CHAPTER 3 CPU O PERA TION This section explains the CPU operations and the operation timings. 3.1 T iming Generator and Bus Cycle The S1C63000 has a built-in timing generator . The timing generator of the S1C63000 generates the two- phase divided signals PK and PL based on the clock (CLK) i[...]

S1C63000 CORE CPU MANUAL EPSON 23 CHAPTER 3: CPU OPERATION 3.3 Data Bus (Data Memory) Control 3.3.1 Data bus status The S1C63000 output the data bus status in each bus cycle externally on the DBS0 and DBS1 signals as a 2-bit status. The peripheral cir cuits perform the direction contr ol of the bus driver and other contr ols with these signals. The[...]

24 EPSON S1C63000 CORE CPU MANUAL CHAPTER 3: CPU OPERATION 3.3.3 Interrupt vector read When an interrupt is generated, the CPU r eads the interrupt vector output to the data bus by the periph- eral circuit that has generated the interr upt. The interrupt vector r ead status indicates this bus cycle. The peripheral circuit outputs the interr upt vec[...]

S1C63000 CORE CPU MANUAL EPSON 25 CHAPTER 3: CPU OPERATION 3.3.5 Memory read In an execution cycle that reads data fr om the data memory , the read signal RD is output between the T2 and T3 states and data is read fr om the data bus. The address bus outputs the tar get addr ess during this bus cycle. The 4-bit/16-bit access is the same as the memor[...]

26 EPSON S1C63000 CORE CPU MANUAL CHAPTER 3: CPU OPERATION After an initial reset, all the interr upts including NMI ar e masked until both the stack pointers SP1 and SP2 are set by softwar e. 3.4.2 Initial setting of internal registers An initial reset initializes the internal r egisters in the CPU as shown in T able 3.4.2.1. T able 3.4.2.1 Initia[...]

S1C63000 CORE CPU MANUAL EPSON 27 CHAPTER 3: CPU OPERATION Each of the addresses listed above corr esponds to an interrupt factor individually . A branch (jump) instruction to the interrupt service r outine should be written to these addr esses. Up to 15 hardwar e interrupt vectors ar e available, however , the number of vectors is dif ferent depen[...]

28 EPSON S1C63000 CORE CPU MANUAL CHAPTER 3: CPU OPERATION 3. Instructions that set the stack pointer LDB %SP1,%BA LDB %SP2,%BA These two instructions ar e also accepted after fetching the next instruction. However , these instructions must be executed as a pair . When one of them is fetched at first, all the interr upts including NMI are masked (i[...]

S1C63000 CORE CPU MANUAL EPSON 29 CHAPTER 3: CPU OPERATION CLK PK PL PC FETCH BS16 DBS1/0 WR RD RDIV DA00 – DA15 D0 – D3 M00 – M15 IRQ IACK NACK IF 0 12345 DUMMY (010xH) ANY pc-3 pc-1 010xH ANY 212 A N Y pc SP2-1 DUMMY SP1-1 F reg. xH pc ANY LD %A,[%X] 03 ANY [00xxH] pc-2 LDB %EXT,imm8 ANY 00xxH Interrupt processing by the hardware Executing [...]

30 EPSON S1C63000 CORE CPU MANUAL CHAPTER 3: CPU OPERATION • Software interrupts The software interr upts are generated by the INT instruction. T ime of the interrupt generation is determined by the software, so the I flag setting does not af fect the interrupt. That pr ocessing is the same as the subroutine that evacuates the F r egister into th[...]

S1C63000 CORE CPU MANUAL EPSON 31 CHAPTER 3: CPU OPERATION 3.6 Standby Status The S1C63000 has a function that stops the CPU operation and it can greatly r educe power consumption. This function should be used to stop the CPU when ther e is no processing to be executed in the CPU, example while the application program waits an interr upt. This is a[...]

32 EPSON S1C63000 CORE CPU MANUAL CHAPTER 3: CPU OPERATION During SLEEP status, as in the HAL T status, the contents of the r egisters in the CPU that have been set before shifting ar e maintained if rated voltage is supplied. Figure 3.6.2.1 shows the sequence of shifting to the SLEEP status and r estarting. When an interrupt that r eleases the SLE[...]

S1C63000 CORE CPU MANUAL EPSON 33 CHAPTER 4: INSTRUCTION SET CHAPTER 4I NSTR UCTION S ET The S1C63000 offers high machine cycle ef ficiency and a high speed instruction set. It has 47 basic instructions (412 instructions in all) that ar e designed as an instruction system permitting r elocatable programming. This chapter explains about the addr ess[...]

34 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET • Register direct addressing The register dir ect addr essing is the addressing mode when specifying a r egister for the sour ce and/ or destination. Register names should be written with % in fr ont. Instructions in which the operand has the following r egister name operate in this add[...]

S1C63000 CORE CPU MANUAL EPSON 35 CHAPTER 4: INSTRUCTION SET These instructions perform a PC r elative branch using the content (4 bits) of a memory specified with the [addr6] as a relative addr ess. The branch destination addr ess is [the addr ess next to the branch instruction] + [the contents (0 to 15) of the memory specified with the addr6]. (2[...]

36 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET Examples: LDB %EXT,0x15 LDB %XL,0x7D ...W orks as "LD %X, 0157D" LDB %EXT,0xB8 ADD %X,0x4F ...W orks as "ADD %X, 0xB84F" LDB %EXT,0xE6 CMP %X,0xA2 ...W orks as "CMP %X, 0x19A2" ∗ 19H = FFH - [EXT] (E6H) Above examples use the X register , but they work the [...]

S1C63000 CORE CPU MANUAL EPSON 37 CHAPTER 4: INSTRUCTION SET • Signed 16-bit PC relative addressing The addressing mode of the following branch instr uctions, which have an 8-bit r elative address as the operand, change to the signed 16-bit PC relative addr essing with the E flag set to "1". Consequently , it is possible to extend the b[...]

38 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET 4.2.2 Symbol meanings The following indicates the meanings of the symbols used in the instruction list. Register names A ........................... Data register A (4 bits) B ........................... Data register B (4 bits) BA ........................ BA regist e r pa i r ( 8 b i t s[...]

S1C63000 CORE CPU MANUAL EPSON 39 CHAPTER 4: INSTRUCTION SET Memory [%X], [X] ............. Memory where the X register specifies [%Y], [Y] ............. Memory where the Y r egister specifies [00addr6] ............ Memory within 0000H to 003FH where the addr6 specifies [FFaddr6] ............ Memory within FFC0H to FFFFH wher e the addr6 specifies [...]

40 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET 4.2.3 Instruction list by function LD %A,%A %A,%B %A,%F %A,imm4 %A,[%X] %A,[%X]+ %A,[%Y] %A,[%Y]+ LD %B,%A %B,%B %B,imm4 %B,[%X] %B,[%X]+ %B,[%Y] %B,[%Y]+ LD %F,%A %F,imm4 LD [%X],%A [%X],%B [%X],imm4 [%X],[%Y] [%X],[%Y]+ [%X]+,%A [%X]+,%B [%X]+,imm4 [%X]+,[%Y] [%X]+,[%Y]+ LD [%Y],%A [%Y][...]

S1C63000 CORE CPU MANUAL EPSON 41 CHAPTER 4: INSTRUCTION SET ADD %A,%A %A,%B %A,imm4 %A,[%X] %A,[%X]+ %A,[%Y] %A,[%Y]+ ADD %B,%A %B,%B %B,imm4 %B,[%X] %B,[%X]+ %B,[%Y] %B,[%Y]+ ADD [%X],%A [%X],%B [%X],imm4 [%X]+,%A [%X]+,%B [%X]+,imm4 ADD [%Y],%A [%Y],%B [%Y],imm4 [%Y]+,%A [%Y]+,%B [%Y]+,imm4 ADC %A,%A %A,%B %A,imm4 %A,[%X] %A,[%X]+ %A,[%Y] %A,[%Y[...]

42 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET SUB %B,%A %B,%B %B,imm4 %B,[%X] %B,[%X]+ %B,[%Y] %B,[%Y]+ SUB [%X],%A [%X],%B [%X],imm4 [%X]+,%A [%X]+,%B [%X]+,imm4 SUB [%Y],%A [%Y],%B [%Y],imm4 [%Y]+,%A [%Y]+,%B [%Y]+,imm4 SBC %A,%A %A,%B %A,imm4 %A,[%X] %A,[%X]+ %A,[%Y] %A,[%Y]+ SBC %B,%A %B,%B %B,imm4 %B,[%X] %B,[%X]+ %B,[%Y] %B,[%Y[...]

S1C63000 CORE CPU MANUAL EPSON 43 CHAPTER 4: INSTRUCTION SET CMP [%X],%A [%X],%B [%X],imm4 [%X]+,%A [%X]+,%B [%X]+,imm4 CMP [%Y],%A [%Y],%B [%Y],imm4 [%Y]+,%A [%Y]+,%B [%Y]+,imm4 INC [00addr6] DEC [00addr6] ADC %B,%A,n4 ∗ 1 %B,[%X],n4 %B,[%X]+,n4 %B,[%Y],n4 %B,[%Y]+,n4 ADC [%X],%B,n4 ∗ 1 [%X],0,n4 [%X]+,%B,n4 [%X]+,0,n4 ADC [%Y],%B,n4 ∗ 1 [%Y[...]

44 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET AND %A,%A %A,%B %A,imm4 %A,[%X] %A,[%X]+ %A,[%Y] %A,[%Y]+ AND %B,%A %B,%B %B,imm4 %B,[%X] %B,[%X]+ %B,[%Y] %B,[%Y]+ AND %F,imm4 AND [%X],%A [%X],%B [%X],imm4 [%X]+,%A [%X]+,%B [%X]+,imm4 AND [%Y],%A [%Y],%B [%Y],imm4 [%Y]+,%A [%Y]+,%B [%Y]+,imm4 OR %A,%A %A,%B %A,imm4 %A,[%X] %A,[%X]+ %A,[...]

S1C63000 CORE CPU MANUAL EPSON 45 CHAPTER 4: INSTRUCTION SET XOR %A,%A %A,%B %A,imm4 %A,[%X] %A,[%X]+ %A,[%Y] %A,[%Y]+ XOR %B,%A %B,%B %B,imm4 %B,[%X] %B,[%X]+ %B,[%Y] %B,[%Y]+ XOR %F,imm4 XOR [%X],%A [%X],%B [%X],imm4 [%X]+,%A [%X]+,%B [%X]+,imm4 XOR [%Y],%A [%Y],%B [%Y],imm4 [%Y]+,%A [%Y]+,%B [%Y]+,imm4 BIT %A,%A %A,%B %A,imm4 %A,[%X] %A,[%X]+ %A[...]

46 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET SLL %A %B [%X] [%X]+ [%Y] [%Y]+ SRL %A %B [%X] [%X]+ [%Y] [%Y]+ RL %A %B [%X] [%X]+ [%Y] [%Y]+ RR %A %B [%X] [%X]+ [%Y] [%Y]+ 1000011110000 1000011110100 1000011100000 1000011100001 1000011100010 1000011100011 1000011110001 1000011110101 1000011100100 1000011100101 1000011100110 100001110[...]

S1C63000 CORE CPU MANUAL EPSON 47 CHAPTER 4: INSTRUCTION SET Note: • The e xtended addressing (combined with the E flag) is a vailab le only f or the instructions indi- cated with ● ● in the EXT . mode ro w . Operation of other instructions (indicated with × ) cannot be guaranteed, therefore do not write data to the EXT register or do not se[...]

48 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET 4.2.4 List in alphabetical order ADC %A,%A %A,%B %A,imm4 %A,[%X] %A,[%X]+ %A,[%Y] %A,[%Y]+ %B,%A %B,%A,n4 %B,%B %B,imm4 %B,[%X] %B,[%X],n4 %B,[%X]+ %B,[%X]+,n4 %B,[%Y] %B,[%Y],n4 %B,[%Y]+ %B,[%Y]+,n4 [%X],%A [%X],%B [%X],%B,n4 [%X],imm4 [%X],0,n4 [%X]+,%A [%X]+,%B [%X]+,%B,n4 [%X]+,imm4 [[...]

S1C63000 CORE CPU MANUAL EPSON 49 CHAPTER 4: INSTRUCTION SET ADD [%X],imm4 [%X]+,%A [%X]+,%B [%X]+,imm4 [%Y],%A [%Y],%B [%Y],imm4 [%Y]+,%A [%Y]+,%B [%Y]+,imm4 AND %A,%A %A,%B %A,imm4 %A,[%X] %A,[%X]+ %A,[%Y] %A,[%Y]+ %B,%A %B,%B %B,imm4 %B,[%X] %B,[%X]+ %B,[%Y] %B,[%Y]+ %F,imm4 [%X],%A [%X],%B [%X],imm4 [%X]+,%A [%X]+,%B [%X]+,imm4 [%Y],%A [%Y],%B [...]

50 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET BIT [%Y],imm4 [%Y]+,%A [%Y]+,%B [%Y]+,imm4 CALR [00addr6] CALR sign8 CALZ imm8 CLR [00addr6],imm2 [FFaddr6],imm2 CMP %A,%A %A,%B %A,imm4 %A,[%X] %A,[%X]+ %A,[%Y] %A,[%Y]+ %B,%A %B,%B %B,imm4 %B,[%X] %B,[%X]+ %B,[%Y] %B,[%Y]+ %X,imm8 %Y,imm8 [%X],%A [%X],%B [%X],imm4 [%X]+,%A [%X]+,%B [%X][...]

S1C63000 CORE CPU MANUAL EPSON 51 CHAPTER 4: INSTRUCTION SET INC [%X],n4 [%X]+,n4 [%Y],n4 [%Y]+,n4 [00addr6] INT imm6 JP %Y JR %A %BA sign8 [00addr6] JRC sign8 JRNC sign8 JRNZ sign8 JRZ sign8 LD %A,%A %A,%B %A,%F %A,imm4 %A,[%X] %A,[%X]+ %A,[%Y] %A,[%Y]+ %B,%A %B,%B %B,imm4 %B,[%X] %B,[%X]+ %B,[%Y] %B,[%Y]+ %F,%A %F,imm4 [%X],%A [%X],%B [%X],imm4 [[...]

52 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET LDB %BA,%YH %BA,%YL %BA,imm8 %BA,[%X]+ %BA,[%Y]+ %EXT,%BA %EXT,imm8 %SP1,%BA %SP2,%BA %XH,%BA %XL,%BA %XL,imm8 %YH,%BA %YL,%BA %YL,imm8 [%X]+,%BA [%X]+,imm8 [%Y]+,%BA NOP OR %A,%A %A,%B %A,imm4 %A,[%X] %A,[%X]+ %A,[%Y] %A,[%Y]+ %B,%A %B,%B %B,imm4 %B,[%X] %B,[%X]+ %B,[%Y] %B,[%Y]+ %F,imm4[...]

S1C63000 CORE CPU MANUAL EPSON 53 CHAPTER 4: INSTRUCTION SET RETI RETS RL %A %B [%X] [%X]+ [%Y] [%Y]+ RR %A %B [%X] [%X]+ [%Y] [%Y]+ SBC %A,%A %A,%B %A,imm4 %A,[%X] %A,[%X]+ %A,[%Y] %A,[%Y]+ %B,%A %B,%A,n4 %B,%B %B,imm4 %B,[%X] %B,[%X],n4 %B,[%X]+ %B,[%X]+,n4 %B,[%Y] %B,[%Y],n4 %B,[%Y]+ %B,[%Y]+,n4 [%X],%A [%X],%B [%X],%B,n4 [%X],imm4 [%X],0,n4 [%X[...]

54 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET SLL [%X] [%X]+ [%Y] [%Y]+ SLP SRL %A %B [%X] [%X]+ [%Y] [%Y]+ SUB %A,%A %A,%B %A,imm4 %A,[%X] %A,[%X]+ %A,[%Y] %A,[%Y]+ %B,%A %B,%B %B,imm4 %B,[%X] %B,[%X]+ %B,[%Y] %B,[%Y]+ [%X],%A [%X],%B [%X],imm4 [%X]+,%A [%X]+,%B [%X]+,imm4 [%Y],%A [%Y],%B [%Y],imm4 [%Y]+,%A [%Y]+,%B [%Y]+,imm4 TST [[...]

S1C63000 CORE CPU MANUAL EPSON 55 CHAPTER 4: INSTRUCTION SET 4.2.5 List of extended addressing instructions ↓ ––– ↓ ––– ↓ ––– ↓ ––– ↓ ––– ↓ ––– ↓ ––– ↓ ––– ↓ ––– ↓ ––– ↓ ––– ↓ ––– ↓ ––– ↓ ––– ↓ – ↓ – ↓ – ↓ – ↓ – ↓ ?[...]

56 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – [FFimm8] ← [FFimm8] + A[...]

S1C63000 CORE CPU MANUAL EPSON 57 CHAPTER 4: INSTRUCTION SET ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –[...]

58 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ –– ↓ – ↓ – ↓ – ↓ – ↓ [...]

S1C63000 CORE CPU MANUAL EPSON 59 CHAPTER 4: INSTRUCTION SET 4.3 Instruction F ormats All the instructions of the S1C63000 ar e configured with 1 wor d (13 bits) as follows: I OP Code Examples: LD ADD PUSH %A,%B %A,[%X] %F II OP Code Examples: LD ADC BIT %A,imm4 [%Y],%B,n4 %B,imm4 III OP Code Examples: INC CALR INT [addr6] [addr6] imm6 IV OP Code E[...]

60 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET Add with carry r' reg. to r reg. 1 cycle Function: r ← r + r' + C Adds the content of the r' r egister (A or B) and carry (C) to the r register (A or B). Code: Mnemonic MSB LSB ADC %A,%A 11001111 1000 X 19F0H, (19F1H) ADC %A,%B 11001111 1001 X 19F2H, (19F3H) ADC %B,%A 110[...]

S1C63000 CORE CPU MANUAL EPSON 61 CHAPTER 4: INSTRUCTION SET ADC %r ,%r' ADC %r ,imm4 Add with carry immediate data imm4 to r reg. 1 cycle Function: r ← r + imm4 + C Adds the 4-bit immediate data imm4 and carry (C) to the r r egister (A or B). Code: Mnemonic MSB LSB ADC %A,imm4 1100 11100 i 3 i 2 i 1 i 0 19C0H–19CFH ADC %B,imm4 1100 11101 [...]

62 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET ADC %r ,[%ir] Add with carry location [ir reg.] to r reg. 1 cycle Function: r ← r + [ir] + C Adds the content of the data memory addressed by the ir r egister (X or Y) and carry (C) to the r register (A or B). Code: Mnemonic MSB LSB ADC %A,[%X] 1100111100000 19E0H ADC %A,[%Y] 1100111100[...]

S1C63000 CORE CPU MANUAL EPSON 63 CHAPTER 4: INSTRUCTION SET ADC [%ir],%r Add with carry r reg. to location [ir reg.] 2 cycles Function: [ir] ← [ir] + r + C Adds the content of the r register (A or B) and carry (C) to the data memory addressed by the ir register (X or Y). Code: Mnemonic MSB LSB ADC [%X],%A 1100111101000 1 9 E 8 H ADC [%X],%B 1100[...]

64 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET ADC [%ir],imm4 ADC [%ir]+,imm4 Add with carry immediate data imm4 to location [ir reg.] 2 cycles Function: [ir] ← [ir] + imm4 + C Adds the 4-bit immediate data imm4 and carry (C) to the data memory addressed by the ir register (X or Y). Code: Mnemonic MSB LSB ADC [%X],imm4 1100 11000 i [...]

S1C63000 CORE CPU MANUAL EPSON 65 CHAPTER 4: INSTRUCTION SET ADC %B,%A,n4 Add with carry A reg. to B reg. in specified radix 2 cycles Function: B ← N's adjust (B + A + C) Adds the content of the A register and carry (C) to the B register . The operation r esult is adjusted with n4 as the radix. The C flag is set by a carry accor ding to the [...]

66 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET ADC %B,[%ir]+,n4 ADC [%ir],%B,n4 Add with carry B reg. to location [ir reg.] in specified radix 2 cycles Function: [ir] ← N's adjust ([ir] + B + C) Adds the content of the B register and carry (C) to the data memory addr essed by the ir register (X or Y). The operation r esult is a[...]

S1C63000 CORE CPU MANUAL EPSON 67 CHAPTER 4: INSTRUCTION SET ADC [%ir]+,%B,n4 Add with carry B reg. to location [ir reg.] in specified radix and increment ir reg. 2 cycles Function: [ir] ← N's adjust ([ir] + B + C), ir ← ir + 1 Adds the content of the B register and carry (C) to the data memory addr essed by the ir register (X or Y). The o[...]

68 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET ADC [%ir]+,0,n4 ADD %r ,%r' Add r' reg. to r reg. 1 cycle Function: r ← r + r' Adds the content of the r' register (A or B) to the r register (A or B). Code: Mnemonic MSB LSB ADD %A,%A 110010111000X 1970H, (1971H) ADD %A,%B 110010111001X 1972H, (1973H) ADD %B,%A 1100[...]

S1C63000 CORE CPU MANUAL EPSON 69 CHAPTER 4: INSTRUCTION SET ADD %r ,imm4 Add immediate data imm4 to r reg. 1 cycle Function: r ← r + imm4 Adds the 4-bit immediate data imm4 to the r register (A or B). Code: Mnemonic MSB LSB ADD %A,imm4 1100 10100 i 3 i 2 i 1 i 0 1940H–194FH ADD %B,imm4 1100 10101 i 3 i 2 i 1 i 0 1950H–195FH Flags: EIC Z ↓ [...]

70 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET ADD %r ,[%ir]+ Add location [ir reg.] to r reg. and increment ir reg. 1 cycle Function: r ← r + [ir], ir ← ir + 1 Adds the content of the data memory addressed by the ir r egister (X or Y) to the r r egister (A or B). Then increments the ir r egister (X or Y). The flags change due to [...]

S1C63000 CORE CPU MANUAL EPSON 71 CHAPTER 4: INSTRUCTION SET ADD [%ir]+,%r Add r reg. to location [ir reg.] and increment ir reg. 2 cycles Function: [ir] ← [ir] + r , ir ← ir + 1 Adds the content of the r register (A or B) to the data memory addressed by the ir r egister (X or Y). Then increments the ir r egister (X or Y). The flags change due [...]

72 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET ADD [%ir]+,imm4 Add immediate data imm4 to location [ir reg.] and increment ir reg. 2 cycles Function: [ir] ← [ir] + imm4, ir ← ir + 1 Adds the 4-bit immediate data imm4 to the data memory addr essed by the ir register (X or Y). Then increments the ir r egister (X or Y). The flags cha[...]

S1C63000 CORE CPU MANUAL EPSON 73 CHAPTER 4: INSTRUCTION SET ADD %ir ,sign8 Add immediate data sign8 to ir reg. 1 cycle Function: ir ← ir + sign8 Adds the signed 8-bit immediate data sign8 (-128 to 127) to the ir r egister (X or Y). This instr uc- tion does not affect the C flag r egardless of the operation r esult. Code: Mnemonic MSB LSB ADD %X,[...]

74 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET AND %r ,imm4 Logical AND of immediate data imm4 and r reg. 1 cycle Function: r ← r ∧ imm4 Performs a logical AND operation of the 4-bit immediate data imm4 and the content of the r register (A or B), and stores the r esult in the r register . Code: Mnemonic MSB LSB AND %A,imm4 1101 00[...]

S1C63000 CORE CPU MANUAL EPSON 75 CHAPTER 4: INSTRUCTION SET AND %r ,[%ir] AND %r ,[%ir]+ Logical AND of location [ir reg.] and r reg. and increment ir reg. 1 cycle Function: r ← r ∧ [ir], ir ← ir + 1 Performs a logical AND operation of the content of the data memory addr essed by the ir register (X or Y) and the content of the r r egister (A[...]

76 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET AND [%ir],%r Logical AND of r reg. and location [ir reg.] 2 cycles Function: [ir] ← [ir] ∧ r Performs a logical AND operation of the content of the r r egister (A or B) and the content of the data memory addressed by the ir r egister (X or Y), and stores the r esult in that address. C[...]

S1C63000 CORE CPU MANUAL EPSON 77 CHAPTER 4: INSTRUCTION SET AND [%ir],imm4 Logical AND of immediate data imm4 and location [ir reg.] 2 cycles Function: [ir] ← [ir] ∧ imm4 Performs a logical AND operation of the 4-bit immediate data imm4 and the content of the data memory addressed by the ir r egister (X or Y), and stores the r esult in that ad[...]

78 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET BIT %r ,%r’ T est bit of r reg. with r’ reg. 1 cycle Function: r ∧ r’ Performs a logical AND of the content of the r ’ register (A or B) and the content of the r register (A or B) to check the bits of the r r egister . The Z flag is changed due to the operation r esult, but the [...]

S1C63000 CORE CPU MANUAL EPSON 79 CHAPTER 4: INSTRUCTION SET BIT %r ,[%ir] BIT %r ,[%ir]+ T est bit of r reg. with location [ir reg.] and increment ir reg. 1 cycle Function: r ∧ [ir], ir ← ir + 1 Performs a logical AND of the content of the data memory addr essed by the ir register (X or Y) and the content of the r register (A or B) to check th[...]

80 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET BIT [%ir],%r T est bit of location [ir reg.] with r reg. 1 cycle Function: [ir] ∧ r Performs a logical AND of the content of the r r egister (A or B) and the content of the data memory addressed by the ir r egister (X or Y) to check the bits of the memory . The Z flag is changed due to [...]

S1C63000 CORE CPU MANUAL EPSON 81 CHAPTER 4: INSTRUCTION SET BIT [%ir],imm4 BIT [%ir]+,imm4 T est bit of location [ir reg.] with immediate data imm4 and increment ir reg. 1 cycle Function: [ir] ∧ imm4, ir ← ir + 1 Performs a logical AND of the 4-bit immediate data imm4 and the content of the data memory addressed by the ir r egister (X or Y) to[...]

82 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET CALR [addr6] Call subroutine at relative location [addr6] 2 cycles Function: ([(SP1-1) * 4+3]~[(SP1-1) * 4]) ← PC + 1, SP1 ← SP1 - 1, PC ← PC + [addr6] + 1 (addr6 = 0000H–003FH) Saves the address next to this instruction to the stack as a r eturn address, then adds the content of [...]

S1C63000 CORE CPU MANUAL EPSON 83 CHAPTER 4: INSTRUCTION SET CALZ imm8 Call subroutine at location imm8 1 cycle Function: ([(SP1-1) * 4+3]~[(SP1-1) * 4]) ← PC + 1, SP1 ← SP1 - 1, PC ← imm8 Saves the address next to this instruction to the stack as a r eturn address, then unconditionally calls the subroutine started fr om the addr ess (0000H?[...]

84 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET CMP %r ,%r’ CMP %r ,imm4 Compare r reg. with immediate data imm4 1 cycle Function: r - imm4 Subtracts the 4-bit immediate data imm4 fr om the content of the r register (A or B). It changes the flags (Z and C), but does not change the content of the r egister . Code: Mnemonic MSB LSB CMP[...]

S1C63000 CORE CPU MANUAL EPSON 85 CHAPTER 4: INSTRUCTION SET CMP %r ,[%ir] CMP %r ,[%ir]+ Compare r reg. with location [ir reg.] 1 cycle Function: r - [ir] Subtracts the content of the data memory addr essed by the ir register (X or Y) from the content of the r register (A or B). It changes the flags (Z and C), but does not change the content of th[...]

86 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET CMP [%ir],%r CMP [%ir]+,%r Compare location [ir reg.] with r reg. and increment ir reg. 1 cycle Function: [ir] - r , ir ← ir + 1 Subtracts the content of the r register (A or B) from the content of the data memory addr essed by the ir register (X or Y). It changes the flags (Z and C), b[...]

S1C63000 CORE CPU MANUAL EPSON 87 CHAPTER 4: INSTRUCTION SET CMP [%ir],imm4 CMP [%ir]+,imm4 Compare location [ir reg.] with immediate data imm4 and increment ir reg. 1 cycle Function: [ir] - imm4, ir ← ir + 1 Subtracts the 4-bit immediate data imm4 fr om the content of the data memory addressed by the ir register (X or Y). It changes the flags (Z[...]

88 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET CMP %ir ,imm8 DEC [addr6] Compare ir reg. with immediate data imm8 1 cycle Function: ir - imm8 Subtracts the 8-bit immediate data imm8 from the content of the ir r egister (X or Y). It changes the flags (Z and C), but does not change the r egister . Code: Mnemonic MSB LSB CMP %X,imm8 0111[...]

S1C63000 CORE CPU MANUAL EPSON 89 CHAPTER 4: INSTRUCTION SET DEC [ir],n4 Decrement location [ir] in specified radix 2 cycles Function: [ir] ← N’s adjust ([ir] - 1) Decrements (-1) the content of the data memory addr essed by the ir r egister (X or Y). The operation result is adjusted with n4 as the radix. Code: Mnemonic MSB LSB DEC [%X],n4 1110[...]

90 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET DEC %sp EX %A,%B Exchange A reg. and B reg. 1 cycle Function: A ↔ B Exchanges the contents of the A register and B register . Code: Mnemonic MSB LSB E X % A , % B 1111111110111 1FF7H Flags: EIC Z ↓ ––– Mode: Src: Register direct Dst: Register dir ect Extended addressing: Invalid[...]

S1C63000 CORE CPU MANUAL EPSON 91 CHAPTER 4: INSTRUCTION SET EX %r ,[%ir] Exchange r reg. and location [ir reg.] 2 cycles Function: r ↔ [ir] Exchanges the contents of the r register (A or B) and data memory addressed by the ir r egister (X or Y). Code: Mnemonic MSB LSB EX %A,[%X] 1000011111000 10F8H EX %A,[%Y] 1000011111010 1 0 F A H EX %B,[%X] 1[...]

92 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET HAL T Set CPU to HALT mode 2 cycles Function: Halt Sets the CPU to HAL T status. The CPU stops operating, thus the power consumption is reduced. Peripheral cir cuits such as the oscillation circuit still operate. An interrupt causes it to r eturn from HAL T status to the normal pr ogram e[...]

S1C63000 CORE CPU MANUAL EPSON 93 CHAPTER 4: INSTRUCTION SET INC [ir],n4 Increment location [ir] in specified radix 2 cycles Function: [ir] ← N’s adjust ([ir] + 1) Increments (+1) the content of the data memory addr essed by the ir r egister (X or Y). The operation result is adjusted with n4 as the radix. Code: Mnemonic MSB LSB INC [%X],n4 1110[...]

94 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET INC %sp INT imm6 Software interrupt 3 cycles Function: [SP2-1] ← F , SP2 ← SP2 - 1, ([(SP1-1) * 4+3]~[(SP1-1) * 4]) ← PC + 1, SP1 ← SP1 - 1, PC ← imm6 (imm6 = 0100H–013FH) Saves the content of the F register and the r eturn addr ess (this instruction addr ess + 1) to the stack[...]

S1C63000 CORE CPU MANUAL EPSON 95 CHAPTER 4: INSTRUCTION SET JP %Y Indirect jump using Y reg. 1 cycle Function: PC ← Y Loads the content of the Y r egister into the PC to branch unconditionally . Code: Mnemonic MSB LSB J P % Y 1111 11111001 X 1FF2H, (1FF3H) Flags: EIC Z ↓ ––– Mode: Register direct Extended addressing: Invalid JR %A J ump [...]

96 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET JR %BA Jump to relative location BA reg. 1 cycle Function: PC ← PC + BA + 1 Adds the content of the BA r egister to the addr ess next to this instruction, to unconditionally branch to that address. Branch destination range is the next addr ess of this instruction +0 to 255. Code: Mnemon[...]

S1C63000 CORE CPU MANUAL EPSON 97 CHAPTER 4: INSTRUCTION SET JR sign8 Jump to relative location sign8 1 cycle Function: PC ← PC + sign8 + 1 (sign8 = -128~127) Adds the relative addr ess specified with the sign8 to the addr ess next to this instruction, to unconditionally branch to that address. Branch destination range is the next addr ess of thi[...]

98 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET JRNC sign8 Jump to relative location sign8 if C flag is reset 1 cycle Function: If C = 0 then PC ← PC + sign8 + 1 (sign8 = -128~127) Executes the "JR sign8" instruction if the C (carry) flag has been r eset to "0", otherwise executes the next instruction. Code: Mnemo[...]

S1C63000 CORE CPU MANUAL EPSON 99 CHAPTER 4: INSTRUCTION SET JRZ sign8 Jump to relative location sign8 if Z flag is set 1 cycle Function: If Z = 1 then PC ← PC + sign8 + 1 (sign8 = -128~127) Executes the "JR sign8" instruction if the Z (zer o) flag has been reset to "0", otherwise executes the next instruction. Code: Mnemonic [...]

100 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET LD %r ,imm4 Load immediate data imm4 into r reg. 1 cycle Function: r ← imm4 Loads the 4-bit immediate data imm4 into the r r egister (A, B or F). Code: Mnemonic MSB LSB L D % A , i m m 4 111101100 i 3 i 2 i 1 i 0 1EC0H–1ECFH L D % B , i m m 4 111101101 i 3 i 2 i 1 i 0 1ED0H–1EDFH L[...]

S1C63000 CORE CPU MANUAL EPSON 101 CHAPTER 4: INSTRUCTION SET LD %r ,[%ir]+ Load location [ir reg.] into r reg. and increment ir reg. 1 cycle Function: r ← [ir], ir ← ir + 1 Loads the content of the data memory addressed by the ir r egister (X or Y) into the r register (A or B). Then increments the ir r egister (X or Y). Code: Mnemonic MSB LSB [...]

102 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET LD [%ir]+,%r Load r reg. into location [ir reg.] and increment ir reg. 1 cycle Function: [ir] ← r, i r ← ir + 1 Loads the content of the r register (A or B) into the data memory addressed by the ir r egister (X or Y). Then incr ements the ir r egister (X or Y). Code: Mnemonic MSB LSB[...]

S1C63000 CORE CPU MANUAL EPSON 103 CHAPTER 4: INSTRUCTION SET LD [%ir]+,imm4 Load immediate data imm4 into location [ir reg.] and increment ir reg. 1 cycle Function: [ir] ← imm4, ir ← ir + 1 Loads the 4-bit immediate data imm4 into the data memory addr essed by the ir register (X or Y). Then increments the ir r egister (X or Y). Code: Mnemonic [...]

104 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET LD [%ir],[%ir’]+ Load location [ir’ reg.] into location [ir reg.] and increment ir’ reg. 2 cycles Function: [ir] ← [ir ’], ir ’ ← ir ’ + 1 Loads the content of the data memory addressed by the ir ’ register (X or Y) into the data memory addressed by the ir r egister (Y [...]

S1C63000 CORE CPU MANUAL EPSON 105 CHAPTER 4: INSTRUCTION SET LD [%ir]+,[%ir’]+ Load location [ir’ reg.] into location [ir reg.] and increment ir and ir’ reg. 2 cycles Function: [ir] ← [ir ’], ir ← ir + 1, ir ’ ← ir ’ + 1 Loads the content of the data memory addressed by the ir ’ register (X or Y) into the data memory addressed [...]

106 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET LDB %BA,[%ir]+ Load location [ir reg.] into BA reg. and increment ir reg. 2 cycles Function: A ← [ir], B ← [ir + 1], ir ← ir + 2 Loads the 2-word data in the data memory into the BA register . The content of the data memory addressed by the ir r egister (X or Y) is loaded into the [...]

S1C63000 CORE CPU MANUAL EPSON 107 CHAPTER 4: INSTRUCTION SET LDB %BA,%rr Load rr reg. into BA reg. 1 cycle Function: BA ← rr Loads the content of the rr register (XL, XH, YL or YH) into the BA register . Code: Mnemonic MSB LSB LDB %BA,%XL 1111 111001000 1FC8H LDB %BA,%XH 1111111001001 1FC9H LDB %BA,%YL 1111 111001010 1FCAH LDB %BA,%YH 1111111001[...]

108 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET LDB [%ir]+,%BA Load BA reg. into location [ir reg.] and increment ir reg. 2 cycles Function: [ir] ← A, [ir + 1] ← B, ir ← ir + 2 Loads the content of the BA r egister into the data memory . The content of the A r egister is loaded into the data memory addressed by the ir r egister [...]

S1C63000 CORE CPU MANUAL EPSON 109 CHAPTER 4: INSTRUCTION SET LDB %EXT ,imm8 Load immediate data imm8 into EXT reg. 1 cycle Function: EXT ← imm8 Loads the 8-bit immediate data into the EXT register . The E flag is set to "1". Code: Mnemonic MSB LSB L D B % E X T , i m m 8 0100 0 i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 0800H–08FFH Flags: EIC Z[...]

110 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET LDB %rr ,imm8 Load immediate data imm8 into rr reg. 1 cycle Function: rr ← imm8 Loads the 8-bit immediate data imm8 into the rr (XL or YL) register . Code: Mnemonic MSB LSB LDB %XL,imm8 01010 i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 0A00H–0AFFH LDB %YL,imm8 01011 i 7 i 6 i 5 i 4 i 3 i 2 i 1 i[...]

S1C63000 CORE CPU MANUAL EPSON 111 CHAPTER 4: INSTRUCTION SET LDB %sp,%BA Load BA reg. into stack pointer 1 cycle Function: sp ← BA Loads the content of the BA register into the stack pointer sp (SP1 or SP2). Code: Mnemonic MSB LSB LDB %SP1,%BA 111111100010 X 1 F C 4 H , (1FC5H) LDB %SP2,%BA 111111100011 X 1 F C 6 H , (1FC7H) Flags: EIC Z ↓ –[...]

112 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET OR %r ,%r’ OR %r ,imm4 Logical OR of r’ reg. and r reg. 1 cycle Function: r ← r ∨ r’ Performs a logical OR operation of the content of the r ’ register (A or B) and the content of the r register (A or B), and stores the r esult in the r register . Code: Mnemonic MSB LSB O R %[...]

S1C63000 CORE CPU MANUAL EPSON 113 CHAPTER 4: INSTRUCTION SET OR %F ,imm4 Logical OR of immediate data imm4 and F reg. 1 cycle Function: F ← F ∨ imm4 Performs a logical OR operation of the 4-bit immediate data imm4 and the content of the F (flag) register , and stores the r esult in the r r egister . It is possible to set any flag. Code: Mnemon[...]

114 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET OR %r ,[%ir]+ Logical OR of location [ir reg.] and r reg. and increment ir reg. 1 cycle Function: r ← r ∨ [ir], ir ← ir +1 Performs a logical OR operation of the content of the data memory addr essed by the ir register (X or Y) and the content of the r r egister (A or B), and store[...]

S1C63000 CORE CPU MANUAL EPSON 115 CHAPTER 4: INSTRUCTION SET OR [%ir]+,%r Logical OR of r reg. and location [ir reg.] and increment ir reg. 2 cycles Function: [ir] ← [ir] ∨ r , ir ← ir +1 Performs a logical OR operation of the content of the r register (A or B) and the content of the data memory addressed by the ir r egister (X or Y), and st[...]

116 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET OR [%ir]+,imm4 Logical OR of immediate data imm4 and location [ir reg.] and increment ir reg. 2 cycles Function: [ir] ← [ir] ∨ imm4, ir ← ir +1 Performs a logical OR operation of the 4-bit immediate data imm4 and the content of the data memory addressed by the ir r egister (X or Y)[...]

S1C63000 CORE CPU MANUAL EPSON 117 CHAPTER 4: INSTRUCTION SET POP %ir PUSH %r Push r reg. onto stack 1 cycle Function: [SP2-1] ← r , SP2 ← SP2 -1 Decrements the stack pointer SP2, then stor es the content of the r r egister (A, B or F) into the address indicated by the SP2. Code: Mnemonic MSB LSB PUSH %A 1111111100111 1FE7H PUSH %B 111111110011[...]

118 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET PUSH %ir Push ir reg. onto stack 1 cycle Function: ([(SP1-1) * 4+3]~[(SP1-1) * 4]) ← ir , SP1 ← SP1 -1 Decrements the stack pointer SP1, then stor es the content of the ir r egister (X or Y) into the addresses (4 wor ds) indicated by the SP1 (SP1 indicates the lowest addr ess). Code:[...]

S1C63000 CORE CPU MANUAL EPSON 119 CHAPTER 4: INSTRUCTION SET RETD imm8 Return from subroutine and load imm8 into location [X] 3 cycles Function: PC ← ([SP1 * 4+3]~[SP1 * 4]), SP1 ← SP1 +1, [X] ← i3-0, [X+1] ← i7-4, X ← X + 2 After executing the RET instruction, stor es the 8-bit immediate data imm8 into the data memory (2 words) indicate[...]

120 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET RETS RL %r Rotate left r reg. with carry 1 cycle Function: Rotates the content of the r register (A or B) including the carry (C) to the left for 1 bit. The content of the C flag moves to bit 0 of the r register and bit 3 moves to the C flag. Code: Mnemonic MSB LSB R L % A 1000011110010 [...]

S1C63000 CORE CPU MANUAL EPSON 121 CHAPTER 4: INSTRUCTION SET RL [%ir] Rotate left location [ir reg.] with carry 2 cycles Function: Rotates the content of the data memory addressed by the ir r egister (X or Y) including the carry (C) to the left for 1 bit. The content of the C flag moves to bit 0 of the data memory and bit 3 moves to the C flag. Co[...]

122 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET RR %r RR [%ir] Rotate right r reg. with carry 1 cycle Function: Rotates the content of the r register (A or B) including the carry (C) to the right for 1 bit. The content of the C flag moves to bit 3 of the r register and bit 0 moves to the C flag. Code: Mnemonic MSB LSB R R % A 10000111[...]

S1C63000 CORE CPU MANUAL EPSON 123 CHAPTER 4: INSTRUCTION SET RR [%ir]+ Rotate right location [ir reg.] with carry and increment ir reg. 2 cycles Function: , ir ← ir +1 Rotates the content of the data memory addressed by the ir r egister (X or Y) including the carry (C) to the right for 1 bit. The content of the C flag moves to bit 3 of the data [...]

124 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET SBC %r ,imm4 Subtract with carry immediate data imm4 from r reg. 1 cycle Function: r ← r - imm4 - C Subtracts the 4-bit immediate data imm4 and carry (C) from the r r egister (A or B). Code: Mnemonic MSB LSB SBC %A,imm4 110001100 i 3 i 2 i 1 i 0 18C0H–18CFH SBC %B,imm4 110001101 i 3 [...]

S1C63000 CORE CPU MANUAL EPSON 125 CHAPTER 4: INSTRUCTION SET SBC %r ,[%ir]+ Subtract with carry location [ir reg.] from r reg. and increment ir reg. 1 cycle Function: r ← r - [ir] - C, ir ← ir + 1 Subtracts the content of the data memory addr essed by the ir register (X or Y) and carry (C) from the r r egister (A or B). Then increments the ir [...]

126 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET SBC [%ir]+,%r Subtract with carry r reg. from location [ir reg.] and increment ir reg. 2 cycles Function: [ir] ← [ir] - r - C, ir ← ir + 1 Subtracts the content of the r register (A or B) and carry (C) from the data memory addr essed by the ir register (X or Y). Then increments the i[...]

S1C63000 CORE CPU MANUAL EPSON 127 CHAPTER 4: INSTRUCTION SET SBC [%ir]+,imm4 Subtract with carry immediate data imm4 from location [ir reg.] and increment ir reg. 2 cycles Function: [ir] ← [ir] - imm4 - C, ir ← ir + 1 Subtracts the immediate data imm4 and carry (C) fr om the data memory addressed by the ir register (X or Y). Then incr ements t[...]

128 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET SBC %B,[%ir],n4 Subtract with carry location [ir reg.] from B reg. in specified radix 2 cycles Function: B ← N’s adjust (B - [ir] - C) Subtracts the content of the data memory addr essed by the ir register (X or Y) and carry (C) from the B r egister . The operation result is adjusted[...]

S1C63000 CORE CPU MANUAL EPSON 129 CHAPTER 4: INSTRUCTION SET SBC [%ir],%B,n4 Subtract with carry B reg. from location [ir reg.] in specified radix 2 cycles Function: [ir] ← N’s adjust ([ir] - B - C) Subtracts the content of the B r egister and carry (C) from the data memory addr essed by the ir register (X or Y). The operation r esult is adjus[...]

130 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET SBC [%ir],0,n4 Subtract carry from location [ir reg.] in specified radix 2 cycles Function: [ir] ← N’s adjust ([ir] - 0 - C) Subtracts the carry (C) from the data memory addr essed by the ir r egister (X or Y). The opera- tion result is adjusted with n4 as the radix. The C flag is se[...]

S1C63000 CORE CPU MANUAL EPSON 131 CHAPTER 4: INSTRUCTION SET SET [addr6],imm2 Set bit imm2 in location [addr6] 2 cycles Function: [addr6] ← [addr6] ∨ (2 imm2 ) (addr6 = 0000H–003FH or FFC0H–FFFFH) Sets the bit specified with the imm2 in the data memory specified with the addr6 to "1". Code: Mnemonic MSB LSB SET [00addr6],imm2 1 0[...]

132 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET SLL [%ir] SLL [%ir]+ Shift left location [ir reg.] logical and increment ir reg. 2 cycles Function: , ir ← ir + 1 Shifts the content of the data memory addr essed by the ir register (X or Y) to the left for 1 bit. Bit 3 of the r register moves to the C flag and bit 0 goes "0"[...]

S1C63000 CORE CPU MANUAL EPSON 133 CHAPTER 4: INSTRUCTION SET SLP Set CPU to SLEEP mode 2 cycles Function: Sleep Sets the CPU to SLEEP status. The CPU and the peripheral circuits including the oscillation cir cuit stops operating, thus the power consumption is substantially reduced. An interrupt from outside the MCU causes it to r eturn fr om SLEEP[...]

134 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET SRL [%ir] Shift right location [ir reg.] logical 2 cycles Function: Shifts the content of the data memory addr essed by the ir register (X or Y) to the right for 1 bit. Bit 0 of the r register moves to the C flag and bit 3 goes "0". Code: Mnemonic MSB LSB S R L [ % X ] 10000111[...]

S1C63000 CORE CPU MANUAL EPSON 135 CHAPTER 4: INSTRUCTION SET SUB %r ,%r’ Subtract r’ reg. from r reg. 1 cycle Function: r ← r - r ’ Subtracts the content of the r ’ register (A or B) from the r register (A or B). Code: Mnemonic MSB LSB SUB %A,%A 110000111000 X 1870H, (1871H) SUB %A,%B 110000111001 X 1872H, (1873H) SUB %B,%A 110000111010 [...]

136 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET SUB %r ,[%ir] SUB %r ,[%ir]+ Subtract location [ir reg.] from r reg. and increment ir reg. 1 cycle Function: r ← r - [ir], ir ← ir + 1 Subtracts the content of the data memory addr essed by the ir register (X or Y) from the r register (A or B). Then increments the ir r egister (X or [...]

S1C63000 CORE CPU MANUAL EPSON 137 CHAPTER 4: INSTRUCTION SET SUB [%ir],%r SUB [%ir]+,%r Subtract r reg. from location [ir reg.] and increment ir reg. 2 cycles Function: [ir] ← [ir] - r , ir ← ir + 1 Subtracts the content of the r register (A or B) from the data memory addr essed by the ir register (X or Y). Then incr ements the ir register (X [...]

138 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET SUB [%ir],imm4 Subtract immediate data imm4 from location [ir reg.] 2 cycles Function: [ir] ← [ir] - imm4 Subtracts the 4-bit immediate data imm4 from the data memory addr essed by the ir r egister (X or Y). Code: Mnemonic MSB LSB SUB [%X],imm4 1100 00000 i 3 i 2 i 1 i 0 1800H – 180F[...]

S1C63000 CORE CPU MANUAL EPSON 139 CHAPTER 4: INSTRUCTION SET TST [addr6],imm2 XOR %r ,%r’ Exclusive OR r’ reg. and r reg. 1 cycle Function: r ← r ∀ r’ Performs an exclusive OR operation of the content of the r ’ register (A or B) and the content of the r register (A or B), and stores the r esult in the r register . Code: Mnemonic MSB L[...]

140 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET XOR %r ,imm4 Exclusive OR immediate data imm4 and r reg. 1 cycle Function: r ← r ∀ imm4 Performs an exclusive OR operation of the 4-bit immediate data imm4 and the content of the r register (A or B), and stores the r esult in the r register . Code: Mnemonic MSB LSB XOR %A,imm4 110111[...]

S1C63000 CORE CPU MANUAL EPSON 141 CHAPTER 4: INSTRUCTION SET XOR %r ,[%ir] Exclusive OR location [ir reg.] and r reg. 1 cycle Function: r ← r ∀ [ir] Performs an exclusive OR operation of the content of the data memory addr essed by the ir register (X or Y) and the content of the r r egister (A or B), and stores the result in the r r egister . [...]

142 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET XOR [%ir],%r Exclusive OR r reg. and location [ir reg.] 2 cycles Function: [ir] ← [ir] ∀ r Performs an exclusive OR operation of the content of the r r egister (A or B) and the content of the data memory addressed by the ir r egister (X or Y), and stores the r esult in that address. [...]

S1C63000 CORE CPU MANUAL EPSON 143 CHAPTER 4: INSTRUCTION SET XOR [%ir],imm4 Exclusive OR immediate data imm4 and location [ir reg.] 2 cycles Function: [ir] ← [ir] ∀ imm4 Performs an exclusive OR operation of the 4-bit immediate data imm4 and the content of the data memory addressed by the ir r egister (X or Y), and stores the r esult in that a[...]

144 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET Index ADC %r ,%r ’ ............ 61 ADC %r ,imm4 ........ 61 ADC %r ,[%ir] .......... 62 ADC %r ,[%ir]+ ........ 62 ADC [%ir],%r .......... 63 ADC [%ir]+,%r ....... 63 ADC [%ir],imm4 ..... 64 ADC [%ir]+,imm4 .. . 64 ADC %B,%A,n4 ..... 65 ADC %B,[%ir],n4 . .. 65 ADC %B,[%ir]+,n4 . 66 ADC[...]

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http://www.epson.co.jp/device/ Core CPU Manual S1C63000 EPSON Electronic Devices Website ELECTRONIC DEVICES MARKETING DIVISION First issue July, 1 995 Printed February, 2001 in Japan A M[...]