Intel Core 2 Duo E8230 manuale d’uso

Intel ® Core ™ 2 Duo Processor E8000 Δ and E7000 Δ Series Specification Update — on 45 nm Process in the 775-land LGA Package June 2009 Notice: The Intel ® Core TM 2 Duo processor may contain design defects or errors known as errata which may cause the product to deviate from published speci fications. Current characte rized err ata are do [...]

2 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNE CTION WITH INTEL® PRODUCTS . NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL AS[...]

Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 3[...]

4 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e Contents Contents ....................................................................................................................... ...... 4 Revision History ............................................................................................................... .... 5 Preface [...]

Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 5 Revision History Revision Number Description Date 001 Initial release of Intel ® Core ™ 2 Duo Desktop Processor E8000 Series Specification Update Jan 7 th 2008 002  Added Erratum AW51 Feb 1 st 2008 003  Added Errata AW52 to AW54 Feb 13 th 2008 004  Changed document tit le to inc[...]

Preface 6 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e Preface This doc ument is an u pdate t o the spe cifications c ontained in the docu ments liste d in the following Affected Documents/Related Documents tabl e. It is a compilation of device and document errata and specification cl arifications and changes, and i s intended for hardw[...]

Preface Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 7 Nomenclature S-Spec Number is a five-dig it code used to identify products. Products are differentiated by their unique characteri sti cs (e.g., core speed, L2 cache size, package type, etc.) as described in the processor i den tification information table. Care should be taken to r[...]

Summary Tables of Changes 8 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e Summary Tables of Changes The following table ind icates t he Specifica tion Chang es, Errata , Specificat ion Clarifications or Document ation Chang es, which app ly to the liste d MCH ste ppings. Intel intends to fix some of the errata in a future stepping of the[...]

Summary Tables of Changes Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 9 Item Numbering Each Spec ification Upd ate ite m is prefixe d with a cap ital lette r to disting uish the product. The key below details the letters that are used i n Intel’s microprocessor specific ation up date s: A = Dual-Core Intel® Xeon® processor 7000 seq[...]

Summary Tables of Changes 10 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e AH = Intel® Core™2 Duo/Solo processor for Intel® Centrino® Duo processor technology AI = Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000 and E4000 sequence AJ = Quad-Core Intel® Xeon® processor 5300 series AK = Inte[...]

Summary Tables of Changes Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 11 NO C0 M0 E0 R0 Plan ERRATA AW4 X X X X No Fix Non-Temporal Data Store May be Observed in Wrong Program Order AW5 X X X X No Fix Page Access Bit May be Set Prior to Signaling a Code Segment Limit Fault AW6 X X X X No Fix Updating Code Page Direct ory Attributes wit[...]

Summary Tables of Changes 12 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e NO C0 M0 E0 R0 Plan ERRATA AW25 X X X X No Fix Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt AW26 X X X X No Fix Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced Before Higher Priority Interrupts [...]

Summary Tables of Changes Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 13 NO C0 M0 E0 R0 Plan ERRATA AW45 X X Fixed Partial Streaming Load Instruction Sequence May Cause the Processor to Hang AW46 X X Fixed Self/Cross Modifying Code Ma y Not be Detected or May Cause a Machine Check Exception AW47 X X Fixed Data TLB Eviction Condition in[...]

Summary Tables of Changes 14 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e NO C0 M0 E0 R0 Plan ERRATA AW67 X X No Fix Enabling PECI via the PECI_CTL MSR incorrectly writes CPUID_FEATURE_MASK1 MSR AW68 X X No Fix INIT Incorrectl y Resets IA32_LSTAR MSR AW69 X X X X No Fix Corruption of CS Segment Register During RSM While Transitioning Fr[...]

Identification Information Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 15 Identification Information Figure 1. Processor Package Example §[...]

Component Identification Information 16 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e Component Identification Information The Intel ® Core™2 duo processor can be iden tified by the following values: Reserved Extended Family 1 Extended Model 2 Reserved Processor Type 3 Family Code 4 Model Number 5 Stepping ID 6 31:28 27:20 19:16 15:14[...]

Component Identification Information Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 17 Table 1. Intel ® Core™2 Duo Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Processor Number Speed Core/Bus Package Notes SLAPC M0 3 MB 10676h E7200 2.53 GHz / 1066 MHz 775-land LGA 1, 2, 3, 6, 7, 8[...]

Errata 18 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e Errata AW1. EFLAGS Discrepancy on Page Faults after a Translation Change Problem: This erratum is regarding the case where paging structures are modified to change a linear address from writ able to non-writable w ithout software performing an appropriate TLB invalidat ion. When a s[...]

Errata Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 19 AW3. Store to WT Memory Data May be Seen in Wrong Order by Two Subsequent Loads Problem: When data of Store to WT memory is used by two subsequent lo ads of one thread and another thread performs ca cheable write to the same address the first load may get the data from extern al mem[...]

Errata 20 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e Violation #GP (General Prot ection Fault). Due to th is erratum, code #PF may be handled incorrectly , if all of the f ollowing condit ions are met:  A PDE (Page Directory Entry) i s modified without invali dating the corresponding TLB (Translation Look-aside Buffer) entry  Co[...]

Errata Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 21 Workaround: None identified. Status: For the steppings affected, see th e Summary Tables of Changes. AW9. A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware Problem: The MONITOR inst ruction is used to ar m the address monitoring hardw[...]

Errata 22 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e AW12. Code Segment Limit Violation May Occur on 4 Gigabyte Limit Check Problem: Code Segment limit v iolation may occur on 4 Gigabyt e limit check when t he code streamwraps around in a way that one instruction ends at the last byte of the segment and the next instruction begins at [...]

Errata Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 23 AW15. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering Violations. Problem: Under certain condit ions as described in the Soft ware Developers Manual section “Out[...]

Errata 24 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e Workaround: None identified. Status: For the steppings affected, see th e Summary Tables of Changes. AW18. Code Segment Limit/Canonical Fa ults on RSM May be Serviced before Higher Priority Interrupts/Exceptions Problem: Normally, when the processor encounter s a Segment Limit or Ca[...]

Errata Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 25 AW21. Premature Execution of a Load Operation Prior to Exception Handler Invocation Problem: If any of the below circumstances occur, it is possible that the load portion of the instruction will have executed bef ore the exception h andler is entered. 1) If an instruction that perfo[...]

Errata 26 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e b) RSM from an SMI during a HLT instruction. Implication: There may be a smaller than expe cted value in the INST_RETIRED performance monitoring counter. The ex tent to which th is value is smaller than expected is determined by the frequency of the above cases. Workaround: None ide[...]

Errata Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 27 will be left set in th e in-service register and mask all in terrupts at the same or lower priority. Workaround: Any vector programmed i nto an LVT entry must have an ISR associated with it, even if that vector was programmed as masked. This ISR routine must do an EOI to clear any u[...]

Errata 28 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e  The processor is in protected mode with paging enabled and the page global enable flag i s set (PGE bit of CR4 register)  G bit for the page tabl e entry is set  TLB entry is present in TLB when INIT occurs Implication: Software may encounter unexpected page fault or incor[...]

Errata Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 29 Problem: Software w hich is writt en so that mult ip le agents can modify the same shared unaligned memory location at the sa me time may experience a memory ordering issue if multiple loads access this shared data shortly thereafter. Exposure to this problem requ ires the use of a [...]

Errata 30 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e Problem: CPUID leaf 0Ah reports the architectura l performance monitoring versio n that is available in EAX[7:0]. D ue to this erratum C PUID reports the support ed version as 2 instead of 1. Implication: Software will observe an incorrect version n umber in CPUID. 0Ah.EAX [7:0] in [...]

Errata Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 31 Workaround: BIOS must leave the xTPR update transactions disabled (default). Status: For the steppings affected, see th e Summary Tables of Changes. AW37. Performance Monitoring Ev ent IA32_FIXED_CTR2 May Not Function Properly when Max Ratio is a Non-Integer Core-to-Bus Ratio Proble[...]

Errata 32 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e Implication: This erratum has not been observed with commercially available software. Workaround: Although it is possible to have a single physical pa ge mapped by two different linear addresses with differe nt memory types, Intel has strongly discouraged this practice as it may lea[...]

Errata Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 33 VM-execution control field above that of the TPR shadow while either of those bits is 1, incorrect behavior may resu lt. This may lead to VM M software prematurely injecting an interrupt into a guest. Intel has not observed thi s erratum with any commercially available software. Wor[...]

Errata 34 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e should (1) save from the VMCS (using VMREAD) the val ue of RIP before any VM entry to the wait-for SIPI state; and (2) restore to the VMCS (using VMWRITE) that value before the next VM entry that resumes the guest in any state other than wait-for-SIPI. Status: For the steppings affe[...]

Errata Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 35 Problem: If instructions from at least three diffe rent ways in the same instruction cache set exist in the pipelin e combined with some rare int ernal state, self- modifying code (SMC) or cross-modifyin g code may not be detected and/or handled. Implication: An instruction that sho[...]

Errata 36 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e Problem: RSM instruction execution, under certain conditio ns triggered by a complex sequence of internal processor micro-architectural events, may lead to processor hang, or unexpected instruction execution results. Implication: In the above sequence, the processor may live lock or[...]

Errata Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 37 [r/e]BP instruct ions without h aving an invalid stack du ring interrupt h andling. However, an enabled debug breakpoint or single step trap may be taken after MOV SS/POP SS if this in struction is followed by an instruction t hat signals a floating point exception rather than a MOV[...]

Errata 38 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e Implication: IA32_MC1_STATUS MSR bit [60] may not reflect the correct state of the enable bit in the IA32_MC1_CTL MSR at the time of the last update. Workaround: None identified. Status: For the steppings affected, see th e Summary Tables of Changes. AW55. A VM Exit Due to a Fault W[...]

Errata Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 39 Status: For the steppings affected, see th e Summary Tables of Changes. AW57. IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception Problem: In IA-32e mode, it is possible to get an Ali gnment Check Exception (#AC) on the IRET instru ction even thou gh alig[...]

Errata 40 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e Implication: In the event of a therma l event while a processor is waking up from Intel Deep Power-D own State, th e processor will initiate an appropriat e throttle response. However, the associated thermal interrupt generated may be lost. Workaround: None identified. Status: For t[...]

Errata Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 41 the PECI hold-off indication by keeping the PECI bus high when the PECI host sends the first bit of the address timing negoti ation phase. If the PECI host does not choose to complete the transaction, it should consider the transaction a failure and retry 1ms afte r the processor de[...]

Errata 42 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e AW65. Global Instruction TLB Entries May Not be Invalidated on a VM Exit or VM Entry Problem: If a VMM is using global page entrie s (CR4.PGE is enabled and any present page-directories or page-table entrie s are marked global), then on a VM entry, the instruction TLB (Translati on [...]

Errata Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 43 AW68. INIT Incorrectly Resets IA32_LSTAR MSR Problem: In response to an INIT reset initiated ei ther via the INIT# pin or an IPI (Inter Processor Interrupt), the processor sh ould leave MSR values unchanged. Due to this erratum IA32_LSTAR MSR (C0000082H), which is used by the iA32e [...]

Errata 44 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e Workaround: None identified. Status: For the steppings affected, see th e Summary Tables of Changes. AW71. The XRSTOR Instruction May Fail to Cause a General-Protection Exception Problem: The XFEATURE_ENABLED_MASK register (X CR0) bits [63:9] are reserved and must be 0; consequently[...]

Errata Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 45 Implication: Execution of the stores in XSAVE, when XSAVE is used to store SSE context only, may not follow program order an d may execute before older stores. Intel has not observed th is erratum with any commercially available software. Workaround: None identified. Status: For the[...]

Errata 46 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e AW76. A Page Fault May Not be Generated When the PS bit is set to “1” in a PML4E or PDPTE Problem: On processors supporting Intel® 64 archit ecture, the PS bit (Page Size, bit 7) is reserved in PML4Es an d PDPTEs. If the translation of the linear address of a memory access enco[...]

Specification Changes Intel ® Core ™ 2 Duo Processor Specifica tion Upda te 47 Specification Changes The Spe cification Cha nges liste d in this s ection ap ply to the fo llowing docu ments:  Intel ® Core ™ 2 Duo Processor E8000 and E7000 Series Datasheet  Intel ® 64 and IA-32 Architectures Software Developer’s Manual volumes 1,2A, 2[...]

Specification Clarifications 48 Intel ® Core ™ 2 Duo Processor Specifica tion Updat e Specification Clarifications The Spe cification Cla rifications listed in t his sectio n apply to t he following d ocument s:  Intel ® Core ™ 2 Duo Processor E8000 and E7000 Series Datasheet  Intel ® 64 and IA-32 Architectures Software Developer’s M[...]