Intel NetBurst manuale d’uso

A Detailed Look Inside the Intel ® NetBurst™ Micro-Architecture of the Intel Pentium ® 4 Processor November, 2000[...]

A Detailed Look Inside the Intel ® NetBurst ™ Micro-Architecture of the Intel Pentium ® 4 Processor P age 2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms a[...]

A Detailed Look Inside the Intel ® NetBurst ™ Micro-Architecture of the Intel Pentium ® 4 Processor P age 3 Revision History Revision Date Revision Major Changes 11/2000 1.0 Release[...]

A Detailed Look Inside the Intel ® NetBurst ™ Micro-Architecture of the Intel Pentium ® 4 Processor P age 4 Table of Contents ABOUT THIS DOCUMENT ................................................................................................................. 5 INTRODUCTION .......................................................................[...]

A Detailed Look Inside the Intel ® NetBurst ™ Micro-Architecture of the Intel Pentium ® 4 Processor P age 5 About this Document The Intel ® NetBurst ™ micro-architecture is the foundation for the Intel ® Pentium ® 4 processor. It includes several important new features and innovations that will allow the Intel Pentium 4 processor and futur[...]

A Detailed Look Inside the Intel ® NetBurst ™ Micro-Architecture of the Intel Pentium ® 4 Processor P age 6 Introduction The Intel ® Pentium ® 4 processor, utilizing the Intel ® NetBurst TM micro-architecture, is a complete processor re- design that delivers new technologies and capabilities while advancing many of the innovative features, s[...]

A Detailed Look Inside the Intel ® NetBurst ™ Micro-Architecture of the Intel Pentium ® 4 Processor P age 7 computations to operate on packed double-precision floating-point data elements and 128-bit packed integers. There are 144 instructions in the SSE2 that can operate on two packed double-precision floating-point data elements, or on 16 pac[...]

A Detailed Look Inside the Intel ® NetBurst ™ Micro-Architecture of the Intel Pentium ® 4 Processor P age 8 The SSE instructions are useful for 3D geometry, 3D rendering, speech recognition, video encoding and decoding. For more information on the Streaming SIMD Extensions, refer to the IA-32 Intel ® Architecture Software Developer’s Manual [...]

A Detailed Look Inside the Intel ® NetBurst ™ Micro-Architecture of the Intel Pentium ® 4 Processor P age 9 Intel ® NetBurst™ Micro-architecture The Pentium ® 4 processor is the first hardware implementation of a new micro-architecture, the Intel NetBurst micro-architecture. To help reader understand this new micro-architecture, this sectio[...]

A Detailed Look Inside the Intel ® NetBurst ™ Micro-Architecture of the Intel Pentium ® 4 Processor P age 10 Overview of the Intel ® NetBurst TM Micro-architecture Pipeline The pipeline of the Intel NetBurst micro-architecture contain three sections: § the in-order issue front end § the out-of-order superscalar execution core § the in-order[...]

A Detailed Look Inside the Intel ® NetBurst ™ Micro-Architecture of the Intel Pentium ® 4 Processor P age 11 µops called traces, which are stored in the execution trace cache. The execution trace cache stores these µops in the path of program execution flow, where the results of branches in the code are integrated into the same cache line. Th[...]

A Detailed Look Inside the Intel ® NetBurst ™ Micro-Architecture of the Intel Pentium ® 4 Processor P age 12 Prefetching The Intel NetBurst micro-architecture supports three prefetching mechanisms: § the first is for instructions only § the second is for data only § the third is for code or data. The first mechanism is hardware instruction f[...]

A Detailed Look Inside the Intel ® NetBurst ™ Micro-Architecture of the Intel Pentium ® 4 Processor P age 13 The Static Predictor . Once the branch instruction is decoded, the direction of the branch (forward or backward) is known. If there was no valid entry in the BTB for the branch, the static predictor makes a prediction based on the direct[...]

A Detailed Look Inside the Intel ® NetBurst ™ Micro-Architecture of the Intel Pentium ® 4 Processor P age 14 § selecting IA-32 instructions that can be decoded into less than 4 µ ops and/or have short latencies § ordering IA-32 instructions to preserve available parallelism by minimizing long dependence chains and covering long instruction l[...]

A Detailed Look Inside the Intel ® NetBurst ™ Micro-Architecture of the Intel Pentium ® 4 Processor P age 15 Port 3 . Port 3 supports the dispatch of one store address operation per cycle. Thus the total issue bandwidth can range from zero to six µops per cycle. Each pipeline contains several execution units. The µops are dispatched to the pi[...]

A Detailed Look Inside the Intel ® NetBurst ™ Micro-Architecture of the Intel Pentium ® 4 Processor P age 16 b) avoiding the need to access off-chip caches, which can increase the realized bandwidth compared to a normal load-miss, which returns data to all cache levels. The situations that are less likely to benefit from software-controlled dat[...]

A Detailed Look Inside the Intel ® NetBurst ™ Micro-Architecture of the Intel Pentium ® 4 Processor P age 17 branches are resolved. However, speculative loads cannot cause page faults. Reordering loads with respect to each other can prevent a load miss from stalling later loads. Reordering loads with respect to other loads and stores to differe[...]