Renesas SH7709S manuale d’uso

2003.9.18 32 SH7709S Group Hardware Manual Renesas 32-Bit RISC Micr ocomputer SuperH  RISC engi ne Family /SH7700 Serie s Rev.5.00 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.[...]

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Renesas 32-B it RISC M icroc om puter SuperH  RISC engine Family/SH7700 Se ries SH7709S Group Hardware Manual REJ09B0081-0500O[...]

Rev. 5.00, 09/0 3, page iv of x liv Cautions Keep safe ty first i n y our circuit des igns! 1. Rene sas T echno log y Corp . p uts t he maxi mum e ffo rt in to mak ing s emic onduc tor product s better and more reliable, but there is always the po ssibility that tr ouble may occur with them. Trouble wi th s emiconductors m ay lead to personal inju [...]

Rev. 5.00, 09/0 3, page v of xliv General Precautions on Handling o f Product 1. Treatm ent of NC Pins Note: Do not connect an ything to the NC pins. The NC (not con nected) pins are either not con nected to any of the internal circuitry or are used as test pins or to redu ce noise. If so mething is connected to the NC pins, the operatio n of the L[...]

Rev. 5.00, 09/0 3, page v i of x liv Configuration of This Manual This manual comprises the f ollo wing items: 1. Gen eral Precaution s on Han dling of Product 2. C onf i gurat ion of T his Manu al 3. Preface 4. Cont ents 5. Overvi ew 6. Description of Functional Mo dules • CPU an d System -Contr ol Module s • On-Ch ip Peripheral Modules The co[...]

Rev. 5.00, 09/0 3, page v ii of x liv Preface This LSI is a microprocessor wi th the 32- bit SH-3 CPU as its core and periphera l functions necessary for conf iguring a u ser system. This LSI is built i n with a variety of peripheral functions such as cache memory, memory management unit (MMU), interru pt controller, timer, th ree serial communicat[...]

Rev. 5.00, 09/0 3, page v iii of xliv • User manuals for develo p ment tools Name of Document Document No. C/C++ Compiler, As sem bler, O pti miz ing Lin kag e Editor User’s M anual ADE-702-246 Simulator/Debug ger User’s Manual ADE-702-186 Embedded Workshop User’s Manual ADE-702-201[...]

Rev. 5.0, 0 9/03, pag e ix of x liv List of Item s Revised or Added for This Version Section Page Description 1.2 Bl ock Diag r am Figure 1.1 Block Diagram 6 ASERAM deleted from figure BRIDGE External bus interface UDI INTC CPG/WDT I bus 2 ASERAM deleted from legend 2.5.1 Processor St ates 53 Descripti on amended In the pow er-on reset state, t he [...]

Rev. 5.0, 0 9/03, pag e x of x liv Section Page Description 5.4.3 Examples of Usage 115, 116 (1) Invalidati ng a Spe cific Entry Descripti on amended A s pecific ca che entry can be inva lidate d by accessi ng the allocated mem ory cac he an d writing a 0 to the ent ry’s U and V bit s . Th e A bit is cleared to 0, and an address is specified for [...]

Rev. 5.0, 0 9/03, pag e xi of x liv Section Page Description 8.3.3 Precaution s when Using t he Sleep Mode 187 Newley added 8.5.1 Transit ion to Module Standby Function 191 Note * 3 added to bit table Note: 3. Before putting t he RTC into module sta ndby status, first access on e or more of the RTC, SCI, and TMU registers. T he RTC may then b e put[...]

Rev. 5.0, 0 9/03, pag e xii of x liv Section Page Description 10.2.13 MCS0 Control Register ( MCSCR0) 258 Descripti on added Bit 6—CS2/CS0 S elect (CS2/0) Only 0 sho uld be used for the C S2/0 bit i n MCSCR0. Either 0 or 1 may be u sed for MC SCR1 to MC SCR7. 10.3.4 Synch r onous DRAM Interface 290 Bank Active d escription add ed … .In bank act[...]

Rev. 5.0, 0 9/03, pag e xiii of x liv Section Page Description 16.4 SCIF I nterr upts 550 Descripti on amended W hen the TDFE flag i n the serial s tatus register (SCSSR) is set to 1, a TX I interrupt requ est is gen erated. The D MAC can be activated a nd data transfer perfor med when this interrupt is generated. When data exceeding the trans mit [...]

Rev. 5.0, 0 9/03, pag e xiv of xliv Section Page Description 20.3 Bus Maste r Interface Figure 20.2 A/D Data Register Acce ss Operation (Read ing H'AA40) 622 Figure amend ed Bus interface TEMP [H'40] ADDRn L [H'40] ADDRn H [H'AA] n = A to D CPU receives data H'AA Upper byte read Module internal data bus Bus interface TEMP [[...]

Rev. 5.0, 0 9/03, pag e xv of xliv Section Page Description 23.3.6 Synch r onous DRAM Timing Figure 23.31 Synchronous D RAM Burst Read Bus Cycle (RAS Down, Same Row Address, CAS Laten cy = 2) 690 Tnop cycle deleted fro m figure A 25 to A16 (High) t AD t AD t AD t CASD2 t CSD3 t RWD t DQMD t BSD t RDH2 t RDS2 t RDH2 t RDS2 t BSD t RASD2 t CASD2 t DQ[...]

Rev. 5.0, 0 9/03, pag e xv i of xliv Section Page Description Function inf orma tion amended for V CC –RTC, V CC –PLL1, V CC – PLL2, and V CC Pin Pin No. (FP-208C, FP-208E) Pin No. (BP- 240A) I/O Function V CC – RTC 3 E2 Pow er supply RT C oscillator p ower supply (2.0/1.9/1.8/1.7 V) V CC – PLL1 V CC – PLL2 145 150 F16, E17 Power supply[...]

Rev. 5.00, 09/0 3, page xv ii of xliv Contents Section 1 Overview and Pin Functions .......................................................................... 1 1.1 SH7709S Feat ure s ............................................................................................................ .1 1.2 Block Diagram ....................................[...]

Rev. 5.00, 09/0 3, page xv iii of xliv 3.4 MMU Functions ............................................................................................................... .6 9 3.4 .1 M MU Ha rd ware Ma nagemen t ............................................................................. 69 3.4.2 MMU Software Manag ement ............................[...]

Rev. 5.00, 09/0 3, page xix of xliv 5.1.2 Cache Structure .................................................................................................... 103 5.1.3 Register Conf i guration ......................................................................................... 105 5.2 Register Description .....................................[...]

Rev. 5.00, 09/0 3, page xx of xliv Section 7 User Break Controller ...................................................................................... 149 7.1 Overview .................................................................................................................... ....... 149 7.1.1 Features ...................................[...]

Rev. 5.00, 09/0 3, page xx i of xliv 8.4.1 Transition to Standby Mode ................................................................................. 188 8.4.2 Canceling Standby Mode ..................................................................................... 189 8.4.3 Clock Paus e Function ...............................................[...]

Rev. 5.00, 09/0 3, page xx ii of xliv Section 10 Bus State Cont roller (BSC ) ......................................................................... 223 10.1 Overview ................................................................................................................... ........ 223 10.1.1 Features ...................................[...]

Rev. 5.00, 09/0 3, page xx iii of xliv 11.1.1 Features ................................................................................................................ 3 27 11.1.2 Block Diagram ..................................................................................................... 329 11.1.3 Pin Configu ration ........................[...]

Rev. 5.00, 09/0 3, page xx iv of xliv 12.3 TMU Operation .............................................................................................................. ... 400 12.3.1 General Operation ................................................................................................ 400 12.3.2 Input C apture Function .................[...]

Rev. 5.00, 09/0 3, page xx v of xliv 13.4.3 Precautions w hen Using RTC Module Stan dby ................................................... 426 Section 14 Serial Communication I nterface (SC I) ..................................................... 427 14.1 Overview ....................................................................................[...]

Rev. 5.00, 09/0 3, page xx vi of xliv 15.4.1 Receive Data Timing and Receive Margin in Asynchron ous Mode .................... 507 15.4.2 Retransmission (R eceive and Transmit Modes) ................................................... 509 Section 16 Serial Communication I nterface with F IFO (SCIF) ............................. 511 16.1 Overview ..[...]

Rev. 5.00, 09/0 3, page xx vii of xliv 18.3.1 Port A Cont rol Register (PACR) .......................................................................... 570 18.3.2 Port B Control Regist er (PBCR) .......................................................................... 571 18.3.3 Port C Control Re gister (PCCR) ....................................[...]

Rev. 5.00, 09/0 3, page xx viii of xliv 19.11.1 Register Des cription ............................................................................................. 605 19.11.2 Port K Data Register (PKDR) .............................................................................. 606 19.12 Port L ..................................................[...]

Rev. 5.00, 09/0 3, page xx ix of xliv Section 22 User Debugging Interface (UD I) ............................................................... 641 22.1 Overview ................................................................................................................... ........ 641 22.2 User Debugg ing Interface (UDI) .....................[...]

Re v. 5 . 0 0, 0 9 / 0 3 , p a ge xxx of xl i v A.3 T reatment of Unused Pins ................................................................................................. 724 A.4 Pin States in Access to Each Address Space ..................................................................... 725 Appendix B Memory-Mapped Control Re gisters .....[...]

Re v. 5 . 0 0, 0 9 / 0 3 , p a ge xxxi o f xl iv Figu res Figure 1.1 Block Diagram ..................................................................................................... 6 Figure 1.2 Pin As signment (FP-208C, FP-208E) .................................................................. 7 Figure 1.3 Pin Ass ignment (BP-240A ) ..........[...]

Rev. 5.00, 09/0 3, page xx xii of x liv Figure 8.3 Manual Reset STATUS Output ............................................................................ 193 Figure 8.4 Standby to Interru pt ST ATUS Output .................................................................. 194 Figure 8.5 Standby to Power-On Reset STATUS Output......................[...]

Rev. 5.00, 09/0 3, page xx xiii of x liv Figure 10.28 Synchron ous DRAM Mode Write Timing ........................................................... 303 Figure 10.29 Burst RO M Wait Access Timing ......................................................................... 305 Figure 10.30 Burst RO M Basic Access Timing ...............................[...]

Re v. 5 . 0 0, 0 9 / 0 3 , p a ge xxxiv of xl i v Figure 11.23 Tim ing Chart o f Sou rce Address Reload Function............................................... 373 Figure 11.24 Block Diag ram of CMT ....................................................................................... 376 Figure 11.25 Counter Operation ............................[...]

Re v. 5 . 0 0, 0 9 / 0 3 , p a ge xxxv o f xl i v Figure 14.17 Data Format in Syn chronous Comm unication ..................................................... 474 Figure 14.18 Sample Flowchart for SCI In itialization ............................................................... 476 Figure 14.19 Sample Flowchart for Transmitting Serial Data .....[...]

Re v. 5 . 0 0, 0 9 / 0 3 , p a ge xxxvi of xl i v Figure 19.8 Port H .............................................................................................................. ..... 601 Figure 19.9 Port J .............................................................................................................. ...... 603 Figure 19.10 Port K[...]

Re v. 5 . 0 0, 0 9 / 0 3 , p a ge xxxvi i o f xl i v Figure 23.19 Burst RO M Bus Cycle (No Wait) ........................................................................ 678 Figure 23.20 Burst RO M Bus Cycle (Two Waits) .................................................................... 679 Figure 23.21 Burst R OM Bus Cycle (Ex ternal Wait, WAITSE[...]

Re v. 5 . 0 0, 0 9 / 0 3 , p a ge xxxvi ii o f xl i v Figure 23.47 TCLK Inpu t Timing ............................................................................................. 707 Figure 23.48 TCLK Clock Input Timing ................................................................................... 707 Figure 23.49 Oscillation Settling T ime a[...]

Re v. 5 . 0 0, 0 9 / 0 3 , p a ge xxxix o f xl iv Tables Table 1.1 SH7709S Features .................................................................................................. 2 Table 1.2 Characteristics....................................................................................................... .. 5 Table 1.3 SH7709S Pin Func tion[...]

Rev. 5.00, 09/0 3, page xl of x liv Table 8.2 Pin Conf iguration.................................................................................................... 1 83 Table 8.3 Register Conf i guration............................................................................................ 183 Table 8.4 Register States in Standby Mode .......[...]

Rev. 5.00, 09/0 3, page xli of x liv Table 13.2 RT C Register s ........................................................................................................ . 410 Table 13.3 Da y-of- Week Codes (RWKC NT) .......................................................................... 413 Table 13.4 Da y-of- Week Codes (RWKA R ) ..............[...]

Rev. 5.00, 09/0 3, page xlii of x liv Table 19.1 P ort A Reg ister ...................................................................................................... . 587 Table 19.2 Po r t A Data Register (PADR) Read/Write Operations ........................................... 588 Table 19.3 P ort B Register....................................[...]

Rev. 5.00, 09/0 3, page xliii of x liv Table 23.8 P eripheral Module Sig nal Timing ........................................................................... 706 Table 23.9 UDI-Related Pin Timing......................................................................................... 709 Table 23.10 A/D Conv erter Characteristics ................[...]

Rev. 5.00, 09/0 3, page xliv of xliv[...]

Rev. 5.00, 09/0 3, page 1 of 760 Section 1 Overview and Pin Functions 1.1 SH7709S Features This LSI is a single-chip RISC microprocessor that integrates a Renesas Technology-original RISC-t yp e Super H TM architecture CPU as its core that has an on-chip multiplier, cache mem ory, and a m e mory management u nit (MMU) as well as periph eral functio[...]

Rev. 5.00, 09/0 3, page 2 of 760 Table 1.1 SH7709S Featu res Item Features CPU • Origina l Renesas T echnology SuperH archi tecture • Object cod e level w ith SH-1, SH-2, and SH-3 Series • 32-bit internal data bus • General-regi ster files  Sixteen 32-bi t general registers ( eight 32-bit shadow registers)  Eight 32-bit contro l regis[...]

Rev. 5.00, 09/0 3, page 3 of 760 Item Features Cache memor y • 16-kbyte cache, m ix ed instruction/d ata • 256 entrie s, 4-way set associat ive, 16-byt e block length • Write-bac k, write-thro ugh, LRU replaceme nt algorith m • 1-stage write-back buffer • Max imum 2 ways of the cache can be loc ke d Interrupt controller (INTC) • 23 exte[...]

Rev. 5.00, 09/0 3, page 4 of 760 Item Features Serial communi- cation interf ace 0 (SCI0/SCI) • Asynchronou s mode or cloc k sy nchr onou s mode can be s ele cted • Full-dupl ex communication • Supports smart card interface Serial communi- cation interf ace 1 (SCI1/IrDA) • 16-byte FIFO for transmi ssion/rece ption • DMA can be transferred[...]

Rev. 5.00, 09/0 3, page 5 of 760 Table 1.2 Characteristics Item Characteristi cs Power supply voltage • I/O: 3.3 ± 0.3 V Internal: 2.0 ± 0.15 V (200 M Hz model) * , 1.9± 0.15 V (167 MHz model), 1.8 (+0.25, –0.15) V (1 33 MHz model), 1.7(+0 .25, –0.15) V (100 M Hz model) Operating fre quency • Internal frequency: m aximum 2 00 MHz(200 M H[...]

Rev. 5.00, 09/0 3, page 6 of 760 1.2 Block Diagram MMU TLB SH-3 CPU UBC SCI TMU RTC IrDA SCIF ADC DAC AUD BRIDGE DMAC CMT I/O port External bus interface BSC CCN CACHE UDI INTC CPG/WDT Peripheral bus 1 Peripheral bus 2 L bus I bus 1 I bus 2 Legend: ADC: AUD: BSC: CACHE: CCN: CMT: CPG/WDT: CPU: DAC: DMAC: UDI: A/D converter Advanced user debugger Bu[...]

Rev. 5.00, 09/0 3, page 7 of 760 1.3 Pin De scription 1.3.1 Pi n Ass i gnment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 MD1 MD2 V CC -RTC XT AL2 EXT AL2 V SS -RTC NMI IRQ0/ IRL0 /PTH[0] IRQ1/ IRL1 /PTH[1] IRQ2/ IRL2 /PTH[2] IRQ3/ IRL3 /PTH[3] IR[...]

Rev. 5.00, 09/0 3, page 8 of 760 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ABC DE FG H J K LM N P RTU V W ABC DE FG H J K LM N P RTU V W Note: The pin area enclosed in broken lines is an inner view. SH7709S BP-240A (Top view) Figure 1.3 Pi n Assign m ent (BP-240A)[...]

Rev. 5.00, 09/0 3, page 9 of 760 1.3.2 Pi n Functi on Table 1.3 SH7709S Pi n Function Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 1 D2 MD1 I Clock mo de sett ing 2 C2 MD2 I Clock mo de sett ing 3 E2 Vcc-R TC * 1 — RTC pow er supply ( * 3 ) 4 D1 XTAL2 O On-chip RT C crystal oscill ator pin 5 D3 EXTAL2 I On-chip RT C crystal osc[...]

Rev. 5.00, 09/0 3, page 10 of 760 Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 27 K3 Vss — Pow er supply (0 V) — K4 Vss — Power supply (0 V) 28 K1 D19/PTA[3] I/O Data b u s / input/o utput port A 29 L3 Vcc — Pow er supply (1.9 V/1. 8 V * 3 ) — L4 Vcc — Pow er supply ( * 3 ) 30 L2 D18/PTA[2] I/O Data bus / in put/outpu[...]

Rev. 5.00, 09/0 3, page 11 of 760 Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 57 U4 VssQ — Input/output pow er supply (0 V) 58 W5 A4 O Address bus 59 U3 VccQ — Input/output pow er supply (3.3 V) 60 U5 A5 O Address bus 61 T5 A6 O Address bus 62 W6 A7 O Address bus 63 V6 A8 O Address bus 64 U6 A9 O Address bus 65 T6 A10 O Addr[...]

Rev. 5.00, 09/0 3, page 12 of 760 Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 87 W12 BS /PTK[4] O / I/O Bus cycle start s ignal / input /output port K 88 T13 RD O Read s trobe 89 U13 WE0 /DQM LL O D7–D0 sele ct signal / DQM (SDRAM) 90 V13 WE1 /DQMLU/ WE O D15–D 8 select sig nal / DQM (SDRAM) 91 W13 WE2 /DQMUL/ ICIORD / PTK[6[...]

Rev. 5.00, 09/0 3, page 13 of 760 Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 106 U18 RAS3L /PTJ[0] O / I/O Lower 32 M / 64 M bytes address (SDRAM) RAS / input/o utput port J 107 U19 PTJ[1] O / I/O Input/output p ort J * 5 108 R18 CASL /PTJ[2] O / I/O Lower 32 M / 64 Mbytes address (SDRAM) CAS / input/o utput port J 109 T19 VssQ[...]

Rev. 5.00, 09/0 3, page 14 of 760 Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 130 L17 AUDATA[3]/PTG[3] I/O / I AUD data / input port G 131 K18 AUDATA[2]/PTG[2] I/O/I AUD data / input port G 132 K17 Vss — Power supply (0 V) — K16 Vss — Power supply (0 V) 133 K19 AUDATA[1]/PTG[1] I/O / I AUD data / input port G 134 J17 Vcc ?[...]

Rev. 5.00, 09/0 3, page 15 of 760 Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description — D19 Vss — Power supply (0 V) 154 E18 Vcc — Power supply ( * 3 ) — C19 Vcc — Power supply ( * 3 ) 155 C18 XTAL O Clock osci llator pin 156 D18 EXTAL I External clock / cry st al oscill ator pin 157 B16 STATUS0/PT J [6] O / I/O Processor sta [...]

Rev. 5.00, 09/0 3, page 16 of 760 Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 176 A11 CTS2 /IRQ5/SCPT [7] I Transmit cl ear 2 / ex ternal interrupt request / SCI inp ut port 177 B11 MCS[7] /PTC[7]/PINT[7] O / I/O / I M ask RO M chip select / input/out put port C / port interrupt 178 D11 MCS[6] /PTC[6]/PINT[6] O / I/O / I M ask R[...]

Rev. 5.00, 09/0 3, page 17 of 760 Number of Pins FP-208C FP-208E BP-240A Pin Name I/O Description 198 B6 AVss — Analog power supply (0 V) 199 A6 AN[0]/PTL[0] I A/D converter input / input port L 200 D5 AN[1]/PTL[1] I A/D converter input / input p ort L 201 C5 AN[2]/PTL[2] I A/D converter input / input p ort L 202 D4 AN[3]/PTL[3] I A/D converter i[...]

Rev. 5.00, 09/0 3, page 18 of 760[...]

Rev. 5.00, 09/0 3, page 19 of 760 Section 2 CPU 2.1 Register Configuration 2.1.1 Privileged M ode and B anks Proce ssor M odes: T here are tw o processor modes: user mode and pr ivileged mode. The SH7709S norm all y operates i n user mode, and enters pri v ileged mode when an excepti on occurs or an in terrupt i s accepted. There are thr ee kinds o[...]

Rev. 5.00, 09/0 3, page 20 of 760 31 0 R0 _ BANK0 * 1 * 2 R1 _ BANK0 * 2 R2 _ BANK0 * 2 R3 _ BANK0 * 2 R4 _ BANK0 * 2 R5 _ BANK0 * 2 R6 _ BANK0 * 2 R7 _ BANK0 * 2 R8 R9 R10 R1 1 R12 R13 R14 R15 SR GBR MACH MACL PR PC User mode register configuration Notes: 1. 2. R0 functions as an index register in the indexed register-indirect addressing mode and [...]

Rev. 5.00, 09/0 3, page 21 of 760 R0_BANK1 * 1 * 2 R1_BANK1 * 2 R2_BANK1 * 2 R3_BANK1 * 2 R4_BANK1 * 2 R5_BANK1 * 2 R6_BANK1 * 2 R7_BANK1 * 2 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR PC SPC GBR MACH MACL PR VBR 31 0 a. Privileged mode register configuration (RB = 1) R0_BANK0 * 1 * 3 R1_BANK0 * 3 R2_BANK0 * 3 R3_BANK0 * 3 R4_BANK0 * 3 R5_BANK0 * 3 R6_BA[...]

Rev. 5.00, 09/0 3, page 22 of 760 Register v alues after a reset are sh own in table 2.1. Table 2.1 Initial Register Values Type Registers Initial Value * General regi sters R0 to R15 Undefined Control regi sters SR MD bit = 1, RB bit = 1, B L bit = 1, I3–I0 = 1111 (H'F), reserved bits = 0, others unde fined GBR, SSR, SPC Undefin ed VBR H&ap[...]

Rev. 5.00, 09/0 3, page 23 of 760 2.1.3 S ystem Registers System re gister s can be accesse d by the LDS and STS i nstructi ons. When an ex ception occurs, t he contents of the program counter (PC) are saved in the saved progr am counter (SPC). The SPC contents are res tored to the PC by the RT E instruction used at the end of the exceptio n handli[...]

Rev. 5.00, 09/0 3, page 24 of 760 SSR Saved Status Register (SSR) Stores current SR value at time of exception to indicate processor status in return to instruction stream from exception handler. Saved Program Counter (SPC) Stores current PC value at time of exception to indicate return address at completion of exception handling. Global Base Regis[...]

Rev. 5.00, 09/0 3, page 25 of 760 2.2 Data Formats 2.2.1 Data Form at in Regi sters Register operan ds are al ways longwords (32 bit s, fig ure 2.6). When a m emory operand is only a byt e (8 bits) or a word (16 bits), it i s sign-extende d into a longword when loaded in to a regis ter. Longword 31 0 Figure 2.6 Long word 2.2.2 Data Form at in Memor[...]

Rev. 5.00, 09/0 3, page 26 of 760 2.3 Instruction Features 2.3.1 E xecution E nvironment Data Length: T he SH7709S i n struction se t is im plemented with fixed- length 16-bit wide instructions executed in a pipelined s equence with s ingle-cycle executi on for most instructio ns. All operation s are executed in 32-bit longword un its. Memory can b[...]

Rev. 5.00, 09/0 3, page 27 of 760 T bit: The T bit in the status register (S R) is used to indicate the resu lt of compare operations, and is read as a TRUE/FALSE condition deter mining if a cond itio nal br anch is taken or not. T o improve pro cessin g speed, the T b it logic state is modified only by s p e cific operati ons. An example of h ow t[...]

Rev. 5.00, 09/0 3, page 28 of 760 2.3.2 Addressing M odes Address ing modes and effectiv e address calculati on metho ds are shown in table 2.2. Table 2.2 Addressing M odes and Eff ect ive Addresse s Addressing Mode Instruction Format Effective Address C alculation Meth od Calculati on Formula Register di rect Rn Effective address is re gister Rn. [...]

Rev. 5.00, 09/0 3, page 29 of 760 Addressing Mode Instruction Format Effective Address C alculation Meth od Calculati on Formula Register indirect w ith displa cement @(disp:4, Rn) Effective addre ss is register Rn contents w ith 4-bit displace ment disp added . After di sp is zero-ex tended, it is mu ltiplied by 1 (b yte), 2 (word), or 4 (lo ngwor[...]

Rev. 5.00, 09/0 3, page 30 of 760 Addressing Mode Instruction Format Effective Address C alculation Meth od Calculati on Formula PC-relative wit h displa cement @(disp:8, PC) Effective addre ss is regis ter PC cont ents with 8-bit disp lacement disp ad ded. Aft er disp is zero-e xtended, it is mult iplied by 2 (word), or 4 (lo ngword), accord ing t[...]

Rev. 5.00, 09/0 3, page 31 of 760 Addressing Mode Instruction Format Effective Address C alculation Meth od Calculati on Formula PC-relative Rn Effectiv e address is sum of regis ter PC and Rn content s. PC R0 + PC + R0 PC + Rn Immediat e #imm:8 8-bit immed iate data imm of TST , AND, OR , or XOR instruction is zero -extended. — #imm:8 8-bit im m[...]

Rev. 5.00, 09/0 3, page 32 of 760 2.3.3 I nstructi on Formats Table 2.3 explains the mean ing of instructio n formats and so urce and des tination operands. The meaning of t he operands depends on the operation code. The following sym bols are used. xxxx: O perat i on code mmmm: Source regi ster nnnn: Destination re gister iiii: Immediate data dddd[...]

Rev. 5.00, 09/0 3, page 33 of 760 Instruction Format Source Operand Destinatio n Operand Instruction Example nm format nnnn xxxx xxxx 15 0 mmmm mmmm: r egister direct nnnn: regi ster direct ADD Rm,Rn mmmm: r egister indirect nnnn: r egister indirect MOV.L Rm,@Rn mmmm: r egister indirect w ith post- inc rem ent (multiply- and- accumulate operation) [...]

Rev. 5.00, 09/0 3, page 34 of 760 Instruction Format Source Operand Destinatio n Operand Instruction Example nmd format nnnn xxxx dddd 15 0 mmmm mmmm: r egister direct nnnndddd: register indirect w ith displa cement MOV.L Rm,@(disp,Rn) mmmmdddd: register indir ect with dis placement nnnn: regi ster direct MOV.L @(disp,Rm),Rn d format dddd xxxx 15 0[...]

Rev. 5.00, 09/0 3, page 35 of 760 2.4 Instruction Set 2.4.1 Instruction Set Cla ssified by Function The SH7709S in struct ion set in cludes 68 basic i nstructi on types, a s listed in table 2.4. Table 2.4 Classification of Instructions Classification Ty pes Operation Code Function No. of Instructions Data transfer 5 MOV Data transfer 39 MOVA Effect[...]

Rev. 5.00, 09/0 3, page 36 of 760 Classification Ty pes Operation Code Function No. of Instructions 21 MUL Double- prec is ion mul tip lic atio n (32 × 32 bits) 33 Arithmetic operation s (cont) MULS Signed multi plication (16 × 16 b its ) MULU U nsig ned mul tip lic atio n (16 × 16 bits) NEG Negatio n NEGC Negatio n with borrow SUB Binary subtra[...]

Rev. 5.00, 09/0 3, page 37 of 760 Classification Ty pes Operation Code Function No. of Instructions Branch 9 BF Conditional bra nch, delayed con ditional branch (T = 0) 11 BT Conditional branc h, delayed conditiona l branch (T = 1) BRA Unconditional bra nch BRAF Unconditional bra nch BSR Branch to subroutine procedure BSRF Branch to subrouti ne pro[...]

Rev. 5.00, 09/0 3, page 38 of 760 Table 2.5 lists the SH7709S inst ruction code f ormats. Table 2.5 Instruction Code Fo rmat Item Format Explanation Instructi on mnemonic OP.Sz SRC,DEST OP: Operati on code Sz: Size SRC: Source DEST: Destination Rm: Source re gister Rn: Dest ination regi ster imm: Immed iate data disp: Dis placement Instructi on cod[...]

Rev. 5.00, 09/0 3, page 39 of 760 Table 2.6 lists the SH 7709S data trans fer inst ructions Table 2.6 Data Transfer Instructions Instruction Operation Code Privile ged Mode C ycles T Bit MOV #imm,Rn imm → Sign exten sion → Rn 1110nnnniiiiiiii —1 — MOV.W @(disp,PC),Rn (disp × 2 + PC) → Sign extension → Rn 1001nnnndddddddd —1 — MOV.L[...]

Rev. 5.00, 09/0 3, page 40 of 760 Instruction Operation Code Privileged Mode Cy cl es T Bit MOV.W Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0101 —1 — MOV.L Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0110 —1 — MOV.B @(R0,Rm),Rn (R0 + Rm) → Sign extension → Rn 0000nnnnmmmm1100 —1 — MOV.W @(R0,Rm),Rn (R0 + Rm) → Sign extension → Rn 00[...]

Rev. 5.00, 09/0 3, page 41 of 760 Table 2.7 lists the SH7709S arithm etic instruction s. Table 2.7 Arithmetic Instructions Instruction Operation Code Privileged Mode Cy cl es T Bit ADD Rm,Rn Rn + Rm → Rn 0011nnnnmmmm1100 —1 — ADD #imm,Rn Rn + imm → Rn 0111nnnniiiiiiii —1 — ADDC Rm,Rn Rn + Rm + T → Rn, Carry → T 0011nnnnmmmm1110 — [...]

Rev. 5.00, 09/0 3, page 42 of 760 Instructio n Operation Code Pri vileged Mode C ycles T Bit DMULS.L Rm,Rn Signed operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bits 0011nnnnmmmm1101 — 2(to 5) * — DMULU.L Rm,Rn Unsigned operat ion o f Rn × Rm → MACH, MACL 32 × 32 → 64 bits 0011nnnnmmmm0101 — 2(to 5) * — DT Rn Rn – 1 → Rn, if[...]

Rev. 5.00, 09/0 3, page 43 of 760 Instruction Operation Code Privileged Mode Cy cl es T Bit NEG Rm,Rn 0–Rm → Rn 0110nnnnmmmm1011 —1 — NEGC Rm,Rn 0–Rm–T → Rn, Borrow → T 0110nnnnmmmm1010 — 1 Borrow SUB Rm,Rn Rn–Rm → Rn 0011nnnnmmmm1000 —1 — SUBC Rm,Rn Rn–Rm–T → Rn, Borrow → T 0011nnnnmmmm1010 — 1 Borrow SUBV Rm,Rn[...]

Rev. 5.00, 09/0 3, page 44 of 760 Table 2.8 lists the SH 7709S logic operat ion in structions. Table 2.8 Logic Operation Instructions Instruction Operation Code Privile ged Mode Cy cl es T Bit AND Rm,Rn Rn & Rm → Rn 0010nnnnmmmm1001 —1 — AND #imm,R0 R0 & imm → R0 11001001iiiiiiii —1 — AND.B #imm,@(R0,GBR) (R0 + GB R) & imm ?[...]

Rev. 5.00, 09/0 3, page 45 of 760 Table 2.9 lists the S H7709S sh ift inst ructions. Table 2.9 Shift Instr uctions Instruction Operation Code Privileged Mode Cy cles T Bit ROTL Rn T ← Rn ← MSB 0100nnnn00000100 —1 M S B ROTR Rn LSB → Rn → T 0100nnnn00000101 —1 L S B ROTCL Rn T ← Rn ← T 0100nnnn00100100 —1 M S B ROTCR Rn T → Rn ?[...]

Rev. 5.00, 09/0 3, page 46 of 760 Table 2.10 lis ts th e SH7709S branch in structions . Table 2.10 Branch Instructions Instruction Operation Code Privileged Mode C ycles T Bit BF label If T = 0, disp × 2 + PC → PC; if T = 1, nop 10001011dddddddd —3 / 1 * — BF/S label Delayed branch , i f T = 0, disp × 2 + PC → PC; if T = 1, nop 10001111dd[...]

Rev. 5.00, 09/0 3, page 47 of 760 Table 2.11 lis ts t he SH7709S sy stem con trol instru ctions. Table 2.11 System Control Instructions Instruction Operation Code Privile ged Mode C ycles T Bit CLRMAC 0 → MACH, MACL 0000000000101000 —1 — CLRS 0 → S 0000000001001000 —1 — CLRT 0 → T 0000000000001000 —1 0 LDC Rm,SR Rm → SR 0100mmmm00[...]

Rev. 5.00, 09/0 3, page 48 of 760 Instructio n Operation Code Pri vileged Mode Cy cl es T Bit LDC.L @Rm+, R6_BANK (Rm) → R6_BANK, Rm + 4 → Rm 0100mmmm11100111 √ 5— LDC.L @Rm+, R7_BANK (Rm) → R7_BANK, Rm + 4 → Rm 0100mmmm11110111 √ 5— LDS Rm,MACH Rm → MAC H 0100mmmm00001010 —1 — LDS Rm,MACL Rm → MAC L 0100mmmm00011010 —1 ?[...]

Rev. 5.00, 09/0 3, page 49 of 760 Instruction Operation Code Privile ged Mode C ycles T Bit STC.L SSR,@ – Rn Rn–4 → Rn, SSR → (Rn) 0100nnnn00110011 √ 2— STC.L SPC,@ – Rn Rn–4 → Rn, SPC → (Rn) 0100nnnn01000011 √ 2— STC.L R0_BANK, @ – Rn Rn–4 → Rn, R0_BAN K → (Rn) 0100nnnn10000011 √ 2— STC.L R1_BANK, @ – Rn Rn–[...]

Rev. 5.00, 09/0 3, page 50 of 760 2.4.2 Instruction Code M ap Table 2.12 show s the in struction code map. Table 2.12 Instruction Code Map Inst ruction C ode Fx: 0 000 Fx: 0001 Fx: 0010 Fx: 0 011 to 111 1 MSB LSB MD: 0 0 MD: 01 MD: 10 MD: 11 0000 Rn Fx 0000 0000 Rn Fx 0001 0000 Rn 00MD 0010 STC SR,Rn STC GBR,Rn STC VBR,Rn STC SSR,Rn 0000 Rn 01 MD 0[...]

Rev. 5.00, 09/0 3, page 51 of 760 Inst ruction C ode Fx: 0 000 Fx: 0001 Fx: 0010 Fx: 0 011 to 111 1 MSB LSB MD: 0 0 MD: 01 MD: 10 MD: 11 0100 Rn Fx 0000 SHLL Rn DT Rn SHA L Rn 0100 Rn Fx 0001 SHLR Rn CMP/PZ R n SHAR R n 0100 Rn Fx 00 10 STS.L MACH,@-Rn STS.L MACL,@-Rn STS.L PR,@-Rn 0100 Rn 00MD 0011 STC.L SR ,@-Rn ST C.L GBR,@-R n STC.L VBR,@-Rn ST[...]

Rev. 5.00, 09/0 3, page 52 of 760 Inst ruction C ode Fx: 0 000 Fx: 0001 Fx: 0010 Fx: 0 011 to 111 1 MSB LSB MD: 0 0 MD: 01 MD: 10 MD: 11 1000 00MD Rn disp MOV.B R0,@(disp:4,Rn) MOV.W R0,@(disp:4,Rn) 1000 01MD Rm disp MOV.B @(disp:4,R m),R0 MOV.W @(disp:4,R m),R0 1000 10MD imm /disp CMP/EQ #im m:8,R0 B T label:8 BF label: 8 1000 11MD imm /disp BT/S [...]

Rev. 5.00, 09/0 3, page 53 of 760 2.5 Processor States and Processor Modes 2.5.1 Proces sor States The SH7709S has fiv e processor states: the reset state, excep ti on-han dling state, bus-release d state, program execution state, and po wer-down state. Reset State: In this state the CPU is reset. The CPU enters the power-on r eset state if the RES[...]

Rev. 5.00, 09/0 3, page 54 of 760 From any state when RESETP = 0 From any state but hardware standby mode when RESETM = 0 Note: * The hardware standby mode is entered when the CA pin goes low from any state. RESETP = 1 RESETM = 1 RESETP = 0 CA = 1, RESETP =0 Power-on reset state Manual reset state Program execution state Bus-released state Sleep mo[...]

Rev. 5.00, 09/0 3, page 55 of 760 Section 3 Memory Manag ement Uni t (MMU) 3.1 Overview 3.1.1 Features The SH7709S ha s an on -chip memory management uni t (MMU) that implem ents address translation. The SH7709S features a residen t translation loo k-aside buffer (TLB) that cach es information f or user-created address translation tables located in[...]

Rev. 5.00, 09/0 3, page 56 of 760 case, the MMU will generate a n e xception, change the p hysical memory mapping, and record the new address translation in for matio n. Although the functions of the MMU could also be implemented by software alone, the nee d for translation to be performed by software each time a pro cess accesses ph ysical memor y[...]

Rev. 5.00, 09/0 3, page 57 of 760 Process 1 Physical memory MMU (1) (2) (3) (4) Process 1 Physical memory Process 1 Virtual memory MMU Physical memory Process 1 Process 2 Process 3 Physical memory Process 1 Process 2 Process 3 Virtual memory Physical memory Figure 3.1 MMU Funct ions[...]

Rev. 5.00, 09/0 3, page 58 of 760 3.1.3 SH7709S MMU Virtual Address Space: T he SH7709S us es 32-bit v i rtual addresses to access a 4- Gbyte virtual address space that is divided into several areas. Address space mapping is shown in f igure 3.2. • Privileged Mode In privileged m od e, t here are fi ve areas, P 0 – P4 . The P0 and P3 areas are [...]

Rev. 5.00, 09/0 3, page 59 of 760 H'80000000 H'A0000000 H'C0000000 H'E0000000 H'FFFFFFFF 2-Gbyte virtual space, cacheable (write-back/write-through) 2-Gbyte virtual space, cacheable (write-back/write-through) Address error H'00000000 H'00000000 H'80000000 H'FFFFFFFF Area P0 Area P1 Area P2 Area P3 Area P[...]

Rev. 5.00, 09/0 3, page 60 of 760 If the virtual address is n ot registered in the TLB, a T LB miss exception occurs an d processing will shift to the TLB miss handler. In the TLB mis s handler, the TLB address translation table in extern al memory is searched and the correspond ing physical ad dress and the page control info r mation ar e r egi st[...]

Rev. 5.00, 09/0 3, page 61 of 760 3.1.4 Regi ster Configurati on A register that has an u ndefined initial value must be in itialized by software. Table 3.1 show s the confi gur atio n of t he M MU c ontr ol regi ster s. Table 3.1 Register Configuration Name Abbrev iation R/W Size Initial Value * 1 A ddress Page table entry re gister high PTEH R/ W[...]

Rev. 5.00, 09/0 3, page 62 of 760 5. The MMU control register (MMUCR) r esiding at addres s H'FFFFFFE0 , whi ch m akes the MMU settings des cribed in f igure 3.3. Any program that m odif i es MMUCR shoul d reside in the P1 or P2 area. The MMU registers are shown in figure 3.3. 31 7 VPN PTEH PTEL ASID 0 PPN 000 0 10 31 29 28 31 TTB TTB 0 31 Vir[...]

Rev. 5.00, 09/0 3, page 63 of 760 3.3 TLB Func tions 3.3.1 C on figuration of th e TLB The T LB caches address tran s l ation table information located in the external memory. The address translation table s tores the phy sical page number translated from the virtual page num ber and the control information for the page, which is the unit of addres[...]

Rev. 5.00, 09/0 3, page 64 of 760 31 9 VPN Virtual address (1-kbyte page) Virtual address (4-kbyte page) TLB entry Offs et VPN VPN (31–17) VPN (1 1–10) ASID V PPN D Offs et 0 10 31 1 1 0 (15) (2) (19) (8) SH (1) (1) C PR (2) SZ (1) (1) (1) 12 VPN: Virtual page number. Top 22 bits of virtual address for a 1-kbyte page, or top 20 bits of virtual [...]

Rev. 5.00, 09/0 3, page 65 of 760 3.3.2 T LB Indexi ng The TLB uses a 4-way s et associative scheme, so entries must be selected by index. VPN bits 16 to 12 and ASID bits 4 to 0 in P TEH a re us e d as the index nu mb er reg ardl ess of the p age si ze. T he index number can be generated in two different w ays depending o n t he setting of the IX b[...]

Rev. 5.00, 09/0 3, page 66 of 760 31 16 11 12 17 0 Virtual address Ways 0 − 3 VPN(31 − 17) VPN(11 − 10) ASID(7 − 0) V 0 Address array Data array PPN(28 − 10) PR(1 − 0) SZ C D SH Index 31 Figure 3.7 T LB In dexing (IX = 0) 3.3.3 T LB Add ress C omparison The results of address comparison determine whether a specific v irtual page number [...]

Rev. 5.00, 09/0 3, page 67 of 760 The sharing information (SH) determines whether the PT EH.ASID and the ASID in the T LB entry are c om par ed. ASIDs are c ompare d when the re is no sha r ing between processes (SH = 0) bu t not when there is sharing (SH = 1). When s ing l e virt u al memory is support ed (MMUCR .SV = 1) and privileged mode is eng[...]

Rev. 5.00, 09/0 3, page 68 of 760 3.3.4 Page Man agemen t Inform ation In addition to the SH and SZ bits, the page management information of TLB entries also includes D, C, and P R bits. The D bit of a TLB entr y indicates whether the page is dirty (i.e., has been written to). If the D bit is 0, an attem pt to write to the page res ults in an initi[...]

Rev. 5.00, 09/0 3, page 69 of 760 3.4 MMU Functions 3.4.1 MMU Hard w are Managem ent There are two k i nds of MMU hardware m an agement as follows: 1. The MMU decodes the virtu al address accessed b y a process and performs address translati on by controlling the T LB in accordance with the MMUCR settings. 2. In address translation, the MMU receive[...]

Rev. 5.00, 09/0 3, page 70 of 760 3.4.3 MMU In struction (LDTL B) The load TLB instruction (LDTLB) is used to r ecord TLB entries. When the I X bit in M MU CR is 0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR to the v alue specified by PTEH an d PTEL, u sing V PN bits 16–12 s pecified in PTEH as t he in[...]

Rev. 5.00, 09/0 3, page 71 of 760 VPN(31 − 17) VPN(11 − 10) ASID(7 − 0) V VPN 0 ASID VPN 0 SV 0 0 RC 0 TF IX AT PPN 0 000 V 0 PR SZ C D SH 0 Write PPN(28 − 10) PR(1 − 0) SZ C D SH Write Data array Address array Way selection Ways 0 to 3 31 9 0 MMUCR Index 31 17 12 10 8 0 PTEH register 31 28 29 10 0 PTEL register 0 31 Figure 3.9 Op eration[...]

Rev. 5.00, 09/0 3, page 72 of 760 3.4.4 Avo iding Synony m Proble ms When a 1-k byte page is recorded in a T LB entry, a syn onym problem m ay arise. If a number of virtu al addresses are mapped on to a sing le phys ical address, the same phy sical address data will be record ed in a number of cache entries, and it wi ll no t be po ssible to guar a[...]

Rev. 5.00, 09/0 3, page 73 of 760 When using a 4-kbyte page Virtual address 31 VPN 0 12 11 10 Offset Physical address 31 PPN 0 Offset Virtual address (11 − 4) Physical address (28 − 10) Cache address array When using a 1-kbyte page Virtual address 31 VPN 0 10 11 Offset Physical address 31 PPN 000 000 0 10 11 Offset Virtual address (11 − 4) Ph[...]

Rev. 5.00, 09/0 3, page 74 of 760 3.5 MMU Exceptions There are four MMU exceptions: TLB miss, TLB protection violation, TLB invalid, and initial page write. 3.5. 1 TLB M iss Exce pt io n A TLB miss results when the vi rtual address and the address arra y of the selected TLB entry are compared an d no match i s found. TLB m iss exception processing [...]

Rev. 5.00, 09/0 3, page 75 of 760 2. If using software for way selection for entry replacement, write the desired val ue to the RC field i n MM UC R. 3. Issue t he LDT LB instruction to load the contents of P TEH and PTEL into t he TLB. 4. Issue the retur n from exception handler (RTE ) instructi on to terminate the handler routine and return to th[...]

Rev. 5.00, 09/0 3, page 76 of 760 3.5.3 T LB Inval id Exception A TLB invalid exception res ults when the virtu al address is compared to a selected TLB entry address arr ay and a match is fo und but the entry is not v alid (the V bit i s 0) . TLB invalid exception processin g includes both hardware and software operatio n s. Hardware Operations: I[...]

Rev. 5.00, 09/0 3, page 77 of 760 3.5.4 I nitial Page Wri te Excepti on An initial page write e xception r esults in a write a cc ess when the vir tual add ress and the address array of the selected TLB entry are co mpared and a valid entry with t he appropriate access rights is found to match, but the D (dirt y) bit of the entry is 0 (the page has[...]

Rev. 5.00, 09/0 3, page 78 of 760 Start TLB miss exception Initial page write exception PR check PR check Yes SH = 0 and (MMUCR.SV = 0 or SR.MD = 0)? VPNs and ASIDs match? VPNs match? No Yes Yes Yes Yes User or privileged? D = 1? C = 1? V = 1? No No User mode Privileged mode No No TLB protection violation exception TLB protection violation Cache ac[...]

Rev. 5.00, 09/0 3, page 79 of 760 3.5.5 Processi ng Flow in Event of MMU Exception (Same Processing Flow for Address Error) Figure 3.12 shows the MMU exception signals in the instructio n fetch mode. ID E X M A W B ID E X M A W B ID E X M A W B NOP NOP IF ID E X M A W B : Exception source stage IF ID EX MA WB NOP MMU exception handler Handler trans[...]

Rev. 5.00, 09/0 3, page 80 of 760 Figure 3 . 13 sho ws the MMU e x cep tio n signal s in the da ta access mode . IF ID EX IF ID EX IF ID ID EX M A WB ID EX M A W B ID EX M A W B NOP NOP IF ID EX M A W B : Exception source stage : Stage cancellation for instruction that has begun execution IF ID EX MA WB NOP = Instruction fetch = Instruction decode [...]

Rev. 5.00, 09/0 3, page 81 of 760 In the addre ss field, specify VPN i n bits 16-12 as the index address that sel ects th e ent ry, W in bit s 9-8 to select the way, and H'F2 in bits 31- 24 to indicate access to the addres s array. Selecti on of the index addres s depends on the MMUCR.IX set t in g . The following 2 types of operations on the [...]

Rev. 5.00, 09/0 3, page 82 of 760 VPN 31 23 1111 0010 * * 16 (1) TLB Address Array Access Read access W 0 * VPN * 31 23 24 24 17 17 17 1111 0010 * ** * 16 Write access Read/write access W 60 * * 0 VPN 31 23 24 1111 0 0 11 000 * * 16 17 Address field W 0 * * 31 29 28 Data field 10 PPN 8 9 7 654 3 2 1 0 X V XX VPN 31 16 Data field (2) TLB Data Array [...]

Rev. 5.00, 09/0 3, page 83 of 760 3.6.3 U sage Exam ples Invalidat ing Specif ic Entries: Speci fic TLB entries can be invalidat ed by writ ing 0 to the entry’ s V bit. When the A bit is 1, the VPN and ASID sp ecified by the write data is c ompared to the VPN and ASID within the TLB entry selected b y the entry address and data is written to the [...]

Rev. 5.00, 09/0 3, page 84 of 760[...]

Rev. 5.00, 09/0 3, page 85 of 760 Section 4 Exception Handling 4.1 Overview 4.1.1 Features Exc eption han dling is sepa rat e from norm al progr am proces sin g, an d is pe rform ed by a rou tin e separate f rom the norm al program . In respons e to an exception handling req u est due to abnor mal terminat i on of t he executing ins t ruct i on , c[...]

Rev. 5.00, 09/0 3, page 86 of 760 contents of PC an d SR to return to the processor state at the point of inte rruption and the addres s where the exception occurred. A basic exception handli ng sequence consists of the foll owing operat i ons: 1. The contents of PC and SR are saved in SPC and SSR, respectively. 2. T he b lock (B L) bit in SR is se[...]

Rev. 5.00, 09/0 3, page 87 of 760 Table 4.2 Exception Event Vectors Exception Ty pe Current Instruction Exception Event Priorit y * 1 Exception Order Vector Address Vector Offset Reset Aborted Power-on reset 1 — H'A00000000 — Manual reset 1 — H'A00000000 — UDI reset 1 — H'A00000000 — Aborted and retried CPU address error [...]

Rev. 5.00, 09/0 3, page 88 of 760 4.2.3 Acceptance of E xceptions Processo r resets and interrupts are asynchronous events unrelated to the ins truction str eam. All exception ev ents are prioritized to establish an acceptance order w henever two or more exception events occur simultaneously . All general exceptio n events occur i n a relative ord [...]

Rev. 5.00, 09/0 3, page 89 of 760 IF Instruction n ID EX MA TLB miss (data access) WB IF Instruction n + 1 Instruction n + 2 ID EX MA TLB miss (instruction access) WB IF ID EX MA RIE (reserved instruction exception) WB Pipeline Sequence: TLB miss (instruction n) Re-execution of instruction n 1 2 3 TLB miss (instruction n + 1) Re-execution of instru[...]

Rev. 5.00, 09/0 3, page 90 of 760 instruction or d elay slot is accepted after executio n o f the delayed branch inst ru cti on. The del ay slot here refers either to the next instructio n after a delayed uncondit ional branc h instruction or to the next instr uction whe n a dela yed conditional br anch instr uction is true. 4.2.4 E xception C odes[...]

Rev. 5.00, 09/0 3, page 91 of 760 Exception Ty pe Exception Ev ent Exception Code General interrupt reque sts External hardw are interrupt s (cont): (cont) IRL3–IRL0 = 001 0 H'240 IRL3–IRL0 = 001 1 H'260 IRL3–IRL0 = 010 0 H'280 IRL3–IRL0 = 010 1 H'2A0 IRL3–IRL0 = 011 0 H'2C0 IRL3–IRL0 = 011 1 H'2E0 IRL3–I[...]

Rev. 5.00, 09/0 3, page 92 of 760 4.3 Register Descriptions There are four r egisters related to exception han dling. These are periphe ral module registers, and therefore resid e in area P 4. T hey can be accessed by spe c ifying the address in privileg ed mode only . 1. The exception event register ( E XPEV T) resides a t addr es s H 'FFFFFF[...]

Rev. 5.00, 09/0 3, page 93 of 760 4.4 Exception Handling Operation 4.4.1 Reset The res et seq ue nce is us ed t o po wer up o r re sta rt th e S H7709S fr om the in itialization state. The RESETP an d RESETM signals are s ampled every clock cycle, an d in the case of a po wer-on reset, all processi ng being execut ed (exc ludi ng the RTC) is suspen[...]

Rev. 5.00, 09/0 3, page 94 of 760 4.4.3 G eneral Exceptions When the SH7709S encounters any exception condition other than a reset or interrupt reques t, it executes the follo wing operations: 1. The contents of PC and SR are saved to SPC and SSR, res pectively. 2. T he BL bit in SR is set to 1, masking any subsequent exceptions (except the NMI int[...]

Rev. 5.00, 09/0 3, page 95 of 760 • UDI Reset  Condition s: UDI reset comma nd input (see sect ion 22.4.3, UDI Reset)  Operations: EXPEVT set to H'000, VBR and S R initialized, br anch t o PC = H'A 0000000. Initialization sets th e VBR register to H'0000000 . In SR, th e MD, RB and BL bits are set to 1 and the i nt err upt ma[...]

Rev. 5.00, 09/0 3, page 96 of 760 • TLB invalid exception  Conditio ns: Co mpariso n of T LB addr esses shows a ddress match but th e TLB entry v alid bit (V) is 0.  Operations : The virtu al address (32 bits) t hat caused the exception is set in T EA and the cor r esp o nding vi r tua l page num be r (22 bit s) is se t in PTEH (31–10). T[...]

Rev. 5.00, 09/0 3, page 97 of 760 • CPU address error  Condition s: a. Instru c tion fetch from odd address (4n + 1, 4n + 3) b. Word data access ed from addres ses oth er than word boundaries (4 n + 1, 4n + 3) c. Longw ord accessed f rom addresses other than longw ord boundaries (4n + 1, 4n + 2, 4n + 3) d. Virtual space accessed i n user mode [...]

Rev. 5.00, 09/0 3, page 98 of 760 • Illegal slot instr uction  Condition s: a. When un defined code in a delay slot is decoded Delay br a nc h instruct ions: J MP, JSR, B RA, BRA F, BSR, B SRF, RT S, RT E , BT /S, BF/S b. When an inst ruction t h at rewrit es PC i n a delay slot i s decoded Instruc tio ns that re write P C: JMP , J SR, BRA, B [...]

Rev. 5.00, 09/0 3, page 99 of 760 4.5.3 Interrupt s 1. NMI — Condit ions: NMI pin edge det ection — Operations: PC after the inst ruction that receives the interru pt is saved to SPC, and SR at the poin t t he interrupt is accepted is s aved to SSR. H'01C0 is set to INTEVT a nd INT EVT 2. T he B L, MD, a nd RB bits o f the SR ar e set t o [...]

Rev. 5.00, 09/0 3, page 100 of 760 5. On-Chip Peri pheral In terrupt s — Co nditi ons: The inter rupt mask bits in SR are l ower than the on-ch ip mo dule ( TMU , RTC, SCI, IrDA, SCIF, A /D, DMAC, WDT, REF) interrupt level and the BL bit in SR is 0. The interru pt is accepted at an i nstruction boundary. — Operations : The PC valu e after the i[...]

Rev. 5.00, 09/03, pa ge 101 of 760 • SPC when exception occurs: The PC saved to SPC when an exception occu rs is as shown below:  Re-executing-type exceptions: PC of the instruction that caused t he exception is set in SPC and re-execut e d after retu r n from except ion handling. If the exception occur r ed in a delay slot, ho wever , P C of [...]

Rev. 5.00, 09/0 3, page 102 of 760[...]

Rev. 5.00, 09/03, pa ge 103 of 760 Section 5 Cache 5.1 Overview 5.1.1 Features The cache specificati ons are listed in table 5.1. Table 5.1 Cache Specifications Parameter Specification Capacity 16 k bytes Structure Instruction/d a ta mixed, 4-w ay set asso ciative Locking Way 2 and way 3 are lock able Line size 16 bytes Number of entrie s 256 entri[...]

Rev. 5.00, 09/0 3, page 104 of 760 24 (1 + 1 + 22) bits 128 (32 × 4) bits 6 bits LW0 − LW3: Longword data 0 − 3 Entry 0 Entry 1 Entry 255 0 1 255 0 1 255 V U Tag address LW0 LW1 LW2 LW3 Address array (ways 0 − 3) Data array (ways 0 − 3) LRU . . . . . . . . . . . . . . . . . . Figure 5.1 Cache Structure Address Array: T he V bit indi cates [...]

Rev. 5.00, 09/03, pa ge 105 of 760 The LRU bits are initialized to 000000 by a power-on reset, but are not initialize d by a manual reset. Table 5.2 LRU and Way Replace ment (When the cache lock function is not used) LRU (5–0) Way to be Replaced 000000, 00010 0, 010100, 100000, 1 10000, 110100 3 000001, 00001 1, 001011, 100001, 1 01001, 101011 2 [...]

Rev. 5.00, 09/0 3, page 106 of 760 CE WT CF CB 0 1 2 3 4 5 6 31 …… … …… …… …  : Reserved bits. Always 0 when reading. Data written here is also always 0. CF: Cache flush bit. Writing 1 flushes all cache entries (clears the V, U, and LRU bits of all cache entries to 0). Always reads 0. Write-back to external memory is not performe[...]

Rev. 5.00, 09/03, pa ge 107 of 760 31 9 8 7 2 1 0 W2 LOAD W3 LOCK W3 LOAD W2 LOCK W2LOCK: W ay 2 lock bit. W2LOAD: W ay 2 load bit. When W2LOCK = 1 & W2LOAD = 1 & SR, CL = 1, the prefetched data will always be loaded into W ay2. In all other conditions the prefetched data will be loaded into the way pointed by LRU. W3LOCK: W ay 3 lock bit. [...]

Rev. 5.00, 09/0 3, page 108 of 760 Table 5.5 Way Repla cement w hen Instructio ns Except for PRE F Instruc tion Ended Up in a Cache Miss DSP bit W3LOAD W3LOCK W2LOAD W2LOCK Wa y to be replaced 0 **** D epends on LRU (table 5.2) 1 * 0 * 0 Depends on LRU (table 5.2) 1 * 0 * 1 Depends on LRU (table 5.6) 1 * 1 * 0 Depends on LRU (table 5.7) 1 * 1 * 1 D[...]

Rev. 5.00, 09/03, pa ge 109 of 760 5.3 Cache Operati on 5.3.1 Searching the Cache If the cache is enable d, w henever instructions or data in memory are accessed the cach e w i l l be searched to see if the desired instructio n or data is in the cache. Figure 5 .4 illustrates the method by which the cache is searched. The cache is a phy sical cache[...]

Rev. 5.00, 09/0 3, page 110 of 760 0 1 255 V U Tag address LW0 LW1 LW2 LW3 Ways 0 − 3 Ways 0 − 3 31 12 11 4 3 2 1 0 Virtual address CMP0 CMP1 CMP2 CMP3 Physical address CMP0: Comparison circuit 0 CMP1: Comparison circuit 1 CMP2: Comparison circuit 2 CMP3: Comparison circuit 3 Hit signal 1 Entry selection Longword (LW) selection MMU Figure 5.4 C[...]

Rev. 5.00, 09/03, pa ge 111 of 760 5.3.2 Read Acces s Read Hit: In a read access, instru ctions and data are transferred from the cache to the CP U. The transfer unit is 32 bits . The LRU is updated. Read M iss: An external bus cycle starts and the entry is updated. The way replaced is the one least recently us ed. Entries are u pdated in 16-byte u[...]

Rev. 5.00, 09/0 3, page 112 of 760 Longword 0 Longword 1 Longword 2 Longword 3 P A (31 − 4) PA (31 − 4): Longword 0 − 3: Physical address written to external memory The line of cache data to be written to external memory Figure 5.5 Writ e-Back Buffer Configuratio n 5.3.6 Coherency of Cache and E xternal Memory Use software to ensure co herenc[...]

Rev. 5.00, 09/03, pa ge 113 of 760 The following three operations on the address array are possible. (1) Address Array Read Reads the tag address, LRU, U bit, and V bit fro m the entry that corresp onds to the entry address and w`ay that were specified in the address field. No associative operati on will be performed, regardless of the value of the[...]

Rev. 5.00, 09/0 3, page 114 of 760 The following two operations on the data ar ray are possible. Note that these operati ons w ill not change the inf ormation in the address array. (1) Data Array Read Reads th e data at the pos ition selected by the L bits (3-2) o f the add ress field fro m the entry that corresponds to the entry address and way t [...]

Rev. 5.00, 09/03, pa ge 115 of 760 5.4.3 Examples of Us age (1) Invalidat ing a Specific Entry A specific c ache entry can be invalidate d by access ing the all ocated memor y cache a nd writing a 0 to the ent ry’s U an d V bits. T he A bit is cle a red to 0, an d a n ad d ress is specifi ed f or the entry address and the way. I f the U bit of t [...]

Rev. 5.00, 09/0 3, page 116 of 760 In the fo llo wing exa mpl e , an add ress (3 2-b it) t o be purged is s pecifi ed in R 0. MOV.L #H'00000FF0, R1 ; AND R0, R1 ; The entry address is fetched. MOV.L #H'F0000008, R2 ; OR R1, R2 ; The start is set to H'F0 and the A bit to 1. MOV.L #H'1FFFFC00, R3 ; AND R0, R3 ; The tag address is [...]

Rev. 5.00, 09/03, pa ge 117 of 760 Section 6 In terrupt Controller (INTC) 6.1 Overview The interrupt controller (INTC) asc e rtains the priori ty of interrupt sourc es and controls interrupt requests to the CPU. T he INTC registers set the o r der of priority of ea ch interrupt, al l owing t he user to proce ss interrupt req uests according to the [...]

Rev. 5.00, 09/0 3, page 118 of 760 6.1.2 Block Diagra m Figure 6.1 s hows a bl ock diag ram of t he INTC. REF IrDA DMAC ICR Input/output control Com- parator Priority identifier 3 4 6 16 Interrupt request SR IPRA–IPRE IRL3 – IRL0 NMI IRQ0–IRQ5 PINT0–PINT15 IRQOUT : Timer unit : Realtime clock unit : Serial communication interface : Serial c[...]

Rev. 5.00, 09/03, pa ge 119 of 760 6.1.3 Pi n Configur ation Table 6.1 show s the INTC pi n con figuration . Table 6.1 INTC Pi ns Name Abbrev iation I/O Description Nonmaska ble interrupt input pin NM I I Input of interrupt request s ignal, not maskable b y the interrupt mas k bits in SR. Interrupt input pin s IRQ5–IRQ0 IRL3 – IRL0 IRLS3 - IRLS[...]

Rev. 5.00, 09/0 3, page 120 of 760 6.1.4 Regi ster Configurati on The INTC h as th e 12 registers lis ted in t able 6.2. Table 6.2 INTC Registers Name Abbr. R/W Initial V alue * 1 Address A ccess Size Interrupt contro l register 0 ICR0 R/ W * 2 H'FFFFFEE0 16 Interrupt contro l register 1 ICR1 R/ W H'0000 H'04000010 (H'A400001 0)[...]

Rev. 5.00, 09/03, pa ge 121 of 760 6.2 Interrup t Sources There are five types of in terrupt s ources: NMI, IRQ, IR L,PI NT , and on -chip peri pheral mod ules. Each interrupt has a priority level (0–16), w ith 0 the lowest and 16 th e highest. Priority level 0 mask s a n interru pt. 6.2.1 NM I Interrupt The NMI inter rup t has t he hi ghest pri [...]

Rev. 5.00, 09/0 3, page 122 of 760 Inter rupt s IRQ4 –IRQ 0 c an wake the chip u p fr om the s tandby s tate w hen th e r elev ant i nter rupt level is high er than the s e tting of I3–I0 in the SR regi ster (but only w he n the RTC 32-k Hz oscillator is used). If th e IRQ edge is input immediately before the CPU enters the stan dby mode (durin[...]

Rev. 5.00, 09/03, pa ge 123 of 760 Table 6. 3 I I I IR R R RL L L L3 3 3 3 – I I I IR R R RL L L L0 0 0 0 / I I I IR R R RL L L LS S S S3 3 3 3 – I I I IR R R RL L L LS S S S0 0 0 0 Pins and Interrupt Levels I I I IR R R RL3 L3 L3 L3/ / / / I I I IR R R RL L L LS S S S3 3 3 3 I I I IR R R RL2 L2 L2 L2/ / / / I I I IR R R RL L L LS S S S2 2 2 2 [...]

Rev. 5.00, 09/0 3, page 124 of 760 6.2.4 PI NT Interru p ts PINT interrupts are input b y level from pins PINT0 – PINT15. The prio rity level can be set by interru pt priority register D (IPRD) in a range from 0 to 15, in groups of PINT0–PI NT7 and PINT8–PIN T15. The PI NT0/1 interrupt level shoul d be held until t he interrupt is accepted an[...]

Rev. 5.00, 09/03, pa ge 125 of 760 6.2.6 I nterrupt Ex ception Hand ling and Priority Tables 6.4 and 6.5 list the codes for the interrupt event registers (INT EVT and INTEVT2) , and the order of interrupt priority . Each interru pt source is assigned a u n ique code. The start address o f the interrupt service rout ine is common to each interrupt s[...]

Rev. 5.00, 09/0 3, page 126 of 760 Table 6.4 Interrupt Exception Handling Sources and Priority (IRQ Mode) Interrupt Source INTEVT Code (INTEVT2 Code) Interrupt Priority (Initial Value) IPR (Bit Numbers) Priority within IPR Setting Unit Default Priority NMI H'1C0 (H'1C0) 16 — — High UDI H'5E0 (H'5E0) 15 — — IRQ IRQ0 H&apo[...]

Rev. 5.00, 09/03, pa ge 127 of 760 Interrupt Source INTEVT Code (INTEVT2 Code) Interrupt Priority (Initial Value) IPR (Bit Numbers) Priority within IPR Setting Unit Default Priority RTC ATI H'480 (H'480) 0–15 (0) IPRA (3–0) High High PRI H'4A0 (H'4A0) CUI H'4C0 (H'4C0 ) Low SCI ERI H'4E0 (H'4E0) 0–15 ( [...]

Rev. 5.00, 09/0 3, page 128 of 760 Table 6.5 Interrupt Exception Handling Sources and Priority (IRL Mode) Interrupt Source INTEVT Code (INTEVT2 Code) Interrupt Priority (Initial Value) IPR (Bit Numbers) Priority within IPR Setting Unit Defa ult Priority NMI H'1C0 (H'1 C0 ) 1 6 — — High UDI H'5E0 (H'5 E0) 15 — — IRL IRL(3[...]

Rev. 5.00, 09/03, pa ge 129 of 760 Interrupt Source INTEVT Code (INTEVT2 Code) Interrupt Priority (Initial Value) IPR (Bit Numbers) Priority within IPR Setting Unit Defa ult Priority SCIF ERI2 H' 200–3C0 * 1 (H'900) 0–15 (0) IPRE (7–4) High High RXI2 H '200–3C0 * 1 (H '920) BRI2 H'200–3C0 * 1 (H'940) TXI2 H&a[...]

Rev. 5.00, 09/0 3, page 130 of 760 Table 6.6 Interrupt Level s and INTEV T Code s Interrupt level INTEVT Code 15 H'200 14 H'220 13 H'240 12 H'260 11 H'280 10 H'2A0 9H ' 2 C 0 8H ' 2 E 0 7 H'300 6 H'320 5 H'340 4 H'360 3 H'380 2H ' 3 A 0 1H ' 3 C 0[...]

Rev. 5.00, 09/03, pa ge 131 of 760 6.3 INTC Registers 6.3.1 Interrupt Priority Registers A to E (IPRA–IPRE) Interrupt prior ity register s A to E (IP RA to IPRE) ar e 1 6-bit readable/writable registers in which priority le vels from 0 to 15 are set for on-c hip periphera l module, IRQ, and P INT in terrupts. These registers are initialized to H&[...]

Rev. 5.00, 09/0 3, page 132 of 760 6.3.2 I nterrupt Control Register 0 (ICR0) ICR0 is a regi ster that sets t he input sig nal detection mode of external interrupt input pin NMI, and indicates the input sig nal level at the NMI pin. This register is initialized to H '0000 or H'8000 by a power-on reset o r manual reset, but is not i nitial[...]

Rev. 5.00, 09/03, pa ge 133 of 760 6.3.3 I nterrupt Control Register 1 (ICR1) ICR1 is a 16-bit re gi ster that specifie s the detection mode for extern al interrupt input pins IRQ0 to IRQ5 individually: ris ing edge, f alling edge, or low level. This register is initialized to H'4000 by a power-on reset o r manual reset, but is not i nitialize[...]

Rev. 5.00, 09/0 3, page 134 of 760 Bit 12— I I I IR R R RL L L LS S S S Enable (IRLSEN): Enables pins IRLS3 – IR LS0 . This bit is vali d only w hen the IRQLVL bit is 1. Bit 12: IRLSEN Description 0P i n s IRLS3 – IRLS0 disa bled (Initial valu e) 1P i n s IRLS3 – IRLS0 enabl ed Bits 11 and 10— IRQ5 Sense Select (IRQ 51S , IRQ50S): Select [...]

Rev. 5.00, 09/03, pa ge 135 of 760 Bits 5 and 4 —IRQ2 Sense Select (I RQ21S, I RQ20S): Select whether the interr upt signal to the IRQ2 pin is detected at the rising edge, at the fa lling edge, or at the low level. Bit 5: IRQ 21S Bit 4: IRQ20S Description 0 0 An interrupt requ est is detected at IRQ2 input fal ling edge (Initial valu e) 1 An inte[...]

Rev. 5.00, 09/0 3, page 136 of 760 6.3.4 I nterrupt Control Register 2 (ICR2) ICR2 i s a 1 6-b it re ada ble/ writa ble regi ster tha t sets t he det ectio n mo de fo r e xt erna l int errup t input pins PINT0 to PINT15. This regis ter is in itialized to H' 0000 by a p ower-o n reset or manua l reset, but is not initializ ed in st andby mode. [...]

Rev. 5.00, 09/03, pa ge 137 of 760 6.3.5 PI NT In terrupt Enabl e Register (PI NTER) PINTER is a 1 6-bit readable/ writable register tha t enables interrupt req uests input to external inte rrupt inpu t pins PINT0 t o PINT15. T his regist er is initi alized to H' 0000 by a power-on reset or manual reset, but is n ot initialized in standby mode[...]

Rev. 5.00, 09/0 3, page 138 of 760 6.3.6 I nterrupt Request Register 0 (IRR0) IRR0 is a n 8-bit r e gi ster tha t indic a t es inte rrupt r e ques ts f rom e x t e rn al input pins IRQ 0 to IRQ5 and PINT0 to PINT15. T his register is initialized to H '00 by a p ower-on reset or manual reset, but is not initialized i n standb y mode. B i t : 76[...]

Rev. 5.00, 09/03, pa ge 139 of 760 Bit 4—IRQ 4 Interrupt Reques t (IRQ4R): Indi cates whether there i s interru pt request i nput to the IRQ4 pin. When e dge detecti on mod e is set for I R Q4, an interr up t req ue st is cle ared by clearing the IRQ4R bit. Bit 4: IRQ 4R Description 0 No interrupt reque st input to IRQ4 pin (Initi al value) 1 Int[...]

Rev. 5.00, 09/0 3, page 140 of 760 6.3.7 I nterrupt Request Register 1 (IRR1) IRR1 is an 8-bit read- only register that indicates whether DMAC or IrDA interrupt requests have been generated. This register is initialized to H'00 by a p ower- on reset o r manual reset, but is not initialized in standb y mode. B i t : 76543210 TXI1R BRI1R RXI1R E[...]

Rev. 5.00, 09/03, pa ge 141 of 760 Bit 3—DEI3 In terrupt Request (DEI3R): Indicates w hether a DEI3 (DMAC) i nterrupt request has be en ge nera ted . Bit 3: DE I3R Description 0 DEI3 interrupt requ est not generated (Initial valu e) 1 DEI3 interrupt requ est generated Bit 2—DEI2 In terrupt Request (DEI2R): Indicates w hether a DEI2 (DMAC) in te[...]

Rev. 5.00, 09/0 3, page 142 of 760 Bits 7 to 5—Reserved: These bits are always read as 0. The write value shoul d always be 0. Bit 4—ADI Interru pt Reques t (ADI R): Indicates whether an ADI (A DC) interrupt reques t has been generated. B it 4: A DIR Description 0 ADI interrupt reque st not genera ted (Initial valu e) 1 ADI interrupt reque st g[...]

Rev. 5.00, 09/03, pa ge 143 of 760 6.4 INTC Operation 6.4.1 Interrupt Sequence The sequen ce of int errupt operation s is described be low. Figure 6.3 i s a f lowchart of the operations. 1. T he interrupt request source s send interrupt request signa ls to th e interrupt contro ller. 2. T he interrupt controller selects the hig hest-priorit y inter[...]

Rev. 5.00, 09/0 3, page 144 of 760 No Yes Yes Yes Yes Yes Yes Yes No No No No No Level 15 interrupt? I3 − I0: Interrupt mask bits in status register (SR) Program execution state ICR1.MAI = 1? Interrupt generated? NMI = low? SR.BL= 0 or sleep mode? Yes Yes Yes Yes Yes Yes No No No No No No No ICR1.BLMSK = 1? NMI? NMI? IRQOUT = low Set interrupt ca[...]

Rev. 5.00, 09/03, pa ge 145 of 760 6.4.2 Mult iple Interrupts When handling m ultiple inte rrupts , an inte r ru pt handle r should in clu de th e fol l ow ing procedures: 1. Branch to a specif ic interrupt handler correspondin g to a code set in INTEVT and I NT EVT2. The code in IN TEVT and IN TEVT2 can be used as a b ranch-offset f o r branching [...]

Rev. 5.00, 09/0 3, page 146 of 760 Table 6.8 Interrupt Response Time Number of States Item NM I IRQ PINT Peripheral Modules Notes 0.5 × Icyc + 1.5 × Pcyc * 5 Time for priori ty decision a nd SR mask bit com pa ris o n 0.5 × Icyc + 0.5 × Bcyc + 0.5 × Pcyc 0.5 × Icyc + 1 × Bcyc + 4.5 × Pcyc * 4 0.5 × Icyc + 3.5 × Pcyc 0.5 × Icyc + 3 × Pcy[...]

Rev. 5.00, 09/03, pa ge 147 of 760 Number of States Item NM I IRQ PINT Peripheral Modules Notes Response time Total (5.5 + X) × Icyc + 1.5 × Pcyc * 5 (5.5 + X) × Icyc + 0.5 × Bcyc + 0.5 × Pcy c (5.5 + X) × Icyc + 1 × Bcyc + 4.5 × Pcyc * 4 (5.5 + X) × Icyc + 3.5 × Pcyc * 5 (5.5 + X) × Icyc + 3 × Pcyc * 6 Min i m u m case * 2 7.5 16.5 12.[...]

Rev. 5.00, 09/0 3, page 148 of 760 Interrupt acceptance IRL 0.5 × Icyc + 0.5 × Bcyc + 2 × Pcyc Instruction (instruction replaced by interrupt exception handling) IF ID EX EX EX EX IF IF ID EX 5 × Icyc Start of interrupt handling IF: Instruction fetch: Instruction is fetched from memory in which program is stored. ID: Instruction decode: Fetched[...]

Rev. 5.00, 09/03, pa ge 149 of 760 Section 7 User Break Controller 7.1 Overview The user break control ler (UBC) pro vides fun ctions that simplify pro gram debugging. This funct ion makes it easy t o design an effective se lf-monitoring de bugger, e n abl ing the c h ip t o debug programs without using an in-circuit emulator . Break conditions tha[...]

Rev. 5.00, 09/0 3, page 150 of 760 7.1.2 Block Diagram Figure 7.1 s hows a bl ock diag ram of t he UBC. BBRA BARA BAMRA BASRA ASID comparator CPU state signals IAB LAB MDB Access comparator Address comparator Channel A ASID comparator Access comparator Address comparator Data comparator PC T race CONTROL Channel B BBRB BETR BARB BAMRB BASRB BDRB BD[...]

Rev. 5.00, 09/03, pa ge 151 of 760 7.1.3 Regi ster Configurati on Table 7.1 Register Configuration Name Abbr. R/W Initial Value * 1 A ddress Access Size Location Break address regi ster A BARA R/W H'000000 00 H'FFFFFFB0 32 U BC Break address ma sk register A BAMRA R /W H'000000 00 H'FFFFFFB4 32 UBC Break bus cycle regist er A BB[...]

Rev. 5.00, 09/0 3, page 152 of 760 7.2 Register Descriptions 7.2.1 Break Address Register A (BARA) BARA is a 32-bit read/ write register. B ARA specifies the address used as a break condition in channel A. A power-on reset initializes BARA t o H'00000000. Bit: 31 30 29 28 27 26 25 24 BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 I n i t i a [...]

Rev. 5.00, 09/03, pa ge 153 of 760 7.2.2 Break Address Ma sk Register A (BAMRA) BAMRA is a 32-bit read/w rite register. BAMRA s pecifies bits m as ked in the break address specifi ed by BARA. A po wer-on reset initializes BAMRA to H'00000000. Bit: 31 30 29 28 27 26 25 24 BAMA31 BAMA30 BAM A29 BAMA28 BAMA 27 BAMA26 BAMA25 BAM A24 I n i t i a l [...]

Rev. 5.00, 09/0 3, page 154 of 760 7.2.3 Break Bus Cycle Register A (BBRA) Break bus cy cle registe r A (BBRA ) is a 16- bit read/w rite reg ister, w hich specifi es (1) CPU cy cle or DMAC cyc l e , (2) instruc tio n fetc h or data acces s, ( 3 ) read or writ e, an d (4 ) op e rand size in the break conditions of channel A. A power-on reset in itia[...]

Rev. 5.00, 09/03, pa ge 155 of 760 Bits 3 and 2—Read/Write Select A (RWA1, RWA0): Selects the read cycle or w rite cycle as the bus cy cle of the channel A break condition. Bit 3: RWA 1 Bit 2: RWA 0 Description 0 0 Condition compari so n is not perf orme d (Initial value) 1 The break condition is the read cycle 1 0 The break condition is the writ[...]

Rev. 5.00, 09/0 3, page 156 of 760 7.2.4 Break Address Register B (BA RB) BARB is a 32-bit read /write register . BARB speci fies the address used as a break condition in channel B. A po wer-o n reset initializes BARB to H'00000000. Bit: 31 30 29 28 27 26 25 24 BAB31 BAB30 BAB29 BAB28 BAB27 BAB26 BAB25 BAB24 I n i t i a l v a l u e : 00000000 [...]

Rev. 5.00, 09/03, pa ge 157 of 760 7.2.5 Brea k Address M a sk Register B ( B AM RB) BAMRB is a 32- bit read/write register. BAMRB specifies bits masked in the break addres s specified by BARB. A power-on res et initializes BAMRB to H'00000000. Bit: 31 30 29 28 27 26 25 24 BAMB31 BAMB30 BAM B29 BAMB28 BAMB 27 BAMB26 BAMB25 BAM B24 I n i t i a [...]

Rev. 5.00, 09/0 3, page 158 of 760 7.2.6 Break Data Register B ( B DRB) BDRB is a 32- bit read/w rite regist er. A power- on reset i nitializes BDRB to H'00000000. Bit: 31 30 29 28 27 26 25 24 BDB31 BDB30 BDB29 BDB28 BDB27 BDB26 BDB25 BDB24 I n i t i a l v a l u e : 00000000 R/W: R/W R/ W R/W R/ W R/W R/ W R/W R/W Bit: 23 22 21 20 19 18 17 16 [...]

Rev. 5.00, 09/03, pa ge 159 of 760 7.2.7 Break Data Mask Register B (BD MRB) BDMRB is a 32-bit read/w rite register. BDMRB specifies bits masked in the break data specif ied by BDRB. A pow er -on res et initializes BDMRB to H'00000000. Bit: 31 30 29 28 27 26 25 24 BDMB31 BDMB 30 BDMB29 BDMB28 BDM B27 BDMB26 BDM B25 BDMB24 I n i t i a l v a l u[...]

Rev. 5.00, 09/0 3, page 160 of 760 7.2.8 Break Bus Cycle Register B (BBRB) Break bus cycle register B (BBRB) is a 16-bit read/w rite register, wh ich specifies, (1) CPU cycle or DMAC cycl e , (2) instructio n fetc h or data acces s, ( 3 ) read/wri t e , and ( 4 ) op e rand size in the break con ditions of c hannel B. A pow er-on reset initializes B[...]

Rev. 5.00, 09/03, pa ge 161 of 760 Bits 3 and 2— Read/Write Select B (RWB1, RWB0): Select the read cycle or write cycle as the bus cycle of the channel B break condition. Bit 3: RWB 1 Bit 2: RWB0 Descr iption 0 0 Condition compari so n is not perf orme d (Initial value) 1 The break condition is the read cycle 1 0 The break condition is the write [...]

Rev. 5.00, 09/0 3, page 162 of 760 7.2.9 Break Control Register (BRCR) BRCR sets the following condition s: 1. Chan nels A and B are used in two independent channels conditio n or under the sequential condition. 2. A break is set before or after instruction execution. 3. A break is set by the number of execution times. 4. Deter mine whether to incl[...]

Rev. 5.00, 09/03, pa ge 163 of 760 Bit 21—Break ASID Ma sk A (BASM A): Specifies wheth er the bits of t he channel A break ASID7-A SID0 (BASA 7 to BASA 0) set in BAS RA are mask ed or no t. Bit 21: BA SM A Description 0 All BASRA bits are i ncluded in break conditio n, ASID is checke d (Initial valu e) 1 No BASRA bits are inc luded in br eak cond[...]

Rev. 5.00, 09/0 3, page 164 of 760 Bit 13—DMAC Condition Match Flag A (SCMFDA): When the on- chip DM AC bus cy cl e conditio n in the brea k conditio ns s et for channel A is sa tisfi ed, this flag is set to 1 (not clear ed to 0). In order to clear this flag, w rite 0 into t his bit. Bit 13: SCMFDA Description 0 The DMAC cycle condit ion for chan[...]

Rev. 5.00, 09/03, pa ge 165 of 760 Bit 6—PC Break S elect B (PCBB): Selects th e break tim i ng of the instruction fetch cycle for channel B as before or after ins tructio n execution. Bit 6: PCB B Description 0 PC break of channel B is se t before instruct ion execution (Initial value) 1 PC break of channel B is se t after instru cti on executio[...]

Rev. 5.00, 09/0 3, page 166 of 760 7.2.10 Execution Times Break Register (BETR) When the exec ution-times br eak condition of channel B is enabled, this register sp ecifies the number of execution times to make the break. The m aximum number is 2 12 – 1 t imes . A powe r- on reset initializes BETR to H'0000. When a break condition is satisfi[...]

Rev. 5.00, 09/03, pa ge 167 of 760 7.2.11 Branch Source Register (BRSR) BRSR is a 32-bit read register. BR SR s tores the l ast fetched addres s before bran ch an d the pointer (3 bits) which indicates the n umber of cycles from fet ch to execution for the last executed instruction. BRSR has the flag bit that is set to 1 when branch occurs. This fl[...]

Rev. 5.00, 09/0 3, page 168 of 760 Bits 30 to 28—Instruction Decode Pointer (PID2 t o PID 0 ): PID is a 3-bi t binary pointer (0–7). These bits indicate the inst ruction buff er number wh ich stores the last executed ins truction before branch. Bits 30 to 28 : PID Description Even PID indicat es the instr uction buff er number. Odd PiD+2 indi c[...]

Rev. 5.00, 09/03, pa ge 169 of 760 Bit 31—BRDR Valid Flag (DVF): Indicates w h ether a branch destination address is stored. When a branch destinat ion address is fetched, this fla g is set to 1. This flag is s et to 0 in reading BRDR . Bit 31: DV F Description 0 The value of BRDR register is invalid 1 The value of BRDR register is valid Bits 30 [...]

Rev. 5.00, 09/0 3, page 170 of 760 7.3 Operation Descri p ti on 7.3.1 Flow of the User Break Operation The flow from setting of break conditions to user break exception proc essing is described below: 1. The break addres ses an d the correspondin g ASIDs are loaded in the break address reg isters (BARA and BARB) and break ASID r egisters (BASRA and[...]

Rev. 5.00, 09/03, pa ge 171 of 760 3. When the condition is specified to be occurred after execu t ion, the instructi o n se t with the break condition is executed and the n the break is generated prior to the execution of th e next instruction. As with pre-execution br eaks, this cannot b e used with overrun fetch instr uctions. When t hi s ki nd [...]

Rev. 5.00, 09/0 3, page 172 of 760 7.3.4 Sequential Brea k 1. By specifying SEQ in BRCR is set to 1, the seque ntia l break is issued whe n channel B break condition matches after channel A break condition matches. A user break is ignored even if channel B break condition matches before c hannel A br eak condition matches. When ch annels A and B co[...]

Rev. 5.00, 09/03, pa ge 173 of 760 7.3.6 PC Trace 1. Setting PCT E in BRCR to 1 enables PC traces. W hen branch (branch instruction, repeat, and interrupt) is generated, the a ddress fr om which the branch sourc e address can be calculated and the branch destination addres s are st ored in BRSR and BRDR, respectively. The branch address an d the po[...]

Rev. 5.00, 09/0 3, page 174 of 760 reaches the botto m of the queues. After s witchin g the P CTE b it (in BRCR) off and on, the values in the queues are inv alid. T he read pointer stay at the p ositi on before PCTE is switched, but the trace pointer restart at the bo tt om of t he queues. 7.3.7 U sage Exam ples Break Condition Specified to a CPU [...]

Rev. 5.00, 09/03, pa ge 175 of 760 2. Register specifications BARA = H'00037226, BAMRA = H'0000000 0, BBRA = H'0056, BA RB = H'0003722E , BAMR B = H'00000000, B BRB = H' 0056, BDRB = H' 00000000, BDMR B = H'00000000, BRCR = H' 00000008, BAS RA = H'80, BA SRB = H'70 Specified conditions: Chann e[...]

Rev. 5.00, 09/0 3, page 176 of 760 4. Register specifications BARA = H'00037226, BAMRA = H'0000000 0, BBRA = H'005A , BARB = H' 0003722E, BAMR B = H'00000000, B BRB = H' 0056, BDRB = H' 00000000, BDMR B = H'00000000, BRCR = H' 00000008, BAS RA = H'80, BA SRB = H'70 Specified conditions: Channel[...]

Rev. 5.00, 09/03, pa ge 177 of 760 6. Register specifications BARA = H' 00008404, BA MRA = H'00000FFF, BBRA = H'0054, BA RB = H'0000801 0, BAMR B = H'00000006, B BRB = H' 0054, BDRB = H' 00000000, BDMR B = H'00000000, BRCR = H' 00000400, BAS RA = H'80, BA SRB = H'70 Specified condition s: Chann[...]

Rev. 5.00, 09/0 3, page 178 of 760 Break Condition Specified to a DMAC Data Access Cycle 1. Register specifications : BARA = H'00314156, BAMR A = H'0000000 0, BBRA = H'0094, BAR B = H'00055555, BAMR B = H'00000000, B BRB = H' 00A9, BDR B = H'0000007 8, BDMRB = H' 0000000F, BRCR = H' 00000080, BAS RA = H&[...]

Rev. 5.00, 09/03, pa ge 179 of 760 7.3.8 Notes 1. Only CPU can read/write UBC registers. 2. UBC cannot monitor CPU and DM AC access in the sa me channel. 3. Notes in specification of sequential break are described belo w: a. A condition m atch occurs when B-channel match o ccurs in a bus c ycle after an A-channel match occurs in another b us cycle [...]

Rev. 5.00, 09/0 3, page 180 of 760[...]

Rev. 5.00, 09/03, pa ge 181 of 760 Section 8 Power-Down Modes 8.1 Overview In the pow er -down modes, all CPU and som e on-chip peripheral module funct i ons are halted. This lowers power consum ption. 8.1.1 Power -Down Modes The SH7709S h as th e followi ng power- down modes and fun ction: 1. Sleep m ode 2. Standby mode 3. Module stan db y functio[...]

Rev. 5.00, 09/0 3, page 182 of 760 Table 8.1 Power-Down Modes State Mode Tran si ti on Conditions CPG CPU CPU Reg- ister On-Chip Me mory On-Chip Peripheral Modules Pins External Me mory Ca nceling Procedure Sleep mod e E xecute SLEEP instru ction w ith STBY bi t cleare d to 0 in STBC R Runs Hal ts Held Held Run Held Refres h 1. Inter rupt 2. Reset [...]

Rev. 5.00, 09/03, pa ge 183 of 760 8.1.2 Pi n Configur ation Table 8.2 lists the pi ns used f or the power- down modes. Table 8.2 Pin Configura tion Pin Name Abbrev iation I/O Description Processing state 1 STATUS1 O Operating st ate of th e processor. Processing state 0 STATUS0 HH: Reset, HL : Sleep mod e, LH: Standby mod e, LL: Normal operation W[...]

Rev. 5.00, 09/0 3, page 184 of 760 Bit 7— St a ndby (STBY) : Sp ecifies transitio n to standb y mode. Bit 7: STBY Description 0 Executing SLEEP instr uct ion put s chip into sleep mo de (Initial value) 1 Executing SLEEP instr uct ion puts chip into standby mode Bits 6, 5, and 3—Res erved: T hese bits are always read as 0. The write value should[...]

Rev. 5.00, 09/03, pa ge 185 of 760 Bit 0—M odule Sta ndby 0 (MST P 0): Specifies halting of the cl ock supply to the serial communication interface SCI (an on -chip periphera l module). W hen the MSTP0 bit is set to 1, the supply of the clock to the SC I is halted. Bit 0: MSTP0 D escription 0 SCI operates (Initial valu e) 1 Clock su pply to SCI i[...]

Rev. 5.00, 09/0 3, page 186 of 760 Bit 4—M odule Sto p 7 (M STP7): Sp eci fies ha l ti ng of the clo ck supp ly to the D MAC ( an on- chip peripheral m odule). When the MSTP7 bit is set to 1, t he supply of the clock to the DMAC is halted. Bit 4: MSTP7 D escription 0 DMAC runs (Initial value) 1 Clock su pply to DM AC halted Bit 3—M odule Sto p [...]

Rev. 5.00, 09/03, pa ge 187 of 760 8.3 Sleep Mo de 8.3.1 Transition t o Sleep M ode Execut ing the S LEEP instruc tion when the ST BY bit in S TBCR is 0 causes a trans iti on fr om the program execution state to sleep mode. A lthough the CPU halts imm ediately after executing the SLEEP instruct ion, the conte nts of its internal regis ters remain u[...]

Rev. 5.00, 09/0 3, page 188 of 760 8.4 Standby Mode 8.4.1 Transition t o Sta ndby M ode To e nter standb y mode, set t he STB Y b it to 1 in S TBCR , then exec ute the S LEE P i nstru ct ion. The chip sw itches from the program execution state to standby mode. In s tandby m ode, pow er consumption is greatly reduced b y h alting not only the CPU, b[...]

Rev. 5.00, 09/03, pa ge 189 of 760 8.4.2 Canceling St a ndby M ode Standby mode is can celed by an interrupt (NMI, IRQ, IR L, PINT, or on-chip peripheral module) or a reset. Canceling with an I n terrupt: The on-ch ip WDT can be used f or hot starts. When the c hip detects an NMI, IR L, IRQ, PINT * 1 , or on- chip per ipheral mod ule (except interv[...]

Rev. 5.00, 09/0 3, page 190 of 760 Canceling with a Reset: Stan dby mode is canceled by a reset (pow er-on or m anual). Keep the RESET p in low until the clock os cillation se ttles . The in ter nal c lock w ill continue to be output to the C KIO and CKIO2 pin s. 8.4.3 C lock Pause Fu nction In standby mode, the clock inp ut from the EXTAL pin or C[...]

Rev. 5.00, 09/03, pa ge 191 of 760 8.5 Module St andby F unction 8.5.1 Transition to M odule St a ndby Functio n Setting the standb y control register MST P8–MSTP 0 bits to 1 halts the supply of clo cks to the correspo nding on-chip peripheral modules. This function can be used to re duce the p ower consum ption in norm al m ode and s leep m ode.[...]

Rev. 5.00, 09/0 3, page 192 of 760 8.6 Timing of STATUS P in Changes The timi ng of STATUS1 and STATUS0 pi n cha nges is s hown in f igures 8.1 to 8.8. 8.6.1 T iming for Rese ts Power-On Reset CKIO, CKIO2 * 4 RESETP STATUS Normal * 2 Normal * 2 Reset * 1 PLL settling time 0 to 5 Bcyc * 3 0 to 30 Bcyc * 3 RESETOUT Notes: 1. Reset: HH (STATUS1 high, [...]

Rev. 5.00, 09/03, pa ge 193 of 760 Manual Reset CKIO, CKIO2 * 5 RESETM STATUS Normal * 3 Normal * 3 Reset * 2 0 Bcyc or more * 4 0 to 30 Bcyc * 4 RESETOUT Notes: 1. In a manual reset, ST A TUS becomes HH (reset) and the internal reset begins after waiting for the executing bus cycle to end. 2. Reset: HH (STATUS1 high, STATUS0 high) 3. Normal: LL (S[...]

Rev. 5.00, 09/0 3, page 194 of 760 8.6.2 Timing fo r Ca nceling St andby Standby to Interrupt CKIO, CKIO2 * 3 STATUS Normal * 2 Normal * 2 WDT count Oscillation stops Standby * 1 Interrupt request WDT overflow WAKEUP Notes: 1. Standby: LH (STATUS1 low, STATUS0 high) 2. Normal: LL (STATUS1 low, STATUS0 low) 3. The CKIO2 output is available only in c[...]

Rev. 5.00, 09/03, pa ge 195 of 760 Standby to P ow er- O n Reset CKIO, CKIO2 * 7 STATUS Normal * 5 Normal * 5 Oscillation stops Standby * 4 0 to 10 Bcyc * 6 0 to 30 Bcyc * 6 Reset Reset * 3 RESETP * 1 * 2 Notes: 1. When standby mode is cleared with a power-on reset, the WDT does not count. Keep RESETP low during the PLL ’s oscillation settling ti[...]

Rev. 5.00, 09/0 3, page 196 of 760 Standby t o M a nua l Reset CKIO, CKIO2 * 6 STATUS Normal * 4 Normal * 4 Oscillation stops Standby * 3 Reset * 2 0 to 20 Bcyc * 5 Reset RESETM * 1 Notes: 1. When standby mode is cleared with a manual reset, the WDT does not count. Keep RESETM low during the PLL ’ s oscillation settling time. 2. Reset: HH (STATUS[...]

Rev. 5.00, 09/03, pa ge 197 of 760 Sleep to Po wer-On Reset CKIO, CKIO2 * 7 STATUS Normal * 5 Normal * 5 Sleep * 4 0 to 10 Bcyc * 6 0 to 30 Bcyc * 6 Reset Reset * 3 * 2 RESETP * 1 Notes: 1. When the PLL1 ’ s multiplication ratio is changed by a power-on reset, keep RESETP low during the PLL ’ s oscillation settling time. 2. Undefined 3. Reset: [...]

Rev. 5.00, 09/0 3, page 198 of 760 Sleep to M anual Reset CKIO, CKIO2 * 6 0 to 80 Bcyc * 5 0 to 30 Bcyc * 5 Reset STATUS Normal * 4 Normal * 4 Sleep * 3 Reset * 2 RESETM * 1 Notes: 1. Keep RESETM low until ST A TUS becomes reset. 2. Reset: HH (ST A TUS1 high, ST A TUS0 high) 3. Sleep: HL (ST A TUS1 high, ST A TUS0 low) 4. Normal: LL (ST A TUS1 low [...]

Rev. 5.00, 09/03, pa ge 199 of 760 8.7 Hardware St andby Mode 8.7.1 Transition to H a rdw are Standby M ode Driving the CA pin low causes a transition to hard ware standb y mode. In hard ware standby mode, all modules ex cept those operating on an RTC clock are ha lt e d, as in t h e standby mode entered on execution of a SLEEP instruction ((softwa[...]

Rev. 5.00, 09/0 3, page 200 of 760 8.7.3 Hardw are Standby M ode Timing Figures 8.10 and 8.1 1 s how e xamples of pi n timin g i n hardware standb y mode. The CA pin is sampled usin g EXTAL2 (32. 768 kHz) , and a h ar dware stand by requ est i s only rec o gn ized w hen th e pin is l o w for tw o conse c uti ve clock c y cles. The CA pin must be he[...]

Rev. 5.00, 09/03, pa ge 201 of 760 Normal * 3 STATUS CA CKIO, CKIO2 * 6 Standby * 2 Reset * 1 R ESETP Undefined 2 Rcyc or more * 5 0 − 10 Bcyc * 4 Standby WDT operation Notes: 1. Reset: HH (STATUS1 high, STATUS0 high) 2. Standby: LH (STATUS1 low, STATUS0 high) 3. Normal: LL (STATUS1 low, STATUS0 low) 4. Bcyc: Bus clock cycle 5. Rcyc: EXTAL2 (32.7[...]

Rev. 5.00, 09/0 3, page 202 of 760[...]

Rev. 5.00, 09/03, pa ge 203 of 760 Section 9 On-Chip Oscillation Circuits 9.1 Overview The on-chip oscillation circuits consist of a clock pulse generator (CP G) block an d a watchdog timer (WD T) bl ock. The WDT is a single-cha nnel timer that co unts the clock s ettling time and is used when clearing standb y mode and t empora ry stan dbys, such [...]

Rev. 5.00, 09/0 3, page 204 of 760 9.2 Overview of CPG 9.2.1 C PG Bl ock Diagram A block di ag ram of the on-chi p clock pu lse generator is shown i n fi gure 9.1. CAP1 CKIO Cycle = Bcyc CAP2 XTAL EXTAL MD2 MD1 MD0 FRQCR Internal bus Bus interface STBCR PLL circuit 1 ( × 1, 2, 3, 4, 6) Divider 1 Internal clock (I φ ) Cycle = Icyc Peripheral clock[...]

Rev. 5.00, 09/03, pa ge 205 of 760 The clock p u l se generator blocks function as follows: 1. PLL Circuit 1: PLL circuit 1 doubles, triples, quadruples, s extupl es, o r leaves uncha nge d the input cloc k freque nc y fro m the CKIO pin. T he mu ltiplic atio n rate is set by the fre quency control regis ter. When this is done, the phase of the lea[...]

Rev. 5.00, 09/0 3, page 206 of 760 9.2.2 CPG Pin Conf iguration Table 9.1 lists the CPG pi ns an d their fun ctions. Table 9.1 CPG Pins and Functio ns Pin Name S y mbol I/O Description MD0 I Set the clock operating mode MD1 I Mode control pins MD2 I XTAL O Connects a crystal oscillator Crystal I/O p ins (clock input pins) EXTAL I Connects a cry sta[...]

Rev. 5.00, 09/03, pa ge 207 of 760 9.3 Clock Operating Modes Ta b le 9 .3 sho ws the r e latio nshi p be tween the mode c ontrol p in (MD2–MD0) combinatio ns and the clock operatin g modes. Table 9.4 sh ows the us able frequency ranges in the clock operating modes. Table 9.3 Clock Operating Modes Pin Values Clock I/O Mode MD2 MD1 MD0 Source Outpu[...]

Rev. 5.00, 09/0 3, page 208 of 760 Mode 7: In this mode, the CKIO pin is an input, an external clock is i nput to this p in, and undergoes waveform shaping, and also freque ncy multiplication according to the setting, b y PLL circ uit 1 bef ore b eing supp lie d to the ch ip. In m odes 0 to 2, th e system clock is generated from the outpu t of th e[...]

Rev. 5.00, 09/03, pa ge 209 of 760 Clock Mode FRQCR PLL1 PLL2 Clock Rate * (I :B:P ) Input Frequency Range CKIO Frequency Range 1, 2 H'0100 ON ( × 1) ON ( × 4) 4:4:4 6.25 M Hz to 8.34 MHz 25 MH z to 33.3 4 MH z H'0101 ON ( × 1) ON ( × 4) 4:4:2 6.25 MHz to 16.6 7 MHz 25 MH z to 66.6 7 MH z H'0102 ON ( × 1) ON ( × 4) 4:4:1 6.25 M[...]

Rev. 5.00, 09/0 3, page 210 of 760 Cautions: 1. The frequency of th e internal clock (I φ ) beco mes: • The product of the frequency of the CKIO pin, the frequency multiplicatio n ratio of PLL circuit 1, and th e division ratio of div ider 1. • Do not se t the int ern al cl ock fre quency l ower than the CK IO pin f req uency. 2. The frequency[...]

Rev. 5.00, 09/03, pa ge 211 of 760 9.4 Register Descriptions 9.4.1 Frequency Control Register (FRQCR) The frequency control register (FRQCR) i s a 16-bit readable/w r itable register used to specify the frequency multiplicatio n ratio of PLL circuit 1 and the freq uency di vision ratio of the internal clock and the peripheral clock. Only w ord acce[...]

Rev. 5.00, 09/0 3, page 212 of 760 Bits 14, 3, an d 2—Intern al Clock Frequency Di vision R atio (IFC): These bits specify the frequency divisio n ratio of the internal clo ck with respect to the output frequency of PLL circuit 1. Bit 14: IFC2 Bit 3: IFC1 Bit 2: IFC0 Description 000 × 1 (Initial value) 001 × 1/2 100 × 1/3 010 × 1/4 Except abo[...]

Rev. 5.00, 09/03, pa ge 213 of 760 9.5 Changing the Frequency The frequen cy of th e internal clock and per ipheral clock ca n be changed either b y changing the multiplication ratio of PLL cir cuit 1 o r by changing the division ratios of dividers 1 a n d 2. All of these are co ntrolled b y software th rough the frequency control register. The met[...]

Rev. 5.00, 09/0 3, page 214 of 760 9.6 Overview of WDT 9.6.1 Block Diagra m of WDT Figure 9.2 s hows a bl ock diag ra m of t he WDT. WTCSR Standby control Bus interface WTCNT Divider Clock selector Clock Standby mode Peripheral clock Standby cancellation Reset control Clock selection WDT Overflow Internal reset request Interrupt control Interrupt r[...]

Rev. 5.00, 09/03, pa ge 215 of 760 9.7 WDT Registers 9.7.1 W atchdog Timer C ounter (WTCNT) The watchdog timer counter (WTCNT) is an 8-bit readable/w r itable counter t hat increments on t he selected clock. WT CNT differs from other registers in that it is mor e diff icult to write to. See section 9.7.3, Notes on R egister Access, f or details. Wh[...]

Rev. 5.00, 09/0 3, page 216 of 760 Bit 6—Timer Mode Select (WT/ I I I IT T T T ): Selects whether to use the WDT as a w atc hdog time r or an interval timer. Bit 6: WT/ I I I IT T T T Description 0 Used as i nterval tim er (Initi al value) 1 Used as w atchdog timer Note: If W T/ IT is modifi ed when th e W DT is r unning, the up-count may not be [...]

Rev. 5.00, 09/03, pa ge 217 of 760 Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Division Ratio Overflow Period (when P φ φ φ φ = 15 MH z) 0001 ( I n i t i a l v a l u e ) 1 7 µ s 1 1/4 68 µ s 1 0 1/16 273 µ s 1 1/32 546 µ s 1001 / 6 4 1 . 0 9 m s 1 1/256 4.36 ms 1 0 1/1024 17.48 ms 1 1/4096 69.91 ms Note: If bits CKS2 – CKS0 are mod ified wh[...]

Rev. 5.00, 09/0 3, page 218 of 760 9.8 Using the WDT 9.8.1 Canceling St a ndby The WDT can be u sed to cancel s tandby m ode with an NMI or oth er interru pt. The procedu re is desc r ibe d bel ow. ( Th e WDT does not run when a res e t is u s ed f o r canc el ing, so kee p the RESE T pin low until the cl ock stabilizes.) 1. B efor e tra nsitionin [...]

Rev. 5.00, 09/03, pa ge 219 of 760 When the f ol low ing t h ree cond ition s ar e a ll m et, FRQC R sho ul d no t b e cha n g ed w hile a DMAC transfer is in progress . • Bits IFC2 to IFC0 are chan ged. • STC2 to STC0 are not chan ged. • The clock ratio of I φ (on-chip clock ) to B φ (bus clo ck) a fte r the ch ang e is oth e r than 1 : 1.[...]

Rev. 5.00, 09/0 3, page 220 of 760 9.9 Notes on Board Design When Usin g an External Crysta l Resonator: Place the cr ystal resonator, capaci tors CL1 and CL2 cl o se t o th e EXT AL and XT AL pins. T o pr event ind uc tion f rom in terfering with corre ct oscillation, use a common grou nding point fo r the cap acitor s connecte d to th e reso nato[...]

Rev. 5.00, 09/03, pa ge 221 of 760 CAP2 V CC (PLL2) V CC (PLL1) V CC C1 = 470 pF C2 = 470 pF V SS CAP1 V SS (PLL2) V SS (PLL1) Avoid crossing signal lines Power supply Reference values C2 C1 Figure 9.5 Points for Attent ion whe n Using PLL O scillator Circuit[...]

Rev. 5.00, 09/0 3, page 222 of 760[...]

Rev. 5.00, 09/03, pa ge 223 of 760 Section 10 Bus State Controller (BSC) 10.1 Overview The bus state controller (BSC) divi des physical address sp ace an d output control signals for various t ypes of memor y and bus interface s pec ificati ons. BSC f uncti ons enable the chip to link directl y with sync hrono u s DRAM, SRAM, ROM, and othe r memo r[...]

Rev. 5.00, 09/0 3, page 224 of 760 • Short refresh cy cle control  The overflow interrupt function of the refresh coun ter enables the ref resh function immediately after a self-refres h operation using low power-consumptio n DRAM • The refresh counter can be us ed as an interv al timer  Ou tpu ts an in ter ru pt r equ est s ign al usi ng[...]

Rev. 5.00, 09/03, pa ge 225 of 760 10.1.2 Block D iagram Figure 10.1 shows a block diagram of the bus state controll er. WCR1 WCR2 BCR1 Module bus MCR BSC RFCR RTCNT Comparator Refresh controller Peripheral bus Internal bus Interrupt controller Memory controller Area controller Wait controller WAIT CS0 , CS6 to CS2 , CE2A , CE2B MCS0 to MCS7 BS RD [...]

Rev. 5.00, 09/0 3, page 226 of 760 10.1.3 Pin Configurati on Table 10.1 sh ows t he BSC pi n conf igurati on. Table 10. 1 BSC Pins Pin Name Signal I/O Description Address bus A25–A0 O Address output Data bus D15–D0 I/O Data I/O D31–D16 I/O Data I/O when u sing 32-bit bus width Bus cycle start BS O Shows start of bus cycle. During bur st trans[...]

Rev. 5.00, 09/03, pa ge 227 of 760 Pin Name Signal I/O Description Data enable 3 WE3 /DQMUU/ ICIOWR O W hen me mory other than synchronou s DRAM and PCMCIA is us ed, D31–D24 w rite strobe signal. When sy nchronou s DRAM is used, selects D 31– D24. W hen PCM CIA is used, strobe signa l indicat ing I/O write. Read RD O Strobe signal ind ica ting [...]

Rev. 5.00, 09/0 3, page 228 of 760 10.1.4 Register C onfiguration The BSC has 21 registers (t able 10.2). Sync h ronous DRAM als o has a buil t- i n synchronous DRAM mode register. These reg isters control direct conn ection interfaces to memory, w ait states, and refreshes devices. Table 10. 2 BSC Registers Name Abbr. R/W Initial Value * Address B[...]

Rev. 5.00, 09/03, pa ge 229 of 760 10.1.5 Area Overvie w Space Allocation: In the architecture of the SH7709S, both logical spaces and physical spaces have 32-bit ad dress spaces . The logical sp ace is divided into five are a s b y the value o f the upper bits of the address. The physical space is divided into eight areas. Logical space can be all[...]

Rev. 5.00, 09/0 3, page 230 of 760 Table 10.3 Physical Address Space M ap Area Connectable Memory Ph y sical Address Capacity Access Size 0 H'00000000 to H'03FFFFFF 64 Mbytes 8, 16, 32 * 2 Ordinary me mory * 1 , burst ROM H' 00000000 + H'20 000000 × n to H'03FFFFFF + H'20000000 × n Shadow n = 1–6 1 H'04000000 [...]

Rev. 5.00, 09/03, pa ge 231 of 760 Area 0: H'00000000 Area 1: H'04000000 Area 2: H'08000000 A rea 3: H'0C000000 Area 4: H'10000000 Area 5: H'14000000 The PCMCIA interface is shared by the memory and I/O card The PCMCIA interface is shared by the memory and I/O card Area 6: H'18000000 Ordinary memory/ burst ROM Int[...]

Rev. 5.00, 09/0 3, page 232 of 760 Shadow Space: Areas 0 and 2–6 are decoded by physical address es A28– A26, whic h co rre sp on d to areas 000 to 110. Address bits 31–29 are ign ored. This means that the range of area 0 addresses, for exam ple, is H'00000000 to H' 03FFFFFF, and its correspon ding shadow s pace is the address space[...]

Rev. 5.00, 09/03, pa ge 233 of 760 Table 10.6 PCMCIA Support Int erface IC Memory Card Interface I/O Card Interface Pin Signal I/O Function Signal I/O Function SH7709S Pin 1 GND — Ground GND — Ground — 2 D3 I/O Data D3 I/O Data D3 3 D4 I/O Data D4 I/O Data D4 4 D5 I/O Data D5 I/O Data D5 5 D6 I/O Data D6 I/O Data D6 6 D7 I/O Data D7 I/O Data [...]

Rev. 5.00, 09/0 3, page 234 of 760 IC Memory Card Interface I/O Card Interface Pin Signal I/O Function Signal I/O Function SH7709S Pin 31 D1 I/O Data D1 I/O Data D1 32 D2 I/O Data D2 I/O Data D2 33 W P O W rite protect IOIS16 O 16-bit I/O port IOIS16 34 GND Ground G ND Ground — 35 GND Ground G ND Ground — 36 CD1 O Card detection CD1 O Card dete[...]

Rev. 5.00, 09/03, pa ge 235 of 760 IC Memory Card Interface I/O Card Interface Pin Signal I/O Function Signal I/O Function SH7709S Pin 61 REG I Attribute memory space sele ct REG I Attribut e memory space select — 62 BVD2 O Battery voltage det ect ion SPKR O Digital voice signa l — 63 BVD1 O Battery voltage det ect ion STSCHG O Card state chang[...]

Rev. 5.00, 09/0 3, page 236 of 760 Bit 15—Pin A25 to A0 Pull-Up (PULA): Specifies w hether or n ot pins A25 to A 0 are pulled u p for 4 cy cles immediately after BACK is asse rted. Bit 15: PULA Description 0 Not pulled up (Initial value) 1 Pulled up Bit 14—Pin D31 to D0 Pull-Up (PULD): Specifies w hether or n ot pins D31 to D0 are pu lled up wh[...]

Rev. 5.00, 09/03, pa ge 237 of 760 Bits 10 and 9 —Area 0 Bur st ROM Contro l (A0BST1, A0BST0 ): Specify whether to use b urst ROM in physical space are a 0. When burst ROM is used, these bits set the n umber of burst transfers. Bit 10: A 0BST1 Bit 9: A0BST0 Description 0 0 Access area 0 a cce ss ed as ordin ary me mory (Initial valu e) 1 Access a[...]

Rev. 5.00, 09/0 3, page 238 of 760 Bit 6: A6BS T1 Bit 5: A6BST0 Description 0 0 Access area 6 accessed as ordin ary me mory (initial val ue) 1 Burst acc ess of area 6 ( 4 conse cutive a ccesses). Can be used w hen bus width is 8, 16, or 32. 1 0 Burst access of area 6 (8 consecut ive accesses). Can be used w hen bus width is 8 or 16. Should not be s[...]

Rev. 5.00, 09/03, pa ge 239 of 760 Bit 0—Area 6 Bu s Typ e (A6PCM): Designates whether to access physical space area 6 as PCMCIA space. Bit 0: A6PCM Description 0 Physical spac e area 6 ac ces s ed as ord inary m emory (Initial value) 1 Physica l space area 6 ac ces sed as PCMCIA space 10.2.2 Bus Con trol Register 2 (BCR2 ) Bus control reg ister [...]

Rev. 5.00, 09/0 3, page 240 of 760 Bit 2n + 1: A n SZ1 Bit 2n: AnSZ0 Port A / B Description 0 0 Not used Reserved (Setting pr ohibited) 1 Byte (8-bit) size 1 0 W ord (16-bit) size 1 Longword (32-bit) siz e 0 0 Used Res e rved (Setting prohibited) 1 Byte (8-bit) size 1 0 W ord (16-bit) size 1 Reserved (Settin g prohibited) 10.2.3 Wait State Con trol[...]

Rev. 5.00, 09/03, pa ge 241 of 760 Bit 15—WAIT Sampling Ti ming Select (WAIT SEL): Specifies the WAIT signal s ampling timing. Bit 15: WA ITSEL Description 0 Setting to 1 w hen using the WA IT signal * (Initi al value) 1 Sampled WAIT signal at fall of CKIO Note: * Operation is not guar anteed if WAIT is asserte d while W E ITSEL = 0. Bits 14, 3, [...]

Rev. 5.00, 09/0 3, page 242 of 760 Bits 15 t o 13—Area 6 Wait Con trol (A6W2, A 6W1, A6W0): Specify t he num ber of wait stat es inserted in ph ysical space area 6 . Also spe ci fy the number of states for burst tr ansfer. Description First Cy cle Burst C y cle (Excluding First C ycle) Bit 15: A6W 2 Bit 14: A6W 1 Bit 13: A6W 0 Inserted Wait State[...]

Rev. 5.00, 09/03, pa ge 243 of 760 Bits 9 to 7—Area 4 Wait Contro l (A4W2, A4W1, A4W0) : Specify the n umber of w ait states inserted in physical space area 4. Description Bit 9: A4W2 Bit 8: A4W1 Bit 7: A4W0 Inserted Wait State W W W WA A A AI I I IT T T T Pin 0000 I gnored 1 1 Enabled 1 0 2 Enabled 1 3 Enabled 1004 E nabled 1 6 Enabled 1 0 8 Ena[...]

Rev. 5.00, 09/0 3, page 244 of 760 Bits 4 and 3 —Area 2 Wai t Control (A 2W1, A2W 0): Specify the number of wait states inserted in physi cal space area 2. • For Ordinary Memor y Description Bit 4: A2W0 Bit 3: A2W0 Inserted Wait States W W W WA A A AI I I IT T T T Pin 0 0 0 Ignored 1 1 Enabled 1 0 2 Enabled 1 3 Enabled (Initial value) • For S[...]

Rev. 5.00, 09/03, pa ge 245 of 760 10.2.5 Ind ividual Me m ory Control Regis ter (MCR) The individual memory con trol register (MCR) is a 16-bit readable/ writable register that specifi es RAS and CAS timing for s ynchronous DRAM ( areas 2 and 3), specifies address multipl exing, and controls ref resh. This enables direct connection of synchronous [...]

Rev. 5.00, 09/0 3, page 246 of 760 Bits 13 and 12—RAS–CAS Delay (RCD1, RCD0): When syn c hronous DRAM interface is selected as con nected mem ory, these bits set the bank active read/write command delay time. Bit 13: RCD1 Bit 12: RCD0 Description 0 0 1 cycle (Initial valu e) 1 2 cycles 1 0 3 cycles 1 4 cycles Bits 11 and 10—Write-Precharge De[...]

Rev. 5.00, 09/03, pa ge 247 of 760 Bits 6 to 3—Addres s Multip l ex (AMX3, AMX2, AMX1, AMX0): Specify address multiplexi ng for s ynchr o no us DR AM. For Synchron ous DRAM Interface: Bit6: AMX 3 Bit5: AMX 2 Bit 4: AMX 1 Bit 3: AMX0 Description 1101T h e r o w address begins w ith A10 (T he A10 valu e is output at A1 when the row address is outpu[...]

Rev. 5.00, 09/0 3, page 248 of 760 Bit 1—Refresh Mod e (RMODE): Selects w hether t o perform an ordinar y refresh or a self- refr e sh whe n the RFS H b i t is 1 . When the RFSH bit is 1 and this bit is 0, an auto-refr esh i s per fo rmed on synchronous D RAM at the peri od set by ref resh- rela t ed r eg iste r s RTCN T, RTCOR, and RTCSR. When a[...]

Rev. 5.00, 09/03, pa ge 249 of 760 Bit 15—Area 6 Wait Co ntrol (A6W3): Specif ies the number of inserted w ait states for area 6 combin ed with bits A6W2–A 6W0 in WCR2. A lso specifies t he number of transfer states in burs t transfer. Clear this bit to 0 when area 6 is not set to PCMCIA. First Cy cle Burst C y cle A6W 3 A6W 2 A6 W1 A6 W0 Inser[...]

Rev. 5.00, 09/0 3, page 250 of 760 Bits 11 , 7, and 6 —Area 5 Ad d ress O O O OE E E E / W W W WE E E E Assert Delay (A5TED2, A5TED1, A5TED0 ): Specify the delay tim e from address output to OE / WE assertion for the P CMCI A interface connected to area 5. Bit 11: A5T ED 2 Bit 7: A5T ED 1 Bit 6: A5TED0 Descr iption 0000 . 5 - c y c l e d e l a y [...]

Rev. 5.00, 09/03, pa ge 251 of 760 Bits 9, 3, and 2—Area 5 O O O OE E E E / W W W WE E E E Negate Addres s Delay (A5T EH2, A5TE H1, A5TEH0): Specify the address hold dela y time from OE / WE negation for th e PCMCIA interface connected to area 5. Bit 9: A5T EH 2 Bit 3: A5T EH 1 Bit 2: A5TEH0 Descr iption 0000 . 5 - c y c l e d e l a y ( I n i t i[...]

Rev. 5.00, 09/0 3, page 252 of 760 10.2.7 Synchron ous DRAM Mode Re gister (SDMR) The s ynchrono u s DRAM mode regist e r (SDMR) is an 8-bit wri te-only registe r that is written to via th e syn chron ous DRAM address bus. It s e t s synchronou s DRAM mode for areas 2 and 3. SDMR must be set befo re acces sing the synch ronous DRAM. Wri t es to the[...]

Rev. 5.00, 09/03, pa ge 253 of 760 10.2.8 Refresh Timer Control/Status Register (RT CSR) The r efresh ti me r co ntr ol/stat us registe r (RTCSR) is a 16-bit readable/ writable register that spec i fie s the re fr e sh cyc l e, wh e ther to ge ner ate an int errup t, an d the cycl e of th a t in terru pt. It is initialized to H'0000 b y a powe[...]

Rev. 5.00, 09/0 3, page 254 of 760 Bits 5 to 3—Clock Select Bits (CKS2 to CKS0): Select the c lock inp ut t o RT CN T. The so urce clock is the external bus clock ( CKIO). The R TCNT count clock is CKIO divided by the specified ratio. RT COR must be set b efore setti n g CKS2-CKS0 . Description Bit 5: CK S2 Bit 4: CK S1 Bit 3: CKS0 Normal externa[...]

Rev. 5.00, 09/03, pa ge 255 of 760 Bit 0—Refresh Count Overflow Limit Select (LMTS): Indicates the count limit value to be compa r ed t o the n umb e r o f re fr es he s i ndic ated in the r efre sh co u nt regi ste r (RFCR ) . When the value in RFCR ov erflows the value specified by LMTS, the OVF flag is set. Bit 0: LMTS Description 0 Count limi[...]

Rev. 5.00, 09/0 3, page 256 of 760 10.2.10 Refres h Time Cons tant Register (R TCOR) The refresh time constant r egister (RTCOR) sp ecifies the upper-limit valu e of RTC NT . The va lues of R TCOR and RTCNT (lower 8 bi ts) are constan tly compared. When the value s match, the compar e matc h fla g ( CMF) in RT CS R is set and RTCN T is clea red t o[...]

Rev. 5.00, 09/03, pa ge 257 of 760 Bit: 15 14 13 12 11 10 9 8 I n i t i a l v a l u e : 00000000 R / W : —————— R / W R / W B i t : 76543210 I n i t i a l v a l u e : 00000000 R/W: R/W R/ W R/W R/ W R/W R/ W R/W R/W 10.2.12 Ca utions on Accessi ng Refresh Co ntrol Relat ed Registers RFCR, RT CSR, RT CNT , and RT COR require that a sp ec[...]

Rev. 5.00, 09/0 3, page 258 of 760 10.2.13 MCS0 Contr ol Register (MCSCR 0) The MCS0 control regi ster (MCSCR0) is a 16-bit readable/ w ritable register that specifies the MCS[0] pin output conditions. MCSCR0 is initialized to H'0000 b y a p ower-on reset, but is not initialized by a manual reset or in standby mode. As the MCS [0] pin is multi[...]

Rev. 5.00, 09/03, pa ge 259 of 760 10.2.14 MCS1 Contr ol Register (MCSCR 1) The MCS1 contro l register (MCS CR1) specifies the MCS [1] pin output conditions. The bit configuration and fun ctions are the same a s those of MCSCR0. 10.2.15 MCS2 Contr ol Register (MCSCR 2) The MCS2 contro l register (MCS CR2) specifies the MCS [2] pin output conditions[...]

Rev. 5.00, 09/0 3, page 260 of 760 10.3 BSC Operation 10.3.1 Endian/Access Size and Data Alignment The SH7709S su pport s both bi g endian, in which the 0 address is the most signif i cant byte in the byte data, and little endian, in which the 0 address is the least sig ni fica nt byte. Switchin g between the two is des ignated by an e xternal pin [...]

Rev. 5.00, 09/03, pa ge 261 of 760 Table 10.8 16-Bit Extern al Device/Big-En d ian Access an d Data Alignm ent Data Bus St robe Signals Operation D31– D24 D23– D16 D15–D8 D7–D0 W W W WE E E E3 3 3 3 , DQMUU W W W WE E E E2 2 2 2 , DQMUL W W W WE E E E1 1 1 1 , DQMLU W W W WE E E E0 0 0 0 , DQMLL Byte a ccess at 0 — — Data 7–0 —A s s[...]

Rev. 5.00, 09/0 3, page 262 of 760 Table 10.9 8-Bit Extern al Device/Bi g-Endi an Access and D ata Alignm ent Data Bus Strobe Si gnals Operation D31– D24 D23– D16 D15– D8 D7–D0 W W W WE E E E3 3 3 3 , DQMUU W W W WE E E E2 2 2 2 , DQMUL W W W WE E E E1 1 1 1 , DQMLU W W W WE E E E0 0 0 0 , DQMLL Byte a ccess at 0 — — — Data 7– 0 Ass[...]

Rev. 5.00, 09/03, pa ge 263 of 760 Table 10.10 32-Bit Extern al Device/L ittle-Endian Access and Data Alignm ent Data Bus Strobe Signals Operation D31–D24 D23–D16 D15–D8 D7–D0 W W W WE E E E3 3 3 3 , DQMUU W W W WE E E E2 2 2 2 , DQMUL W W W WE E E E1 1 1 1 , DQMLU W W W WE E E E0 0 0 0 , DQMLL Byte a ccess at 0 ——— D a t a 7–0 Asse[...]

Rev. 5.00, 09/0 3, page 264 of 760 Table 10.12 8-Bit External De vice/Littl e-Endian Access and Data A lignm e nt Data Bus Strobe Signals Operation D31– D24 D23– D16 D15–D8 D7–D0 W W W WE E E E3 3 3 3 , DQMUU W W W WE E E E2 2 2 2 , DQMUL W W W WE E E E1 1 1 1 , DQMLU W W W WE E E E0 0 0 0 , DQMLL Byte a ccess at 0 — — — Data 7–0 As[...]

Rev. 5.00, 09/03, pa ge 265 of 760 10.3.2 Description of Areas Area 0: Area 0 p hysical address b its A28–A26 are 000. Addre ss bits A31–A29 are i gnored and the address ran ge is H'00000000 + H ' 20000000 × n – H'03FFFFFF + H' 20000000 × n (n = 0–6 and n = 1–6 are the shadow spaces). Ordinar y memories suc h as SRAM[...]

Rev. 5.00, 09/0 3, page 266 of 760 Area 3: Area 3 p hysical address b its A28–A26 are 011. Addre ss bits A31–A29 are i gnored and the address ran ge is H'0C000000 + H'20000000 × n – H'0FFFFFFF + H'2000000 0 × n (n = 0–6 and n = 1–6 are the shadow spaces). Ordinary memories such as SRAM and ROM, as well as sy nchronou[...]

Rev. 5.00, 09/03, pa ge 267 of 760 When the area 5 space is accessed and ordinary memory is connect ed, the CS5 signal is asserted. The RD signal that can be used as OE and the WE0 – WE3 signals for w rite control are also asserted. When the PCMCIA interface is us ed, the CE1 A signal , CE2A si gnal, RD signal as OE signal, an d WE1 signal are as[...]

Rev. 5.00, 09/0 3, page 268 of 760 10.3.3 Basic I nterface Basic T i mi ng: The basic interface of the SH7709S us es strobe sig nal output in consideration of th e f act t hat mainl y stati c RAM w i ll b e di re ctly c o nnected. F igure 10.6 show s the basic timing of normal space acc esses. A no-wait no rmal access is c ompleted in two cycles. T[...]

Rev. 5.00, 09/03, pa ge 269 of 760 T 1 CKIO A25 to A0 CSn RD/WR RD D31 to D0 WEn D31 to D0 BS T 2 Read Write Figu re 10.6 Bas ic Timing of Bas ic In terf ace[...]

Rev. 5.00, 09/0 3, page 270 of 760 Figures 10.7, 10.8, an d 10.9 sh ow exampl es of con nection to 32, 16 , and 8-bit data -w idth static RAM, respectively. •••• •••• •••• •••• •••• A16 A0 CS OE I/O7 I/O0 WE •••• •••• •••• •••• A18 A2 CSn RD D31 D24 WE3 D23 D16 WE2 D15 D8 WE1 D[...]

Rev. 5.00, 09/03, pa ge 271 of 760 A16 A0 CS OE I/O7 I/O0 WE •••• •••• •••• •••• A17 A1 CSn RD D15 D8 WE1 D7 D0 WE0 SH7709S 128k × 8-bit SRAM •••• A16 A0 CS OE I/O7 I/O0 WE •••• •••• •••• •••• •••• •••• •••• •••• Figure 10.8 Exampl e of 16-Bit D[...]

Rev. 5.00, 09/0 3, page 272 of 760 A16 A0 CSn RD D7 D0 WE0 SH7709S 128k × 8-bit SRAM •••• A16 A0 CS OE I/O7 I/O0 WE •••• •••• •••• •••• •••• •••• •••• Figure 10.9 Exampl e of 8-Bit Data-Width Static RAM Connec tion[...]

Rev. 5.00, 09/03, pa ge 273 of 760 Wait Stat e Co ntrol: Wait state insertion on the basic interface c an be controlled by the WCR2 settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a software w ait is inserted in accordance with that specification. For details, s ee section 10.2.4, Wait State C ontrol R[...]

Rev. 5.00, 09/0 3, page 274 of 760 When so ftware wait i nsertio n is sp ec ified by WCR 2, the ext ernal wait input WA IT signa l is also sampled. WAIT pin sam pling i s sh own in figure 10.11. A 2- cycle w ait is specified as a sof t ware wait. Sampling is performed at the transition fro m the T w state to the T 2 state; therefore, if the WAIT si[...]

Rev. 5.00, 09/03, pa ge 275 of 760 T 1 CKIO A25 to A0 CSn RD/ WR RD D31 to D0 WEn D31 to D0 WAIT Tw Tw Tw T 2 Read Write BS Wait states inserted by WAIT signal Figure 10.11 Basi c Interface Wait Sta te Timing (Wai t State In sertion by W W W WA A A AI I I IT T T T Signal WAITSEL = 1 )[...]

Rev. 5.00, 09/0 3, page 276 of 760 10.3.4 Synchron ou s DRAM Interface Synchronous DRAM Direct Connection: Since synchronous DRAM can be selected by th e CS signal, phy sical space areas 2 and 3 can be connected us ing RAS and other control sig nals in common. If the me mor y ty pe bits (DRAMTP2–0) in BCR 1 are set to 010, area 2 is ord inary mem[...]

Rev. 5.00, 09/03, pa ge 277 of 760 A15 A2 CKI0 CKE CSn RAS3x CASx RD/ WR D31 D16 DQMUU DQMUL D15 D0 DQMLU DQMLL SH7709S 64M synchronous DRAM (1M × 16-bit × 4-bank ) •••• A13 A0 CLK CKE CS RAS CAS WE DQ15 DQ0 DQMU DQML •••• •••• •••• A13 A0 CLK CKE CS RAS CAS WE DQ15 DQ0 DQMU DQML •••• •••• •••[...]

Rev. 5.00, 09/0 3, page 278 of 760 SH7709S 64M synchronous DRAM (1M × 16 bit × 4 bank) A14 A13 A12 A1 CKIO CKE CSn RAS3x CASx RD/ WR D15 D0 DQMLU DQMLL A13 A12 A1 1 A0 CLK CKE CS RAS CAS WE DQ15 DQ0 DQMU DQML ••• ••• ••• ••• ••• ••• ••• ••• Figure 10.13 Exam ple of 64-Mbit S ynchron ous DRAM Connect[...]

Rev. 5.00, 09/03, pa ge 279 of 760 Table 10.13 Relationship bet ween Bus Width, AMX Bits, and Address Multiplex Output Setting External A ddress Pins Bus Widt h Memo ry Ty pe AM X 3 AM X 2 AM X 1 AM X 0 Output Tim in g A1 t o A8 A9 A1 0 A1 1 A1 2 A1 3 A1 4 A1 5 A1 6 32 bits 4M × 16bits × 4banks * 1 1101C o l u m n address A1 to A8 A9 A10 A11 L/H [...]

Rev. 5.00, 09/0 3, page 280 of 760 Setting External A ddress Pins Bus Widt h Memo ry Ty pe AM X 3 AM X 2 AM X 1 AM X 0 Output Tim in g A1 t o A8 A9 A1 0 A1 1 A1 2 A1 3 A1 4 A1 5 A1 6 2M × 16bits × 4banks * 2 0101C o l u m n address A1 to A8 A9 A10 L/H * 3 A12 A2 2 * 4 A23 * 4 A24 Row address A10 to A17 A18 A19 A2 0 A21 A22 * 4 A23 * 4 A2 4 1M × [...]

Rev. 5.00, 09/03, pa ge 281 of 760 Table 10.1 4 Exa mple of Correspo ndence between SH7709S an d Synchronous DRAM Address Pi n s (AMX [3:0] = 0100 (32-Bi t Bus Width )) SH7709S Addr ess Pin Synchronous DR AM A ddress Pin RAS Cy cle CAS Cy cle Function A15 A23 A23 A13(BA1) A14 A22 A22 A12(BA0) BANK select bank address A13 A21 A13 A11 Address A12 A20[...]

Rev. 5.00, 09/0 3, page 282 of 760 indepen dently for areas 2 and 3 b y m eans of bits A2W1 and A2W0 or A3W 1 and A3W 0 in WCR2. This num ber of cycles correspon ds to the number of sy nchronous DRAM CAS l a t e n c y cycles. CKIO A 25 to A16, A 13 A 12 A 15, A14, A 11 to A0 CS2 or CS3 RAS3x CASx RD/ WR DQMxx D31 to D0 BS Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4[...]

Rev. 5.00, 09/03, pa ge 283 of 760 Figure 10.15 s hows the burs t read timi ng when RCD is set to 1, A3W 1 and A3W0 are set to 10, and TPC is set to 1. The B S cycle, whic h i s asserte d for o ne c ycle at the s tart of a bus cycle fo r n ormal acces s space, is asserted in each of cycles Td1–Td4 in a sy n chron ous DRAM cycle. When a burst read[...]

Rev. 5.00, 09/0 3, page 284 of 760 Single Read: Figure 10.16 show s the timing when a single addre ss read is perfor med. As the b urst length is set to 1 in synchro nous DRA M burst rea d/sing le wr ite mode, only the re quired data is output. Co nseque ntly, no unneces sar y bus cycles are gener ated e ven whe n a cache-thr ough area is accessed.[...]

Rev. 5.00, 09/03, pa ge 285 of 760 Burst Write: The tim i n g chart for a burst write is shown in figure 10.17. In the SH7709S , a burst write o cc ur s o nly i n t he event of c a che wri t e-b ack o r 16- byte D MAC t ran sf er. In a burs t write operation, f ollowing the Tr cycle in which ACTV com mand outp ut is performed, a W RIT command is is[...]

Rev. 5.00, 09/0 3, page 286 of 760 CKIO CSn RD/ WR RAS3x CASx DQMxx D31 to D0 (read) BS Tr Tc1 Tc2 Tc3 Tc4 (Trwl) (Tpc) A ddress upper bits A 12, A11, A 10 or A9 A ddress lower bits Figure 10.17 Basic Ti ming for Synchr onous DRAM Burst W rite[...]

Rev. 5.00, 09/03, pa ge 287 of 760 Single Write: T he basic tim ing chart for w rite acce ss is shown in figure 10.18. In a single w rite operation, f ollowing the Tr cycle in which ACTV com mand outp ut is performed, a W RITA command that perf orms auto-precharge is issued in t he Tc1 cycle. In th e write cycle, the write data is output at the sam[...]

Rev. 5.00, 09/0 3, page 288 of 760 CKIO CSn RD/ WR RAS3x CASx DQMxx D31 to D0 BS A ddress upper bits A 12 or A10 A ddress lower bits CKE Tr Tc1 (Trwl) (Tpc) Figure 10. 18 Basic Timing fo r Synchronous DR AM Single Write[...]

Rev. 5.00, 09/03, pa ge 289 of 760 Bank Active: The sy nchronous DRAM bank function is us ed to support h igh-s peed accesses to the same row addres s. When the RASD bit in MCR is 1, read/write command accesses are perform ed using comm ands without auto-precharge (READ, WRIT). In this cas e, precharging is no t pe rf orm ed wh en th e access end s[...]

Rev. 5.00, 09/0 3, page 290 of 760 A Tnop cycle, in which no opera tion is performed, is inserted before the T c cycle in which the READ command is i ss u ed in figure 10.20, bu t when syn chron ous DRAM is read, there is a tw o- cycle latency for the DQMxx signal that perf orms the byte specification. If th e T c cycle were perform ed i m mediatel[...]

Rev. 5.00, 09/03, pa ge 291 of 760 CKIO A 25 to A16, A 13 (A25 to A 16, A11) A 12 (A10) A 15, A14, A 11 to A0 (A15 to A12, A 9 to A0) CS2 or CS3 RAS3x CASx RD/ WR DQMxx D31 to D0 BS Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 Figure 10.19 Burst Rea d Timing (No Precharge)[...]

Rev. 5.00, 09/0 3, page 292 of 760 CKIO A 25 to A16, A 13 (A25 to A 16, A11) A 12 (A10) A 15, A14, A 11 to A0 (A15 to A12, A 9 to A0) CS2 or CS3 RAS3x CASx RD/ WR DQMxx D31 to D0 BS Tnop Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 Figure 10.20 Burst Rea d Timing (Same Row Addr ess)[...]

Rev. 5.00, 09/03, pa ge 293 of 760 CKIO A 25 to A16, A 13 (A25 to A 16, A11) A 12 (A10) A 15, A14, A 11 to A0 (A15 to A12, A 9 to A0) CS2 or CS3 RAS3x CASx RD/ WR DQMxx D31 to D0 BS Tp Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 Figure 10.21 Bu rst Read T i ming (Different Row Add resses)[...]

Rev. 5.00, 09/0 3, page 294 of 760 CKIO A 25 to A16, A 13 (A25 to A 16, A11) A 12 (A10) A 15, A14, A 11 to A0 (A15 to A12, A 9 to A0) CS2 or CS3 RAS3x CASx RD/ WR DQMxx D31 to D0 BS Tr Tc1 Tc2 Tc3 Tc4 Figure 10.22 Burst Writ e Timing (No Precharge)[...]

Rev. 5.00, 09/03, pa ge 295 of 760 CKIO A 25 to A16, A 13 (A25 to A 16, A11) A 12 (A10) A 15, A14, A 11 to A0 (A15 to A12, A 9 to A0) CS2 or CS3 RAS3x CASx RD/ WR DQMxx D31 to D0 BS Tc1 Tc2 Tc3 Tc4 Figure 10.23 Burst Writ e T i ming (S ame Row Address)[...]

Rev. 5.00, 09/0 3, page 296 of 760 CKIO A 25 to A16, A 13 (A25 to A 16, A11) A 12 (A10) A 15, A14, A 11 to A0 (A15 to A12, A 9 to A0) CS2 or CS3 RAS3x CASx RD/ WR DQMxx D31 to D0 BS Tp Tr Tc1 Tc2 Tc3 Td4 Figure 10.24 Bu rst Write Timing (Different Ro w Addresses)[...]

Rev. 5.00, 09/03, pa ge 297 of 760 Refreshing: T he bus state controller is provided with a function for contro lling synchronous DRAM ref reshing. Auto-ref reshing can be perform ed by clearing the RMODE bi t to 0 and setting the RFSH bit to 1 in MCR. If synchr onous DRAM is not accessed for a long period, self-refresh mode, in which the pow er co[...]

Rev. 5.00, 09/0 3, page 298 of 760 RTCOR value RTCNT H'00000000 RTCSR.CKS(2 to 0) CMF External bus CMF flag cleared by start of refresh cycle = 000 ≠ 000 RTCNT cleared to 0 when RTCNT = RTCOR Auto-refresh cycle Time Figure 10.25 Auto-Refre sh Operation[...]

Rev. 5.00, 09/03, pa ge 299 of 760 Tp TRr TRrw TRrw CKIO CKE CSn RAS3U , RAS3L CASU , CASL RD/ WR Figure 10.26 Synchronous DRAM Auto-Refresh Timing[...]

Rev. 5.00, 09/0 3, page 300 of 760 • Self-Ref re shing Sel f-ref resh mod e is a k ind o f sta ndby mode in wh ich t he ref res h timin g an d re fres h addr esses are generated within the synchron ous DRAM. Self-refreshing is activated by setting both th e RMODE bit and the R FSH bit to 1. The sel f-refresh state is maintained while the CKE s ig[...]

Rev. 5.00, 09/03, pa ge 301 of 760 TRs1 CKIO RD/WR CSn RAS3U, RAS3L CASU, CASL CKE (TRs2) (TRs2) TRs3 (Tpc) (Tpc) Tp Figure 10.27 S ynchronous DRAM Self-Refres h Timing • Relation ship be tween Ref resh Re qu ests and Bus Cycle R equ ests If a refresh reques t is generated during ex e c u t i o n of a bus cycle, ex ecut i o n of the refresh is de[...]

Rev. 5.00, 09/0 3, page 302 of 760 Power-On Sequence: In order to use sy nchron ous DRAM, m ode setting must first be perf ormed after po wering on. To perform synchr onous DRAM initializ ati on correctly, the bus s tate con tr oller regist ers must first be set, f ollo wed by a w rite t o the sy nchronous DRAM m ode register. In synchronous DRAM m[...]

Rev. 5.00, 09/03, pa ge 303 of 760 Before m ode register se tting, a 100 µ s idle time (depending on the m emory manufacturer) must be guarant eed aft e r powe ring on requested by the synchronous DRAM . If th e reset s ignal pu l s e width is greater than this idle time, there is no problem in performing mode register setting immediately. The num[...]

Rev. 5.00, 09/0 3, page 304 of 760 10.3.5 Burst R OM Interface Setting bits A0BST1–0, A5BST1–0, and A 6BST1–0 in BCR1 to a n on-zero va lue all ows burst ROM to be connected to areas 0, 5, and 6. Th e burst ROM interface provide s high-speed access to ROM that ha s a nibb le access funct i on. The timing fo r nibble acces s to burst R OM is s[...]

Rev. 5.00, 09/03, pa ge 305 of 760 T 1 T W T W T B2 T B1 T W T B2 CKIO A 25 to A4 A 3 to A0 CSn RD/ WR RD D31 to D0 BS WAIT T 2 Note: For a write cycle, a basic bus cycle (write cycle) is performed. T B1 Figure 10.29 Burst ROM Wait A ccess Timing[...]

Rev. 5.00, 09/0 3, page 306 of 760 T 1 T B2 T B1 T B2 T B1 T B2 T B1 T 2 CKIO A25 to A4 A3 to A0 CSn RD/ WR RD D31 to D0 BS WAIT Note: For a write cycle, a basic bus cycle (write cycle) is performed. Figure 10.30 Burst ROM Basic Acc ess Timing[...]

Rev. 5.00, 09/03, pa ge 307 of 760 10.3.6 PCMCIA Interface In th e SH7709S , se t t in g th e A5PC M bit i n BCR1 to 1 makes the b u s int erface for p hysic a l space area 5 an IC mem ory card and I/O card interface as stipulated i n JEIDA version 4 . 2 (PCMCIA2.1). Setting the A6PCM bit to 1 makes the b u s int erface for physic a l space area 6 [...]

Rev. 5.00, 09/0 3, page 308 of 760 A24 to A0 D15 to D0 RD/WR CE1B/(CS6) CE1A/(CS5) RD WE1 ICIORD ICIOWR WAIT IOIS16 SH7709S A25 to A0 D15 to D0 CE2 OE WE/PGM (IORD) (IOWR) WAIT (IOIS16) CD1, CD2 CE1 PC card (memory/IO) G G G DIR DIR G D7 to D0 D15 to D8 A25 to A0 D15 to D0 CE2 OE WE/PGM WAIT CD1, CD2 CE1 PC card (memory/IO) G G G DIR DIR G D7 to D0[...]

Rev. 5.00, 09/03, pa ge 309 of 760 Memory Card In terface Basic Timing: Fig ure 10.32 show s the basic timing for t he PCMC IA IC memory card interface. When phy sical sp ace areas 5 and 6 are designated as PCMCIA interface areas, bus accesses are automatically pe rformed as IC memory card interface accesses. With a high e xternal bu s frequency (C[...]

Rev. 5.00, 09/0 3, page 310 of 760 CKIO Tpcm1 Tpcm2 A 25 to A0 CExx RD/ WR D15 to D0 (read) D15 to D0 (write) RD (read) WE (write) BS Figure 10.32 Basi c Timing for PCMCIA Memory Card Interface[...]

Rev. 5.00, 09/03, pa ge 311 of 760 CKIO Tpcm0 A 25 to A0 RD/ WR CExx RD (read) D15 to D0 (read) D15 to D0 (write) WE (write) BS WAIT Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w Figure 10.33 Wait T iming for PCMCIA Memory Card Interface[...]

Rev. 5.00, 09/0 3, page 312 of 760 Memory Card In terface Burst Timing: In th e SH7709S, w he n the IC memor y card interface is selected, page m ode burst access m ode can be used, for read access only , by setting bit s A5B ST1 and A 5BST0 in BCR1 f o r physical space area 5, or bit s A6BST1 a nd A6BS T0 in BCR1 for area 6. This burst access mode[...]

Rev. 5.00, 09/03, pa ge 313 of 760 CKIO Tpcm0 A25 to A4 CExx A3 to A0 RD/WR RD (read) D15 to D0 (read) BS WAIT Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm1 Tpcm1w Tpcm2 Tpcm2w Figure 10.35 Wait Timing for PCMCI A Memory Card Interface Burst Access[...]

Rev. 5.00, 09/0 3, page 314 of 760 When the entire 32 -Mbyte mem ory s pace is used as IC memory card inte rface space, the common memory/attribute memor y switching signal REG is generate d using a port, etc. I f 16 Mbytes or less of memory space is sufficient, using 16 Mbytes of memory space as c ommon memor y space and 16 Mbytes as attribute mem[...]

Rev. 5.00, 09/03, pa ge 315 of 760 I/O Card In terface Timing: Figu res 1 0.37 a nd 10 .38 s how the timing for t he PCMC IA I/O car d interface. Switching between the I/O card interface and the IC memory card inte rface is perfo rmed according to the a c ce sse d ad d r es s. When PCMC IA is de si gned for physical space area 5, the bus access is [...]

Rev. 5.00, 09/0 3, page 316 of 760 CKIO Tpci1 Tpci2 A 25 to A0 RD/ WR CExx ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) BS Figure 10.37 Basic Ti ming for PCMCIA I/O Ca rd Interfac e[...]

Rev. 5.00, 09/03, pa ge 317 of 760 CKIO A 25 to A0 RD/ WR CExx ICIORD (read) ICIOWR (write) D15 to D0 (read) D15 to D0 (write) BS WAIT IOIS16 Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w Figure 10.38 W ait Ti ming for PCMCIA I/ O Card Interfa ce[...]

Rev. 5.00, 09/0 3, page 318 of 760 CKIO Tpci0 A 25 to A1 CExx A 0 RD/ WR ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) BS WAIT IOIS16 Tpci1 Tpci1w Tpci2 Tpci1 Tpci1w Tpci2 Tpci2w Figure 10.39 Dyn amic Bus Sizing Timing for PCMCIA I/O Card Interface[...]

Rev. 5.00, 09/03, pa ge 319 of 760 10.3.7 Waits between Access Cycles A problem as sociated with higher ex ternal memory bus operating f r eque ncie s is that data buffer turn-off on completion of a read from a low-speed device may be t oo slow, c ausing a collision with data in the next access. This resu lts in lower reliabilit y or incorrect oper[...]

Rev. 5.00, 09/0 3, page 320 of 760 T 1 CKIO CSm CSn A 25 to A0 BS RD/ WR RD D31 to D0 T 2 Twait T 1 T 2 Twait T 1 T 2 Area m read Area m inter-access wait specification Area n inter-access wait specification Area n space read Area n space write Figure 10.40 Waits between Access Cycles 10.3.8 Bus Ar b itration When a bu s release request ( BRE Q ) i[...]

Rev. 5.00, 09/03, pa ge 321 of 760 I I I IR R R RQ Q Q QO O O OU U U UT T T T Pin Assertio n Condition s: • When a me mor y re fre sh r eque st has be en gener ated bu t the refr esh cy cl e has n ot ye t b egun • When an i nter rupt is ge ner ate d with a n int err upt r eque st l evel h ighe r than the s ett ing of the interrupt mask bits (I3[...]

Rev. 5.00, 09/0 3, page 322 of 760 Pull-up CKIO D31 to D0 RD CSn Pull-up Figure 10.42 Pu ll-Up T iming for Pi ns D31 to D0 (Read Cycle) Pull-up CKIO D31 to D0 WEn CSn Pull-up Figure 10.43 Pu ll-Up T iming for Pin s D31 to D0 (Write C ycle)[...]

Rev. 5.00, 09/03, pa ge 323 of 760 10.3.10 M M M MC C C CS S S S[ [ [ [0 0 0 0] ] ] ] to M M M MC C C CS S S S[ [ [ [7 7 7 7] ] ] ] Pin Control The SH7709S i s prov ided wi th pin s MCS[ 0] – MCS[7] as dedicated CS pins for the R OM connected to area 0 or 2. Assertion of MCS[0] – MCS[7] is controlled b y settings in M CSCR0– MCSCR7. This enab[...]

Rev. 5.00, 09/0 3, page 324 of 760 Table 10. 15 MCSCRx Setting s and M M M MC C C CS S S S[ [ [ [x x x x] ] ] ] Assertion Con ditions (x: 0–7) MCSCRx Settin gs M M M MC C C CS S S S[ [[ [x x x x] ]] ] A ssertion Conditions CS 2/ 0 C AP 1 C AP 0 A2 5 A2 4 A2 3 A2 2 C C C CS S S S0 0 0 0C C C CS S S S2 2 2 2 A ddress Bus A [25: 0] Notes 0110 — ?[...]

Rev. 5.00, 09/03, pa ge 325 of 760 MCSCRx Settin gs M M M MC C C CS S S S[ [[ [x x x x] ]] ] A ssertion Conditions CS 2/ 0 C AP 1 C AP 0 A2 5 A2 4 A2 3 A2 2 C C C CS S S S0 0 0 0C C C CS S S S2 2 2 2 A ddress Bus A[25:0] Notes 1110 — — — H LH ' 0 000000 to H'1FFFFFF 256-Mbit ROM 1 — — — H L H'2000000 t o H'3FFFFFF 1 [...]

Rev. 5.00, 09/0 3, page 326 of 760[...]

Rev. 5.00, 09/03, pa ge 327 of 760 Section 11 Direct Memory Access Controller (DMAC) 11.1 Overview The SH7709S includes a four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perfor m high-speed transfers bet ween ex ternal devices that have DACK (transfe r request acknowledge sign al), external memor y, [...]

Rev. 5.00, 09/0 3, page 328 of 760  Channel 3: In th is ch a nnel, direct address mode or indirect address trans fer m ode can be specified. • Reload function: The value th at was specified in the source address register can be automatically reloaded ev ery four DMA transfers. This fun ction is only a vailable in channel 2. • Tr a nsfe r re [...]

Rev. 5.00, 09/03, pa ge 329 of 760 11.1.2 Block D iagram Figure 11.1 s hows a block diagram of the DMAC . Peripheral bus Internal bus DREQ0 , DREQ1 Iteration control SARn DMAC module Register control Start-up control Request priority control Bus interface Bus state controller On-chip peripheral module DARn DMATCRn CHCRn DMAOR IrDA, SCIF A/D convert[...]

Rev. 5.00, 09/0 3, page 330 of 760 11.1.3 Pin C onfigurati on Table 11.1 sh ows th e DM AC pins. Table 11.1 DMAC Pins Channel Name Sy mbol I/O Function 0 DMA transfer requ est DREQ0 I DMA transfer requ est input from external dev ice to cha nnel 0 DMA transfer r equest acceptance D AC K0 O Strobe output to an external I/O upon DMA transfer r equest[...]

Rev. 5.00, 09/03, pa ge 331 of 760 11.1.4 Register C onfiguration Table 11.2 summarizes the DMAC registers. The DMAC has a total of 17 reg isters: each channel has four reg isters, and one overall DMAC c ontrol register. Table 11.2 DM AC Registers Channel Name A b brevi- ation R /W Initial Va lue Addre ss Register Size Ac ce s s Size 0 DMA sourc e [...]

Rev. 5.00, 09/0 3, page 332 of 760 Channel Name Ab br e v i - ation R /W Initial Va lue Addre ss Register Size A c cess Size 3 DMA sourc e address register 3 SAR3 R/W Undefined H'04000050 (H'A4000050) * 4 32 16, 32 * 2 DMA destination address regist er 3 DAR3 R/W Undefined H'04000054 (H'A4000054) * 4 32 16, 32 * 2 DMA transfer c[...]

Rev. 5.00, 09/03, pa ge 333 of 760 11.2 Register Descriptions 11.2.1 DMA Source Address Regis ters 0–3 (SAR0–SAR3) DMA source address re gisters 0–3 (SAR0–SAR3) are 32-bit readable/ writable registers that specify the source address of a D MA transfer. During a DMA transfer, these registers indicate the next sour ce add res s . To transf er[...]

Rev. 5.00, 09/0 3, page 334 of 760 11.2.2 DMA Destination Address Regi sters 0–3 (DAR0–DAR3) DMA destin a tion address registers 0–3 (DA R0–DAR3) are 32-bit reada ble/ writabl e reg is t ers that specify the destination address of a DMA transfer. These reg isters include a c ount function, and during a DMA transfer, these reg isters indicat[...]

Rev. 5.00, 09/03, pa ge 335 of 760 11.2.3 DMA Trans fer Count Regis ters 0–3 (DMATCR0–D M ATCR3) DMA t ransfer count registers 0–3 (DMATCR0–D MATCR3) are 24-bit readable/w ritable reg isters that specify the DMA transfer count (bytes, w o rds, or longwords). The num ber of transfers is 1 when th e sett ing i s H'000001, an d 16,777,216[...]

Rev. 5.00, 09/0 3, page 336 of 760 11.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) DMA chann el control regi sters 0–3 (CHCR 0–CHCR3) are 32-bit readable/writable reg isters that specify the operation mode, transfer m ethod, etc., for each channel. Bit 20 is only used i n CHCR3 ; it is not us e d in CH CR0 to CH CR2. Cons eq uently, [...]

Rev. 5.00, 09/03, pa ge 337 of 760 Bits 31 t o 21—Reserved: T hese bits are a lways read as 0. The write va lue shoul d always b e 0. Bit 20—Direct/Indirect Selection (DI): Sel ect s direct address mode or indirect addres s m ode in channel 3. This bit is onl y valid in C HCR3. Writing to t h is bit is invalid in CHCR 0 to CHCR 2; 0 is read if [...]

Rev. 5.00, 09/0 3, page 338 of 760 Bit 17—Ackn owledge Mode Bit (A M): Specifies wheth er DACK is output in the data read cycle or in t he data wri te cycle in du al address mode. DACK is always output i n single addre ss mode, regardless of this bit specificati on. This bit is only val i d in CHCR0 and CHCR 1. W riting to this bit is invalid in [...]

Rev. 5.00, 09/03, pa ge 339 of 760 Bits 13 and 12—Source Address Mode Bits 1 and 0 (SM1, SM0): Select w hether the DMA sou rce a ddr es s i s i ncreme nted , d ecr em ente d, or le ft f ixed. Bit 13: SM1 Bit 12: SM0 Description 0 0 Fixed source addre ss (Initial valu e) 0 1 Source addr ess is incre m ented (+1 in 8-bit tr ansfer, +2 in 16- bit tr[...]

Rev. 5.00, 09/0 3, page 340 of 760 Bits 11 t o 8—Resource Select Bits 3 to 0 (RS3 to RS0 ): Specify which tra nsfer r e quests w ill be sent to th e D MAC. Bit 11: RS3 Bit 10: RS2 Bit 9: RS1 Bit 8: RS0 Description 0 0 0 0 Ex ternal request * , dual address mode (Initi al value) 0 0 0 1 Setting pro hibited 0 0 1 0 Ex ternal request / S ingle addre[...]

Rev. 5.00, 09/03, pa ge 341 of 760 Bit 6— D D D DR R R RE E E EQ Q Q Q Select Bit (DS): Selects low-level or falling -edge detection a s the samplin g method for t h e DREQ pin used in extern al requ est mode. This bit is only val i d in CHCR0 and CHCR 1. W riting t o this bit is inva lid in CH CR2 and CHCR3 ; 0 is re a d if this bit is r e ad . [...]

Rev. 5.00, 09/0 3, page 342 of 760 Bit 1—Trans fer End Bit (TE): Set to 1 on completion of the number of data transfers specified in DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated. If data tran sfer ends du e to an NMI interrupt, a DMAC address error, or clearin g of the DE bit or the DME bit in DMAO R b efore [...]

Rev. 5.00, 09/03, pa ge 343 of 760 11.2.5 DMA Operation Register (DMA OR) The DMA operation register (DMAOR) is a 16-bit readable/ w ritable register that controls the DMAC transfer mode. These r egister va l ues are i nitialize d to 0 in a r eset. Th e pr evi ous value is r etain ed in stan d by mode. Bit: 15 14 13 12 11 10 9 8 —————— [...]

Rev. 5.00, 09/0 3, page 344 of 760 Bit 2—Address E rror Flag Bit (AE): Indicates th at an address error occurred b y the DMAC. If this bit is set during data transfer, transfers on all channels are suspended. The CPU cannot write 1 to this bit. This bit can only be cleared by writing 0 after reading 1. Bit 2: AE Description 0 No DM AC address err[...]

Rev. 5.00, 09/03, pa ge 345 of 760 11.3 Operation When there is a DMA transfer request, the DMA C starts the transfer according to the predetermined channel p riority order ; when the transfer e nd conditio ns are satisfied, it ends the transfer. Transfers can be requ ested in three m odes: auto-request, extern al request, and on -chip module reque[...]

Rev. 5.00, 09/0 3, page 346 of 760 Normal end AE = 1 or NMIF = 1 or DE = 0 or DME = 0? Bus mode, transfer request mode, DREQ detection selection system Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) Transfer (1 transfer unit); DMATCR − 1 → DMATCR, SAR and DAR updated DEI interrupt request (when IE = 1) No Yes No Yes No Yes Yes No Yes No * 3 *[...]

Rev. 5.00, 09/03, pa ge 347 of 760 11.3.2 DMA Transfer R equests DMA transfer requests are basical ly generated in ei the r the data transfer sourc e or destin ati on, but they can also be generated by devices and on-chip periphera l modules that are neither the source nor the destination . Transfers can be requ ested in three m odes: auto-request,[...]

Rev. 5.00, 09/0 3, page 348 of 760 request sign al. T he source of the transfer req uest does not have to be the data transfe r source or destination. W hen RXI is s et as the transfer request, however, the t ransfer source mus t be the S CI's receive data register (RDR). Likewise, when TX I is set as the transfer reque st, the t ransfe r so u[...]

Rev. 5.00, 09/03, pa ge 349 of 760 11.3.3 Channe l Priority When the DMAC receives simultaneo us transfer requests on two or m ore channels, it se lects a channel according to a predeterm ined priority order. Two m odes (fixed m ode and round-robi n mode) are s elected by pri ority bit s PR1 an d PR0 in the DMA operati on reg ister (DMAOR). Fixed M[...]

Rev. 5.00, 09/0 3, page 350 of 760 CH1 > CH2 > CH3 > CH0 CH0 > CH1 > CH2 > CH3 CH2 > CH3 > CH0 > CH1 CH0 > CH1 > CH2 > CH3 CH2 > CH3 > CH0 > CH1 CH0 > CH1 > CH2 > CH3 CH0 > CH1 > CH2 > CH3 CH3 > CH0 > CH1 > CH2 CH0 > CH1 > CH2 > CH3 (1) When channel 0 transfers Initial[...]

Rev. 5.00, 09/03, pa ge 351 of 760 Figure 11.4 show s ho w the priority order chang es when ch annel 0 and channel 3 transfers are requested simultan eously and a channel 1 transfer i s requested during the channel 0 tran sfer . The DMAC opera tes as follows: 1. Tr a nsfer r e quests a r e generat e d sim u ltan e ous ly f or c h annels 0 and 3. 2.[...]

Rev. 5.00, 09/0 3, page 352 of 760 11.3.4 DMA Transfer T ypes The DMAC supports th e transfers sh own in ta ble 11.5. Dual address mode has a direct address mode and i ndirect address mode. In direct address m ode, an output addres s valu e is the data transfer target address ; in indirect address mode, the value stored in the output address , not [...]

Rev. 5.00, 09/03, pa ge 353 of 760 (1) In direct address transfer m ode, DMA transfer requires two bu s cycles b ecause data is read from the transfer s ource in a data read cy cle and written to the trans fer destination in a data write cycle. At this time, transfer data is temporaril y stored in the DMAC. In the transfer between extern al memorie[...]

Rev. 5.00, 09/0 3, page 354 of 760 (1st cycle) (2nd cycle) Data read cycle Data write cycle Transfer source address Transfer destination address CKIO A25 to A0 CSn D31 to D0 RD WEn DACKn Note: In transfer between external memories, with DACK output in the read cycle, DACK output timing is the same as that of CSn . Figure 11.6 Examp le of DMA Transf[...]

Rev. 5.00, 09/03, pa ge 355 of 760 Memory Transfer source module Transfer destination module SAR3 DAR3 Data buffer Temporary buffer D M A C When the value in SAR3 is an address, the memory data is read and the value is stored in the temporary buffer. The value to be read must be 32 bits since it is used for the address. If data bus connected to an [...]

Rev. 5.00, 09/0 3, page 356 of 760 T ransfer source address (H) T ransfer source address (L) Indirect address NOP T ransfer destination address Indirect address (H) Indirect address (L) T ransfer data T ransfer data T ransfer data T ransfer data T ransfer data T ransfer source address * 1 T ransfer source address * 2 Indirect address NOP Indirect a[...]

Rev. 5.00, 09/03, pa ge 357 of 760 • Sing le Addres s Mode In sing le addres s mode, eit her the transfer source or tran sfer destination peripheral device is accessed (selected) by means of the DACK s ignal, and the other dev ice is accessed by address. In th is mode, the DMAC perf orms one DMA transfer in one bus cy cle, accessing one of the ex[...]

Rev. 5.00, 09/0 3, page 358 of 760 Address output to external memory space Data output from external device with DACK DACK signal (active-low) to external device with DACK Write strobe signal to external memory space Address output to external memory space Data output from external memory space DACK signal (active-low) to external device with DACK [...]

Rev. 5.00, 09/03, pa ge 359 of 760 CKIO A25 to A0 D31 to D0 RD WEn DACKn CSn Transfer source address +4 +8 +12 Figure 11 .11 E xample of DMA Transfe r Timing in Single A ddre ss Mode (16-byte Trans fer, External Memory Space (Ordinary Memory) → → → → External Device with DACK) Bus M odes: There are two bus modes: cycle-steal and burst. Sele[...]

Rev. 5.00, 09/0 3, page 360 of 760 CPU CPU CPU DMAC DMAC CPU DMAC DMAC CPU CPU DREQ Bus cycle Bus returned to CPU Read Write Write Read Figure 11.12 Example of DMA Transfer in Cycle-Steal Mode • Burst Mode Once the bus is obtain ed, the transf er is performed con tinuously until the transfer e nd condition is satisfied. In exte rnal re quest mode[...]

Rev. 5.00, 09/03, pa ge 361 of 760 Relationship between Reque st Modes and Bus M odes by DMA Transfer Category: Tabl e 11. 6 sho ws the rela t i o nship be twe en r eques t modes and bus m ode s by DMA t ransf e r cate g ory. Table 11.6 Relationship between Reque st M odes and Bus Modes by DMA Transfer Category Address Mode Transfer Category Reques[...]

Rev. 5.00, 09/0 3, page 362 of 760 Bus M ode and Channel P riority Order: When, for example, channel 1 is transferring in burst mode and there is a transfer request to channel 0, which has higher priority, the channel 0 transfer will b egi n imme dia tel y. At this time, if the priorit y is set in the fixed mode (CH 0 > CH1), the channel 1 trans[...]

Rev. 5.00, 09/03, pa ge 363 of 760 11.3.5 Num ber of Bus C ycle States an d D D D DR R R RE E E EQ Q Q Q Pin S ampling Timing Number of Bus Cycle States : When the DMAC is the bus master, the num ber of bus cycle st ates is controlled by the bus state control ler (BSC) in the same way as when the CPU is the bus master. For details, see sectio n 10,[...]

Rev. 5.00, 09/0 3, page 364 of 760 • Burst Mode, Level Detection In the case of burst mode with level detection, the DREQ samplin g timing is the same as in cycle-steal mode. For example, in figure 11.20 , DMAC transfer begins, at the earliest, three cycles after the first sampl ing is performe d. The second sam pling is start ed two cy c les aft[...]

Rev. 5.00, 09/03, pa ge 365 of 760 CKIO DRAK DREQ DACK Bus cycle DMAC(R) CPU DMAC(W) DMAC(R) CPU DMAC(W) 1st sampling 2nd sampling 3rd sampling Figure 11.15 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles)[...]

Rev. 5.00, 09/0 3, page 366 of 760 CPU CPU CKIO DRAK DREQ DACK DMAC(R) DMAC(W) DMAC(R) 1st sampling 2nd sampling 3rd sampling Bus cycle Figure 11.16 Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles)[...]

Rev. 5.00, 09/03, pa ge 367 of 760 CKIO DRAK (High output) Bus cycle DREQ DACK (RD output) DMAC(W) CPU DMAC(W) DMAC(R) CPU 1st sampling 2nd sampling 3rd sampling Figure 11.17 Cycle-Steal Mode, Level input (CPU Access: 2 Cycl es, DMA RD Access: 4 Cycles)[...]

Rev. 5.00, 09/0 3, page 368 of 760 CKIO DRAK Bus cycle DREQ DACK (RD output) CPU CPU DMAC(W) DMAC(R) DMAC(W) DMAC(R) CPU 3rd sampling is performed, but since DREQ is high, per-cycle sampling starts 2nd sampling is performed, but since DREQ is high, per-cycle sampling starts 1st sampling 2nd sampling 3rd sampling Figure 11.18 Cycle-Steal Mode, Level[...]

Rev. 5.00, 09/03, pa ge 369 of 760 CKIO DRAK Bus cycle DREQ DACK (RD output) CPU CPU DMAC(W) DMAC(R) DMAC(W) DMAC(R) CPU High High High High 3rd sampling is performed, but since there is no DREQ falling edge, per-cycle sampling starts 2nd sampling is performed, but since there is no DREQ falling edge, per-cycle sampling starts 1st sampling 2nd samp[...]

Rev. 5.00, 09/0 3, page 370 of 760 CKIO DRAK DREQ DACK Bus cycle DMAC(R) DMAC(W) DMAC(R) DMAC(W) DMAC(R) CPU 1st sampling 2nd sampling 3rd sampling Figure 11.20 Burst Mode, Lev el Input[...]

Rev. 5.00, 09/03, pa ge 371 of 760 CKIO DRAK DREQ DACK Bus cycle CPU DMAC(R) DMAC(W) DMAC(R) DMAC(W) DMAC(R) 1st sampling Figure 11.21 Burst Mode , Edge Inp u t[...]

Rev. 5.00, 09/0 3, page 372 of 760 11.3.6 Source Address Reload Function Channel 2 includes a reload function, i n which the value is returned to the value set in the source add ress re gister (SAR 2 ) ev e ry f our t ran sf ers by set t ing the RO bi t in CH CR2 t o 1 . 16-byte t ra nsfer cannot be us ed. Figure 11.22 s hows this operation. Figu r[...]

Rev. 5.00, 09/03, pa ge 373 of 760 CK Internal address bus Internal data bus SAR2 DAR2 DAR2 DAR2 DAR2 SAR2+2 SAR2+4 SAR2+6 SAR2 SAR2 data SAR2+2 data SAR2+4 data SAR2+6 data First transfer on channel 2 Second transfer Third transfer Fourth transfer Fifth transfe r SAR2 output DAR2 output SAR2+2 output DAR2 output SAR2+4 output DAR2 output SAR2+6 ou[...]

Rev. 5.00, 09/0 3, page 374 of 760 11.3.7 DMA Trans fer Endi ng Conditi ons The DMA transfer ending conditio ns are different for ending on an individual c hannel and ending on all cha nnel s toget her. At the end of trans fer , the follo wing cond itions are app lie d e xcept in the case where the value set in the DMA transfer count regis ter (DMA[...]

Rev. 5.00, 09/03, pa ge 375 of 760 Conditions fo r Ending on All Channels S imultaneo usly: Transfers on all ch annels end (1) when the AE or NMIF (NMI flag) bit is set to 1 in DMAOR, or (2) when the DME b it in DMAOR is cleared to 0. • Tr ansfer endin g wh en the N MIF b it is se t to 1 i n DMAOR: When an NMI i nterru pt occur s, th e AE or NMIF[...]

Rev. 5.00, 09/0 3, page 376 of 760 11.4 Co mpare Match Timer (CMT) 11.4.1 Overvie w The DMAC has an on-chip compare match timer (CMT) to generate DMA tr ansfer requests. The CMT has a 16- bit counter. Features The CMT has the following features: • Four types of coun ter input clock can be selected  One of four intern al clocks (P φ /4, P φ /[...]

Rev. 5.00, 09/03, pa ge 377 of 760 Register Configuratio n Table 11.7 summ arizes the CMT regis ter configuration. Table 11.7 Register Configuration Name Abbreviation R/W Initial Value Address Access Size (Bits) Compare ma tch ti mer start register CMSTR R/(W ) H'0000 H '04000070 (H'A400007 0) * 2 8, 16, 32 Compare ma tch timer contr[...]

Rev. 5.00, 09/0 3, page 378 of 760 Bit 0—Count Start 0 (STR0): Selects whether to operate or halt CMCNT 0. Bit 0: STR0 Description 0 CMCNT0 count opera tion halted (Initial valu e) 1 CMCNT 0 count operation Compare Match Timer Control/Status Register 0 (CMCSR0) The compare match timer control/status register 0 (CMCSR0) is a 16-bit register that i[...]

Rev. 5.00, 09/03, pa ge 379 of 760 Bit 6—Reserved: Thi s bi t ca n be rea d or writte n. The wit e valu e shou ld alw ays be 0 . Bits 1 and 0 —Clock Select 1 and 0 (CKS1, CKS0): Select th e cloc k inpu t to CM CNT from among t h e four internal clocks obt ai n ed by dividing the sys tem clock (P φ ). When the STR bit in CMSTR is set to 1, CMCN[...]

Rev. 5.00, 09/0 3, page 380 of 760 Compare Match Cons tant Register 0 (C MCOR0) Compare match constant regis ter 0 (CMCOR0) is a 16- bit register that s ets the CMCNT0 compare match peri od. CMCOR0 is initial ized to H'FFFF b y a reset, but retains its previo us value in standb y mode. Bit: 15 14 13 12 11 10 9 8 I n i t i a l v a l u e : 11111[...]

Rev. 5.00, 09/03, pa ge 381 of 760 CMCNT0 Co unt Ti ming One of fou r clocks (P φ /4, P φ /8, P φ /16, P φ /64) obt ained by divi ding the P φ clock can be selected with the CKS1 and CKS0 bits in CMCSR0. Figure 11.26 shows th e timing . N+1 CK Internal clock CMCNT0 input clock CMCNT0 N-1 N Figure 11.26 C ount T iming 11.4.4 Compare Match Compa[...]

Rev. 5.00, 09/0 3, page 382 of 760 CK CMCOR0 CMCNT0 input clock Compare match signal CMF CMI CMCNT0 N N 0 Figure 11.27 CMF Setting Ti ming Compare Match Flag Clearing Timi ng The CMF bit in the CMCSR 0 register is cleare d by wri t ing 0 to it after reading 1 . Figure 11.28 shows the timing when the CMF bit is cleared by the CPU. CK CMF CMCSR0 writ[...]

Rev. 5.00, 09/03, pa ge 383 of 760 11.5 Examples of Use 11.5.1 Exam ple of DMA Transfer between On-C hip IrDA and External Mem ory In th is example, receive data of the on- chip IrDA is transferred to extern al memory using DMAC channel 3. Tab le 11.8 shows the transfer conditions and register sett in gs. In addition, it is recommended that the tri[...]

Rev. 5.00, 09/0 3, page 384 of 760 11.5.2 Example of DMA Transfer be tween A/D Converter and E xternal Memory In t his exam ple, DMA transf er is perf ormed bet ween the on -chip A/D converter (tran sfer source) and the exter nal memory (trans fer destination) with the address reload function on. Table 11.9 shows the tran sfer conditio ns and re gi[...]

Rev. 5.00, 09/03, pa ge 385 of 760 As a result, t he va lues in the DMAC ar e as sh own in tabl e 11 . 10 when the fou rth t ran sfer en ds, depending on whether the addre ss reload function is on or o ff. Table 11.10 Values in DMAC after End of Fourth Transfer Items Address reload on Address r eload off SAR H'04000080 H'04000090 DAR H&ap[...]

Rev. 5.00, 09/0 3, page 386 of 760 Table 11.11 Transfer Conditions and Register Settings for Transfer between External Memory and SCIF Transmitter Transfer Conditions Register Setting Transfer sourc e: External memory SAR3 H'00400000 Value stor ed in address H'00400000 — H'004500 00 Value stor ed in address H'04500000 — H&ap[...]

Rev. 5.00, 09/03, pa ge 387 of 760 11.6 Usage Notes 1. The DMA channel control reg isters (CHCR0–CHCR 3) can be accessed with any data size. The DMA operation register (DMAOR) must be accessed b y byte (8 bits) or word (16 bits); other registers must be accessed by word (16 bits) or longw ord (32 bits). 2. B efore re writing the RS0–R S3 bits i[...]

Rev. 5.00, 09/0 3, page 388 of 760[...]

Rev. 5.00, 09/03, pa ge 389 of 760 Section 12 Timer (TMU) 12.1 Overview The SH7709S h as a th ree-channe l (channels 0 to 2) 32-bi t timer unit (TMU). 12.1.1 Features The TMU has the follo wing features: • Each chan n el is prov ided with a n auto-reload 32-bit do w n c ounter. • Channel 2 is provided with an input capture function. • All cha[...]

Rev. 5.00, 09/0 3, page 390 of 760 12.1.2 Block D iagram Figure 12.1 s hows a block diagram of the TMU. TOCR Prescaler TSTR TCR0 TCNT0 Module bus Internal bus TCOR0 TCR1 TCNT1 TCOR1 Counter controller TCLK P φ RTCCLK TUNI0 Bus interface Ch. 0 Interrupt controller Interrupt controller Interrupt controller Counter controller Counter controller TUNI1[...]

Rev. 5.00, 09/03, pa ge 391 of 760 12.1.3 Pin C onfigurati on Table 12.1 sh ows th e pin confi guration o f th e TMU. Table 12.1 TMU Pin Channel Pin I/O Description Clock in put/ clo ck outp ut TCLK I/O External clock inpu t pin/in put capture control inp ut pin/realtime cl oc k (RTC ) output pin 12.1.4 Register C onfiguration Table 12.2 sh ows th [...]

Rev. 5.00, 09/0 3, page 392 of 760 12.2 TMU Regist ers 12.2.1 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that selects whether to use the external TCLK pin as an external clock or an input capture co ntrol usage input pi n, or an o utput pi n for the on-chip R TC output clock. TOCR i s initialized to H'00 b[...]

Rev. 5.00, 09/03, pa ge 393 of 760 Bits 7 to 3—Reserved: These bits are always read as 0. The write value should a lways be 0 . Bit 2—Coun ter Start 2 (ST R2): Selects whether to ru n or h alt timer coun ter 2 (TCNT2). Bit 2: STR2 Description 0 TCNT2 count h alted (Initial valu e) 1 TCNT 2 counts Bit 1—Coun ter Start 1 (ST R1): Selects whethe[...]

Rev. 5.00, 09/0 3, page 394 of 760 Chann els 0 and 1 TCR B it Config uration: Bit: 15 14 13 12 11 10 9 8 ——————— U N F I n i t i a l v a l u e : 00000000 R / W : RRRRRRR R / W B i t : 76543210 — — UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 I n i t i a l v a l u e : 00000000 R/W: R R R/W R/ W R/W R/ W R/W R/W Channel 2 TCR B it Config urat[...]

Rev. 5.00, 09/03, pa ge 395 of 760 Bit 8—Underflow Flag (UNF): Status flag that indicates occurrence of a TCNT underflow. Bit 8: UN F Descr iption 0 TCNT has not underflow ed Clearing cond ition: W he n 0 is written to UNF (Initial value) 1 TCNT has underflowed Setting condit ion: W hen TCN T underflow s * Note: * Contents do not change when 1 is[...]

Rev. 5.00, 09/0 3, page 396 of 760 Bits 4 and 3 —Cloc k Edge 1 and 0 (CKEG1, C KEG0): Select t he external clock edge when the extern al clock is selected, or when the in put ca pt ure function is used. Bit 4: CK EG1 Bit 3: CKEG0 Description 0 0 Count/capture regis ter set on rising edge (Initial value) 1 Count/capture re gister set on fa lling e[...]

Rev. 5.00, 09/03, pa ge 397 of 760 12.2.4 Timer Constant Registers (TCOR) The TM U has three TCOR registers, one for each channel. T COR specifies the value for settin g in TCN T whe n a T CNT c ount-d o wn res ults i n an u nde r fl o w. TCOR is a 32-bit readab le/ writable register. T COR is initialized to H 'FFFFFFFF b y a power-on reset or[...]

Rev. 5.00, 09/0 3, page 398 of 760 Because the internal bus for the SH7709S on -chip peripheral modules is 16 bits wide, a time lag can occu r between the time wh en the upper 16 bits a nd lower 16 bits are read. S ince TCNT counts sequentially, this time lag can create discrepancies betwee n the data in the upper and lo wer halves. To correct the [...]

Rev. 5.00, 09/03, pa ge 399 of 760 12.2.6 Input Ca pture Regist er (TCPR2) Input capture reg ister 2 (TCPR2) is a read- only 32- bit register provided o n ly in t imer 2. Control o f TCPR2 setting conditions due to the T CLK pin is affected by the input capture function bits (ICPE1/I CPE0 and CKEG1/CKEG0) in TCR2. W hen a TCPR2 setting indicatio n [...]

Rev. 5.00, 09/0 3, page 400 of 760 12.3 TMU Operation Each of three channels has a 32-bit ti mer counter (TC NT) and a 32-bi t timer con stant register (TCOR). TCNT counts down . The auto-reload fu nction enables cycle count i ng and c ounting by external events. Channel 2 has an input capture function. 12.3.1 General Operation When the STR0 – ST[...]

Rev. 5.00, 09/03, pa ge 401 of 760 Select operation Select counter clock Set underflow interrupt generation Set timer constant register Initialize timer counter Start counting (1) (2) (4) (5) (6) Set interrupt generation When using input capture function (3) Note: When an interrupt has been generated, clear the flag in the interrupt handler that ca[...]

Rev. 5.00, 09/0 3, page 402 of 760 Auto-Reload Coun t Operation: Figure 12.3 sh ows the TCNT auto-reload operation. TCNT value TCOR H'00000000 STR0 − STR2 UNF TCOR value set to TCNT during underflow Time Figure 12.3 A uto-Reload Count O peration TCNT Co unt Ti ming: • Internal Clock Operation : Set the TPSC2–TPSC0 bits in TCR to selec t [...]

Rev. 5.00, 09/03, pa ge 403 of 760 • External Clock Operation: Set the T PSC 2–TPSC0 bits in TCR to select t he external clock (TCLK) as the timer clock. Use t he CKEG1 and CKEG0 bits in TCR to select the detecti on edge. Ris ing, falling, or both edg es may be s elected. The pulse width of the external clock must be at least 1.5 per ipheral mo[...]

Rev. 5.00, 09/0 3, page 404 of 760 TCNT value TCOR H'00000000 TCLK TCPR2 Set TCNT value ICPI TCOR value set to TCNT during underflow Time Figure 12. 7 Operation T iming when Usin g Input Capture Func tion (Using TC LK Risi ng Edg e ) 12.4 Interrupts Ther e are two s ources of TMU int errupts: und erfl ow inter rupts (T UNI) and interru pts whe[...]

Rev. 5.00, 09/03, pa ge 405 of 760 12.4.2 Status Flag Cleari ng Timi ng The status flag can be cleared by writing 0 from the CPU. Figure 12.9 shows the timing. P φ Peripheral address bus UNF, ICPF TCR address T 1 T 2 TCR write cycle T 3 Figure 12.9 Stat us Flag Clearing Ti ming 12.4.3 Interrupt Source s and Prio rities The T MU produces un derflow[...]

Rev. 5.00, 09/0 3, page 406 of 760 12.5 Usage Notes 12.5.1 Writin g to Registers Synch ronization processing is not perform ed for timer counting during register writes. When writing t o regis ters, always clear the appropriate star t b i ts for the chann el ( STR2 – STR0) in t he timer start register (TS TR) to hal t timer counting. 12.5.2 Readi[...]

Rev. 5.00, 09/03, pa ge 407 of 760 Section 13 Realtime Clock (RTC) 13.1 Overview The SH7709S has a realtime clock (RTC) with its own 32 . 768-kHz crysta l oscillato r. 13.1.1 Features • Clock and calendar f unctions (BC D display): Seconds, minutes, hours , date, day of the week, month, an d year • 1-Hz to 6 4-Hz timer (b in ary disp lay) • S[...]

Rev. 5.00, 09/0 3, page 408 of 760 13.1.2 Block D iagram Figure 13.1 s hows a block diagram of the RTC. Module bus RTC Internal bus Interrupt control circuit Prescaler ( ÷ 2) RTCCLK Bus interface Carry detection circuit ATI PRI CUI Legend R64CNT: 64 Hz counter RSECCNT: Second counter RMINCNT: Minute counter RHRCNT: Hour counter RWKCNT: Day-of-week[...]

Rev. 5.00, 09/03, pa ge 409 of 760 13.1.3 Pin C onfigurati on Table 13.1 sh ows th e RTC pin configurat ion. Table 13 .1 RTC Pi n s Pin Signal Name I/O Description RTC oscillator crysta l pin EXT AL2 I Connects crystal to RT C oscillator * 2 RTC oscillator crysta l pin XTAL2 O Connects cry s tal to RTC os cillator * 2 Clock in put/ clo ck outp ut T[...]

Rev. 5.00, 09/0 3, page 410 of 760 13.1.4 RTC Reg ister Conf iguration Table 13.2 sh ows th e RTC regist er configurat ion. Table 13 .2 RTC Re gisters Name Abbr eviation R/W Initial Value Address A ccess Size 64-Hz coun ter R64CNT R Undefined H'FFFFFEC0 8 Second count er RSECCNT R/W Undefined H'FFFFFEC2 8 Minute coun ter RMIN CNT R/W Unde[...]

Rev. 5.00, 09/03, pa ge 411 of 760 13.2 RTC Regist ers 13.2.1 64-Hz Counter (R 64CNT) The 64-Hz counter (R 64CNT) is an 8- bit rea d-only register that indi cat es the states of th e RTC divider circu it, RTC prescal er, and R64CNT betw ee n 64 Hz and 1 Hz. R64CNT is initialized to H'00 by set t ing the RES ET bit in RTC co ntrol register 2 (R[...]

Rev. 5.00, 09/0 3, page 412 of 760 13.2.3 M inute Counter (RMINCNT) The minute counter (RMINCNT) is an 8-bit readable/ wr itab le register used for setting/countin g in the BCD-coded minute section of the RTC. The count operation is perfo rmed by a c a rr y for each minute of the second counter. The range that can be set is 00–59 (deci mal). Erra[...]

Rev. 5.00, 09/03, pa ge 413 of 760 13.2.5 Day of We ek Counter (RWKCN T) The day of week counter (RWKCNT) is an 8-bit readable/ writable register us ed for setting/counting in the BCD-coded day of week section of the RTC. The count operation is per for med b y a car ry f or each d ay of th e da te co unt er. The range that can be set i s 0 – 6 (d[...]

Rev. 5.00, 09/0 3, page 414 of 760 13.2.6 Date Co unter (RDAYCNT) The date counter (RDAYCNT) is an 8-bit readable/ writab le register used for setting/counting in the BCD-coded date section of the RT C. The count operation is perfo rmed by a car ry for each d ay of th e hour counter. The range that can be s et is 01 – 31 (decimal). Errant operati[...]

Rev. 5.00, 09/03, pa ge 415 of 760 13.2.8 Year Co unter (RYRCNT) The year coun ter (RYRCNT) is an 8-bit readable/ writable register used f or setting/counting in the BCD-coded y ear section of the RTC. The least significant 2 di gits of the western calendar year are displayed. The count operatio n is performed by a ca rry for each year of the month[...]

Rev. 5.00, 09/0 3, page 416 of 760 13.2.10 M inute Alarm Register (RMINAR) The minute alarm r egister (RMINAR) is an 8-bit readable/writable re gister, and an alarm register correspondin g to the BCD-coded minu te section coun ter RMINCNT of the RTC. When t h e ENB bit is s et to 1, a compar ison with the RMINCNT value is performed. From among the [...]

Rev. 5.00, 09/03, pa ge 417 of 760 13.2.12 Day of Wee k Ala r m Register (R WKAR) The day of week alarm register ( RWKAR) is an 8-bit readable/w r itable register, and an alarm regist er corresponding to the BCD-coded da y of week section counter RWKCNT of the RTC. When t he EN B b i t is se t to 1, a co mp arison with the R WK CNT valu e is p e r [...]

Rev. 5.00, 09/0 3, page 418 of 760 13.2.13 Date Alar m Register (RDAYAR) The date alarm register (RDAYAR) is an 8-bit readable/w ritable regis ter, and an alarm register corres pondin g to th e BCD- coded date se ction coun ter RDAYCNT o f the R TC. When the EN B bit is set to 1, a comp arison w ith the RDAYCNT value is performed. F rom a mong the [...]

Rev. 5.00, 09/03, pa ge 419 of 760 13.2.15 RTC Control Register 1 (RCR1) The RT C contr o l register 1 (RCR1) is an 8-bit rea d able/ writable regi ster tha t a ffec ts ca r ry fla gs and alarm flags. It also selects whether to gen erate interrupts for each flag. Because flags are sometimes set after an operand read, do n ot use this register in re[...]

Rev. 5.00, 09/0 3, page 420 of 760 Bit 3 — Alarm Interrupt Enable Flag (AIE): When the alarm flag (AF ) is set to 1, the AIE bit allows interrupts. Bit 3: AIE Description 0 An alarm interr upt is not generated when the AF flag is set to 1 (Initial valu e) 1 An alarm interr upt is generated when the AF fla g is set to 1 Bit 0 — Alarm Flag (AF): [...]

Rev. 5.00, 09/03, pa ge 421 of 760 Bits 6 to 4—Period i c I n terru pt Flags (PES 2-PE S0): Specify the periodic interru pt. Bit 6: PES2 Bit 5: PES1 Bit 4: PES0 Description 0 0 0 No periodic i nterrupts generated (Initia l value) 1 Periodic interrupt gener ated every 1/256 seco nd 1 0 Periodic interrupt generated every 1/64 second 1 Periodic inte[...]

Rev. 5.00, 09/0 3, page 422 of 760 Bit 0 — Start B it (START): Halts and restart s the counter (clock). Bit 0: STAR T Description 0 Second/minut e/hour/day/week/ month/year coun ter halts 1 Second/minut e/hour/day/week/ month/year coun ter runs norm a lly (Initial valu e) Note: The 64-H z counter always runs unless stopped with the RTCEN bit. 13.[...]

Rev. 5.00, 09/03, pa ge 423 of 760 13.3.3 Readin g the Time Figure 13 . 3 sho ws ho w to re ad t he t ime. I f a ca rry oc curs wh ile r ead ing the tim e , the c o rre ct time will n ot be obtained, s o it must be read ag ain. Part (a) in figu re 13.3 shows t he method of readin g the time without us ing interrupts; part (b) in figure 13.3 shows t[...]

Rev. 5.00, 09/0 3, page 424 of 760 13.3.4 Alarm F unction Figure 13.4 s hows how to use the alar m function. Alar ms ca n be ge nera t ed usi ng se cond s, min ute s, hour s, d a y of the week, dat e , mont h, or a ny combination of these. Set the ENB bit (b it 7) to 1 in the register to which the alarm applies, and then set the alarm t ime in the [...]

Rev. 5.00, 09/03, pa ge 425 of 760 13.3.5 C rystal Oscillat or Circuit Crystal oscillator cir cuit co nstants (reco mmended values) are shown in table 13 .5, and the RTC crystal oscillator circuit i n figure 13.5. Table 13.5 Reco mmended Oscillato r Circuit Consta nts (Reco mme nded Values) fosc Cin Cout 32.768 kHz 10 to 22 pF 10 to 22 pF SH7709S E[...]

Rev. 5.00, 09/0 3, page 426 of 760 13.4 Usage Notes 13.4.1 Register W riting d uring RTC Count The following RTC reg isters cannot be w ritte n to during an RTC co unt (while bit 0 = 1 in RC R2). RSECCNT, RMINCNT, RHRCNT, RDAYCNT, RWKCNT, RMONCNT , RYRCNT The RTC count mus t be halted before writing to any of the above registers. 13.4.2 Use of Real[...]

Rev. 5.00, 09/03, pa ge 427 of 760 Section 14 Serial Communicati on Interface (SCI) 14.1 Overview The SH7709S has an on -chip serial communication interface (SCI) that supports both asynchronou s and clock sy n chronous serial communication. It also has a multiproce ssor commu n ica tio n f unc ti o n for seri al co mmu nic at io n among two o r m [...]

Rev. 5.00, 09/0 3, page 428 of 760 • Internal or external transmit /receive clock source: From either ba ud rate generator (internal) or SCK pin (e xte rnal) • Four types of interru pts: Transmit-data-empty, transmit-en d, receive-data-full, and receive- error interru pts are requ ested in dependently. • When the SCI is not in use, it can be [...]

Rev. 5.00, 09/03, pa ge 429 of 760 Figures 14.2, 14.3, an d 14.4 show bl ock diag ra ms of the SCI I/O port pin s. SCIF pin I/O and data c ontrol is perf ormed by bits 11 to 8 of S CPCR and bit s 5 and 4 o f SCP DR. For det ails , see sect ion 14.2.8, SC Port C ontrol Reg ist er (S CPCR)/SC Port Data R e gister (SCPDR). Internal data bus Output ena[...]

Rev. 5.00, 09/0 3, page 430 of 760 Internal data bus Output enable SCI Serial transmission output R SCP0MD0 PCRW Reset C Q Q D R SCP0MD1 PCRW Reset C QD R SCP0DT1 PDRW Reset SCPT[0]/TxD0 C D PCRW: PDRW: SCPCR write SCPDR write Legend Figure 14.3 SCPT[0]/T xD0 Pin[...]

Rev. 5.00, 09/03, pa ge 431 of 760 SCI Serial receive data Internal data bus PDRR * SCPT[0]/RxD0 PDRR: PDR read Note: * When reading the RxD0 pin, set the RE bit in SCSCR to 1. Legend Figure 14.4 SCP T[0]/RxD0 Pin 14.1.3 Pin C onfigurati on The SCI has th e serial pins summ arized in table 14.1. Table 14.1 SCI Pins Pin Name Abbreviation I/O Functio[...]

Rev. 5.00, 09/0 3, page 432 of 760 14.1.4 Register C onfiguration Table 1 4.2 summarizes the SCI internal regi sters. These register s select the communication mode (asynch ronous or sy nchronou s), specify the data format an d bit rate, and control the trans mitter and receiver s ections. Table 14.2 SCI Re gisters Name A bbreviation R/W Initial V [...]

Rev. 5.00, 09/03, pa ge 433 of 760 14.2.2 Receive Data Register (SCRDR) The receive data register (SCRDR) stores serial receiv e data . The SCI completes the reception of one byte of serial data b y moving the received data from the receive s hift register (SCRSR ) int o SCRDR for storage. SCRSR is then ready to receive th e next data. This double [...]

Rev. 5.00, 09/0 3, page 434 of 760 14.2.4 Transm it Data Register (SCTDR) The transmit data r egister (SCTDR ) is an 8-bi t register th at stores data for serial tra nsmission. When the SCI detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in SCTDR into SCT SR a nd star ts serial t ransmis s ion. Contin uous [...]

Rev. 5.00, 09/03, pa ge 435 of 760 Bit 6—Character Length (CHR): Selects 7- bit or 8-bit data in asy nchronous mode. In th e synchronous mode, the d ata lengt h is always eight bits, regardless o f the CH R setting. Bit 6: CH R Description 0 8-bit data (Initial valu e) 1 7-bit data * Note: * When 7-bit data is se lected, the MSB (bit 7) of t he t[...]

Rev. 5.00, 09/0 3, page 436 of 760 Bit 3—Stop Bit Length (STOP): Selects one or t wo bits as the stop bit l ength in a synchr onous mode. This setting is used only in asyn chronous mode. It is ignore d in synchrono us mode because no stop bi ts are added. When receiving, only th e first stop bit is checked, regardles s o f the STOP bit setting. I[...]

Rev. 5.00, 09/03, pa ge 437 of 760 14.2.6 Serial Con trol Register (S CSCR) The serial con trol regis ter (SCSCR) operates the S CI transmitter/receiver, s elects the serial clock output in asynchronous mode, enables/disab les interrupt requests, and selects the tra nsmit/receive clock source. The CPU can always read and write to SCSCR. SCS CR is i[...]

Rev. 5.00, 09/0 3, page 438 of 760 Bit 5—Tran smit E nable (TE ): Enables or disables the SCI serial transmitter. Bit 5: TE Description 0 Transmitter d isabled * 1 (Initial valu e) 1 Transmitter en abled * 2 Notes: 1 . The transmi t d ata register empty bit (TDRE) in the serial status register (SCSSR) is fixed at 1. 2. Serial tran sm iss ion st a[...]

Rev. 5.00, 09/03, pa ge 439 of 760 Bit 2—Transmit-End I nterrupt Enable (TEIE): Enables or dis ables the tran smit-e nd inte rru pt (TEI) requested if SCTDR does not contain new tr ansmi t data when the MSB is tran smitted. Bit 2: TEIE Description 0 Transmit-end interr upt (TEI) r eq u ests are dis abl ed * (Initial value) 1 Transmit-end interr u[...]

Rev. 5.00, 09/0 3, page 440 of 760 14.2.7 Serial Status Register (S C SSR) The se rial stat us regis ter (SCSSR) is an 8- bit regist er conta ining multiprocessor bit va lues, a nd status flags th at indicate the SCI operating state. The CPU can alw ays read and w r ite to SCSSR, but cannot write 1 to the status flags (TDRE, RDRF, ORE R, PE R, and [...]

Rev. 5.00, 09/03, pa ge 441 of 760 Bit 6—Receive Data Register Full (RDRF): Indicates that SCR DR contains received data. Bit 6: RDRF Description 0 SCRDR does not conta in valid receiv e data (Initial v alue) [Clearing c onditions] (1) RDRF is cleared to 0 w hen the chip is rese t or enters stand by mode. (2) Software reads RDRF after it has bee [...]

Rev. 5.00, 09/0 3, page 442 of 760 Bit 4—Fram i ng Error (FER): Indicates that data reception aborted due to a framing error i n async hro no us mo de . Bit 4: FER Description 0 Receiving i s in progr ess or has end ed normally * 1 (Initial val ue) [Clearing c onditions] (1) FER is cleared t o 0 when the chip is reset or enters stand by mode. (2)[...]

Rev. 5.00, 09/03, pa ge 443 of 760 Bit 2—Tran smit E nd (TEND): In dicates that when the last bit of a serial character w as transmitted, SCTDR did not contain valid data, so transmission has ended. TEND is a read-only bit and cannot be written to. Bit 2: TEND Description 0 Transmissi on is in progress [Clearing c ondition] TEND is cleared to 0 w[...]

Rev. 5.00, 09/0 3, page 444 of 760 14.2.8 SC Port Control Reg ister (SCPCR)/SC Port Data Register (SCPDR) The SC port control regis ter (SCPCR) a nd SC port data register (SCPDR) control I/O and data for the port pins multiplexed with the serial communication interface (SCI) pins. SCPCR settings are u sed to perform I/O control, to enable data writ[...]

Rev. 5.00, 09/03, pa ge 445 of 760 SCPDR Bit 1—Serial Clock Port Data (SCP1DT): Specifies the serial port SCK pin I/O data. Input or o utput is specified by the SC P1MD1 and SCP1MD0 bits. In output mode, the valu e of the SCP1DT bit is output to the SCK pin. Bit 1: SCP1DT Description 0 I/O data is low (Initial value) 1 I/O data is high SCPCR Bits[...]

Rev. 5.00, 09/0 3, page 446 of 760 14.2.9 Bit Ra te Reg ister (SCB RR) The bit rate re gister (SCBRR) is an 8- bit register that, t ogether w ith the ba ud rate generator clock source selected b y the CKS1 and CKS0 bits in the serial mode register (SCSMR) , determines the serial transmit/receive bit rate. The CPU can always read and w rite to SCB R[...]

Rev. 5.00, 09/03, pa ge 447 of 760 Table 14.4 lists ex a mples of SCBRR setting s in asynchron ous mode, and table 14.5 lis t s examples of SC BRR se tti ng s in synchron o us mode. Table 14.4 Bit Rates and S C BRR Setti ngs in A synchronous Mode P φ φ φ φ (MHz) 2 2.097152 2.4576 Bit Rate (bits/s) n N Error ( % % % % ) n N Error ( % % % % ) n N[...]

Rev. 5.00, 09/0 3, page 448 of 760 P φ φ φ φ (MHz) 4.9152 5 6 Bit Rate (bits/s) n N Error ( % % % % ) n N Error ( % % % % ) n N Error ( % % % % ) 110 2 86 0.31 2 88 –0.25 2 106 –0.44 150 1 255 0.00 2 64 0.16 2 77 0.16 300 1 127 0.00 1 129 0.16 1 155 0.16 600 0 255 0.00 1 64 0.16 1 77 0.16 1200 0 127 0.00 0 129 0.16 0 155 0.16 2400 0 63 0.00[...]

Rev. 5.00, 09/03, pa ge 449 of 760 P φ φ φ φ (MHz) 14.7456 16 19.6608 20 Bit Rate (bits/s) n N Error ( % % % % )n N Error ( % % % % )n N Error ( % % % % )n N Error ( % % % % ) 110 3 64 0.70 3 70 0.03 3 86 0.31 3 88 –0.25 150 2 191 0.00 2 207 0.16 2 255 0.00 3 64 0.16 300 2 95 0.00 2 103 0.16 2 127 0.00 2 129 0.16 600 1 191 0.00 1 207 0.16 1 2[...]

Rev. 5.00, 09/0 3, page 450 of 760 Table 14.5 B it Rates a nd SCBRR Settings in Synchron ous Mode P φ φ φ φ (MHz) 4 8 16 28.7 30 Bit Rate (bits/s) n N n N n N n N n N 1 1 0 ————— — — — — — 250 2 249 3 124 3 249 — — — — 500 2 124 2 249 3 124 3 223 3 233 1k 1 249 2 124 2 249 3 111 3 116 2.5k 1 99 1 199 2 99 2 178 2 187[...]

Rev. 5.00, 09/03, pa ge 451 of 760 Table 14.6 indicates t h e maximum bit rate s in asynchron ous mode when the baud rate gene rat or is used. Tables 1 4.7 and 14.8 list the ma ximum rates for external cloc k input. Table 14. 6 M aximum Bit Ra tes for Va rious Frequencies w ith Baud Rat e Generator (Asynchrono us Mo de) Settings P φ φ φ φ (MHz)[...]

Rev. 5.00, 09/0 3, page 452 of 760 Table 14. 7 M a ximum Bit Rate s w ith External Clo ck Input (As ynchronous M ode) P φ φ φ φ (MHz) External I nput Clock ( MHz) Maximum Bit Rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 8 2.0000 125000 9.8304 2.4576 [...]

Rev. 5.00, 09/03, pa ge 453 of 760 14.3 Operation 14.3.1 Overvie w For serial comm unication, the SCI has an asynchronous mode in which characters are synch ro nized indi vidually, an d a synchron ous mode in whi ch communicat ion is synchron ized wi th clock pu lses. A synchronous /synchron ous mode and th e transmissio n format are selected in t [...]

Rev. 5.00, 09/0 3, page 454 of 760 Table 14.9 Serial M ode Register Sett ings and SCI C ommunication Fo rmats SCSMR Settings SCI Communication Format Bit 7 C/ A A A A Bit 6 CHR Bit 5 PE Bit 2 MP Bit 3 STOP Mode Data Length Parity Bit Multipro- cessor Bit Stop Bit Length 0 0 0 0 0 Asynchronou s 8-bit Not set Not set 1 bit 12 b i t s 10 S e t 1 b i t[...]

Rev. 5.00, 09/03, pa ge 455 of 760 14.3.2 Operation i n Asynch ronous Mode In asynchronous m ode, each transmitted or received character beg i n s with a start bit and ends with a stop bit. Ser ial communication i s synchronized one character at a time. The transmitting and receiving sections of th e SCI are independent, so full duplex co mmuni cat[...]

Rev. 5.00, 09/0 3, page 456 of 760 Transmit/Receive Formats: Table 14.11 lists the 12 commun ication for mats that can be selected in asynchronous mode. The for mat is selected by settings in the serial mode register (SCSMR). Table 14.11 Serial Communi c ati on Form ats (Asynchronous Mode) SCSMR Bits Serial Transmit/Receiv e Format and Frame Length[...]

Rev. 5.00, 09/03, pa ge 457 of 760 When the SCI o perates on an inter nal clock, it can o utput a clock signal at the SCK pin. The frequen cy of this outpu t cloc k is equal to the bit rate. The phase is aligned as in figure 14.6 so that the rising edge of the clock occ urs at the center of each transmit data bit. 0 D 0D 1D 2D 3D 4 D 5 D 6 D 7 0 / [...]

Rev. 5.00, 09/0 3, page 458 of 760 Initialization Clear TE and RE bits in SCSCR to 0 Select communication format in SCSMR Set value in SCBRR Set CKE1 and CKE0 bits in SCSCR (TE and RE bits are 0) Wait Set TE and RE bits in SCSCR to 1 and set RIE, TIE, TEIE, and MPIE bits Has a 1-bit interval elapsed? End No Yes (1) (2) (3) (4) Note: Numbers in pare[...]

Rev. 5.00, 09/03, pa ge 459 of 760 TDRE = 1? Write transmit data to SCTDR and clear TDRE bit in SCSSR to 0 All data transmitted? Yes TEND = 1? Read TEND bit in SCSSR Break output? Yes Clear TE bit in SCSCR to 0 End of transmission Yes Read TDRE bit in SCSSR No No Yes No No (1) (2) (3) Start of transmission Set SCPDR and SCPCR Note: Numbers in paren[...]

Rev. 5.00, 09/0 3, page 460 of 760 In transmitting serial d ata, the SCI operates as follo ws: 1. T he SCI monitors the T DRE bit in SCS SR. When TDR E is cleared t o 0, the SCI recognizes that t he tra nsmi t dat a regi ster (SC TDR ) con t ains new d ata, and loads this data from SCTDR into the transmit shi ft register ( SC TSR). 2. After load in[...]

Rev. 5.00, 09/03, pa ge 461 of 760 Figure 14.9 s hows an ex ample of SCI transm it operation in asynch ronous mode. 01 1 1 0/1 0 1 TDRE TEND Parity bit Parity bit Serial data Start bit Data Stop bit Start bit Data Stop bit Idle (mark) state TXI interrupt request generated TEI interrupt request generated TXI interrupt handler writes data to SCTDR an[...]

Rev. 5.00, 09/0 3, page 462 of 760 Start of reception Read ORER, PER, and FER bits in SCSSR All data received? End of reception No Yes PER ∨ FER ∨ ORER = 1? RDRF = 1? Yes Yes Clear RE bit in SCSCR to 0 No No Read RDRF bit in SCSSR Error handling Read receive data from SCRDR and clear RDRF bit in SCSSR to 0 (1) (2) (3) Note: Numbers in parenthes[...]

Rev. 5.00, 09/03, pa ge 463 of 760 Error handling ORER = 1? Overrun error handling FER = 1? Yes Break? No Framing error handling PER = 1? Yes Parity error handling Clear ORER, PER, and FER bits in SCSSR to 0 End No No No Yes Yes Clear RE bit in SCSCR to 0 Figure 14.10 Sample Flowchart for Receiving Serial Da ta ( cont)[...]

Rev. 5.00, 09/0 3, page 464 of 760 In receiving, the SCI operates as follows: 1. T he SCI monitors the c omm unication l ine. When it detects a start bit (0) , the SCI synchr oniz es internally and st arts receiving. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB. 3. T he parity bit and stop bit are received. After receiving[...]

Rev. 5.00, 09/03, pa ge 465 of 760 Figure 14 .11 sho ws an example of SCI receive operat ion in asynch r onous m ode. RDRF FER ERI interrupt request generated by framing error 1 frame RXI interrupt handler reads data and clears RDRF bit to 0 RXI interrupt request generated 01 1 1 0/1 0 1 Parity bit Parity bit Serial data Start bit Data Stop bit Sta[...]

Rev. 5.00, 09/0 3, page 466 of 760 Receiving station A (ID = 01) (ID = 02) (ID = 03) (ID = 04) Receiving station B Receiving station C Serial communication line H'01 H'AA (MPB = 0) (MPB = 1) ID transmit cycle: specifies receiving station Serial data Transmitting station Receiving station D Data transmit cycle: data transmission to receivi[...]

Rev. 5.00, 09/03, pa ge 467 of 760 TDRE = 1? Write transmit data to SCTDR and set MPBT bit in SCSSR Transmission ended? Yes TEND = 1? Read TEND bit in SCSSR Clear TDRE bit to 0 Break output? Yes Clear TE bit SCSCR to 0 End of transmission Yes Read TDRE bit in SCSSR No No Yes No No (1) (2) (3) Start of transmission Set SCPDR and SCPCR Note: Numbers [...]

Rev. 5.00, 09/0 3, page 468 of 760 In transmitting serial d ata, the SCI operates as follo ws: 1. T he SCI monitors t he TDRE b it in SCSSR. When TDRE is cleare d to 0 the SCI recognizes that t he tr a nsmi t da ta re gister (SC T DR) c onta ins n ew dat a, an d tra nsfe rs th is d ata fr om SC TDR into the transmit shi ft register ( SC TSR). 2. Af[...]

Rev. 5.00, 09/03, pa ge 469 of 760 Receiving Multiprocessor Serial Data: Fig ure 14.15 shows a sam ple flowchart for receiving multiprocessor serial data. The pr ocedure for receiv ing multiprocessor serial data is: 1. ID receive cycle: Set the MPIE bit in the serial control register (SCSCR) to 1. 2. SCI status check and compare to ID reception: Re[...]

Rev. 5.00, 09/0 3, page 470 of 760 RDRF = 1? FER = 1 or ORER = 1? RDRF = 1? All data received? No End of reception Yes Set MPIE bit in SCSCR to 1 Read RDRF bit in SCSSR Clear RE bit in SCSCR to 0 No No Read ORER and FER bits in SCSSR FER = 1 or ORER = 1? Read RDRF bit in SCSSR Read receive data from SCRDR Is ID the station's ID? Yes Read ORER [...]

Rev. 5.00, 09/03, pa ge 471 of 760 ORER = 1? Break? Yes Framing error handling Yes Error handling Overrun error handling Yes FER = 1? Clear ORER and FER bits in SCSSR to 0 End No No No Clear RE bit in SCSCR to 0 Figure 14.15 Sample Fl owcha r t for Receiving Multiprocessor Serial D ata ( cont)[...]

Rev. 5.00, 09/0 3, page 472 of 760 Figure 14.16 show s an example of SCI receive operation using a multiprocessor format. RDRF MPIE RDR value ID1 RXI interrupt request (multiprocessor interrupt) generated, MPIE = 0 Example: Own ID does not match data RXI interrupt handler reads RDR data and clears RDRF bit to 0 ID is not station's ID, so MPIE [...]

Rev. 5.00, 09/03, pa ge 473 of 760 RDRF MPIE RDR value Example: Own ID matches data ID1 ID2 Data2 01 1 1 10 1 MPB MPB Serial data Start bit Data (ID2) Data (Data 2) Stop bit Start bit Stop bit Idle (mark ) state D 0 D 1 D 7 D 0 D 1 D 7 0 RXI interrupt request (multiprocessor interrupt) generated, MPIE = 0 RXI interrupt handler reads RDR data and cl[...]

Rev. 5.00, 09/0 3, page 474 of 760 14.3.4 Synch ron ou s Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for hi g h-speed serial communicatio n. The SCI transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. The t[...]

Rev. 5.00, 09/03, pa ge 475 of 760 Clock: An in ter nal cl ock ge nera ted by the on-ch ip b au d ra te gene rat or or an ext ern a l cl ock i nput from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by th e C/ A bit in the serial mode re gister (SCSMR) and bits CKE1 and CKE0 in the serial control regist[...]

Rev. 5.00, 09/0 3, page 476 of 760 Initialization Clear TE and RE bits in SCSCR to 0 (1) Has a 1-bit period elapsed? Set TE and RE bits in SCSCR to 1 and set RIE, TIE, TEIE, and MPIE bits Set transmit/receive format in SCSMR Yes No Set value in SCBRR Set RIE, TIE, TEIE, MPIE, CKE1, and CKE0 bits in SCSCR (TE and RE are 0) End Wait (2) (3) (4) Note:[...]

Rev. 5.00, 09/03, pa ge 477 of 760 Start of transmission Read TDRE bit in SCSSR All data transmitted? Yes No End of transmission (1) (2) TDRE = 1? Write transmit data to SCTDR and clear TDRE bit in SCSSR to 0 Yes No Read TEND bit in SCSSR TEND = 1? Yes No Clear TE bit in SCSCR to 0 Note: Numbers in parentheses refer to steps in the preceding proced[...]

Rev. 5.00, 09/0 3, page 478 of 760 In transmitting serial d ata, the SCI operates as follo ws: 1. T he SCI monitors t he TDRE b it in SCSSR. When TDRE is cleare d to 0 the SCI recognizes that t he tra nsmi t dat a regi ster (SC TDR ) con t ains new da ta and l oad s thi s data f rom S CTDR into the transmit shi ft register ( SC TSR). 2. After load [...]

Rev. 5.00, 09/03, pa ge 479 of 760 Receiving Serial Data (Synchronous Mode): Fig ure 14.21 sh ows a s ample flowchart for receiving s e rial data. When sw itching from asynchronous mode to synch ronou s mode, ma k e sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and both trans mitting and rece[...]

Rev. 5.00, 09/0 3, page 480 of 760 Read ORER bit in SCSSR All data received? End of reception No Yes ORER = 1? RDRF = 1? Yes Clear RE bit in SCSCR to 0 No No Read RDRF bit in SCSSR (3) (2) Yes Error handling (1) Read receive data from SCRDR and clear RDRF bit in SCSSR to 0 Start of reception Note: Numbers in parentheses refer to steps in the preced[...]

Rev. 5.00, 09/03, pa ge 481 of 760 Error handling End ORER = 1? No Clear ORER bit in SCSSR to 0 Yes Overrun error handling Figure 14.21 Sample Flowcha r t for Receiving Serial Da ta (cont ) In receiving, the SCI operates as follows: 1. T he SCI s ynchronizes with serial cloc k input or output and in itializes i nternally. 2. Receive data is shifted[...]

Rev. 5.00, 09/0 3, page 482 of 760 Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Serial clock Serial data Transfer direction Bit 7 RXI interrupt handler reads data and clears RDRF bit to 0 1 frame RXI interrupt request generated RXI interrupt request generated ERI interrupt request generated by overrun error RDRF ORER Figure 14.22 Example of S CI Receive Ope[...]

Rev. 5.00, 09/03, pa ge 483 of 760 Start of transmission/reception Read TDRE bit in SCSSR All data transmitted/received? End of transmission/reception (1) No Yes TDRE = 1? Write transmit data to SCTDR and clear TDRE bit in SCSSR to 0 RDRF = 1? No Yes Yes No Read ORER bit in SCSSR Error processing (2) ORER = 1? No Read RDRF bit in SCSSR (4) Yes (3) [...]

Rev. 5.00, 09/0 3, page 484 of 760 14.4 SCI Interrupts The SCI has four interru pt sources transmit-end (TEI), receive-error (ERI), receive -data-full (RXI), and transmit-data-empty (TXI). Table 14.13 lists the interrupt sources an d indicates their priority . These interrupts can be enabled and d isabled by the TIE, RIE, and TEIE bits in the seria[...]

Rev. 5.00, 09/03, pa ge 485 of 760 14.5 Usage Notes Note the following points when using the SCI. SCTDR Writin g and TDR E Flag: T he TDRE b it in the serial status register ( SCSSR) is a status flag indicating load ing of transmit data from SCT DR into S CTSR. T he SCI sets TDRE to 1 when it transfers data fr om SC TDR to SC TSR. Data can be writt[...]

Rev. 5.00, 09/0 3, page 486 of 760 TEND F l a g and TE Bit P rocessing : The T E ND flag is set to 1 during transmissio n of the stop bit of the last data. Consequently, if the TE bit is cleared to 0 i mmediat el y after set ting of the TEND flag has been con firmed, the stop b it will be in the process of transmis sion and will not be transmitted [...]

Rev. 5.00, 09/03, pa ge 487 of 760 The r eceive margin in a sync hrono us mode can therefor e be expres sed as in equa tion 1. Equa tio n 1: M = 0.5 − 1 2N D − 0.5 N − (L − 0.5)F − (1 + F) × 100% Where: M = Receive margin ( % ) N = Ratio of c lock fr equency t o bit rat e (N = 16) D = Clock duty cy cl e (D = 0 to 1.0) L = Fra me length ([...]

Rev. 5.00, 09/0 3, page 488 of 760[...]

Rev. 5.00, 09/03, pa ge 489 of 760 Section 15 Smart Card Interface 15.1 Overview As an added serial communications interf ace function, the SCI supports an IC card (sma rt card) interface that conf orms to the data transf er protocol (asynchron ous half-duplex character transm ission protocol) of the ISO/IEC7816- 3 (Identif ication C ard) standard.[...]

Rev. 5.00, 09/0 3, page 490 of 760 15.1.2 Block D iagram Figure 15.1 show s a block diagram of the smart card interface. RxD TxD SCK SCI SCBRR SCSCR SCSMR SCTDR SCTSR SCRDR SCRSR SCSCMR SCSSR Parity generation Parity check Clock External clock Module data bus Internal data bus P φ P φ /4 P φ /16 P φ /64 TXI RXI ERI Bus interface Baud rate gener[...]

Rev. 5.00, 09/03, pa ge 491 of 760 15.1.3 Pin C onfigurati on Table 15.1 summarizes the smart card interf ace pins. Table 15.1 Smart Card Interface Pins Pin Name Abbreviation I/O Function Serial clock pin SCK0 O utput Clock output Receive d ata pin Rx D0 Input Receive data inp ut Transmit data pin TxD 0 Output Transmit data out put 15.1.4 Smart Car[...]

Rev. 5.00, 09/0 3, page 492 of 760 15.2 Register Descriptions This section describes the registers added for t he smart card interf ace and th e bits w ho se f unc tions are changed. 15.2.1 S m art Card M ode Register (SCSCM R) The s mart car d mode re gister (SCSCMR) is an 8-bit r eadable/ writable register th at selects sm art card interface fun [...]

Rev. 5.00, 09/03, pa ge 493 of 760 Bit 0—Sm art Card Interface Mod e Select ( SMIF): Enables the smart card interface function. Bit 0 : SMIF Descr iption 0 Smart card interface funct ion dis abl ed (Initial value) 1 Smart card interface funct ion enab led 15.2.2 Serial S tatus Regis ter (SCSSR) In smart card interface mode, the function of SCSSR [...]

Rev. 5.00, 09/0 3, page 494 of 760 Bits 3 to 0: These bits h ave the same function as in the ordin ary SCI. See section 14, Serial Communication Interface (SCI), for more information. The setting conditions for bit 2, the transmit end bit (TEND), are changed as follows. Bit 2: TEND Description 0 Transmissi on is in progress [Clearing c ondition] Cl[...]

Rev. 5.00, 09/03, pa ge 495 of 760 15.3.2 Pin Con n ections Figure 15.2 shows the pin connection diag ram for the smart card interface. During communi cation with an IC card, transmission and reception are bo th carried out over the same data transfer line, so connect the TxD and Rx D pins on the chip. Pull up the data transfer lin e to the power s[...]

Rev. 5.00, 09/0 3, page 496 of 760 15.3.3 Data Form at Figure 15.3 show s the data form at for the smart card interface. In this mode, parity is checked every f ra me whi le receiv ing and error sign als se nt to the transmitti ng side whenever an error is detected so th at data can be re -transm itted. During transmissio n, error signa ls are sa m[...]

Rev. 5.00, 09/03, pa ge 497 of 760 5. The transmitting side transmits the next frame of data un less it receives an error signal. If it does receive an error signal, it returns to step 2 to re-tr an s mit the erroneous data. 15.3.4 Register S ettings Tab le 15 .3 sho ws the bit map of the r egisters that the sma rt ca r d interface uses . Bits sh o[...]

Rev. 5.00, 09/0 3, page 498 of 760 In the inver se c onventi on type, the l ogical 1 level is sta te A, the logical 0 l evel is state Z, and communication is MSB first. The start character data is H'3F. Parity is even (from the smart card standard), an d so the pari ty bi t is 0, which corresponds to state Z. Only dat a bits D 7–D0 are inv e[...]

Rev. 5.00, 09/03, pa ge 499 of 760 Table 15.4 Rela tionship of n to CK S1 and CKS 0 n CKS1 CKS0 000 101 210 311 Table 15.5 Examples of Bit Rate B (Bits/s) f or SCBRR Settings (n = = = = 0) P φ φ φ φ (MHz) N 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 0 9600.0 13440.9 14400.0 17473 .1 19200.0 21505 .4 24193.5 1 4800.0 6720.4 7200.0 8736.6 960[...]

Rev. 5.00, 09/0 3, page 500 of 760 Table 15.7 Maximum Bit Rates for Frequencies (Smart Card Interface Mode) P φ φ φ φ (MHz) Maximum Bit R ate (Bits/s) N n 7.1424 9600 0 0 10.00 13441 0 0 10.7136 14400 0 0 13.00 17473 0 0 14.2848 19200 0 0 16.00 21505 0 0 18.00 24194 0 0 The bit rate e rror is found as follows: Error (%) = ( × 10 6 − 1) × 10[...]

Rev. 5.00, 09/03, pa ge 501 of 760 15.3.6 Data Transmission and Reception Initializatio n: Initialize the SCI usin g the follo wing procedure before sending or receiving data. Initialization is also required for switching f rom transmit mode to receive mode or fro m receive mode to transmit mode. Fi gure 15.5 sho ws a flowchart of the initializatio[...]

Rev. 5.00, 09/0 3, page 502 of 760 Initialization Clear TE and RE bits in SCSCR to 0 Set value in SCBRR Clear FER/ERS, PER and ORER flags in SCSSR to 0 Wait Set TIE, RIE, TE, and RE bits in SCSCR Has a 1-bit interval elapsed? End (2) Set parity in O/ E bit, set clock in CKS1 and CKS0 bits, and set C/ A , in SCSMR (3) Set clock in CKE1 and CKE0 bits[...]

Rev. 5.00, 09/03, pa ge 503 of 760 Serial Data T r ansmi ssion: The processi ng procedu res in the smart card m ode differ f rom ordinary SCI pro cessing because data is retransmitted when an error signal is sampled during a data transmiss ion. This resu lts in the tr ansmissio n processing flo wchart shown in figure 15 .6. 1. Initialize the smart [...]

Rev. 5.00, 09/0 3, page 504 of 760 Start End of transmission Start of transmission Initialize Write transmit data in SCTDR and clear TDRE flag in SCSSR to 0 (1) Clear TE bit in SCSCR to 0 (6) Error handling (2) FER/ERS = 0? TEND = 1? Yes Yes Yes Yes No No All data transmitted? No TEND = 1? No Error handling FER/ERS = 0? Yes No (4) (5) (3) Note: Num[...]

Rev. 5.00, 09/03, pa ge 505 of 760 Serial Data Reception: The processing procedu res in smart card m ode are the same as in ordinary SCI processing. The reception processi n g flowchart is shown i n figure 15.7. 1. Initialize the smart card interf ace mode as described above i n I nitialization and in f igure 15.5. 2. Chec k that the ORER and PER f[...]

Rev. 5.00, 09/0 3, page 506 of 760 Start End of reception Start of reception Initialize Write receive data from SCRDR and clear RDRF flag in SCSSR to 0 (1) Clear RE bit in SCSCR to 0 (6) Error handling (2) ORER = 0 or PER = 0? RDRF = 1? Yes Yes Yes No No All data received? No (4) (5) (3) Note: Numbers in parentheses refer to steps in the preceding [...]

Rev. 5.00, 09/03, pa ge 507 of 760 Switching Mo des: W hen sw itching from receive mode to transmit mode, check that the receive operation is completed before starting initializati on, clearing RE to 0, and setting TE to 1. The RDRF, PER, and ORER flags can be used to chec k if reception is completed. When switching from transmit mode to receiv e m[...]

Rev. 5.00, 09/0 3, page 508 of 760 0 185 371 0 185 371 0 Base clock Receive data (RxD) Synchro- nization sampling timing Data sampling timing 186 clock cycles 372 clock cycles Start bit D0 D1 Figure 15.8 Receive Data Sampling Timing i n Sm art C ard Mode The receive m argin is f ound from the following equation: For smart card m ode: M = (0.5 − )[...]

Rev. 5.00, 09/03, pa ge 509 of 760 15.4.2 Retransmission (Receive and Transmit Modes) Retransmission w hen SCI is in Receive Mode: Figure 15.9 s hows t he retransmi ssion operation in the SCI receive m ode. 1. When the received parity bit is checked and an error is found, the PER bit in SCSSR is automatical ly set to 1. If the RIE bi t in SCSCR is [...]

Rev. 5.00, 09/0 3, page 510 of 760 Retrans mission whe n SCI is in Tr ansmit Mode: Figure 15 . 10 shows the retrans mission operatio n in the SCI transmit mode. 1. After transmis sion of o ne frame is completed, the FER/ERS bit in SCSSR is set to 1 when a error sig nal is retu rned fr o m the r ecei ving side. If the RIE bit in SCSCR is enable d at[...]

Rev. 5.00, 09/03, pa ge 511 of 760 Section 16 Serial Communicati on Interface with FIFO (SCIF) 16.1 Overview The SH7709S has a two-chann el serial co mmuni cation interface with FIFO (SCIF ) that supports asynchronous serial co mmuni cation. It also has 16-stage FIFO registers for both transmission and reception th at enable the SH7709S to per form[...]

Rev. 5.00, 09/0 3, page 512 of 760 16.1.2 Block D iagram Figure 16.1 s hows a block diagram of the SCIF . RxD TxD SCK SCIF SCBRR SCSSR2 SCSCR2 SCFTDR2 SCTSR SCFRDR2 (16 (16 stages) stages) SCRSR SCSMR2 SCFDR2 SCFCR2 SCPCR SCFDR Parity generation Parity check Clock External clock Module data bus Internal data bu s P φ P φ /4 P φ /16 P φ /64 TXI [...]

Rev. 5.00, 09/03, pa ge 513 of 760 Figures 16.2 to 1 6.4 s how the SCIF I/ O port pi ns. SCIF pin I/O and data c ontrol is perf ormed by bits 11 to 8 of S CPCR and bit s 5 and 4 o f SCP DR. For det ails , see sect ion 14.2.8, SC Port C ontrol Reg ist er (S CPCR)/SC Port Data R e gister (SCPDR). Internal data bus Output enable Clock input enable SCI[...]

Rev. 5.00, 09/0 3, page 514 of 760 Internal data bus Output enable SCIF Serial transmission output R SCP4MD0 PCRW Reset C Q Q D R SCP4MD1 PCRW Reset C Q D R SCP4DT1 PDRW Reset SCPT[4]/TxD2 C D PCRW: PDRW: SCPCR write SCPDR write Legend Figure 16.3 SCPT[4]/T xD2 Pin[...]

Rev. 5.00, 09/03, pa ge 515 of 760 SCIF Internal data bus PDRR * Serial receive data SCPT[4]/RxD2 PDRR: SCPDR read Legend Note: * When reading the RxD2 pin, set the RE bit in SCSCR to 1. Figure 16.4 SCP T[4]/RxD2 Pin 16.1.3 Pin C onfigurati on The SCIF has the serial pins summarized in table 16.1. Table 16.1 SCIF Pins Pin Name Abbrev iation I/O Fun[...]

Rev. 5.00, 09/0 3, page 516 of 760 16.1.4 Register C onfiguration Table 16.2 summarizes the SCIF internal registers. These reg isters specify the data fo rmat and bit rate, and control the transmitter and receiver sect ions. Table 16.2 SCIF Regis ters Register Name Abbreviation R/W Initial V alue Address A ccess size Serial mode register 2 SCSMR 2 [...]

Rev. 5.00, 09/03, pa ge 517 of 760 16.2 Register Descriptions 16.2.1 Receive Shift Register (SCRSR) The receive shift register (SCRSR) receives serial data. Data input at the Rx D pin is loaded into SCRSR in the ord er received, LSB (bit 0) first, convertin g t he data to parallel form. When one byte has been received, it is automatically transferr[...]

Rev. 5.00, 09/0 3, page 518 of 760 16.2.4 Transm it F IFO Data Register (SCFT DR) The trans mit FIFO d ata regis ter (SCFTDR) is a FIFO register c omprising sixteen 8 -bit stag es that stores d ata fo r se rial t ransm issi on. When the SC IF d etects that the tra nsmit s hift regist er (SCT SR) is empty, it moves tra nsmit data written in the S CF[...]

Rev. 5.00, 09/03, pa ge 519 of 760 Bit 5—Parit y Enable (PE): Selects wh e ther t o ad d a p a r ity bit to t ransm i t d a ta an d to check the parity of receiv e data. Bit 5: PE Description 0 Parity bit not added or ch ecked (Initial valu e) 1 Parity bit added a nd checked * Note: * When PE is set to 1, an even or odd par ity bit is added t o t[...]

Rev. 5.00, 09/0 3, page 520 of 760 Bits 1 and 0 —Clock Select 1 and 0 (CKS1, CKS0): Select the internal clock source of the on- chip baud rate generator. According to the setting of the CKS1 and CKS0 bi ts four clock sources are available. P φ , P φ /4, P φ /16 and P φ /64 . For further information on the clock source, bit rate register s ett[...]

Rev. 5.00, 09/03, pa ge 521 of 760 Bit 6—Receive Interrupt Enable (RIE): En ables or disables the receive-data-f ull (RXI) and receive-error ( ERI) interrupts reque sted when serial receive data is transferred from the receive shift register (SCRSR) to the receive FIFO data registe r (S CFRDR), whe n the quantity of data in the receive FIFO regis[...]

Rev. 5.00, 09/0 3, page 522 of 760 Bits 1 and 0—Cloc k Enable 1 and 0 (CKE1, CKE0): Select the SCIF clock source and enable or disable clock outp ut from the SCK pin. Depending on t he combination of CKE1 and CKE0, the SCK pin can be u s ed for serial clock ou tput or serial clock input. The CKE 0 settin g is valid only when the SC IF is operati [...]

Rev. 5.00, 09/03, pa ge 523 of 760 Bit 7—Receive Error (ER): Indicates the occurren ce of a f raming error, or of a parity error w hen receiving data that includes parity . Bit 7: ER Description 0 Receiving i s in progr ess or has end ed normally * 1 (Initial valu e) [Clearing c onditions] (1) By a power-on reset or in standby m ode ER is cleared[...]

Rev. 5.00, 09/0 3, page 524 of 760 Bit 5—Tr ansmi t FIFO Data Em pty (TD FE): In dicates that data has been transf erred f rom the transmit FIFO data register (SCFTDR) to the transmit s hift register (SCTSR), the quantity of data in SCFTDR ha s become less tha n the trans mission trig ger number specified by the T TRG1 and TTRG0 bits in the FIFO [...]

Rev. 5.00, 09/03, pa ge 525 of 760 Bit 3—Fram ing Error (FER): Indicates a framing error in the data read from the receive FIFO data r e gister (SCFRDR) . Bit 3: FER Description 0 No receive framin g error occurred in the data read fr o m SCFRDR (Initial value) [Clearing c onditions] (1) W hen the chip undergoes a power- on reset or ent ers stand[...]

Rev. 5.00, 09/0 3, page 526 of 760 Bit 1—Receive FIFO Data Full (RDF): In dicates that receive data h as been transf erred to the receive FIFO data r egis ter (SCFRDR) , an d the quant ity o f data in SCFRDR has be c ome greater than the receive trigger number specified by the RTRG1 and RT RG0 bits in the FIFO control regist er (SCFCR). Bit 1: RD[...]

Rev. 5.00, 09/03, pa ge 527 of 760 Upper 8 bit s: 15 14 13 12 11 10 9 8 PER3 PER2 PER1 PER0 FER3 FER2 FER1 FER0 I n i t i a l v a l u e : 00000000 R / W : RRRRRRRR Bits 15 t o 12—Number of Parity Errors 3 to 0 (P ER3 to PER0): Indicate the quantity of data including a parity error in the receiv e data stored in the receive FIFO data register (SCF[...]

Rev. 5.00, 09/0 3, page 528 of 760 Table 16.3 SCSM R Setting s SCSMR Settings n Clock Source CKS1 CKS0 0P φ 00 1P φ /4 0 1 2P φ /16 1 0 3P φ /64 1 1 Note: The bit rate error is given by the foll owing formu la: Error (%) = P φ × 10 6 − 1 × 100 (N+1) × 64 × 2 2n − 1 × B Table 16.4 lists examples of SCBRR s e t ting s. Table 16.4 B it R[...]

Rev. 5.00, 09/03, pa ge 529 of 760 P φ φ φ φ (MHz) 3 3.6864 4 Bit Rate (bits/s) n N Error ( % % % % ) n N Error ( % % % % ) n N Error ( % % % % ) 110 1 212 0.03 2 64 0.70 2 70 0.03 150 1 155 0.16 1 191 0.00 1 207 0.16 300 1 77 0.16 1 95 0.00 1 103 0.16 600 0 155 0.16 0 191 0.00 0 207 0.16 1200 0 77 0.16 0 95 0.00 0 103 0.16 2400 0 38 0.16 0 47 [...]

Rev. 5.00, 09/0 3, page 530 of 760 P φ φ φ φ (MHz) 6.144 7.3728 8 Bit Rate (bits/s) n N Error ( % % % % ) n N Error ( % % % % ) n N Error ( % % % % ) 110 2 108 0.08 2 130 –0.07 2 141 0.03 150 2 79 0.00 2 95 0.00 2 103 0.16 300 1 159 0.00 1 191 0.00 1 207 0.16 600 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 79 0[...]

Rev. 5.00, 09/03, pa ge 531 of 760 P φ φ φ φ (MHz) 14.7456 16 19.6608 20 Bit Rate (bits/s) n N Error ( % % % % )n N Error ( % % % % )n N Error ( % % % % )n N Error ( % % % % ) 110 3 64 0.70 3 70 0.03 3 86 0.31 3 88 –0.25 150 2 191 0.00 2 207 0.16 2 255 0.00 2 64 0.16 300 2 95 0.00 2 103 0.16 2 127 0.00 2 129 0.16 600 1 191 0.00 1 207 0.16 1 2[...]

Rev. 5.00, 09/0 3, page 532 of 760 Table 16.5 indicates t h e maximum bit rate s in asynchron ous mode when the baud rate gene rat or is used. Ta ble 16. 6 list the maximum r ates fo r exte rnal c lo ck input. Table 16. 5 M aximum Bit Ra tes for Va rious Frequencies w ith Baud Rat e Generator (Asynchrono us Mo de) Settings P φ φ φ φ (MHz) Maxim[...]

Rev. 5.00, 09/03, pa ge 533 of 760 Table 16. 6 M a ximum Bit Rate s w ith External Clo ck Input (As ynchronous M ode) P φ φ φ φ (MHz) External I nput Clock ( MHz) Maximum Bit Rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 8 2.0000 125000 9.8304 2.4576 [...]

Rev. 5.00, 09/0 3, page 534 of 760 16.2.9 FIFO Contro l Register (SCFCR) B i t : 76543210 RTRG1 RTRG0 TTRG1 TTRG0 MCE TFRST RFRST LOOP I n i t i a l v a l u e : 00000000 R/W: R/W R/ W R/W R/ W R/W R/ W R/W R/W The FIFO control register (S CFCR) resets the quantity of data in the transmit and receiv e FIFO regist ers, sets the t rigger data qu antit[...]

Rev. 5.00, 09/03, pa ge 535 of 760 Bit 3—Modem Control Enable (MCE): Enables m ode m cont rol signals C TS and R TS. Bit 3: MCE Description 0 Modem signal disabled * (Initial valu e) 1 Modem signal enabled Note: * CTS is fi xed at active 0 re gardless of the inp ut value, and RTS is also fixed at 0. Bit 2—Transm it FIFO Data Register Reset (T F[...]

Rev. 5.00, 09/0 3, page 536 of 760 16.2.10 FIFO Data Count Reg ister (SCFDR) SCFDR is a 16-bit reg ister which indicates the quantity of data stored in the trans mit FIFO data register (SCF TDR) and the receive FIFO data register (SCFRDR) . It indi cat es the quant it y of transmit d ata in SC FT DR with the up p er 8 bits, and th e quant i ty of r[...]

Rev. 5.00, 09/03, pa ge 537 of 760 16.3 Operation 16.3.1 Overvie w For serial communication , the SCIF has an asynch ronous mode in which characters are synch ronized indivi dually. Refer t o section 14.3.2, Operation in A s ynchronous Mode. The SC IF has a 16- b yte FIFO buffer f or both transm it and receive operations, redu cing the ov erhead of[...]

Rev. 5.00, 09/0 3, page 538 of 760 Table 16.8 SCSCR Setting s and SCIF Clock Source Selection SCSCR Settings SCIF Trans mit/R eceive C loc k Mode Bit 1 CKE1 Bit 0 CKE0 Clock Source SCK Pin Function 0 0 Internal SCIF does not us e the SCK pin 1 Outputs a c lock w ith a frequ ency 1 6 times the bit rate 1 0 External Asynchronou s mode 1 Inputs a cloc[...]

Rev. 5.00, 09/03, pa ge 539 of 760 Clock: An in ter nal cl ock ge nera ted by the on-ch ip b au d ra te gene rat or or an ext ern a l cl ock i nput from the SCK pin can be selected as the SCIF transmit/receive clock. T he clock source is selected by bi ts CKE1 an d CKE0 in the serial control register (S CSCR) (table 16.8). When an external clock is[...]

Rev. 5.00, 09/0 3, page 540 of 760 Initialization Clear TE and RE bits in SCSCR to 0 Set TFRST and RFRST bits in SCFCR to 1 1-bit interval elapsed? Set RTRG1-0, TTRG1-0, and MCE in SCFCR Clear TFRST and RFRST bits to 0 Set TE and RE bits in SCSCR to 1,and set RIE, TIE, TEIE, and MPIE bits Set communication format in SCSMR Yes No Set value in SCBRR [...]

Rev. 5.00, 09/03, pa ge 541 of 760 • Serial data tr ansmission Figure 16. 6 shows a sample flo wchart fo r seri al tra nsmis si on. Use the following procedure for ser ial data transmission after enabli ng the SCIF for transmission. 1. SCIF sta tus check and transmit data write: Read serial status reg ister (SCSSR ) and che ck th at the TD FE fla[...]

Rev. 5.00, 09/0 3, page 542 of 760 Start of transmission Read TDFE bit in SCSSR TEND= 1? Read TEND bit in SCSSR Clear TE bit in SCSCR to 0 Set SCPDR and SCPCR Yes No TDFE= 1? No All data transmitted? No Yes Yes Break output? Yes No Write transmit data (16 - transmit trigger set number) to SCFTDR, read 1 from TDFE bit and TEND flag in SCSSR, then cl[...]

Rev. 5.00, 09/03, pa ge 543 of 760 In serial transmi ssion, the SCIF operates as described below. 1. W hen data is writte n into the trans mit FIFO da ta register (SCF TDR), the SC IF tran sfe rs the data fro m SCFT DR to the transmit s hi ft register (SC TSR) and starts tr ansmitting. Confi rm that the TDFE flag in the serial status register (SCSS[...]

Rev. 5.00, 09/0 3, page 544 of 760 Figure 16.7 s hows an ex ample of th e operation f or transmission. 01 1 1 0/1 0 1 TDFE TEND Parity bit Parity bit Serial data Start bit Data Stop bit Start bit Data Stop bit Idle (mark ) state TXI interrupt request Data written to SCFTDR and TDFE flag read as 1 then cleared to 0 by TXI interrupt handler One frame[...]

Rev. 5.00, 09/03, pa ge 545 of 760 • Serial data recep tion Figures 16.9 and 16.10 s ho w a sample flowch art for serial reception. Use the following procedu re for serial data reception after enabling the SCIF for reception. 1. Receive error handling and break det ection: Read the DR, ER, and BRK flags in SCSSR to identify any error, perform the[...]

Rev. 5.00, 09/0 3, page 546 of 760 Start of reception Read ORER, PER, FER flags in SCSSR All data received? End of reception No Yes PER v FER v ORER = 1? RDF = 1? Yes Yes Clear RE bit in SCSCR to 0 No No Read RDF flag in SCSSR Error handling Read receive data from SCFRDR, and clear RDF flag in SCSSR to 0 (1) (2) (3) Note: Numbers in parentheses ref[...]

Rev. 5.00, 09/03, pa ge 547 of 760 1. Whether a framing error or parity error has occu rred in the receive data read f rom SCFRDR can be ascertained from the F ER and PER bits in SCS SR. 2. When a break signal is received, receive data is n ot tr ansferred to SCFRD R while the BRK flag is set. H owever, note that the last data in SCFRDR is H'0[...]

Rev. 5.00, 09/0 3, page 548 of 760 In serial reception, th e SCIF operates as des cribed below. 1. The SCIF m onitors th e tra nsmiss ion lin e, and if a 0 start bit is detected, per forms interna l synchronization and starts reception. 2. T he received data is stor ed in SCRSR in L SB-to-MSB o rder. 3. The parity bit and stop bit are receiv ed. Af[...]

Rev. 5.00, 09/03, pa ge 549 of 760 Figure 16.11 s hows an ex ample of the operation for reception. RDF FER ERI interrupt request generated by receive error One frame Data read and RDF flag read as 1 then cleared to 0 by RXI interrupt handler RXI interrupt request 01 1 1 0/1 0 1 Parity bit Parity bit Serial data Start bit Data Stop bit Start bit Dat[...]

Rev. 5.00, 09/0 3, page 550 of 760 16.4 SCIF Interrupts The SCIF has four interrupt sou rces: transmit-FIFO-data-empty ( TXI), receive-error (ERI), receive-data-full (R XI), and break (BRI). Table 16.10 sh ows th e interrupt s ources and th eir order of priority . T he inte rrupt sou rces are enabled or disabled b y means of the TIE and RIE bits i [...]

Rev. 5.00, 09/03, pa ge 551 of 760 16.5 Usage Notes Note the following when using the SCIF. 1. SCFTDR Writing an d TDFE Flag: The T DFE flag in the serial status register (SCSSR) is set when the number of trans mit data b ytes written in the tra nsmit FIFO data register ( SCFTDR) has fall en below th e transmit t rigger number set by bits TTRG1 and[...]

Rev. 5.00, 09/0 3, page 552 of 760 5. TEND Fl ag and TE Bit Proces sing: The TEND fl ag is set t o 1 during trans mission of the stop bit of the las t data. Consequ ently, if th e TE bit is cleared to 0 i mmediately after setting of the TEND flag has been confirmed, t he stop bit will be in the process of transmission and will not be transmitted no[...]

Rev. 5.00, 09/03, pa ge 553 of 760 Equa tio n 2: When D = 0.5 and F = 0: M = (0.5 – 1/(2 × 16)) × 100 % = 46.875 % This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.[...]

Rev. 5.00, 09/0 3, page 554 of 760[...]

Rev. 5.00, 09/03, pa ge 555 of 760 Section 17 IrDA 17.1 Overview The SH7709S has an on -chip Infrared Data Association (IrDA) interface which is based on the IrDA 1.0 sy stem and can perform infrared communication. It also can be us ed as the SCIF by making register set t ings . 17.1.1 Features • Conform s to the IrDA 1.0 syst em • Async hr o n[...]

Rev. 5.00, 09/0 3, page 556 of 760 17.1.2 Block D iagram Figure 17.1 s hows a block diagram of the IrDA. SCIF Clock input TxD Transfer clock RxD Switching IrDA/SCIF IrDA SCK TxD1 RxD1 Modulation unit Demodulation unit Legend SCIF: Serial communication interface with FIFO Figure 17.1 Bloc k Diagr am of IrDA[...]

Rev. 5.00, 09/03, pa ge 557 of 760 Figures 17.2 to 17 .4 sho w the IrDA I/ O port pin s. SCIF pin I/O a nd data control is performed by bits 7 to 4 of SCPCR and bit s 3 and 2 of SCPDR. For det ails , see sect ion 14.2.8, SC Port C ontrol Reg ist er (S CPCR)/SC Port Data R e gister (SCPDR). Internal data bus Output enable Clock input enable IrDA Ser[...]

Rev. 5.00, 09/0 3, page 558 of 760 Internal data bus Output enable IrDA Serial transfer output Q R SCP2DT1 PDRW Reset SCPT[2]/TxD1 C D PCRW: PDRW: Legend SCPCR write SCPDR write R SCP2MD0 PCRW Reset C Q D R SCP2MD1 PCRW Reset C QD Figure 17.3 SCPT[2]/T xD1 Pin[...]

Rev. 5.00, 09/03, pa ge 559 of 760 IrDA Serial receive data Internal data bus PDRR * SCPT[2]/RxD1 Legend PDRR: SCPDR read Note: * When reading the RxD1 pin, set the RE bit in SCSCR to 1. Figure 17.4 SCP T[2]/RxD1 Pin 17.1.3 Pin C onfigurati on The IrDA has the s erial pins summarized in table 17.1. Table 17.1 IrDA Pins Pin Name Signal Name I/O Func[...]

Rev. 5.00, 09/0 3, page 560 of 760 17.1.4 Register C onfiguration The IrDA has the internal registers shown in table 17.2. These registers select IrDA or SCIF mode, s pecify the data format and a bit rate, and con trol the transmit and receive units. Table 17.2 IrDA Registers Register Name Abbreviation R/W Initial V a lue Address Access Size Serial[...]

Rev. 5.00, 09/03, pa ge 561 of 760 17.2 Register Desc ription Specifications of the registers in the I rDA are the same as th ose in the SCIF except fo r the serial mode regis ter described below. Therefore, refer to section 16, Serial Communicatio n I nterface with FIFO ( SCIF), for details o f these regis ters. 17.2.1 Serial Mod e Register (S CSM[...]

Rev. 5.00, 09/0 3, page 562 of 760 Bits 6 to 3—Ir Clock Sel ect Bits (I CK3 to ICK0) Bit 2—Output Pul se Width Select (PSEL): PSEL selects an IrD A outpu t pulse width that is 3/ 16 of the bi t l ength for 115 kbps or 3/1 6 of t he bit len gth for th e selected baud rat e. The I r cl o ck selec t bit s shoul d be se t p roperly to fix the outpu[...]

Rev. 5.00, 09/03, pa ge 563 of 760 17.3 Operation Description The IrDA modu le can perform infrared communication conforming to IrDA 1.0 b y connecting infrared transmit/receive units. The serial co mmunication interface unit includes a 16-stage FIFO buffer in the transmit unit and the receive un it, allowing CPU overhead to be reduced and continuo[...]

Rev. 5.00, 09/0 3, page 564 of 760 17.3.3 Receiving Received 3/16 I R fra me bit-width pulses are demo dulated and co nverted to a UA RT fra me, as shown in fi gur e 17 .5 . Demodulation to 0 is perfor med for pulse o utput, and demodulation to 1 is per form ed for no pulse outpu t. UART frame Data IR frame Data Receive Transmit Stop bit Stop bit S[...]

Rev. 5.00, 09/03, pa ge 565 of 760 Section 18 Pin Function Controller 18.1 Overview The pin func tion co nt r oll er ( PFC) is c omposed of regist ers for sele c ting the fu nc tion of multiplexe d p ins and th e input/out put dir ection. The pin func tion and inpu t/output di rection can be selected for each pin individually without regard to the [...]

Rev. 5.00, 09/0 3, page 566 of 760 Port Port Function (Related Module) Other Function (Related Module) C PTC0 input/output (port)/PIN T0 input (INTC) MCS0 output (BSC) D PTD7 input/output (port) DACK1 output ( DMAC) D PTD6 input (port) DREQ1 input (DMAC) D PTD5 input/output (port) DACK0 output ( DMAC) D PTD4 input (port) DREQ0 input (DMAC) D PTD3 i[...]

Rev. 5.00, 09/03, pa ge 567 of 760 Port Port Function (Related Module) Other Function (Related Module) G PTG1 input (por t) AUDATA1 output (AUD) G PTG0 input (por t) AUDATA0 output (AUD) H PTH7 input/output (port) TCLK input/output (TM U ) H PTH6 input (port) AUDCK input (AUD) H PTH5 input (port) ADTRG input (ADC) H PTH4 input (port)/IRQ4 i nput (I[...]

Rev. 5.00, 09/0 3, page 568 of 760 Port Port Function (Related Module) Other Function (Related Module) L PTL4 input ( port) AN4 input (ADC ) L PTL3 input ( port) AN3 input (ADC ) L PTL2 input ( port) AN2 input (ADC ) L PTL1 input ( port) AN1 input (ADC ) L PTL0 input ( port) AN0 input (ADC ) SCPT SCPT7 input (port)/IRQ5 i nput (INTC) CTS2 input (UA[...]

Rev. 5.00, 09/03, pa ge 569 of 760 18.2 Register Conf iguration Table 18.2 sum marizes the registers of the pi n function control ler. Table 18.2 Pin Function Controller Registers Name Abbreviation R/W Initial Value Address A ccess Size Port A control reg ister PACR R/W H'0000 H'04000100 (H'A400010 0) * 16 Port B control reg ister PB[...]

Rev. 5.00, 09/0 3, page 570 of 760 18.3 Register Descriptions 18.3.1 Port A Contr ol Re gister (PACR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PA7 MD1 PA7 MD0 PA6 MD1 PA6 MD0 PA5 MD1 PA5 MD0 PA4 MD1 PA4 MD0 PA3 MD1 PA3 MD0 PA2 MD1 PA2 MD0 PA1 MD1 PA1 MD0 PA0 MD1 PA0 MD0 I n i t i a l v a l u e : 0 000 000000 000000 R/W : R/W R/W R/W R/W R/W R/W R[...]

Rev. 5.00, 09/03, pa ge 571 of 760 18.3.2 Port B Con trol Regis ter (PBCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PB7 MD1 PB7 MD0 PB6 MD1 PB6 MD0 PB5 MD1 PB5 MD0 PB4 MD1 PB4 MD0 PB3 MD1 PB3 MD0 PB2 MD1 PB2 MD0 PB1 MD1 PB1 MD0 PB0 MD1 PB0 MD0 I n i t i a l v a l u e : 0 000 000000 000000 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W [...]

Rev. 5.00, 09/0 3, page 572 of 760 18.3.3 Port C Control Regi ster (PCCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PC7 MD1 PC7 MD0 PC6 MD1 PC6 MD0 PC5 MD1 PC5 MD0 PC4 MD1 PC4 MD0 PC3 MD1 PC3 MD0 PC2 MD1 PC2 MD0 PC1 MD1 PC1 MD0 PC0 MD1 PC0 MD0 I n i t i a l v a l u e : 1 010 101010 101010 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R[...]

Rev. 5.00, 09/03, pa ge 573 of 760 18.3.4 Port D Control Regi ster (PDCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD7 MD1 PD7 MD0 PD6 MD1 PD6 MD0 PD5 MD1 PD5 MD0 PD4 MD1 PD4 MD0 PD3 MD1 PD3 MD0 PD2 MD1 PD2 MD0 PD1 MD1 PD1 MD0 PD0 MD1 PD0 MD0 I n i t i a l v a l u e : 1 010 101010 001010 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R[...]

Rev. 5.00, 09/0 3, page 574 of 760 18.3.5 Port E C ontrol Regis ter (PECR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PE7 MD1 PE7 MD0 PE6 MD1 PE6 MD0 PE5 MD1 PE5 MD0 PE4 MD1 PE4 MD0 PE3 MD1 PE3 MD0 PE2 MD1 PE2 MD0 PE1 MD1 PE1 MD0 PE0 MD1 PE0 MD0 I n i t i a l v a l u e : 1 / 0 010101010101 0 1 / 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W[...]

Rev. 5.00, 09/03, pa ge 575 of 760 18.3.6 Port F Control R egister (PFCR ) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PF7 MD1 PF7 MD0 PF6 MD1 PF6 MD0 PF5 MD1 PF5 MD0 PF4 MD1 PF4 MD0 PF3 MD1 PF3 MD0 PF2 MD1 PF2 MD0 PF1 MD1 PF1 MD0 PF0 MD1 PF0 MD0 I n i t i a l v a l u e : 1 / 0 0 1 / 0 0 1 / 0 0 1 / 0 010 101010 R/W : R/W R/W R/W R/W R/W R/W R/W R/W[...]

Rev. 5.00, 09/0 3, page 576 of 760 18.3.7 Port G Control Regis ter (PGCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PG7 MD1 PG7 MD0 PG6 MD1 PG6 MD0 PG5 MD1 PG5 MD0 PG4 MD1 PG4 MD0 PG3 MD1 PG3 MD0 PG2 MD1 PG2 MD0 PG1 MD1 PG1 MD0 PG0 MD1 PG0 MD0 I n i t i a l v a l u e : 1 0 1 01 / 00 1 01 / 00 1 / 001 / 001 / 00 R/W : R/W R/W R/W R/W R/W R/W R/W R/[...]

Rev. 5.00, 09/03, pa ge 577 of 760 Bit (2n + 1) Bit 2n PGnMD1 PGnMD0 Pin Function 0 0 Other function (n = 1–3, 5) (see table 18.1) (Initial valu e) ( ASEMD0 = 0) 0 1 Reserved 1 0 Port input (Pu ll-up M OS: on) (Initial valu e) ( ASEMD0 = 1) 1 1 Port input (Pu ll-up M OS: off) (n = 1 to 3, 5) Bit (2n + 1) Bit 2n PGnMD1 PGnMD0 Pin Function 0 0 Othe[...]

Rev. 5.00, 09/0 3, page 578 of 760 Bits 15 a nd 14—PH7 Mode 1, 0 (PH7MD1, PH 7MD0): These b its select the pin functions and perform i nput pu ll-up MOS con trol. Bit 15 Bit 14 PH7MD1 PH7MD0 Pin Function 0 0 Other function (see t able 18.1) 0 1 Port output 1 0 Port input (Pu ll-up M OS: on) (Initial valu e) 1 1 Port input (Pu ll-up M OS: off) Bit[...]

Rev. 5.00, 09/03, pa ge 579 of 760 18.3.9 Port J Contr ol Regis ter (PJCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PJ7 MD1 PJ7 MD0 PJ6 MD1 PJ6 MD0 PJ5 MD1 PJ5 MD0 PJ4 MD1 PJ4 MD0 PJ3 MD1 PJ3 MD0 PJ2 MD1 PJ2 MD0 PJ1 MD1 PJ1 MD0 PJ0 MD1 PJ0 MD0 I n i t i a l v a l u e : 0 000 000000 000000 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W [...]

Rev. 5.00, 09/0 3, page 580 of 760 18.3.10 Port K Control R egister (PKCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PK7 MD1 PK7 MD0 PK6 MD1 PK6 MD0 PK5 MD1 PK5 MD0 PK4 MD1 PK4 MD0 PK3 MD1 PK3 MD0 PK2 MD1 PK2 MD0 PK1 MD1 PK1 MD0 PK0 MD1 PK0 MD0 I n i t i a l v a l u e : 0 000 000000 000000 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W [...]

Rev. 5.00, 09/03, pa ge 581 of 760 18.3.11 Port L Control R egister (PLCR ) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PL7 MD1 PL7 MD0 PL6 MD1 PL6 MD0 PL5 MD1 PL5 MD0 PL4 MD1 PL4 MD0 PL3 MD1 PL3 MD0 PL2 MD1 PL2 MD0 PL1 MD1 PL1 MD0 PL0 MD1 PL0 MD0 I n i t i a l v a l u e : 0 000 000000 000000 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W[...]

Rev. 5.00, 09/0 3, page 582 of 760 18.3.12 SC Port Control Regi ster (SCPCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCP7 MD1 SCP7 MD0 SCP6 MD1 SCP6 MD0 SCP5 MD1 SCP5 MD0 SCP4 MD1 SCP4 MD0 SCP3 MD1 SCP3 MD0 SCP2 MD1 SCP2 MD0 SCP1 MD1 SCP1 MD0 SCP0 MD1 SCP0 MD0 I n i t i a l v a l u e : 1 010 100010 001000 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/[...]

Rev. 5.00, 09/03, pa ge 583 of 760 Bits 11 a nd 10—SCP5 Mode 1 and 0 (SCP5MD1, SCP5MD0): These bits select the pin functi o ns a nd p e rf o rm inpu t pu l l-up M OS co ntro l. Bit 11 Bit 10 SCP5MD1 SCP5MD0 Pin Function 0 0 Other function (see t able 18.1) 0 1 Port output 1 0 Port input (Pu ll-up M OS: on) (Initi al value) 1 1 Port input (Pu ll-u[...]

Rev. 5.00, 09/0 3, page 584 of 760 Bits 5 and 4 —SCP2 Mode 1 and 0 (SCP 2 MD1, SC P2MD0): These bits select the pin function and p e rfo rm input pul l -up MOS co ntro l. Bit 5 Bit 4 SCP2MD1 SCP2MD0 Pin Function 0 0 Transmit data output 1 (Tx D1) Receive data input 1 (RxD1) (Initial value) 0 1 General output (SCPT [2] output pin) Receive d ata in[...]

Rev. 5.00, 09/03, pa ge 585 of 760 Bits 1 and 0 —SCP0 Mode 1 and 0 (SCP 0 MD1, SC P0MD0): These bits select th e pin function and p e rfo rm input pul l -up MOS co ntro l. Bit 1 Bit 0 SCP0MD1 SCP0MD0 Pin Function 0 0 Transmit data output 0 (Tx D0) Receive data input 0 (RxD0) (Initial value) 0 1 General output (SCPT [0] output pin) Receive d ata i[...]

Rev. 5.00, 09/0 3, page 586 of 760[...]

Rev. 5.00, 09/03, pa ge 587 of 760 Section 19 I/O Ports 19.1 Overview The SH7709S has twelve 8- bit ports (ports A to L and SC). All port pins are multiplexed with other pin functio ns (the pin function controller (PFC) handles the select ion of pin funct ions and pull-u p MOS control). Each port has a data register wh ich stores data for th e pins[...]

Rev. 5.00, 09/0 3, page 588 of 760 19.2.2 Port A Data Register (PADR) B i t : 76543210 PA7DT PA6DT PA5DT PA4DT PA3DT PA2DT PA1DT PA0DT I n i t i a l v a l u e : 00000000 R/W: R/W R/ W R/W R/ W R/W R/ W R/W R/W The port A data reg ister (PADR) is an 8-bit readable/w ritable register that stores data for pins PTA7 t o PT A0 . B its PA7 D T to PA0 D T[...]

Rev. 5.00, 09/03, pa ge 589 of 760 19.3 Port B Por t B is an 8-bit input /out put p ort wi th the pin configu rati on sh own in fi gure 19.2. Each pin has an input pull-up MOS, which is controlled b y the port B control r egister (PBC R) in the PFC. PTB7 (input/output) / D31 (input/output ) PTB6 (input/output) / D30 (input/output ) PTB5 (input/outp[...]

Rev. 5.00, 09/0 3, page 590 of 760 19.3.2 Port B Data Register (PBDR) B i t : 76543210 PB7DT PB6DT PB5DT PB4DT PB3DT PB2DT PB1DT PB0DT I n i t i a l v a l u e : 00000000 R/W: R/W R/ W R/W R/ W R/W R/ W R/W R/W The port B data register (PBDR) is an 8-bit readable/ writable register that stores data for pins PTB 7 to PTB 0. B its PB7 DT to PB0 DT c o[...]

Rev. 5.00, 09/03, pa ge 591 of 760 19.4 Port C Port C is an 8-bit in p ut/output port with the pin configuration shown i n figure 19.3. Each pin has an in put pull-up MOS, w hich is controlled by th e port C cont rol register (PCCR) in t he PFC. PTC7 (input/output) / PINT7 (input) / MSC7 (output ) PTC6 (input/output) / PINT6 (input) / MSC6 (output [...]

Rev. 5.00, 09/0 3, page 592 of 760 19.4.2 Port C Data Register (PCDR) B i t : 76543210 PC7DT PC6DT PC5DT PC4DT PC3 DT PC2DT PC1DT PC0DT I n i t i a l v a l u e : 00000000 R/W: R/W R/ W R/W R/ W R/W R/ W R/W R/W The p ort C data r egister ( PCDR) is an 8-bi t r eadable/writable register that stores data for pins PTC7 to PT C0 . B it s P C7 DT t o PC[...]

Rev. 5.00, 09/03, pa ge 593 of 760 19.5 Port D Port D c ompris es a 6-bit inp ut/output port a nd 2-bit input p ort with the pin configurat ion shown in figure 19.4. Each pin has a n input pull- up MOS, which is controlled by the port D control register (PD CR) in the P FC. PTD7 (input/output) / DACK1 (output) PTD6 (input) / DREQ1 (input) PTD5 (inp[...]

Rev. 5.00, 09/0 3, page 594 of 760 19.5.2 Port D Data Register (PDDR) B i t : 76543210 PD7DT PD6DT PD5DT PD4DT PD3 DT PD2DT PD1DT PD0DT Initial valu e: 0 * 0 * 0000 R/W: R/W R R/W R R/W R/W R/ W R/W Note: * Undefined The port D data register (PDD R) is a 6-bit readable/w ri table and 2-bit rea d-only register that stores data for pins PTD7 t o P TD[...]

Rev. 5.00, 09/03, pa ge 595 of 760 19.6 Port E Po rt E i s an 8-b it inpu t/output port with th e pin con f iguration show n in figure 19.5. Ea ch pin h as an input pull-up MOS, which is contro lled b y the port E control register (PEC R) in the PFC. PTE7 (input/output) / AUDSYNC (output) PTE6 (input/output) PTE5 (input/output) / CE2B (output) PTE4[...]

Rev. 5.00, 09/0 3, page 596 of 760 19.6.2 Port E D ata Register (PE DR) B i t : 76543210 PE7DT PE6DT PE5DT PE4DT PE3DT PE2DT PE1DT PE0DT I n i t i a l v a l u e : 00000000 R/W: R/W R/ W R/W R/ W R/W R/ W R/W R/W The port E data register (PEDR) i s an 8-bit readable/w r itable register that st ores data for pins PTE 7 to PTE0 . B it s P E 7DT t o PE[...]

Rev. 5.00, 09/03, pa ge 597 of 760 19.7 Port F Por t F is an 8-bit input port wi th the pin c onfi gur at ion shown in f igure 19.6. Each pin has a n i nput pull-up MOS, which is controlled b y the port F contro l register (PFCR ) in the PFC. PTF7 (input) / PINT15 (input) / TRST (input) PTF6 (input) / PINT14 (input) / TMS (input) PTF5 (input) / PIN[...]

Rev. 5.00, 09/0 3, page 598 of 760 19.7.2 Port F Data Regi ster (PFDR) B i t : 76543210 PF7DT PF6DT PF5DT PF4DT PF3DT PF2DT PF1DT PF0DT Initial valu e: ******** R / W : RRRRRRRR Note: * Undefined The port F data regist er (PFDR) is an 8-bit read-only register that stores data for pins PTF7 to PTF0 . B its P F7 DT to PF0 DT co rrespo nd to pins PTF7[...]

Rev. 5.00, 09/03, pa ge 599 of 760 19.8 Port G Port G c ompris es a 5-bit inp ut/output port a nd 3-bit input p ort with the pin configurat ion shown in figur e 1 9.7 . E ach p in has an input pul l-up MO S, whi ch i s cont rol led b y the p or t G c ontr ol regist er (PG CR) in the P FC. PTG7 (input) / IOIS16 (input) PTG6 (input) / ASEMD0 (input) [...]

Rev. 5.00, 09/0 3, page 600 of 760 19.8.2 Port G Data Register (PG DR) B i t : 76543210 PG7DT PG6DT PG5DT PG4DT PG3DT PG2DT PG1DT PG0DT Initial valu e: ******** R / W : RRRRRRRR Note: * Undefined The port G dat a regist er (PGDR) i s an 8-bit read-on ly register that stores data for pins PTG7 to PTG0. Bits PG7DT to PG0DT corres pond to pins PTG7 to[...]

Rev. 5.00, 09/03, pa ge 601 of 760 19.9 Port H Port H c ompris es a 1-bit inp ut/output port a nd 7-bit input p ort with the pin configurat ion shown in figur e 1 9.8 . E ach p in has an input pul l-up MO S, whi ch i s cont rol led b y the p or t H c ontr ol regist er (PH CR) in the P FC. PTH7 (input/output) / TCLK (output ) PTH4 (input) / IRQ4 (in[...]

Rev. 5.00, 09/0 3, page 602 of 760 19.9.2 Port H Data R egister (PHD R) B i t : 76543210 PH7DT PH6DT PH5DT PH4DT PH3 DT PH2DT PH1DT PH0DT Initial valu e: 0 ******* R / W : R / W RRRRRRR Note: * Undefined The port H data register (PHD R) is a 1-bit readable/w ri table and 7-bit rea d-only register that stores data for pins PTH7 t o P TH0. Bits PH7D [...]

Rev. 5.00, 09/03, pa ge 603 of 760 19.10 Port J Port J is an 8- bit input/o utput port with the pin co nfig uration shown in figure 19.9. Eac h pin has an input pull-up MOS, which is controlled b y the port J control r egister (PJC R) in the PFC. PTJ7 (input/output) / STATUS1 (output) PTJ6 (input/output) / STATUS0 (output) PTJ5 (input/output) PTJ4 [...]

Rev. 5.00, 09/0 3, page 604 of 760 19.10.2 Port J Data Register ( PJDR) B i t : 76543210 PJ7DT PJ6DT PJ5DT PJ 4DT PJ3DT PJ2DT PJ 1DT PJ0DT I n i t i a l v a l u e : 00000000 R/W: R/W R/ W R/W R/ W R/W R/ W R/W R/W The port J data regis ter (PJDR) is an 8-bit readable/w r itable register that stores data f o r pins PTJ7 to PTJ 0. Bit s P J 7 DT to P[...]

Rev. 5.00, 09/03, pa ge 605 of 760 19.11 Port K Por t K is an 8-bit input /output po rt with the pin c onfigurat ion shown in figu re 19.10. Each pin has an input pull-up MOS, which is co ntro lled b y the port K control register (PKC R) in the PFC. PTK7 (input/output) / WE3 (output) / DQMUU (output) / ICIOWR (output) PTK6 (input/output) / WE2 (out[...]

Rev. 5.00, 09/0 3, page 606 of 760 19.11.2 Port K Data Register (P KDR) B i t : 76543210 PK7DT PK6DT PK5DT PK4DT PK3DT PK2DT PK1DT PK0DT I n i t i a l v a l u e : 00000000 R/W: R/W R/ W R/W R/ W R/W R/ W R/W R/W The port K data register (PK DR) is an 8-bit readable/w r itable register that stores data for pins PTK 7 to PT K 0 . Bits PK 7 DT t o PK [...]

Rev. 5.00, 09/03, pa ge 607 of 760 19.12 Port L Port L is an 8-bit in put port with the pin configuratio n s hown in figure 19.11. PTL7 (input) / AN7 (input) / DA0 (input) PTL6 (input) / AN6 (input) / DA1 (input) PTL5 (input) / AN5 (input) PTL4 (input) / AN4 (input) PTL3 (input) / AN3 (input) PTL2 (input) / AN2 (input) PTL1 (input) / AN1 (input) PT[...]

Rev. 5.00, 09/0 3, page 608 of 760 19.12.2 Port L Data Regis ter (PLDR) B i t : 76543210 PL7DT PL6DT PL5DT P L4DT PL3DT PL2DT PL1D T PL0DT I n i t i a l v a l u e : 00000000 R / W : RRRRRRRR The port L data register (PLDR) is an 8-bit read -only register that stores data for pin s PTL7 to PTL0. Bits PL7DT to PL0DT corre sp o nd to pins PTL7 to PTL0[...]

Rev. 5.00, 09/03, pa ge 609 of 760 19.13 SC Port The SC port com prises a 4- bit input/ou tput port, 3-bit ou tput port , and 4-bit input p or t with the p in configuration shown in figure 19.12. Each pin has an i nput pull-up MOS, which is controlled by the SC port con trol regi s ter (SCP CR) in the PFC. SCPT7 (input) / CTS2 (input) / IRQ5 (input[...]

Rev. 5.00, 09/0 3, page 610 of 760 19.13.2 SC Port Data Register (SCPDR) B i t : 76543210 SCP7DT SCP6DT SCP5DT SCP4DT SCP3DT SCP2DT SCP1DT SCP0DT Initial valu e: * 0000000 R/W: R R/W R/W R/ W R/W R/W R/ W R/W Note: * Undefined The SC port data regis ter (SCPDR) is a 7-bit readable/w ritable and 1-bit rea d-only register that stores data for pi ns S[...]

Rev. 5.00, 09/03, pa ge 611 of 760 Table 19.24 Read/Write Operation of the SC Port Data Register (SCPDR) SCPnMD1 SCPnMD0 Pin State Read Write 0 0 Other fun ction (see table 18.1) SCPDR value Value is written to SCPDR, b u t does not affect pin st ate 1 Output SCPDR value Write val ue is output from pi n 1 0 Input (P ull-up MOS on) Pin st ate Value [...]

Rev. 5.00, 09/0 3, page 612 of 760[...]

Rev. 5.00, 09/03, pa ge 613 of 760 Section 20 A/ D Converter 20.1 Overview The SH7709S in cludes a 10-bit successiv e-approxim ation A/D convert er allowing selection of up to e ight a nalo g inp ut c hanne ls . 20.1.1 Features A/D converter f eatures are listed below. • 10-bit reso lution • Eight input ch anne ls • High-speed con version [...]

Rev. 5.00, 09/0 3, page 614 of 760 20.1.2 Block D iagram Figure 20.1 s hows a block diagram of the A/D converter. 10-bit D/A ADDRA ADDRB ADDRD Bus interface Peripheral data bus Analog multi- plexer Control circuit Successive approxi- mation register + − Comparator Sample-and- hold circuit ADI interrupt signal AV SS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7[...]

Rev. 5.00, 09/03, pa ge 615 of 760 20.1.3 In put Pins Table 20.1 sum marizes the A/D convert er’s inpu t pins. The ei ght analog i npu t pins are divided into t wo gro ups: gro up 0 (AN 0 t o A N 3) , and g roup 1 (AN4 to AN7) . AV CC and AV SS are the power su pply inputs for the analog circuits in the A/D converter. AVcc also functions as the A[...]

Rev. 5.00, 09/0 3, page 616 of 760 20.1.4 Regi ster Configuration Table 20.2 summarizes the A/D conv erter’s registers. Table 20.2 A/D Converter Registers Name Abbreviation R/W Initial Value Address Access size A/D data register AH ADDRAH R H'00 H'04000080 (H'A400008 0) * 2 16, 8 A/D data register A L ADDRAL R H'00 H'0400[...]

Rev. 5.00, 09/03, pa ge 617 of 760 20.2 Register Descriptions 20.2.1 A/D Data Regi sters A to D (ADDRA to ADDRD) Upper register: H B i t : 76543210 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 I n i t i a l v a l u e : 00000000 R / W : RRRRRRRR Lower register: L B i t : 76543210 A D 1 A D 0 —————— I n i t i a l v a l u e : 00000000 R / W : RRRRRRRR [...]

Rev. 5.00, 09/0 3, page 618 of 760 20.2.2 A/D Control/Status Register (ADCSR) B i t : 76543210 ADF ADIE ADST MULTI CKS CH2 CH1 CH0 I n i t i a l v a l u e : 00000000 R/W: R/(W ) * R/W R/ W R/W R/ W R/W R/W R/ W Note: * W rite 0 to clear the flag. ADCSR is an 8-bit readable/ writable register that selects th e mode and controls the A/D converter. AD[...]

Rev. 5.00, 09/03, pa ge 619 of 760 Bit 5—A/D Start (ADS T): Starts or stop s A/D conversion. The ADST bit remains set to 1 during A/D c onve rsi on. It c an al so be set to 1 by exter na l trigger input at the ADTRG pin. Bit 5: ADST Description 0 A/D conversion is stoppe d (Initial val ue) 1 (1) Single mode: A/D conversio n start s; ADST is auto [...]

Rev. 5.00, 09/0 3, page 620 of 760 Bits 2 to 0—Channel Select 2 to 0 (C H2 to CH0): T hese bits and th e MULTI bit select the analog input chann els. Clear th e ADST bit to 0 before c hangin g t he channe l selection. Channel Selecti on Description CH2 CH1 CH0 Single Mode (MULTI = 0) Multi Mode and Scan Mode (MULTI = 1) 000A N 0 ( I n i t i a l v[...]

Rev. 5.00, 09/03, pa ge 621 of 760 20.2.3 A/D Contro l Register (ADCR) B i t : 76543210 TRGE1 TRGE0 SCN RESVD1 RESVD2 — — — I n i t i a l v a l u e : 00000111 R/W: R/W R/ W R/W R/ W R/W R R R ADCR is an 8-bit readable/ writable reg ister that enables or disables ex ternal triggering of A/D conversion. ADCR is initialized to H'07 b y a re[...]

Rev. 5.00, 09/0 3, page 622 of 760 20.3 Bus Master Interf ace ADDRA to ADDRD are 1 6-bit regis ters, but the y are connected to the bus master by the upper 8 bits of the 16-bit periph eral data bus. Therefore, alth ough the upper by te c an be accessed direc tly by the bus master, th e lower byte i s read th rough an 8-bit te m porary register (TEM[...]

Rev. 5.00, 09/03, pa ge 623 of 760 20.4 Operation The A/D conv erter operates by successive appro ximations with 10-bit resolutio n. It has t hree operating modes: single mode, multi m o de, and scan mode. 20.4.1 Sin gle Mode (MULTI = 0) Single mod e s hould be se lect ed when only one A /D c onve rsi on on one cha nne l is requ ire d. A/D conversi[...]

Rev. 5.00, 09/0 3, page 624 of 760 Channel 0 (AN0) operating ADIE ADST ADF Channel 1 (AN1) operating Channel 2 (AN2) operating Channel 3 (AN3) operating ADDRA ADDRB ADDRC ADDRD Waiting Waiting Waiting Waiting Waiting Waiting A/D conversion starts Set Set Set Clear * Clear A/D conversion result 1 A/D conversion result 2 Read result Read result A/D c[...]

Rev. 5.00, 09/03, pa ge 625 of 760 20.4.2 Multi Mode ( M ULTI = 1, SCN = 0) Multi mod e sho uld be selecte d when perfo rming A/D conver sions on one or more channels . When the ADST bit is set to 1 by software or external trigger input, A/D conv ersion starts on the first channel in th e group (AN0 w hen C H2 = 0, AN4 w h en CH2 = 1). When tw o or[...]

Rev. 5.00, 09/0 3, page 626 of 760 Channel 0 (AN0) operating ADST ADF Channel 1 (AN1) operating Channel 2 (AN2) operating Channel 3 (AN3) operating ADDRA ADDRB ADDRC ADDRD Waiting Waiting Waiting Waiting Set * Clear * Clear A/D conversion result 2 Waiting Waiting A/D conversion result 3 A/D conversion 1 Waiting A/D conversion result 1 Transfer A/D [...]

Rev. 5.00, 09/03, pa ge 627 of 760 20.4.3 Scan Mode (MULTI = 1, SCN = 1) Scan m ode is u seful for m onitoring analog inpu ts in a g roup of o ne or more channels. When the ADST bit in the A/D control/status register (ADCSR) is set to 1 by software or external trigger input, A/D co nver sio n start s o n the fir st c han nel in the g r oup (AN0 w h[...]

Rev. 5.00, 09/0 3, page 628 of 760 ADST ADF Channel 0 (AN 0 ) operating Channel 1 (AN 1 ) operating Channel 2 (AN 2 ) operating Channel 3 (AN 3 ) operating ADDRA ADDRB ADDRC ADDRD Waiting Waiting Waiting Waiting Waiting Waiting Waiting Waiting Waiting Transfer A/D conversion 1 A/D conversion 4 A/D conversion 2 A/D conversion 3 A/D conversion result[...]

Rev. 5.00, 09/03, pa ge 629 of 760 20.4.4 Input Sa mpling and A/D Co nvers io n Time The A/D converter h as a built-in sam ple-and-hold circuit. The A/D converter samples the analog input at a time t D after the ADST bit is set t o 1, then s tarts conv er sion. Figure 20.6 s hows the A/D convers i on t imi ng . Table 20.4 indicates th e A/D convers[...]

Rev. 5.00, 09/0 3, page 630 of 760 Table 20.4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Sy mbol Min T y p Max Min Ty p Max A/D conversion start delay t D 17 — 28 10 — 17 Input sampling t ime t SPL — 129 —— 65 — A/D conversion time t CONV 514 — 525 259 — 266 Note: Value s in the tab le are numbe r s of states ( t cyc ). 20.4 [...]

Rev. 5.00, 09/03, pa ge 631 of 760 20.5 Interrupts The A/D converter g enerates an interrupt (ADI) at the end of A/D conversion. Th e ADI interrupt request can be enabled or disabled b y the ADIE bit in ADCSR. 20.6 Def initions of A/D Conversion Accuracy The A/D converter compares an analog value input from an analog input chan nel with its analog [...]

Rev. 5.00, 09/0 3, page 632 of 760 111 110 101 100 011 010 001 000 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS Analog input voltage FS: Full-scale voltage (3) Quantization error Ideal A/D conversion characteristic (4) Nonlinearity error Ideal A/D conversion characteristic Actual A/D convertion characteristic (2) Full-scale erro r Digital output Analog input v[...]

Rev. 5.00, 09/03, pa ge 633 of 760 20.7.3 Access S ize and Read D ata Table 2 0 .6 shows the relationship between acce ss si ze and read data. Note the read data obtained with dif f erent access size s, bus widths, and endian modes. The case is shown here in which H'3FF is obtaine d whe n AV CC is input as an analog inp ut. FF is the da ta c o[...]

Rev. 5.00, 09/0 3, page 634 of 760 Table 20. 5 Ana lo g Input Pin Ra tings Item Min Max Unit Analog input capa cit an c e — 20 pF Allowable sig nal- source impedance — 5k Ω Table 20.6 Relation ship betwe en Access S ize and Read Data Bus Wi dth 32 Bits (D31–D0) 16 Bits (D15–D0) 8 Bits (D7–D0) Endian Ac c e s s Size Command Big Littl e B[...]

Rev. 5.00, 09/03, pa ge 635 of 760 Section 21 D/ A Converter 21.1 Overview The SH7709S in cludes a D /A converter w ith two channe ls. 21.1.1 Features D/A converter f eatures are listed below. • Eight-bit resol ution • Two output c hanne ls • Conve rsio n ti me: ma ximu m 10 µ s (with 20-pF capacitive load) • Output voltage: 0 V to AVcc 21[...]

Rev. 5.00, 09/0 3, page 636 of 760 21.1.3 I/O Pi ns Table 21.1 sum marizes the D/A conv erter ’s input and outp ut pins. Table 21.1 D/A Converter Pins Pin Name Abbrev iation I/O Function Analog pow er su pply pi n AVcc Input Analog pow er supply Analog ground pin AVss Input Analog ground and reference v oltag e Analog output pin 0 DA0 Output Anal[...]

Rev. 5.00, 09/03, pa ge 637 of 760 21.2 Register Descriptions 21.2.1 D/A Data Registe rs 0 and 1 (DADR0/1) B i t : 76543210 I n i t i a l v a l u e : 00000000 R/W: R/W R/ W R/W R/W R/ W R/W R/W R/ W The D/A data registers (DADR0 and DADR1) are 8-bit readable/w r itable registers that st ore the dat a to b e conve rte d. When an alog out put is e na[...]

Rev. 5.00, 09/0 3, page 638 of 760 Bit 5—D/A Enable (DAE): Control s D/A conv ersion, together wi th bi ts DAOE0 an d DAOE1. When the DAE bit is cleared t o 0, D/A conv ers io n is controlled in d ependentl y in c hannel s 0 an d 1. When the chip enters standby mode while D/A convers ion is enabled, the D/A output is held and the analog p ower-su[...]

Rev. 5.00, 09/03, pa ge 639 of 760 21.3 Operation The D/A conv ert er has two b uilt-i n D/A con ver sio n circ uits t hat can perfo rm conversion independen tly. D/A conversion is performed constantly while enable d in DA CR. If the DA DR0 or DADR1 value is modified, conv ersio n of the new data begins immediately. The conversio n results are outp[...]

Rev. 5.00, 09/0 3, page 640 of 760[...]

Rev. 5.00, 09/03, pa ge 641 of 760 Section 22 User Debugging Interface (UDI) 22.1 Overview This LSI incorp orates a User deb ugging inter face (UDI) and ad vanced user d ebugger (AUD) for program debugging. 22.2 User D ebugging Interface (UDI) The UDI (User debugging inter face) perfo rms on-chip de bugging which is supporte d by t his LSI. The UDI[...]

Rev. 5.00, 09/0 3, page 642 of 760 mode, boun dar y scan and emulator func tions ca n be used. The input lev el a t the ASEMD0 pin should be held fo r at leas t one cycle after R ESETP nega tio n. A A A AS S S SE E E EB B B BR R R R KAK KAK KAK KAK : Dedicated emulator pin 22.2.2 Block D iagram Figure 22.1 s hows a block diagram of the UD I. SDIR T[...]

Rev. 5.00, 09/03, pa ge 643 of 760 Table 22.1 show s the U DI register con f iguration. Table 22.1 UDI Registers CPU Side UDI Side Initial Name Abbrev iation R/W Size Address R/W Size Value * Bypass regi ster SDBPR — — — R/ W 1 Undefined Instruction re gister SDIR R 16 H'04000200 R/W 16 H'FFFF Boundary regi ster SDBSR — — — R/[...]

Rev. 5.00, 09/0 3, page 644 of 760 Table 22. 2 UDI Co mmands Bit 15 to 12 TI3 TI2 TI1 TI0 Description 0000E X T E S T 0100S A M P L E / P R E L O A D 0101R e s e r v e d 0110U D I r e s e t n e g a t e 0111U D I r e s e t a s s e r t 100— R e s e r v e d 101— U D I i n t e r r u p t 110— R e s e r v e d 1110R e s e r v e d 1111B y p a s s m o[...]

Rev. 5.00, 09/03, pa ge 645 of 760 Table 22.3 Pins of t his LSI and Boundary Scan Register Bit s Bit Pin Name I/O Bit Pin Name I/O from TDI 308 D1 IN 338 D31/PTB7 IN 307 D0 IN 337 D30/PTB6 IN 306 MD1 IN 336 D29/PTB5 IN 305 MD2 IN 335 D28/PTB4 IN 304 NMI IN 334 D27/PTB3 IN 303 IRQ0/ IRL0 /PTH0 IN 333 D26/PTB2 IN 302 IRQ1/ IRL1 /PTH1 IN 332 D25/PTB1 [...]

Rev. 5.00, 09/0 3, page 646 of 760 Bit Pin Name I/O Bit Pin Name I/O 277 D10 OUT 247 D12 Control 276 D9 OUT 246 D11 Control 275 D8 OUT 245 D10 Control 274 D7 OUT 244 D9 Control 273 D6 OUT 243 D8 Control 272 D5 OUT 242 D7 Control 271 D4 OUT 241 D6 Control 270 D3 OUT 240 D5 Control 269 D2 OUT 239 D4 Control 268 D1 OUT 238 D3 Control 267 D0 OUT 237 D2[...]

Rev. 5.00, 09/03, pa ge 647 of 760 Bit Pin Name I/O Bit Pin Name I/O 217 A7 OU T 187 CS4 /PTK2 OUT 216 A8 OU T 186 CS5 / CE1A /PTK3 OUT 215 A9 OU T 185 CS6 / CE1B OUT 214 A10 OUT 184 CE2A /PTE4 OUT 213 A11 OUT 183 CE2B /PTE5 OUT 212 A12 OUT 182 A0 Control 211 A13 OUT 181 A1 Control 210 A14 OUT 180 A2 Control 209 A15 OUT 179 A3 Control 208 A16 OUT 1[...]

Rev. 5.00, 09/0 3, page 648 of 760 Bit Pin Name I/O Bit Pin Name I/O 157 A25 Control 127 BREQ IN 156 BS/PTK4 Control 126 WAIT IN 155 RD Control 125 AUDCK/PTH6 IN 154 WE0 /DQM LL Control 124 IOIS16 /PTG7 IN 153 WE1 /DQMLU/ WE Control 123 ASEBRKAK /PTG5 IN 152 WE2 /DQMUL/ ICIORD / PTK6 Control 122 CKIO2/PTG 4 IN 151 WE3 /DQMUU/ ICIOWR / PTK7 Control [...]

Rev. 5.00, 09/03, pa ge 649 of 760 Bit Pin Name I/O Bit Pin Name I/O 97 ASEBRKAK /PTG5 OUT 65 RxD2/SCPT4 IN 96 AUDATA 3/PTG3 OUT 64 WAKEUP /PTD3 IN 95 AUDATA 2/PTG2 OUT 63 RESETOUT /PTD2 IN 94 AUDATA1/PTG1 OUT 62 DRAK0/PTD1 IN 93 AUDATA0/PTG0 OUT 61 DRAK1/PTD0 IN 92 CKE/PTK5 Control 60 DREQ0 /PTD4 IN 91 RAS3L /PTJ0 Control 59 DREQ1 /PTD6 IN 90 PTJ1[...]

Rev. 5.00, 09/0 3, page 650 of 760 Bit Pin Name I/O Bit Pin Name I/O 33 MCS6 /PTC6/PINT6 OUT 15 SCK1/SCPT3 Control 32 MCS5 /PTC5/PINT5 OUT 14 TxD2/SCPT4 Con trol 31 MCS4 /PTC4/PINT4 OUT 13 SCK2/SCPT5 Control 30 WAKEUP /PTD3 OUT 1 2 RTS2/SCPT6 Control 29 RESETOUT /PTD2 OUT 11 MCS7 /PTC7/PINT7 Control 28 MCS3 /PTC3/PINT3 OUT 10 MCS6 /PTC6/PINT6 Contr[...]

Rev. 5.00, 09/03, pa ge 651 of 760 22.4 UDI Operation 22.4.1 TAP C ontroller Figure 22.2 s hows the intern al states of the TAP con troller. Stat e transitions basically conform wi th the JTA G stan dard. T est-logic-reset Capture-DR Shift-DR Exit1-DR Pause-DR Exit2-DR Update-DR Select-DR-scan Run-test/idle 1 0 0 0 0 11 1 1 0 0 1 0 1 1 10 Capture-I[...]

Rev. 5.00, 09/0 3, page 652 of 760 22.4.2 Reset Confi guration Table 22.4 Reset Configuration ASE ASE ASE ASEM M M MD D D D0 0 0 0 * 1 R R R RESE ESE ESE ESET T T TP P P PT T T TR R R RS S S ST T T T Chip State High-level Low-level Low-level Normal reset and U DI reset High-leve l Normal reset High-level Low-level UDI reset only High-leve l Normal [...]

Rev. 5.00, 09/03, pa ge 653 of 760 22.4.3 UDI R e s et An UDI res et is execu te d by se tt ing an UDI r ese t asser t comma nd in SDIR. An UDI res et is of the same ki nd as a po wer-on reset. An UDI reset is release d by inputt ing an UDI reset negate comma nd . UDI reset assert UDI reset negate SDIR Chip internal reset CPU state Branch to H&apos[...]

Rev. 5.00, 09/0 3, page 654 of 760 22.5 Boundary Scan A command can be set in SDIR by the UDI to place the UDI pins in the boundar y scan mode stipulated by JTAG. 22.5.1 Supported Inst ructions This LSI supports the three essential instructions defined in the JTAG standard ( BYPAS S, SAM P LE/ PRE LO AD, a nd E XT EST ) . BYPASS: The B YPASS instru[...]

Rev. 5.00, 09/03, pa ge 655 of 760 Data loaded in to the ou tput pin boundary scan regi ster in the Capture- DR state is not used for extern al circuit testin g (it is repl aced by a shi f t ope r a t i on) . The inst ruction code is 0000. 22.5.2 Points for Atten t i on 1. Boundary scan m ode covers clock -related signals (EXTAL, EXTAL2, XTA L, XTA[...]

Rev. 5.00, 09/0 3, page 656 of 760[...]

Rev. 5.00, 09/03, pa ge 657 of 760 Section 23 Electrical Characteristics 23.1 Absolute Maximu m Ratings Table 23.1 sh ows th e absolute maximum ratings. Table 23. 1 Abso lute M aximum Rating s Item S y mbol Rating Unit Power supply voltage ( I/O) VccQ –0.3 to 4.2 V Power supply voltag e (internal) Vcc Vcc – PLL1 Vcc – PLL2 Vcc – RTC –0.3 [...]

Rev. 5.00, 09/0 3, page 658 of 760 Pin states undefined (Max. 1 ms) 3.3 V 1.7 V/1.8 V/1.9 V/2.0 V 3.3 V power 1.7 V/1.8 V/1.9 V/2.0 V power RESETP A ll other pins * Pin states undefined Power-on reset state Note: * Except power/GND, clock related, and analog pins Power-On Sequence • Pow e r-off order 1. In th e reverse order of po wering- on, fir[...]

Rev. 5.00, 09/03, pa ge 659 of 760 23.2 DC Characteristics Tables 23.2 and 23.3 list DC characteristics. Table 23.2 DC Characteristics Ta = –20 to 75° C Item S y mbol Min T y p Max Unit Measurement Conditi ons Power supply voltage VccQ 3.0 3.3 3.6 V Vcc, 1.85 2.00 2.15 200 MHz model * Vcc-PLL1, 1.75 1.90 2.05 167 MHz model Vcc-PLL2, 1.65 1.80 2.[...]

Rev. 5.00, 09/0 3, page 660 of 760 Item S y mbol Min T y p Max Unit Measurement Conditi ons Input high voltage RESETP , RESETM , NMI, IRQ5 to IRQ0, MD5 to MD 0, IRL3 to IRL0 , IRLS3 to IRLS0 , PINT15 to PINT0, ASEMD0 , ADTRG , TRST , EXTAL, CKIO, RxD1, CA V IH VccQ × 0.9 — VccQ + 0.3 V EXTAL2 — — — W hen not connect ing to a crystal os cil[...]

Rev. 5.00, 09/03, pa ge 661 of 760 Item S y mbol Min Ty p Max Unit Meas urement Conditi ons Input low voltage RESETP , RESETM , NM I, IRQ5–IRQ0, MD5–MD 0, IRL3 to IRL0 , IRLS3 to IRLS0 , PINT15– PINT0, ASEMD0 , ADTRG , TRST , EXTAL, CKIO, RxD1, CA V IL –0.3 — VccQ × 0.1 V EXTAL2 — — — When not connecting to a crystal os cillator, c[...]

Rev. 5.00, 09/0 3, page 662 of 760 Item Sy mbol Min T y p Max Unit Measurement Conditions Analog power- supply voltage AVcc 3.0 3.3 3.6 V Analog power- supply During A/D conversion AIcc — 0.8 2 mA current During A/D and D/A conversion —2 . 4 6 m A Idle — 1 20 µA Ta = 25°C Notes: Even when PLL i s not used, alway s connect Vcc-PLL1 and V cc-[...]

Rev. 5.00, 09/03, pa ge 663 of 760 23.3 AC Ch aracteristics In g eneral, in putting for this LSI should be cloc k synch ronous. Keep the setup a nd hold t imes for each input signal un less otherwise specified. Table 23.4 Opera t ing F requency Ra nge VccQ = 3.3 ± 0.3 V, VccQ = 1.55 to 2 .15 V, A Vcc = 3.3 ± 0.3 V, Ta = –20 t o 75°C Item Sy mb[...]

Rev. 5.00, 09/0 3, page 664 of 760 23.3.1 Clock Timing Table 23.5 Clock Timing VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.1 5 V, AV cc = 3.3 ± 0.3 V, Ta = –20 to 75° C Item Sy mbol Min Max Unit Figure EXTAL clock input frequenc y (clock mode 0) f EX 25 66.67 MHz 23.1 EXTAL clock input cycle tim e (clock mode 0) t EXcyc 15 40 ns EXTAL clock input freq[...]

Rev. 5.00, 09/03, pa ge 665 of 760 t EXH t EXF t EXR t EXL t EXcyc V IH V IH V IH 1/2 V CC Q 1/2 V CC Q V IL V IL EXTAL * (input) Note: * The clock input from the EXTAL pin. Figure 23 .1 EXTAL Cl ock Inpu t T iming t CKIH t CKIF t CKIR t CKIL t CKIcyc V IH 1/2 V CC Q 1/2 V CC Q V IH V IL V IH V IL CKIO (input) Figure 23.2 CKIO Cloc k Input Timing t[...]

Rev. 5.00, 09/0 3, page 666 of 760 V CC min t RESPW t RESPS t OSC1 V CC RESETP CKIO, internal clock Stable oscillation Note: Oscillation settling time when built-in oscillator is used Figure 23.4 P o wer-on O scillation Se ttling Tim e CKIO, internal clock Stable oscillation Standby t OSC2 t RESPW/MW t RESPS/M S RESETP RESETM Note: Oscillation sett[...]

Rev. 5.00, 09/03, pa ge 667 of 760 CKIO, internal clock Stable oscillation Standby t OSC3 NMI Note: Oscillation settling time when built-in oscillator is used in the oscillation off mode WAKEUP Figure 23.6 Oscillatio n Settling Time at S tandby Return (Return by NMI) CKIO, internal clock Stable oscillation Standby t OSC4 IRL3 to IRL0 IRQ4 to IRQ0 P[...]

Rev. 5.00, 09/0 3, page 668 of 760 EXTAL input or CKIO input Stable input clock Reset or NMI interrupt request Stable input clock Normal Normal Standby PLL output, CKIO output Internal clock STATUS 0 STATUS 1 PLL synchronization Note: PLL oscillation settling time during the continued oscillation mode or when clock is input from EXTAL pin or CKIO p[...]

Rev. 5.00, 09/03, pa ge 669 of 760 EXTAL input * 1 (CKIO input) CKIO output * 2 (PLL output) Internal clock Multiplication rate modified t PLL2 Notes: 1. CKIO input in clock mode 7 2. PLL output in other than clock mode 7 Figure 23.10 PLL Synchroni za tion Settlin g Time when Freque ncy Multip lica tion Rate Modified[...]

Rev. 5.00, 09/0 3, page 670 of 760 23.3.2 Control Signal T imin g Table 23.6 Control S ignal T iming Vcc = 3.3 ± 0.3 V, Vcc = 1. 55 to 2.15 V, AV cc = 3.3 ± 0.3 V , Ta = –2 0 to 7 5 °C Item S y mbol Min M ax Unit Figure RESETP pulse w idth t RESPW 20 * 2 — tcyc 23.11, RESETP setup time * 1 t RESPS 20 — ns 23.12 RESETP hold time t RESPH 4?[...]

Rev. 5.00, 09/03, pa ge 671 of 760 CKIO t RESPS/MS t RESPS/MS RESETP RESETM t RESPW/MW Figure 23. 11 Reset I nput Ti ming CKIO RESETP RESETM t RESPH/MH t RESPS/MS V IH V IL NMI t NMIH t NMIS V IH V IL IRQ5 to IRQ0 t IRQH t IRQS V IH V IL Figure 23. 12 Interrupt Signal Input Timing CKIO t IRQOD t IRQOD IRQOUT Figure 23.13 I I I IR R R RQOU QOU QOU Q[...]

Rev. 5.00, 09/0 3, page 672 of 760 CKIO BREQ BACK RD , RD/ WR , RAS , CAS , CSn , WEn , BS , A25 to A0, D31 to D0 t BACKD t BOFF2 t BOFF1 t BON1 t BACKD t BON2 t BREQH t BREQH t BREQS t BREQS MCSn Figure 23.14 Bus Release Ti ming CKIO t STD t BOFF2 t BOFF1 t STD t BON2 t BON1 Normal mode Standby mode Normal mode STATUS 0 STATUS 1 R D , RD/ WR , RAS[...]

Rev. 5.00, 09/03, pa ge 673 of 760 23.3.3 AC Bu s Timi n g Table 23. 7 B us Timing Clock Modes 0/1/2/7, VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75° C Item S y mbol Min Max Unit Figure Address delay time t AD 1.5 12 ns 23.16–23.36, 2 3.39–23.46 Address setup time t AS 0 — ns 23.16–23.18 Address hold tim[...]

Rev. 5.00, 09/0 3, page 674 of 760 Item S y mbol Min Max Unit Figure ICIORD delay ti me t ICRSD — 10 ns 23.44–23.46 ICIOWR delay time t ICWSD — 10 ns 23.44–23.46 IOIS16 setup time t IO16S 6 — ns 23.45, 23. 46 IOIS16 hold t ime t IO16H 4 — ns 23.45, 23.46 DACK delay ti me 1 (Reference f or CKIO rise) t DAKD1 — 10 ns 23.16–23. 36, 23.[...]

Rev. 5.00, 09/03, pa ge 675 of 760 23.3.4 Basic T imin g T 1 CKIO A25 to A0 CSn RD/ WR RD D31 to D0 (read) WEn D31 to D0 (write) BS T 2 t AD t AH t AD t CSD1 t RWD t RSD t CSD2 t WED t WDD1 t RDS1 t BSD t BSD t DAKD1 t DAKD1 t RDH1 t RDH1 t WED t RSD t AH t RWH t RWD t WDH1 t RWH t RWH t AH t WDH3 DACKn (read) (write) t AS Figure 23.16 Basic Bus Cy[...]

Rev. 5.00, 09/0 3, page 676 of 760 T 1 T w T 2 CKIO A25 to A0 CSn RD/ WR RD D31 to D0 (read) WEn D31 to D0 (write) BS WAIT t AD t AD t RWD t RWH t AH t AH t RSD t CSD1 t WED t WDD1 t BSD t WTS t WTH t BSD t RDS1 t CSD2 t WED t RSD t RDH1 t RDH1 t RWD t AH t RWH t WDH3 t WDH1 t RWH t DAKD1 t DAKD1 DACKn (read) (write) t AS Figure 23.17 Basic Bus Cyc[...]

Rev. 5.00, 09/03, pa ge 677 of 760 t RDH1 t AH t RSD t WED t AH t WDD1 T 1 T w T w T 2 CKIO A25 to A0 CSn RD/ WR RD (read) D31 to D0 (read) WEn (write) D31 to D0 (write) BS WAIT t AD t AD t RWD t RSD t WED t WTS t WTH t BSD t BSD t RDS1 t WTS t WTH t CSD1 t CSD2 t RDH1 t RWH t AH t RWH t RWD t RWH t WDH3 t WDH1 t DAKD1 t DAKD2 DACKn t AS Figure 23.[...]

Rev. 5.00, 09/0 3, page 678 of 760 23.3.5 Burs t ROM Tim ing CKIO A25 to A4 A3 to A0 CSn RD/ WR RD D31 to D0 BS DACKn WAIT t AD t AD t AD t AD t CSD1 t RWD t BSD t BSD t AH t BSD t DAKD1 t DAKD2 t CSD2 t RSD t RDS1 t WTS t WTH t WTS t WTH t WTS t WTH t RDS t RSD T 1 T B2 T B1 T B2 T B1 T B2 T B1 T 2 t RSD t RDH1 t RSD t AH t RDH1 t RWH t AH t RWH t[...]

Rev. 5.00, 09/03, pa ge 679 of 760 t RSD t AH t RSD t AH t AH t RDH1 CKIO A25 to A4 A3 to A0 CSn RD/ WE RD D31 to D0 Note: In the write cycle, the basic bus cycle is performed. BS WAIT DACKn t AD t AD t AD t CSD1 t RWH t RWD t RSD t RSD t RDH1 t RDH1 t RDS1 t BSD t DAKD1 t DAKD2 t BSD t BSD t BSD t WTS t WTH t WTS t WTH T 1 T w T w T B2 T B1 T B2 T[...]

Rev. 5.00, 09/0 3, page 680 of 760 CKIO A25 to A4 A3 to A0 CSn RD/ WR RD D31 to D0 BS DACKn WAIT T 1 T w T w T B2 T B1 T 2 T Bw t AD t AD t CSD1 t CSD2 t RWD t RWH t RDH1 t AH t AH t RWD t RSD t RSD1 t AH t AD t BSD t BSD t WTS t WTH t WTS t WTH t WTS t WTH t WTS t WTH t BSD t BSD t RDS1 t RDH1 t RSD t DAKD1 t DAKD2 t RDH1 t RWH t RSD1 t RDS Note: [...]

Rev. 5.00, 09/03, pa ge 681 of 760 23.3.6 Synchron ous DRAM Timing CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE A25 to A16 A15 to A0 Tr tAD Row address Row address Read A command Row address Column address Tc1 Tc2 (Tpc) D31 to D0 tAD tAD tAD tAD tCSD3 tRWD tCSD3 tRWD tRASD2 tDQMD tDQMD tRDH2 tBSD tBSD (High) tRDS2 tRASD2 tCASD2 tCASD2 tAD tAD tA[...]

Rev. 5.00, 09/0 3, page 682 of 760 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE (High) A25 to A16 A15 to A0 Tr Trw Trw Tc1 Tcw Td1 (Tpc) (Tpc) D31 to D0 Row address Row address Read A command Row address Column address tAD tAD tAD tAD tCSD3 tRWD tDQMD tRDH2 tBSD tBSD tRDS2 tCSD3 tRWD tRASD2 tDQMD tRASD2 tCASD2 tCASD2 tAD tAD tAD tAD DACKn t DAKD[...]

Rev. 5.00, 09/03, pa ge 683 of 760 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE (High) A25 to A16 A15 to A0 Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 (Tpc) (Tpc) D31 to D0 Row address Row address Read A command Read command Row address Column address (1-4) tAD tAD tAD tAD tAD tAD tAD tAD tAD tCSD3 tCSD3 tRWD tRWD tRASD2 tDQMD tBSD tBSD tRDS2 tRDH2 tRDS[...]

Rev. 5.00, 09/0 3, page 684 of 760 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE A25 to A16 A15 to A0 Tr Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 (Tpc) D31 to D0 (read) tAD tAD tAD tAD tAD tAD tAD tAD tAD tAD tCSD3 tRWD tDQMD tRDS2 tBSD tBSD tRDH2 tRDS2 tRDH2 tCSD3 tRWD tRASD2 tRASD2 tCASD2 tDQMD tCASD2 Row address Row address Row address Read command[...]

Rev. 5.00, 09/03, pa ge 685 of 760 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE A25 to A16 A15 to A0 Tr Tc1 (Trwl) (Tpc) (High) D31 to D0 tAD Row address Row address Write A command Row address Column address tAD tAD tCSD3 tRWD tRASD2 tAD tAD tAD tAD tAD tCSD3 tRWD tRWD tRASD2 tCASD2 tDQMD tWDD2 tBSD tDQMD tWDH2 tBSD tCASD2 t DAKD1 t DAKD1 DACKn[...]

Rev. 5.00, 09/0 3, page 686 of 760 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE A25 to A16 A15 to A0 Tr Trw Trw Tc1 (Trwl) (Trwl) (Tpc) (Tpc) (High) D31 to D0 tAD Row address Row address Write A command Row address Column address tAD tAD tAD tAD tAD tAD tCSD1 tRWD tRWD tAD tAD tAD tCSD1 tRWD tRASD2 tRASD2 tDQMD tWDD2 tBSD tCASD2 tDQMD tWDH2 tBSD[...]

Rev. 5.00, 09/03, pa ge 687 of 760 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE A25 to A16 A15 to A0 Tr Tc1 Tc2 Tc3 Tc4 (Trwl) (Tpc) (Tpc) (High) D31 to D0 tAD Row address Row address Write A command Write command Row address tAD tAD tAD tAD tCSD3 tRWD tRWD tAD tAD tAD tAD tCSD3 tRWD tRASD2 tRASD2 tDQMD tWDD2 tWDD2 tBSD tCASD2 tDQMD tWDH2 tBSD t[...]

Rev. 5.00, 09/0 3, page 688 of 760 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE (High) A25 to A16 A15 to A0 Tr Trw Tc1 Tc2 Tc3 Td4 (Trwl) (Tpc) D31 to D0 Row address Row address Write A command Write command Row address Column address (1-4) tAD tAD tAD tAD tAD tAD tAD tAD tAD tCSD3 tCSD3 tRWD tRWD tRWD tRASD2 tDQMD tBSD tBSD tWDD2 tWDD2 tWDH2 tD[...]

Rev. 5.00, 09/03, pa ge 689 of 760 CKIO A 12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE A 25 to A16 A 15 to A0 Tnop Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 D31 to D0 t AD t AD t CSD3 t CSD3 t RWD t RWD t RASD2 t DQMD t DQMD t BSD t BSD (High) t AD t AD t AD t RDS2 t RDH2 t RDS2 t RDH2 t CASD2 t CASD2 t AD Row address Read command Column address t DAKD1 t DAKD1[...]

Rev. 5.00, 09/0 3, page 690 of 760 A25 to A16 (High) t AD t AD t AD t CASD2 t CSD3 t RWD t DQMD t BSD t RDH2 t RDS2 t RDH2 t RDS2 t BSD t RASD2 t CASD2 t DQMD t RWD t CSD3 t AD t AD t AD Tc1 Tc2 Tc3/Td1 Tc4/Td2 Td3 Td4 CKIO A12 or A10 A15 to A0 CSn RD/ WR RAS CAS DQMxx D31 to D0 BS CKE Row address DACKn t DAKD1 t DAKD1 Column address Read command F[...]

Rev. 5.00, 09/03, pa ge 691 of 760 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE A25 to A16 A15 to A0 Tp Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 D31 to D0 t AD t AD t CSD3 t CSD3 t RWD t RWD t RWD t RASD2 t RASD2 t DQMD t DQMD t DQMD t BSD t BSD t DAKD1 t DAKD1 (High) t AD t AD t AD t AD t AD t AD t RDS2 t RDH2 t RDS2 t RDH2 t AD Row address Read comm[...]

Rev. 5.00, 09/0 3, page 692 of 760 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE A25 to A16 A15 to A0 Tp Tpw Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 D31 to D0 t AD t AD t CSD3 t CSD3 t RWD t RWD t RWD t RASD2 t RASD2 t RASD2 t RASD2 t DQMD t DQMD t DQMD t BSD t BSD (High) t AD t AD t AD t AD t AD t AD t RDS2 t RDH2 t RDS2 t RDH2 t AD Td4 Row address Read [...]

Rev. 5.00, 09/03, pa ge 693 of 760 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE A25 to A16 A15 to A0 Tc1 Tc2 Tc3 Tc4 D31 to D0 t AD t AD t CSD3 t CSD3 t RWD t RWD t RASD2 t RASD2 t DQMD t DQMD t WDD2 t WDD2 t BSD t BSD (High) t AD t AD t AD t CASD2 t CASD2 t AD Row address Write command Column address t DAKD1 t DAKD1 DACKn Figure 23.3 4 Synchron[...]

Rev. 5.00, 09/0 3, page 694 of 760 t WDD2 t WDD2 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE A25 to A16 A15 to A0 Tp Tr Tc1 Tc2 Tc3 Tc4 D31 to D0 t AD t AD t CSD3 t CSD3 t RWD t RWD t RWD t RWD t RASD2 t RASD2 t DQMD t DQMD t DQMD t BSD t BSD (High) t AD t AD t AD t AD t AD t AD t AD Row address Write command Row address Row address Column addr[...]

Rev. 5.00, 09/03, pa ge 695 of 760 CKIO A12 or A10 RD/ WR CSn RAS CAS BS DQMxx CKE A25 to A16 A15 to A0 Tp Tpw Tr Trw Tc1 Tc2 Tc3 D31 to D0 t AD t AD t CSD3 t CSD3 t RWD t RWD t RWD t RWD t RASD2 t RASD2 t RASD2 t RASD2 t DQMD t DQMD t DQMD t WDD2 t WDD2 t BSD t BSD (High) t AD t AD t AD t AD t AD t AD Td4 Write command Column address t CASD2 t CAS[...]

Rev. 5.00, 09/0 3, page 696 of 760 CKIO CSn RD/ WR CASxx CKE RAS3x Tp Tpc TRr TRrw TRrw (Tpc) (Tpc) t CSD3 t CSD3 t CSD3 t CSD3 t RASD2 t RASD2 t RASD2 t RASD2 t CASD2 t CASD2 t RWD t RWD (High) Figure 23.37 Synchronous DRAM Auto-Refresh Timing (TRAS = 1, TPC = 1)[...]

Rev. 5.00, 09/03, pa ge 697 of 760 Tpc TRa1 (TRs2) (TRs2) TRs3 CKIO CKE CSn RAS CAS RD/ WR t RWD t RWD t CASD2 t RASD2 t CSD3 t CASD2 t CSD3 t RASD2 Tp t CSD3 t CSD3 t RASD2 t RASD2 (Tpc) (Tpc) t CKED t CKED t RWD Figure 23.38 S ynchronous DRAM Self-Refresh Cycle (TRAS = = = = 1, TPC = = = = 1)[...]

Rev. 5.00, 09/0 3, page 698 of 760 CKIO A12 or A10 RD/ WR CSn RAS CASxx D31 to D0 A13 or A11 A11 to A2 or A9 to A2 TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 (High) CKE tAD tAD tAD tAD tAD tAD tAD tAD tAD tAD tAD tCSD3 tCSD3 tRWD tRWD tRWD tRASD2 tRASD2 tRASD2 tRASD2 tCASD2 tCASD2 t DAKD1 t DAKD1 DACKn Figure 23.3 9 Synchrono us DRAM Mode Re gister Wr[...]

Rev. 5.00, 09/03, pa ge 699 of 760 23.3.7 PCMCIA Ti ming T pcm1 T pcm2 CKIO A25 to A0 CExx RD/ WR RD D15 to D0 WE1 D15 to D0 BS DACKn t AD t AD t CSD1 t CSD1 t RWD t RSD t RSD t RWD t DAKD1 t DAKD1 t WED t WDD1 t WED t RDS1 t RDH1 t BSD t BSD t WDH4 t WDH1 (read) (read) (write) (write) Figure 23.40 P CMCIA Memory Bus Cycle ( TED = 0, T EH = 0, No W[...]

Rev. 5.00, 09/0 3, page 700 of 760 CKIO T pcm0 T pcm0w T pcm1 T pcm1w T pcm1w T pcm2 T pcm2w A25 to A0 CExx RD/ WR RD (read) D15 to D0 (read) WE1 (write) D15 to D0 (write) BS DACKn WAIT t AD t CSD1 t RWD t AD t CSD1 t RWD t WDH4 t RSD t RSD t DAKD1 t DAKD1 t WED t WDD1 t WED t WDH1 t RDH1 t BSD t WTS t WTH t WTS t WTH t RDS1 t BSD Figure 23.41 PCMC[...]

Rev. 5.00, 09/03, pa ge 701 of 760 CKIO T pcm1 T pcm2 T pcm1 T pcm2 T pcm1 T pcm2 T pcm1 T pcm2 A25 to A4 A3 to A0 CExx RD/ WR RD D15 to D0 BS DACKn t AD t AD t CSD1 t RWD t CSD1 t RWD t AD t AD t AD t AD t DAKD1 t RSD t RSD t RDH1 t RDH1 t RSD t RSD t BSD t BSD t BSD t BSD t RDS1 t RDS1 Note: Even though burst mode is set, write cycle operation is[...]

Rev. 5.00, 09/0 3, page 702 of 760 t RDS1 t RSD CKIO T pcm0 T pcm1 T pcm1w T pcm1w T pcm1w T pcm2 T pcm1 T pcm1w T pcm2 T pcm2w A25 to A4 A3 to A0 CExx RD/ WR RD (read) D15 to D0 (read) Note: Even though burst mode is set, the write cycle operation is the same as in normal mode. BS DACKn WAIT t AD t AD t CSD1 t RWD t CSD1 t DAKD1 t RWD t AD t AD t [...]

Rev. 5.00, 09/03, pa ge 703 of 760 T pci1 T pci2 CKIO A25 to A0 CExx RD/ WR ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) BS DACKn t AD t AD t CSD1 t CSD1 t RWD t ICRSD t ICRSD t RWD t DAKD1 t DAKD1 t ICWSD t WDD1 t ICWSD t RDH1 t RDS1 t BSD t BSD t WDH1 t WDH4 Figure 23.44 P CMCIA I/O Bus Cycle (TE D = 0, TEH = 0, No W ait)[...]

Rev. 5.00, 09/0 3, page 704 of 760 CKIO T pci0 T pci0w T pci1 T pci1w T pci1w T pci2 T pci2w A25 to A0 CExx RD/ WR ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) BS DACKn WAIT IOIS16 t AD t CSD1 t RWD t AD t CSD1 t RWD t ICRSD t ICRSD t DAKD1 t DAKD1 t ICWSD t WDD1 t ICWSD t WDH1 t WDH4 t RDH1 t WTS t WTH t WTS t WTH t IO16S t IO16[...]

Rev. 5.00, 09/03, pa ge 705 of 760 CKIO T pci0 T pci1 T pci1w T pci2 T pci1 T pci1w T pci2 T pci2w A25 to A4 A0 CExx RD/ WR ICIORD D15 to D0 ICIOWR D15 to D0 BS WAIT IOIS16 DACKn t AD t AD t CSD1 t CSD1 t RWD t RWD t WDD1 t WDH4 t WDH4 t BSD t BSD t AD t AD t ICRSD t ICRSD t ICRSD t ICRSD t ICWSD t WTS t WTH t WTH t IO16S t IO16H t AD t RDS1 t CSD1[...]

Rev. 5.00, 09/0 3, page 706 of 760 23.3.8 Peripheral Module Signal T iming Table 23.8 Periphera l Mo dule Signal Timing VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.1 5 V, AV cc = 3.3 ± 0.3 V, Ta = –20 to 75° C Module Item Sy mbol Min Max Unit Figure Timer input setu p time t TCLKS 15 — ns 23.47 TMU, RTC Timer cl ock input setup time t TCKS 15 — 23[...]

Rev. 5.00, 09/03, pa ge 707 of 760 t TCLKS CKIO TCLK (input) Figure 23.47 TCLK Input Timing t TCKS t TCKS t TCKWH t TCKWL CKIO TCLK (input) Figure 23.48 TCLK Clo ck Input Timing RTC crystal oscillator Stable oscillation V CC V CCmin t ROSC Figure 23.49 Oscillation Settling Time at RTC Crys tal Oscillator Power-on t SCKW SCK (input) t SCKR t SCKF t [...]

Rev. 5.00, 09/0 3, page 708 of 760 t SCYC t TXD SCK TxD (data trans- missiion) RxD (data reception) t RXH t RXS t RTSD RTS CTS t CTSH t CTSS Figure 23.51 S CI I/O Timing in Clock Synchron ous Mode t PORTS1 CKIO PORT 7 to 0 (read) (B:P clock ratio = 1:1) PORT 7 to 0 (read) (B:P clock ratio = 4:1) t PORTH1 t PORTS2 PORT 7 to 0 (read) (B:P clock ratio[...]

Rev. 5.00, 09/03, pa ge 709 of 760 DRAK0/1 CKIO t DRAKD t DRAKD Figure 23.54 D RAK Output Timi ng 23.3.9 UDI-Rel ated Pin Timin g Table 23. 9 UDI-R elated Pin Ti ming VccQ = 3.3 ± 0.3V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3V, Ta = –20 to 75 ° C Item S y mbol Min M ax Unit Figure TCK cycle time t T CKCYC 50 — ns 23.55 TCK high p ulse width t[...]

Rev. 5.00, 09/0 3, page 710 of 760 RESETP t TRSTS t TRSTH TRST Figure 23.56 T T T TR R R RS S S ST T T T Input Tim ing (Reset Hold) TCK TDI TMS t TDIS t TMSS t TDIH t TCKCYC t TMSH t TDOD TDO Figure 23.57 UDI Data Transfer Timing t ASEMD0S t ASEMD0H RESETP ASEMD0 Figure 23.58 A A A AS S S SE E E EM M M MD D D D0 0 0 0 Input Timing[...]

Rev. 5.00, 09/03, pa ge 711 of 760 23.3.10 AC Characteristics Measurement Co nditions • I/O sign al reference level: VccQ/ 2 (VccQ = 3.3 ± 0.3 V, V cc = 1.55 to 2.15 V) • Input pulse lev el: Vss to 3.0 V (where RESETP , RESETM , ASEND0 , IRLS3 to IRLS0 , IRL3 to IRL0 , ADTRG , P INT 1 5 to PI NT 0 , TRST , RxD1, C A, NMI, IRQ5 – IR Q0 , CKIO[...]

Rev. 5.00, 09/0 3, page 712 of 760 23.3.11 Delay Time Variati on Due to Load Capacitance A graph (reference data) of the variation in delay time when a load capacitance greater than that stipul a t e d (3 0 or 50 p F) i s co nnecte d to this L SI 's pi ns is sho w n bel ow. The gra ph shown in fig ure 23.6 0 should be taken int o c onsiderat i[...]

Rev. 5.00, 09/03, pa ge 713 of 760 23.4 A/D Converter Ch aracteristics Table 23.10 lists the A /D converter characteristics. Table 23.10 A/D Converter Characteristics VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.1 5 V, AV cc = 3.3 ± 0.3 V, Ta = –20 to 75° C Item Min T y p Max Unit Resolutio n 10 10 10 bits Conversio n time 15 —— µs Analog input ca[...]

Rev. 5.00, 09/0 3, page 714 of 760[...]

Rev. 5.00, 09/03, pa ge 715 of 760 Appendix A Pin Functions A.1 Pin States Table A.1 show s pin states during resets, pow er-down states, an d the bus-released st ate. Table A.1 Pin States during Resets, Po wer-Down States, and Bus-Released State Reset Power-Do wn Category Pin Power-On Reset Manual Reset Standby Sleep Bus Released E X T A L I IIII [...]

Rev. 5.00, 09/0 3, page 716 of 760 Reset Power-Do wn Category Pin Power-On Reset Manual Reset Standby Sleep Bus Released Address bus A[25:0] Z O ZL * 9 OZ D[15:0] Z I Z IO Z D[23:16]/PTA [7:0] Z IP * 2 ZK * 2 IOP * 2 ZP * 2 Data bus D[31:24]/PTB [7:0] Z IP * 2 ZK * 2 IOP * 2 ZP * 2 CS0 / MCS0 HO Z H * 10 OZ CS[2:4] /PTK[0:2] H OP * 2 ZH * 10 K * 2 [...]

Rev. 5.00, 09/03, pa ge 717 of 760 Reset Power-Do wn Category Pin Power-On Reset Manual Reset Standby Sleep Bus Released RxD0/SCPT[0] Z ZI * 6 ZI Z * 5 IZ * 5 TxD0/SCPT[0] Z ZO * 6 ZK * 2 OZ * 5 OZ * 5 SCI/Smart card without FIFO SCK0/SCPT[1] V ZP * 2 ZK * 2 IOP * 4 IOP * 4 RxD1/SCPT[2] Z ZI * 6 ZI Z * 5 IZ * 5 TxD1/SCPT[2] Z ZO * 6 ZK * 2 OZ * 5 O[...]

Rev. 5.00, 09/0 3, page 718 of 760 Reset Power-Do wn Category Pin Power-On Reset Manual Reset Standby Sleep Bus Released AN[5:0]/PTL[5:0] Z ZI * 6 ZI I Analog AN[6:7]/DA[1:0]/PTL[6:7 ] Z ZI * 6 OZ * 11 IO * 8 IO * 8 I: Input O: Outpu t H: High-level out put L: Low-lev el output Z: High impedance P: Input or ou tput depending o n register settin g K[...]

Rev. 5.00, 09/03, pa ge 719 of 760 A.2 Pin Sp ecifications Table A.2 shows the pin specifications. Table A.2 Pin Specifications Pin Pin No. (FP-208C, FP-208E) Pin No. (BP-240A) I/O Function MD5 197 C6 I Operating mode pin (end ian mod e) MD4, M D3 196, 195 D6, A7 I Operating mode pin ( area 0 bus width) MD2 to M D0 2, 1, 144 C2, D2,G19 I Operatin g[...]

Rev. 5.00, 09/0 3, page 720 of 760 Pin Pin No. (FP-208C, FP-208E) Pin No. (BP-240A) I/O Function A25 to A0 86, 84, 82 , 80, 78 to 72, 70, 68 to 60, 58, 56 to 53 V12, T12, V11, W 10, V10, U9, T9, V9, W 9, T8, U8, W 8, U7, V7, W 7, T6, U6, V6, W6, T5, U5, W 5, W4 , V 5 , V 3, V4 O Address bus D31 to D24/ PTB[7] to PTB[0] 13 to 18, 20, 22 F4, G1, G2, [...]

Rev. 5.00, 09/03, pa ge 721 of 760 Pin Pin No. (FP-208C, FP-208E) Pin No. (BP-240A) I/O Function CS2 /PTK[0] 98 T16 I/O Chip select 2 / I/O p ort CS0 / MCS0 96 T15 O Chip select 0 / Mask ROM chip select 0 BS /PTK[4] 87 W 12 I/O Bus cycle start / I/O port PTJ[5] 113 R17 I/O I/O port PTJ[4] 112 U17 I/O I/O port CASU /PTJ[3] 110 T17 I/O CAS(SDRAM) / I[...]

Rev. 5.00, 09/0 3, page 722 of 760 Pin Pin No. (FP-208C, FP-208E) Pin No. (BP-240A) I/O Function CKIO2/PT G [4] 129 L16 I/O System clock output / input port AUDATA[3]/ PTG[3] 130 L17 I AUD data / input por t AUDATA[2]/ PTG[2] 131 K18 I AUD data / input por t AUDATA[1]/ PTG[1] 133 K19 I AUD data / input por t AUDATA[0]/ PTG[0] 135 J18 I AUD data / i[...]

Rev. 5.00, 09/03, pa ge 723 of 760 Pin Pin No. (FP-208C, FP-208E) Pin No. (BP-240A) I/O Function CKIO 162 A15 I/O System clo ck I/O XTAL2 4 D1 O Crystal oscilla tor pin (for on-chip RTC) EXTAL2 5 D3 I Crystal osci llator pin (f or on-chip RTC) CKE/PTK[5] 105 T18 I/O CK enable for SDRAM / I/O port CA 194 B7 I Setting har dw are standby pin V CC Q 21[...]

Rev. 5.00, 09/0 3, page 724 of 760 A.3 Treatment of Unu sed Pin s • When RT C is no t use d  EXTAL2: Pull up (2.0/1.9/1.8/1.7 V)  XTAL2: Leave un connected  V CC –RTC: Pow er supply (2.0/1.9/1.8/ 1.7 V)  V SS –RTC: Power su pply (0 V) • When PLL2 is not used  CAP2: Leave unconnected  V CC –PLL 2: Power supply (2.0/1.9/1.[...]

Rev. 5.00, 09/03, pa ge 725 of 760 A.4 Pin States in Access to Each Add ress Space Table A.3 Pin States (Ordinary Memory/Little E ndian) 8-Bit Bus W idth 16-Bi t Bus Width Pin Byte/ Word/Long- word A ccess B yte A ccess (Address 2n) Byte A ccess (Address 2n + 1) Word/Longword A cces s CS6 to CS2 , CS 0 Enabled Enabled Enabled E nabled R Low Low Low[...]

Rev. 5.00, 09/0 3, page 726 of 760 32-Bit Bus Width Pin By te Ac c e s s (A ddres s 4n) By te A cces s (Address 4n + 1) By te A cces s (Address 4n + 2) By te Ac c e s s (A ddres s 4n + 3) Wor d Ac c e s s (Address 4n) Wor d A cces s (Address 4n + 2) Longword Ac c e s s CS6 to CS2 , CS 0 Enabled Enabl ed Enabled Enabled Enabled Enabled E nabled R Lo[...]

Rev. 5.00, 09/03, pa ge 727 of 760 Table A.4 Pin States (Ordinary Memory/Big Endian) 8-Bit Bus W idth 16-Bi t Bus Width Pin Byte/ Word/Long- word A ccess B yte A ccess (Address 2n) Byte A ccess (Address 2n + 1) Word/Longword A cces s CS6 to CS2 , CS 0 Enabled Enabled Enabled E nabled R Low Low Low Low RD W High High High Hig h R High High High High[...]

Rev. 5.00, 09/0 3, page 728 of 760 32-Bit Bus Width Pin By te Ac c e s s (A ddres s 4n) By te A cces s (Address 4n + 1) By te A cces s (Address 4n + 2) By te Ac c e s s (A ddres s 4n + 3) Wor d Ac c e s s (Address 4n) Wor d A cces s (Address 4n + 2) Longword Ac c e s s CS6 to CS2 , CS 0 Enabled Enabl ed Enabled Enabled Enabled Enabled E nabled R Lo[...]

Rev. 5.00, 09/03, pa ge 729 of 760 Table A.5 Pin States ( Burst RO M/Little Endian) 8-Bit Bus W idth 16-Bi t Bus Width Pin Byte/ Word/Long- word A ccess B yte A ccess (Address 2n) Byte A ccess (Address 2n + 1) Word/Longword A cces s CS6 to CS2 , CS 0 Enabled Enabled Enabled E nabled R Low Low Low Low RD W — ——— R High High High High RD/ WR [...]

Rev. 5.00, 09/0 3, page 730 of 760 32-Bit Bus Width Pin By te Ac c e s s (A ddres s 4n) By te A cces s (Address 4n + 1) By te A cces s (Address 4n + 2) By te Ac c e s s (A ddres s 4n + 3) Wor d Ac c e s s (Address 4n) Wor d A cces s (Address 4n + 2) Longword Ac c e s s CS6 to CS2 , CS 0 Enabled Enabl ed Enabled Enabled Enabled Enabled E nabled R Lo[...]

Rev. 5.00, 09/03, pa ge 731 of 760 Table A.6 Pin States (Burst ROM/Big En dian) 8-Bit Bus W idth 16-Bi t Bus Width Pin Byte/ Word/Long- word A ccess B yte A ccess (Address 2n) Byte A ccess (Address 2n + 1) Word/Longword A cces s CS6 to CS2 , CS 0 Enabled Enabled Enabled E nabled R Low Low Low Low RD W — ——— R High High High High RD/ WR W ?[...]

Rev. 5.00, 09/0 3, page 732 of 760 32-Bit Bus Width Pin By te Ac c e s s (A ddres s 4n) By te A cces s (Address 4n + 1) By te A cces s (Address 4n + 2) By te Ac c e s s (A ddres s 4n + 3) Wor d Ac c e s s (Address 4n) Wor d A cces s (Address 4n + 2) Longword Ac c e s s CS6 to CS2 , CS 0 Enabled Enabl ed Enabled Enabled Enabled Enabled E nabled R Lo[...]

Rev. 5.00, 09/03, pa ge 733 of 760 Table A.7 Pin States (Synchronous DRAM /Little Endian) 32-Bit Bus Width Pin By te A cces s (Address 4n) By te A cces s (Address 4n + 1) By te A cces s (Address 4n + 2) By te Ac c e s s (Address 4n + 3) Wor d A cces s (Address 4n) Wor d Ac c e s s (Address 4n + 2) Longword Ac c e s s CS6 to CS2 , CS0 Enabl ed Enabl[...]

Rev. 5.00, 09/0 3, page 734 of 760 Table A.8 Pin States (Synchronous DRAM/ Big En di an ) 32-Bit Bus Width Pin By te A cces s (Address 4n) By te Ac c e s s (Address 4n + 1) By te A cces s (Address 4n + 2) By te A cces s (A ddres s 4n + 3) Wor d A cces s (Address 4n) Wor d A cces s (Address 4n + 2) Longword Ac c e s s CS6 to CS2 , CS 0 Enabled Enabl[...]

Rev. 5.00, 09/03, pa ge 735 of 760 Table A.9 Pin States (PCMCIA/Little Endian) PCMCI A Memor y Interface ( Area 5) P CMCIA/IO Interface (Area 5) 8-Bit Bus Widt h 16-Bi t Bus Width 8-Bi t Bus Widt h 16-Bi t Bus Width Pin By te/ Wor d/ Long- wor d Ac c e s s By te A cces s (A d- dress 2n) By te A cces s (A d- dress 2n + 1) Wor d/ Long- wor d A cces s[...]

Rev. 5.00, 09/0 3, page 736 of 760 PCMCI A Memor y Interface ( Area 6) P CMCIA/IO Interface (Area 6) 8-Bit Bus Widt h 16-Bi t Bus Width 8-Bit Bus Widt h 16-Bi t Bus Width Pin By te/ Wor d/ Long- wor d A cces s By te A cces s (A d- dress 2n) By te A cces s (A d- dress 2n + 1) Wor d/ Long- wor d A cces s By te/ Wor d/ Long- wor d A cces s By te Ac c [...]

Rev. 5.00, 09/03, pa ge 737 of 760 Table A.10 Pin States (PCMCIA/Big Endian) PCMCI A Memory Interface (A rea 5) PCMCIA I/O Interface (A rea 5) 8-Bit Bus Widt h 16-Bi t Bus Width 8-Bi t Bus Widt h 16-Bi t Bus Width Pin By te/ Wor d/ Long- wor d Ac c e s s By te A cces s (A d- dress 2n) By te A cces s (A d- dress 2n + 1) Wor d/ Long- wor d A cces s B[...]

Rev. 5.00, 09/0 3, page 738 of 760 PCMCI A Memor y Interface ( Area 6) P CMCIA/IO Interface (Area 6) 8-Bit Bus Widt h 16-Bi t Bus Width 8-Bit Bus Widt h 16-Bi t Bus Width Pin By te/ Wor d/ Long- wor d A cces s By te A cces s (A d- dress 2n) By te A cces s (A d- dress 2n + 1) Wor d/ Long- wor d A cces s By te/ Wor d/ Long- wor d A cces s By te Ac c [...]

Rev. 5.00, 09/03, pa ge 739 of 760 Appendix B Memory-Mapped Control Registers B.1 Register Ad d ress Map Table B.1 M emory-Mapped Co ntrol Regist ers Control Register Module * 1 Bus * 2 Address * 4 Size (Bits) A ccess Size (Bits) 3. PTEH CCN L FFFFFFF0 32 32 PTEL CCN L FFFFFFF4 32 32 TTB CCN L FFFFFFF8 3 2 32 TEA CCN L FFFFFFFC 32 32 MMUCR CCN L FF[...]

Rev. 5.00, 09/0 3, page 740 of 760 Control Register Module * 1 Bus * 2 Address * 4 Size (Bits) A ccess Size (Bits) * 3 W TCSR CPG I FFFFFF86 8 16 BCR1 BSC I FFFFFF60 16 16 BCR2 BSC I FFFFFF62 16 16 W CR1 BSC I FFFFFF64 16 16 W CR2 BSC I FFFFFF66 16 16 MCR BSC I FFFFFF68 1 6 16 PCR BSC I FFFFFF6C 16 16 RTCSR BSC I FFFFFF6E 1 6 16 RTCNT BSC I FFFFFF7[...]

Rev. 5.00, 09/03, pa ge 741 of 760 Control Register Module * 1 Bus * 2 Address * 4 Size (Bits) A ccess Size (Bits) * 3 R W KAR RTC P FFFFFED6 8 8 RDAYAR RTC P FFFFFED8 8 8 RMONAR RTC P FFFFFEDA 8 8 RCR1 RTC P FFFFFEDC 8 8 RCR2 RTC P FFFFFEDE 8 8 ICR0 INTC I FFFFFEE0 16 16 IPRA INTC I FFFFFEE2 16 16 IPRB INTC I FFFFFEE4 16 16 TOCR TMU P FFFFFE90 8 8[...]

Rev. 5.00, 09/0 3, page 742 of 760 Control Register Module * 1 Bus * 2 Address * 4 Size (Bits) A ccess Size (Bits) * 3 ICR1 INTC I 4000010 16 16 ICR2 INTC I 4000012 16 16 PINTER INTC I 4000014 16 16 IPRC INTC I 4000016 16 16 IPRD INTC I 4000018 16 16 IPRE INTC I 400001A 16 16 SAR0 DMAC P 4000020 32 16,32 DAR0 DMAC P 4000024 32 16,32 DMATCR0 DMAC P [...]

Rev. 5.00, 09/03, pa ge 743 of 760 Control Register Module * 1 Bus * 2 Address * 4 Size (Bits) A ccess Size (Bits) * 3 ADDRCL A/D P 400008A 8 8,16 * 5 ADDRDH A/D P 400008C 8 8,16,32 * 5 * 6 ADDRDL A/D P 400008E 8 8,16 * 5 ADCSR A/D P 4000090 8 8,16,32 * 5 * 6 ADCR A/D P 4000092 8 8,16 DADR0 D/A P 40000A 0 8 8,16,32 * 5 * 6 DADR1 D/A P 40000A 2 8 8,[...]

Rev. 5.00, 09/0 3, page 744 of 760 Control Register Module * 1 Bus * 2 Address * 4 Size (Bits) A ccess Size (Bits) * 3 SCSMR1 IrDA P 4000140 8 8 SCBRR1 IrDA P 4000142 8 8 SCSCR1 IrDA P 4000144 8 8 SCFTDR1 IrDA P 4000146 8 8 SCSSR1 IrDA P 4000148 16 16 SCFRDR1 IrDA P 400014A 8 8 SCFCR1 IrDA P 400014C 8 8 SCFDR1 IrDA P 400014E 16 16 SCSMR2 SCIF P 400[...]

Rev. 5.00, 09/03, pa ge 745 of 760 B.2 Regi ster Bits Table B.2 Register Bits Regist er Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ———— SDMR BSC SCSMR C/A CHR PE O/E STOP M P CKS1 CKS0 SCI SCBRR SCI SCSCR TIE RIE TE R E MPIE TEIE CKE1 CKE0 SCI SCTDR SCI SCSSR TDRE RDRF ORE R FE R PER TEND MPB MPBT S CI SCRDR SCI SCSCM R — — [...]

Rev. 5.00, 09/0 3, page 746 of 760 Regist er Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ——————— U N F TCR1 — — UNIE CKEG1 CKEG 0 TPSC2 TPSC1 TPSC0 TMU TCOR2 TMU TCNT2 TMU —————— I C P F U N F T CR2 ICPE1 ICPE0 UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMU TCPR2 TMU R64CNT — 1 Hz 2 Hz 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz [...]

Rev. 5.00, 09/03, pa ge 747 of 760 Regist er Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module RCR1 CF — — CI E AIE — — A F RT C RCR2 P EF PES2 PES1 PES0 RTCEN ADJ RESET ST ART RTC N M L ——— ——— N M I E ICR0 ——————— — INTC TMU0 TM U1 IPRA TMU2 RTC INTC WD T REF IPRB S C I ———— INTC PULA PUL D HIZMEM [...]

Rev. 5.00, 09/0 3, page 748 of 760 Regist er Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ——— — — — — — RFCR BSC STC2 IF C2 PFC2 — — — SLPFRQ CKOEN FRQCR PLLEN PSTBY STC1 STC0 IFC1 IFC0 PFC1 PFC0 CPG STBCR STBY — — STBXTL — MSTP2 MSTP1 MSTP0 CPG STBCR2 MSTP9 MDCHG MST P8 MSTP7 MSTP6 MSTP 5 MSTP4 MSTP 3 CPG W T[...]

Rev. 5.00, 09/03, pa ge 749 of 760 Regist er Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module BAMRA UBC ——————— — BBRA CDA1 CDA0 IDA1 IDA0 RWA1 RW A0 SZA 1 S ZA0 UBC ———— BETR UBC SVF PID2 PID1 PID0 BSA27 BS A26 BSA25 BSA2 4 BSA23 BSA2 2 BSA21 BS A20 BSA19 BSA1 8 BSA17 BSA16 BSA15 BSA1 4 BSA13 BS A12 BSA11 BSA1 0 BS A9[...]

Rev. 5.00, 09/0 3, page 750 of 760 Regist er Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module BASRA UBC BASRB UBC —————— — — —————— — — —————— — — CCR — — 0 0 CF CB WT CE CCN W3 LO AD W3 L OC K CDR2 W2 LO AD W2 L OC K CCN —— PTEH CCN —V PTEL —P R P R S Z C D S H — CCN TTB CCN TEA C[...]

Rev. 5.00, 09/03, pa ge 751 of 760 Regist er Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module IRR0 PINT0R P INT1R IRQ5R IRQ4R IRQ3R I RQ2R IRQ1R I RQ0R INTC IRR1 TXI1R BRI1R R XI1R ERI 1R DEI 3R DEI2R DE I1R DE I0R INTC IRR2 — — — A D I R TXI 2 R B R I 2R R XI 2 R E R I 2R INTC MAI IRQLVL BLMSK — I RQ51S IRQ50S IRQ41S I RQ40S ICR1 IRQ[...]

Rev. 5.00, 09/0 3, page 752 of 760 Regist er Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ——————— — ————— R L A M A L DM1 DM0 S M1 SM0 RS3 RS2 RS1 RS 0 CHCR0 —D S T M T S 1 T S 0 I E T E D E DMAC SAR1 DMAC DAR1 DMAC ——————— — DMATCR1 DMAC ——————— — ————— R L A M A L DM1[...]

Rev. 5.00, 09/03, pa ge 753 of 760 Regist er Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ——————— — ———— R O ——— DM1 DM0 S M1 SM0 RS3 RS2 RS1 RS 0 CHCR2 — — TM TS1 TS0 IE TE DE DMAC SAR3 DMAC DAR3 DMAC ——————— — DMATCR3 DMAC ——————— — ———D I ———— DM1 DM0 S M1 [...]

Rev. 5.00, 09/0 3, page 754 of 760 Regist er Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A /DC ADDRBL AD1 AD0 — — — — — — A/DC ADDRCH A D9 AD8 A D7 AD6 A D5 AD4 AD3 AD2 A /DC ADDRCL AD1 A D0 — — — — — — A /DC ADDRDH A D9 AD8 A D7 AD6 A D5 AD4 AD3 AD2 A /DC ADDRDL AD1 A D0 —[...]

Rev. 5.00, 09/03, pa ge 755 of 760 Regist er Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PG7M D1 PG7M D0 PG6M D1 PG6M D0 PG5M D1 PG5M D0 PG4M D1 PG4M D0 PGCR PG3M D1 PG3M D0 PG2M D1 PG2M D0 PG1M D1 PG1M D0 PG0M D1 PG0M D0 PORT PH7M D1 PH7M D0 PH6M D1 PH6M D0 PH5M D1 PH5M D0 PH4M D1 PH4M D0 PHCR PH3M D1 PH3M D0 PH2M D1 PH2M D0 PH1M D1 PH1[...]

Rev. 5.00, 09/0 3, page 756 of 760 Register BIT7 BI T6 BIT5 BIT4 BIT3 BIT2 BI T1 BIT0 Mod ule TI3 TI2 TI1 TI0 — — — — SDIR ——————— — UDI SCSMR1 IRM0D ICK3 ICK2 I CK1 ICK0 PSEL CKS1 CKS0 I rDA SCBRR1 Ir DA SCSCR1 TIE RIE TE RE — — CKE1 CKE0 IrD A SCFTDR1 IrDA PER3 PER2 PER1 PER0 FER3 FER2 FER1 FER0 SCSSR1 ER TEND TDFE BRK[...]

Rev. 5.00, 09/03, pa ge 757 of 760 Appendix C Product Lineup Table C .1 SH7709S Models Power Sup ply Voltage Ab b r . I/O Internal Operating Frequency Model Marking P ackage 2.0±0.15 V 200 MHz HD6417709SHF200B 208-pin plas tic HQFP (FP-208E) HD6417709SF167B 208-pin pla stic LQFP (FP-208C) 1.9±0.15 V 167 MHz HD6417709SBP167B 240-pin CSP (BP-24 0A)[...]

Rev. 5.00, 09/0 3, page 758 of 760 Appendix D Package Dimensions Figures D.1 to D.3 s how th e SH7709S pack age dimensi ons. Package Code JEDEC JEITA Mass (reference value) FP-208C − Conforms 2.7 g * Dimension including the plating thickness Base material dimension 30.0 ± 0.2 30.0 ± 0.2 0.5 1.70 Max 0° − 8° * 0.17 ± 0.05 156 105 104 52 1 1[...]

Rev. 5.00, 09/03, pa ge 759 of 760 Package Code JEDEC JEITA Mass (reference value) FP-208E − Conforms 5.3 g * Dimension including the plating thickness Base material dimension 30.6 ± 0.2 30.6 ± 0.2 0.5 3.56 Max 0 ° − 8 ° * 0.17 ± 0.05 156 105 104 52 1 157 208 53 * 0.22 ± 0.05 0.10 M 0.10 3.20 0.5 ± 0.1 1.3 28 0.15 +0.10 − 0.15 1.25 0.2[...]

Rev. 5.00, 09/0 3, page 760 of 760 0.65 0.65 13.00 13.00 0.15 4 × 0.2 C C 0.10 C 0.65 0.33 ± 0.05 1.40Max B A D C F E H G K J M L P N T R V U W 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 0.20 C A 0.20 C B B C φ 0.08 AB 240 × φ 0.40 ± 0.05 M 0.65 A Unit: mm Package Code JEDEC JEITA Mass (reference value) BP-240A − − 0.4 g Figure D.3 P[...]

SH7709S Group Hardware Manual Publicat ion Da te: 1st Editi on, Septem ber 2001 Rev.5.00 , Septem ber 18, 2003 Publish ed by: Sales Stra tegic P lanni ng D iv . Renesas T echno logy Cor p. Edited by: T ec hnical Docum entat ion & Inf orm ation Dep artm ent Renesas Kod aira Sem iconduct or Co., Ltd . ©2001, 200 3 Renes as T echnolog y Corp. A l[...]

Colophon 1.0 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, [...]

SH7709S Grou p Hardware M anual REJ09B0081-0500O (ADE-602-250C)[...]