Sony ICX418AKL manuale d’uso

– 1 – E01503B41 Sony reserves the right to change products and specifications without prior notice. This information does not conv ey an y licens e by any implication or otherwise under any patents or other right. Application circuits shown, if an y , are typical e xamples illustr ating the operation of the de vices. Sony cannot assume responsi[...]

– 2 – ICX418AKL USE RESTRICTION NO TICE (December 1, 2003 ver .) This USE RESTRICTION NO TICE ("Notice") is for customers who are considering or currently using the CCD products ("Products") set f or th in this specifications book. Sony Cor poration ("Sony") ma y , at any time , modify this Notice which will be av [...]

– 3 – ICX418AKL Block Dia gram and Pin Configuration (T op Vie w) 11 12 13 14 15 16 17 18 19 20 Note) : Photo sensor NC V DSUB NC GND GND RD φ RG NC H φ 1 H φ 2 10 9 8 7 6 5 4 3 2 1 V OUT V DD GND V L V φ 1 GND φ SUB V φ 2 V φ 3 V φ 4 Note) Horizontal Register V ertical Register Cy Cy Mg G Cy Mg Cy Cy Mg G Cy Mg Ye Ye G Mg Ye G Ye Ye G [...]

– 4 – ICX418AKL Absolute Maximum Ratings Item Substrate cloc k φ SUB – GND Supply v oltage Clock input v oltage V oltage difference betw een ver tical clock input pins V oltage difference between horizontal cloc k input pins H φ 1 , H φ 2 – V φ 4 φ RG – GND φ RG – φ SUB V L – φ SUB Pins other than GND and φ SUB – V L Storag[...]

– 5 – ICX418AKL DC Characteristics Output circuit supply current Item I DD Symbol 5.0 Min. Unit Remarks T yp . Max. mA 10.0 Bias Conditions 1 [when used in substrate bias internal generation mode] Output circuit supply voltage Reset drain v oltage Protectiv e transistor bias Substrate bias circuit supply v oltage Substrate cloc k ∗ 1 V L sett[...]

– 6 – ICX418AKL Clock V oltage Conditions ∗ 1 Input the reset gate clock without applying a DC bias . In addition, the reset gate clock can also be driv en with the fo llowing specifications . Readout clock v oltage V er tical transfer cloc k v oltage Horizontal transf er clock v oltage Reset gate clock voltage ∗ 1 Substrate clock voltage I[...]

– 7 – ICX418AKL Horizontal transfer c lock equivalent cir cuit V ertical transfer cloc k equivalent circuit H φ 1 H φ 2 C φ H1 C φ H2 C φ HH V φ 1 C φ V12 V φ 2 V φ 4 V φ 3 C φ V34 C φ V23 C φ V41 C φ V1 C φ V2 C φ V4 C φ V3 R GND R 4 R 1 R 3 R 2 Clock Equiv alent Circuit Constant C φ V1 , C φ V3 C φ V2 , C φ V4 C φ V12 , [...]

– 8 – ICX418AKL Drive Clock W aveform Conditions (1) Readout cloc k waveform (2) V er tical transfer cloc k waveform V VH = (V VH1 + V VH2 )/2 V VL = (V VL3 + V VL4 )/2 V φ V = V VH n – V VL n (n = 1 to 4) 100% 90% 10% 0% tr tf 0V twh φ M 2 φ M V VT V VH1 V VHH V VHL V VH V VLH V VL1 V VLL V VHL V VHH V VL V VHH V VH V VLH V VLL V VL V VHL[...]

– 9 – ICX418AKL (3) Horizontal transfer cloc k waveform (4) Reset gate cloc k waveform V RGLH is the maximum v alue and V RGLL is the minimum v alue of the coupling wa vef or m during the per iod from P oint A in the abov e diagram until the rising edge of RG. In addition, V RGL is the av erage value of V RGLH and V RGLL . V RGL = (V RGLH + V R[...]

– 10 – ICX418AKL Clock Switc hing Characteristics ∗ 1 When vertical transfer cloc k dr iver CXD1267AN is used. ∗ 2 tf ≥ tr – 2ns. ∗ 3 The ov er lap period for twh and twl of horizontal transf er clocks H φ 1 and H φ 2 is two . Min. two T yp . Max. 16 20 Unit ns Remarks Item Horizontal transfer cloc k Symbol H φ 1 , H φ 2 ∗ 3 Min[...]

– 11 – ICX418AKL Image Sensor Characteristics Item Sensitivity Saturation signal Smear Video signal shading Unif ormity between video signal channels Dark signal Dark signal shading Flick er Y Flick er R-Y Flick er B-Y Line cra wl R Line cra wl G Line cra wl B Line cra wl W Lag Symbol S Ysat Sm SHy ∆ Sr ∆ Sb Ydt ∆ Ydt Fy Fcr Fcb Lcr Lcg L[...]

– 12 – ICX418AKL Image Sensor Characteristics Measurement Method Measurement conditions 1) In the f ollowing measurements, the de vice dr iv e conditions are at the typical values of the bias and clock voltage conditions . (when used with substrate bias e xter nal adjustment, set the substrate v oltage to the v alue indicated on the device .) 2[...]

– 13 – ICX418AKL Definition of standard ima ging conditions 1) Standard imaging condition I : Use a pattern box (luminance 706cd/m 2 , color temperature of 3200K halogen source) as a subject. (P attern f or e valuation is not applicab le.) Use a testing standard lens with CM500S (t = 1.0mm) as an I R cut filter and image at F5.6. The luminous i[...]

– 14 – ICX418AKL 7. Dark signal shading After measuring 6, measure the maximum (Ydmax [mV]) and minimum (Ydmin [mV]) values of the dark signal output and substitute the values into the f ollowing f or mula. ∆ Ydt = Ydmax – Ydmin [mV] 8. Flick er 1) Fy Set to standard imaging condition II . Adjust the luminous intensity so that the av erage [...]

– 15 – ICX418AKL Drive Circuit 1 (substrate bias internal generation mode) 22/16V 0.01 –9V 3.3/16V 3.3/20V 0.01 1/35V 1 100 H φ 1 H φ 2 NC φ RG RD GND GND NC V DSUB NC 22/20V CCD OUT [ ∗ A] 15V XSUB XV2 XV1 XSG1 XV3 XSG2 XV4 H φ 2 H φ 1 RG 100k 0.01 CXD1267AN 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 3.9k V φ 4 V φ 3 V φ 2 [...]

– 16 – ICX418AKL Drive Circuit 2 (substrate bias e xternal adjustment mode) 22/16V 0.01 –9V 3.3/16V 3.3/20V 0.01 1/35V 0.1 100 H φ 1 H φ 2 NC φ RG RD GND GND NC V DSUB NC 22/20V CCD OUT [ ∗ A] 15V XSUB XV2 XV1 XSG1 XV3 XSG2 XV4 H φ 2 H φ 1 RG 27k 0.01 CXD1267AN 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 3.9k 0.1 39k 15k 47k 15k[...]

– 17 – ICX418AKL Spectral Sensitivity Characteristics (Excludes lens characteristics and light source characteristics) Sensor Readout Clock Timing Char t Unit: µs Odd Field Even Field V1 V2 V3 V4 V1 V2 V3 V4 2.5 2.5 2.5 2.5 33.5 1.6 0.2 1.0 0.8 0.6 0.4 0.2 0 400 450 500 Cy Ye Mg G 550 W ave Length [nm] Relative Response 600 650 700[...]

– 18 – ICX418AKL Drive Timing Char t (V er tical Sync) 520 525 1 2 3 4 5 10 15 20 493 494 260 265 270 275 280 494 493 2 1 4 3 6 5 2 1 4 3 6 5 FLD VD BLK HD V1 V2 V3 V4 CCD OUT 13 5 24 6 135 24 6[...]

– 19 – ICX418AKL Drive Timing Char t (Horizontal Sync) 760 768 1 2 3 5 10 20 30 40 1 2 3 5 10 20 22 1 2 3 1 2 3 10 20 HD BLK H1 H2 RG V1 V2 V3 V4 SUB[...]

– 20 – ICX418AKL Notes on Handling 1) Static charge pre vention CCD image sensors are easily damaged by static discharge . Before handling be sure to tak e the fo llowing protectiv e measures. a) Either handle bare handed or use non-chargeab le glov es, clothes or material. Also use conductive shoes . b) When handling directly use an ear th ban[...]

– 21 – ICX418AKL c) The adhesiv e may cause the marking on the rear surf ace to disappear , especially in case the regulated v oltage value is indicated on the rear surf ace. Therefore, the adhesiv e should not be applied to this area, and indicated v alues should be transferred to other locations as a precaution. d) The upper and lower cer ami[...]

– 22 – ICX418AKL P acka ge Outline Unit: mm Sony Corporation 0.3 M P ACKA GE STR UCTURE P ACKA GE MA TERIAL LEAD TREA TMENT LEAD MA TERIAL P ACKA GE MASS Cer-DIP TIN PLA TING 42 ALLO Y 2.6g DRA WING NUMBER AS-B14-01(E) A 1 1 0˚ to 9˚ H V C B ~ ~ 20pin DIP (600mil) 20 10 11 10 11 20 (0.7R) φ 1.4 15.24 0.25 18.0 ± 0.4 9.0 7.55 15.1 ± 0.3 1.2[...]