Texas Instruments TMS320C642x DSP manuale d’uso

TMS320C642x DSP DDR2 Memory Controller User's Guide Literature Number: SPRUEM4A November 2007[...]

2 SPRUEM4A – November 2007 Submit Documentation Feedback[...]

Contents Preface ............................................................................................................................... 6 1 Introduction ................................................................................................................ 7 1.1 Purpose of the Peripheral ...........................................[...]

List of Figures 1 Data Paths to DDR2 Memory Controller .................................................................................. 8 2 DDR2 Memory Controller Clock Block Diagram ......................................................................... 9 3 DDR2 Memory Controller Signals ........................................................[...]

List of Tables 1 PLLC2 Configuration ....................................................................................................... 10 2 DDR2 Memory Controller Signal Descriptions ......................................................................... 11 3 DDR2 SDRAM Commands ..............................................................[...]

Preface SPRUEM4A – November 2007 Read This First About This Manual This document describes the DDR2 memory controller in the TMS320C642x Digital Signal Processor (DSP). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (deci[...]

1 Introduction 1.1 Purpose of the Peripheral 1.2 Features User's Guide SPRUEM4A – November 2007 DDR2 Memory Controller This document describes the DDR2 memory controller in the TMS320C642x Digital Signal Processor (DSP). The DDR2 memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM devices. Memories types such[...]

www.ti.com 1.3 Functional Block Diagram SCR DDR2 memory controller BUS BUS External DDR2 SDRAM DSP Master peripherals EDMA VPSS 1.4 Supported Use Case Statement 1.5 Industry Standard(s) Compliance Statement Introduction The DDR2 memory controller is the main interface to external DDR2 memory. Figure 1 displays the general data paths to on-chip peri[...]

www.ti.com 2 Peripheral Architecture 2.1 Clock Control 2.1.1 Clock Source DDR2 memory controller /2 PLLC2 /3 PLLC1 X2_CLK VCLK DDR_CLK DDR_CLK PLL2_SYSCLK1 SYSCLK2 Peripheral Architecture This section describes the architecture of the DDR2 memory controller as well as how it is structured and how it works within the context of the system-on-a-chip.[...]

www.ti.com 2.1.2 Clock Configuration 2.1.3 DDR2 Memory Controller Internal Clock Domains 2.2 Memory Map Peripheral Architecture The frequency of PLL2_SYSCLK1 is configured by selecting the appropriate PLL multiplier and divider ratio. The PLL multiplier and divider ratio are selected by programming registers within PLLC2. Table 1 shows a list of PL[...]

www.ti.com 2.3 Signal Descriptions DDR_D[31:0] DDR2 memory controller DDR_CLK DDR_CLK DDR_CS DDR_CKE DDR_RAS DDR_WE DDR_DQM[3:0] DDR_CAS DDR_BA[2:0] DDR_DQS[3:0] DDR_A[12:0] DDR_ZN DDR_ZP 200 Ω 200 Ω Peripheral Architecture The DDR2 memory controller signals are shown in Figure 3 and described in Table 2 . The following features are included: ?[...]

www.ti.com 2.4 Protocol Description(s) Peripheral Architecture The DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 3 . Table 4 shows the signal truth table for the DDR2 SDRAM commands. Table 3. DDR2 SDRAM Commands Command Function ACTV Activates the selected bank and row. DCAB Precharge all command. Deactivates (precharges) [...]

www.ti.com 2.4.1 Refresh Mode DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_A[12:0] DDR_BA[2:0] DDR_DQM[3:0] RFR DDR_CLK Peripheral Architecture The DDR2 memory controller issues refresh commands to the DDR2 SDRAM memory ( Figure 4 ). REFR is automatically preceded by a DCAB command, ensuring the deactivation of all CE spaces and banks selected[...]

www.ti.com 2.4.2 Deactivation (DCAB and DEAC) DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_WE DDR_A[12,1 1, 9:0] DDR_BA[2:0] DDR_DQM[3:0] DCAB DDR_A[10] DDR_CAS DDR_CLK Peripheral Architecture The precharge all banks command (DCAB) is performed after a reset to the DDR2 memory controller or following the initialization sequence. DDR2 SDRAMs also require this[...]

www.ti.com DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_WE DDR_A[12,1 1, 9:0] DDR_BA[2:0] DDR_DQM[3:0] DEAC DDR_A[10] DDR_CAS DDR_CLK Peripheral Architecture The DEAC command closes a single bank of memory specified by the bank select signals. Figure 6 shows the timings diagram for a DEAC command. Figure 6. DEAC Command SPRUEM4A – November 2007 DDR2 Memory[...]

www.ti.com 2.4.3 Activation (ACTV) DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_WE DDR_BA[2:0] DDR_DQM[3:0] ACTV DDR_A[12:0] DDR_CAS BANK ROW DDR_CLK Peripheral Architecture The DDR2 memory controller automatically issues the activate (ACTV) command before a read or write to a closed row of memory. The ACTV command opens a row of memory, allowing future acce[...]

www.ti.com 2.4.4 READ Command DDR_CLK DDR_CKE DDR_CS DDR_WE DDR_CAS DDR_DQM[3:0] DDR_D[31:0] DDR_A[12:0] DDR_RAS DDR_DQS[3:0] COL BANK DDR_A[10] DDR_BA[2:0] CAS Latency D0 D1 D2 D3 D4 D5 D6 D7 DDR_CLK Peripheral Architecture Figure 8 shows the DDR2 memory controller performing a read burst from DDR2 SDRAM. The READ command initiates a burst read op[...]

www.ti.com 2.4.5 Write (WRT) Command DDR_CLK DDR_CKE DDR_CS DDR_WE DDR_CAS DDR_DQM[3:0] DDR_D[31:0] DDR_A[12:0] DDR_RAS DDR_DQS[3:0] COL BANK DDR_A[10] DDR_BA[2:0] DQM7 Sample D0 D1 D2 D3 D4 D5 D6 D7 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM8 Write Latency DDR_CLK Peripheral Architecture Prior to a WRT command, the desired bank and row are activated by the[...]

www.ti.com 2.4.6 Mode Register Set (MRS and EMRS) DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_WE DDR_BA[2:0] COL MRS/EMRS DDR_A[12:0] DDR_CAS BANK DDR_CLK Peripheral Architecture DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory for operation. These registers control burst type, burst length, CAS latency, DLL enable/disable[...]

www.ti.com 2.5 Memory Width and Byte Alignment DDR2 memory controller data bus DDR_D[31:24] DDR_D[23:16] DDR_D[15:8] DDR_D[7:0] 32-bit memory device 16-bit memory device Peripheral Architecture The DDR2 memory controller supports memory widths of 16 bits and 32 bits. Table 5 summarizes the addressable memory ranges on the DDR2 memory controller. Se[...]

www.ti.com 2.6 Endianness Support Peripheral Architecture The DDR2 memory controller supports both big-endian and little-endian operating modes. The endianness mode selection at the time of an access determines the order in which data on the internal data bus is written to or read from devices that are not as wide as the internal data bus. However,[...]

www.ti.com 2.7 Address Mapping Peripheral Architecture The DDR2 memory controller views external DDR2 SDRAM as one continuous block of memory. This statement is true regardless of the number of external physical devices mapped to a given chip select space. The DDR2 memory controller receives DDR2 memory access requests along with a 32-bit logical a[...]

www.ti.com Peripheral Architecture Table 9. Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM SDBCR Bit Logical Address (1) IBANK PAGESIZE 31 30 29 28 27 26 25 24 23 22:16 15 14 13 12 11 10 9:2 1:0 0 0 - nrb=13 ncb=8 1 0 - nrb=13 nbb=1 ncb=8 2h 0 - nrb=13 nbb=2 ncb=8 3h 0 - nrb=13 nbb=3 ncb=8 0 1 - nrb=13 ncb=9 1 1 - nrb=13 nbb=1 ncb=9 2h [...]

www.ti.com Col. 0 Col. 1 Col. 2 Col. 3 Col. 4 Col. M−1 Col. M Row 0, bank 0 Row 0, bank 1 Row 0, bank 2 Row 0, bank P Row 1, bank 1 Row 1, bank 0 Row 1, bank 2 Row 1, bank P Row N, bank 2 Row N, bank 1 Row N, bank 0 Row N, bank P Peripheral Architecture Figure 12. Logical Address-to-DDR2 SDRAM Address Map NOTE: M is number of columns (as determin[...]

www.ti.com 0 1 2 3 M Bank 0 Row 0 Row 1 Row 2 Row N C o l l C o l C o l C o Row 0 Row N Row 1 Row 2 C C Bank 1 l l 0 2 1 o o C C l l 3 M o o Row 0 Row N Row 1 Row 2 C C Bank 2 l l 0 2 1 o o l l l l Row N Row 2 Row 0 Row 1 Bank P 0123 M C C l l 3 M o o o C o C o C o C Peripheral Architecture Figure 13. DDR2 SDRAM Column, Row, and Bank Access NOTE: M[...]

www.ti.com 2.8 DDR2 Memory Controller Interface Command/Data Scheduler Command FIFO W rite FIFO Read FIFO Registers Command to Memory W rite Data to Memory Read Data from Memory Command Data Peripheral Architecture To move data efficiently from on-chip resources to external DDR2 SDRAM memory, the DDR2 memory controller makes use of a command FIFO, [...]

www.ti.com 2.8.1 Command Ordering and Scheduling, Advanced Concept Peripheral Architecture The DDR2 memory controller performs command re-ordering and scheduling in an attempt to achieve efficient transfers with maximum throughput. The goal is to maximize the utilization of the data, address, and command buses while hiding the overhead of opening a[...]

www.ti.com 2.8.2 Command Starvation 2.8.3 Possible Race Condition Peripheral Architecture The reordering and scheduling rules listed above may lead to command starvation, which is the prevention of certain commands from being processed by the DDR2 memory controller. Command starvation results from the following conditions: • A continuous stream o[...]

www.ti.com 2.9 Refresh Scheduling 2.10 Self-Refresh Mode Peripheral Architecture The DDR2 memory controller issues autorefresh (REFR) commands to DDR2 SDRAM devices at a rate defined in the refresh rate (RR) bit field in the SDRAM refresh control register (SDRCR). A refresh interval counter is loaded with the value of the RR bit field and decrement[...]

www.ti.com 2.11 Reset Considerations DDR2 memory controller registers Hard Reset from PLLC1 State machine VRST VCTL_RST DDR PSC Peripheral Architecture Once in self-refresh mode, the DDR2 memory controller input clocks (VCLK and X2_CLK) may be gated off or changed in frequency. Stable clocks must be present before exiting self-refresh mode. See Sec[...]

www.ti.com 2.12 VTP IO Buffer Calibration 2.13 Auto-Initialization Sequence Peripheral Architecture The DDR2 memory controller is able to control the impedance of the output IO. This feature allows the DDR2 memory controller to tune the output impedance of the IO to match that of the PCB board. Control of the output impedance of the IO is an import[...]

www.ti.com 2.13.1 Initializing Configuration Registers Peripheral Architecture Table 14. DDR2 SDRAM Configuration by MRS Command DDR2 Memory Controller DDR2 SDRAM Address Bus Value Register Bit DDR2 SDRAM Field Function Selection DDR_A[12] 0 12 Power Down Exit Fast exit DDR_A[11:9] t_WR 11:9 Write Recovery Write recovery from autoprecharge. Value o[...]

www.ti.com 2.13.2 Initializing Following Device Power Up and Device RESET Peripheral Architecture CAUTION The following power-up sequence is preliminary and is documented to reflect the intended-use case. This power-up sequence may change at a future date. Following device power up, the DDR2 memory controller is held in reset with the internal cloc[...]

www.ti.com 2.14 Interrupt Support 2.15 DMA Event Support 2.16 Power Management PLLC2 CLKSTOP_REQ DDR PSC CLKSTOP_ACK MODCLK MODRST LRST DDR2 memory controller VCLKSTOP_REQ VCLKSTOP_ACK VCLK VRST VCTL_RST X2_CLK /2 SYSCLK2 PLL2_SYSCLK1 Peripheral Architecture The DDR2 memory controller supports two addressing modes, linear incrementing and cache lin[...]

www.ti.com 2.16.1 DDR2 Memory Controller Clock Stop Procedure 2.17 Emulation Considerations Peripheral Architecture CAUTION The following clock stop procedures are preliminary and are documented to reflect the intended-use cases. These clock stop procedures may change at a future date. Note: If an access occurs to the DDR2 memory controller after c[...]

www.ti.com 3 Supported Use Cases 3.1 Connecting the DDR2 Memory Controller to DDR2 Memory 3.2 Configuring Memory-Mapped Registers to Meet DDR2-400 Specification Supported Use Cases The DDR2 memory controller allows a high degree of programmability for shaping DDR2 accesses. The programmability inherent to the DDR2 memory controller provides the DDR[...]

www.ti.com DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_WE DDR_RAS DDR_CAS DDR_DQM[0] DDR_DQM[1] DDR_DQS[0] DDR_DQS[1] DDR_BA[2:0] DDR_A[12:0] DDR_D[15:0] DDR_DQM[2] DDR_DQM[3] DDR_DQS[2] DDR_DQS[3] DDR_D[31:16] DDR_ZN DDR_ZP DDR2 memory CK CK CKE CS WE RAS CAS LDM UDM LDQS UDQS BA[2:0] A[12:0] DQ[15:0] DDR2 memory x16−bit LDQS DQ[15:0] A[12:0] BA[2:0] UDQ[...]

www.ti.com 3.2.1 Configuring SDRAM Bank Configuration Register (SDBCR) 3.2.2 Configuring SDRAM Refresh Control Register (SDRCR) Supported Use Cases The SDRAM bank configuration register (SDBCR) contains register fields that configure the DDR2 memory controller to match the data bus width, CAS latency, number of banks, and page size of the attached [...]

www.ti.com 3.2.3 Configuring SDRAM Timing Registers (SDTIMR and SDTIMR2) Supported Use Cases The SDRAM timing register (SDTIMR) and SDRAM timing register 2 (SDTIMR2) configure the DDR2 memory controller to meet the data sheet timing parameters of the attached DDR2 device. Each field in SDTIMR and SDTIMR2 corresponds to a timing parameter in the DDR[...]

www.ti.com 3.2.4 Configuring DDR PHY Control Register (DDRPHYCR) Supported Use Cases The DDR PHY control register (DDRPHYCR) contains a read latency (READLAT) field that helps the DDR2 memory controller determine when to sample read data. The READLAT field should be programmed to a value equal to CAS latency plus round trip board delay minus 1. The[...]

www.ti.com 4 DDR2 Memory Controller Registers DDR2 Memory Controller Registers Table 22 lists the memory-mapped registers related to the DDR2 memory controller. See the device-specific data manual for the memory addresses of these registers. The DDR2 memory controller peripheral interfaces to the CPU using a 64-bit data bus, and supports both big-e[...]

www.ti.com 4.1 SDRAM Status Register (SDRSTAT) DDR2 Memory Controller Registers The SDRAM status register (SDRSTAT) is shown in Figure 19 and described in Table 25 . Figure 19. SDRAM Status Register (SDRSTAT) 31 30 16 BE Reserved R-x R-4000h 15 3 2 1 0 Reserved PHYRDY Reserved R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after r[...]

www.ti.com 4.2 SDRAM Bank Configuration Register (SDBCR) DDR2 Memory Controller Registers The SDRAM bank configuration register (SDBCR) contains fields that program the DDR2 memory controller to meet the specification of the attached DDR2 memory. These fields configure the DDR2 memory controller to match the data bus width, CAS latency, number of i[...]

www.ti.com DDR2 Memory Controller Registers Table 26. SDRAM Bank Configuration Register (SDBCR) Field Descriptions (continued) Bit Field Value Description 11-9 CL 0-7h CAS latency. 0-1h Reserved 2h CAS latency of 2 3h CAS latency of 3 4h CAS latency of 4 5h CAS latency of 5 6h-7h Reserved 8-7 Reserved 0 Reserved 6-4 IBANK 0-7h Internal DDR2 bank se[...]

www.ti.com 4.3 SDRAM Refresh Control Register (SDRCR) DDR2 Memory Controller Registers The SDRAM refresh control register (SDRCR) is used to configure the DDR2 memory controller to: • Enter and Exit the self-refresh state. • Enable and disable MCLK, stopping when in the self-refresh state. • Meet the refresh requirement of the attached DDR2 d[...]

www.ti.com 4.4 SDRAM Timing Register (SDTIMR) DDR2 Memory Controller Registers The SDRAM timing register (SDTIMR) configures the DDR2 memory controller to meet many of the AC timing specification of the DDR2 memory. The SDTIMR register is programmable only when the TIMUNLOCK bit is set to 1 in the SDBCR. Note that DDR_CLK is equal to the period of [...]

www.ti.com 4.5 SDRAM Timing Register 2 (SDTIMR2) DDR2 Memory Controller Registers Like the SDRAM timing register (SDTIMR), the SDRAM timing register 2 (SDTIMR2) also configures the DDR2 memory controller to meet the AC timing specification of the DDR2 memory. The SDTIMR2 register is programmable only when the TIMUNLOCK bit is set to 1 in the SDBCR.[...]

www.ti.com 4.6 Peripheral Bus Burst Priority Register (PBBPR) DDR2 Memory Controller Registers The peripheral bus burst priority register (PBBPR) helps prevent command starvation within the DDR2 memory controller. To avoid command starvation, the DDR2 memory controller momentarily raises the priority of the oldest command in the command FIFO after [...]

www.ti.com 4.7 Interrupt Raw Register (IRR) DDR2 Memory Controller Registers The interrupt raw register (IRR) displays the raw status of the interrupt. If the interrupt condition occurs, the corresponding bit in IRR is set independent of whether or not the interrupt is enabled. The IRR is shown in Figure 25 and described in Table 31 . Figure 25. In[...]

www.ti.com 4.8 Interrupt Masked Register (IMR) DDR2 Memory Controller Registers The interrupt masked register (IMR) displays the status of the interrupt when it is enabled. If the interrupt condition occurs and the corresponding bit in the interrupt mask set register (IMSR) is set, then the IMR bit is set. The IMR bit is not set if the interrupt is[...]

www.ti.com 4.9 Interrupt Mask Set Register (IMSR) DDR2 Memory Controller Registers The interrupt mask set register (IMSR) enables the DDR2 memory controller interrupt. The IMSR is shown in Figure 27 and described in Table 33 . Note: If the LTMSET bit in IMSR is set concurrently with the LTMCLR bit in the interrupt mask clear register (IMCR), the in[...]

www.ti.com 4.10 Interrupt Mask Clear Register (IMCR) DDR2 Memory Controller Registers The interrupt mask clear register (IMCR) disables the DDR2 memory controller interrupt. Once an interrupt is enabled, it may be disabled by writing a 1 to the IMCR bit. The IMCR is shown in Figure 28 and described in Table 34 . Note: If the LTMCLR bit in IMCR is s[...]

www.ti.com 4.11 DDR PHY Control Register (DDRPHYCR) DDR2 Memory Controller Registers The DDR PHY control register (DDRPHYCR) configures the DDR2 memory controller DLL for operation and determines whether the DLL is in reset, whether it is powered up, and the read latency. The DDRPHYCR is shown in Figure 29 and described in Table 35 . Figure 29. DDR[...]

www.ti.com 4.12 VTP IO Control Register (VTPIOCR) DDR2 Memory Controller Registers The VTP IO control register (VTPIOCR) is used to control the calibration of the DDR2 memory controller IOs with respect to voltage, temperature, and process (VTP). The voltage, temperature, and process information is used to control the IO's output impedance. Th[...]

www.ti.com 4.13 DDR VTP Register (DDRVTPR) 4.14 DDR VTP Enable Register (DDRVTPER) DDR2 Memory Controller Registers The DDR VTP register (DDRVTPR) is used in conjunction with the VTP IO control register (VTPIOCR) to calibrate the output impedance of the DDR2 memory controller IOs with respect to voltage, temperature, and process. Following the cali[...]

www.ti.com Appendix A Revision History Appendix A Table A-1 lists the changes made since the previous version of this document. Table A-1. Document Revision History Reference Additions/Modifications/Deletions Global Changed DDR_CLKO to DDR_CLK in text, figures, and tables. Global Changed DDR_CLKO to DDR_CLK in text, figures, and tables. Global Chan[...]

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