Texas Instruments TMS320C6722 manuale d’uso

www.ti.com 1 TMS320C6727, TMS320C6726, TMS320C6722 DSPs 1.1 Features TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 • C672x: 32-/64-Bit 300-MHz Floating-Point DSPs • Three Multichannel Audio Serial Ports – Transmit/Receive Clocks up to 50 MHz • Upgrades to C67x+ [...]

www.ti.com 1.2 Description TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The TMS320C672x is the next generation of Texas Instruments' C67x generation of high-performance 32-/64-bit floating-point digital signal processors. The TMS320C672x includes the TMS320C6727, [...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The C6727 extends SDRAM support to 256M-bit and 512M-bit devices. Asynchronous memory support is typically used to boot from a parallel non-multiplexed NOR flash device that can be 8, 16, or 32 bits wide. Booting [...]

www.ti.com 1.2.1 Device Compatibility TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Real-Time Interrupt Timer (RTI). The real-time interrupt timer module includes: • Two 32-bit counter/prescaler pairs • Two input captures (tied to McASP direct memory access [DMA] ev[...]

www.ti.com 1.3 Functional Block Diagram Program/Data RAM 256K Bytes 256 256 Program/Data ROM Page0 256K Bytes 256 Program/Data ROM Page1 128K Bytes 32 32 DMP PMP CSP 32 256 32K Bytes Program Cache 64 D1 Data R/W R/W Data D2 64 256 Program Fetch INT I/O C67x+ CPU Memory Controller 32 High-Performance Crossbar Switch 32 McASP DMA Bus JT AG EMU 32 32 [...]

www.ti.com Contents TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 1 TMS320C6727, TMS320C6726, TMS320C6722 4.3 Recommended Operating Conditions ............... 33 DSPs ........................................................ 1 4.4 Electrical Characteristics .............[...]

www.ti.com 2 Device Overview 2.1 Device Characteristics TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 2-1 provides an overview of the C672x DSPs. The table shows significant features of each device, including the capacity of on-chip memory, the peripherals, the ex[...]

www.ti.com 2.2 Enhanced C67x+ CPU .D1 .M1 .S1 .L1 Register File A Data Path A Cross Paths .D2 .M2 .S2 .L2 Register File B Data Path B TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The TMS320C672x floating-point digital signal processors are based on the new C67x+ CPU. T[...]

www.ti.com 2.3 CPU Interrupt Assignments TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 2-2. New Floating-Point Instructions for C67x+ CPU FLOATING-POINT INSTRUCTION IMPROVES OPERATION (1) MPYSPDP SP x DP → DP Faster than MPYDP. Improves high Q biquads (bass mana[...]

www.ti.com 2.4 Internal Program/Data ROM and RAM 00 20 27 07 2F 28 08 0F 3F 38 37 30 1F 18 10 17 3F 38 37 30 1F 18 17 10 2F 28 27 20 0F 08 00 07 Byte ROM Page 1 Base Address 0x0004 0000 ROM Page 0 Base Address 0x0000 0000 Bank 0 Bank 1 Bank 2 Bank 3 13 33 10 30 17 37 14 34 1B 3B 18 38 1F 3F 1C 3C RAM Page 0 Base Address 0x1000 0000 00 20 03 23 07 0[...]

www.ti.com 2.5 Program Cache TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The C672x DSP executes code directly from a large on-chip 32K-byte program cache. The program cache has these key features: • Wide 256-bit path to internal ROM/RAM • Single-cycle access on ca[...]

www.ti.com 2.6 High-Performance Crossbar Switch SYSCLK3 SYSCLK1 SYSCLK2 SYSCLK3 BR3 BR4 2 1 Priority EMIF External Memory SDRAM/ Flash Priority 2 1 3 4 T2 SYSCLK2 SYSCLK1 BR1 SYSCLK2 SYSCLK1 BR2 Program Master Port (PMP) CPU Slave Port (CSP) Data Master Port (DMP) Memory Controller M1 T1 M2 Priority 1 2 3 PLL SPI0 I2C0 I2C1 RTI SPI1 Peripheral Conf[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The five bus masters arbitrate for five different target groups: T1 On-chip memories through the CPU Slave Port (CSP). T2 Memories on the external memory interface (EMIF). T3 Peripheral registers through the perip[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 2-5 shows the bit layout of the device-level bridge control register (CFGBRIDGE) and Table 2-7 contains a description of the bits. 31 16 Reserved 15 1 0 Reserved CSPRST R/W, 1 LEGEND: R/W = Read/Write; R = [...]

www.ti.com 2.7 Memory Map Summary TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 A high-level memory map of the C672x DSP appears in Table 2-8 . The base address of each region is listed. Any address past the end address must not be read or written. The table also lists [...]

www.ti.com 2.8 Boot Modes TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The C672x DSP supports only one hardware bootmode option, this is to boot from the internal ROM starting at address 0x0000 0000. Other bootmode options are implemented by a software bootloader store[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 2-6 shows the bit layout of the CFGPIN0 register and Table 2-10 contains a description of the bits. 31 8 Reserved 76543210 PINCAP7 PINCAP6 PINCAP5 PINCAP4 PINCAP3 PINCAP2 PINCAP1 PINCAP0 LEGEND: R/W = Read/[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 2-7 shows the bit layout of the CFGPIN1 register and Table 2-11 contains a description of the bits. 31 8 Reserved 76543210 PINCAP15 PINCAP14 PINCAP13 PINCAP12 PINCAP11 PINCAP10 PINCAP9 PINCAP8 LEGEND: R/W =[...]

www.ti.com 2.9 Pin Assignments 2.9.1 Pin Maps SPI0_ENA /I2C1_ SDA SPI0_CLK /I2C0_ SCL DV DD V SS EM_RW EM_RAS V SS EM_BA[1] EM_A[0] V SS EM_A[3] EM_A[5] EM_A[7] EM_A[9] DV DD V SS DV DD EM_WE_ DQM[3] EM_A[1 1] EM_A[8] EM_A[6] EM_A[4] EM_A[2] EM_A[1] EM_A[10] EM_BA[0] EM_CS[0] EM_CS[2] EM_OE /I2C1_ SPI0_SCS SCL SIMO SPI0_ DV DD AXR0[0] SPI0_ SOMI /I[...]

www.ti.com 78 EM_A[7] 109 1 108 72 2 107 3 106 4 105 5 104 6 103 7 102 8 101 9 100 10 99 1 1 98 12 97 13 96 14 95 15 94 16 93 17 92 18 91 19 90 20 89 21 88 22 87 23 86 24 85 25 84 26 83 27 82 28 81 29 80 30 79 31 32 77 33 76 34 75 35 74 36 73 1 10 71 1 1 1 70 1 12 69 1 13 68 1 14 67 1 15 66 1 16 65 1 17 64 1 18 63 1 19 62 120 61 121 60 122 59 123 5[...]

www.ti.com 2.9.2 Terminal Functions TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 2-12 , the Terminal Functions table, identifies the external signal names, the associated pin/ball numbers along with the mechanical package designator, the pin type (I, O, IO, OZ, o[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 2-12. Terminal Functions (continued) GDH/ SIGNAL NAME RFP TYPE (1) PULL (2) GPIO (3) DESCRIPTION ZDH External Memory Interface (EMIF) Data Bus / Universal Host-Port Interface (UHPI) Address Bus Option EM_D[0[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 2-12. Terminal Functions (continued) GDH/ SIGNAL NAME RFP TYPE (1) PULL (2) GPIO (3) DESCRIPTION ZDH Universal Host-Port Interface (UHPI) Data and Control UHPI_HD[0] - K13 IO IPD Y UHPI_HD[1] - K14 IO IPD Y [...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 2-12. Terminal Functions (continued) GDH/ SIGNAL NAME RFP TYPE (1) PULL (2) GPIO (3) DESCRIPTION ZDH McASP0, McASP1, McASP2, and SPI1 Serial Ports AHCLKR0/AHCLKR1 143 B3 IO - Y McASP0 and McASP1 Receive Mast[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 2-12. Terminal Functions (continued) GDH/ SIGNAL NAME RFP TYPE (1) PULL (2) GPIO (3) DESCRIPTION ZDH Clocks OSCIN 23 J2 I - N 1.2-V Oscillator Input OSCOUT 24 J3 O - N 1.2-V Oscillator Output OSCV DD 25 J4 P[...]

www.ti.com 2.10 Development 2.10.1 Development Support 2.10.2 Device Support TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 TI offers an extensive line of development tools for the TMS320C6000™ DSP platform, including tools to evaluate the performance of the processors[...]

www.ti.com C672x DSP: 6727 6726 6722 PREFIX DEVICE SPEED RANGE TMS 320 C6727 GDH 250 TMX = Experimental device TMP = Prototype device TMS = Qualified device DEVICE F AMIL Y 320 = TMS320 t DSP family P ACKAGE TYPE ‡ § GDH = 256-terminal plastic BGA ZDH = 256-terminal Green plastic BGA RFP = 144-pin PowerP AD  Green TQFP DEVICE ¶ † The exten[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 2.10.2.2 Documentation Support Extensive documentation supports the TMS320™ DSP family of devices from product announcement through applications development. The types of documentation available include: data ma[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 SPRAA69 Using the TMS320C672x Bootloader Application Report. This document describes the design details about the TMS320C672x bootloader. This document also addresses parallel flash and HPI boot to the extent rele[...]

www.ti.com 3 Device Configurations 3.1 Device Configuration Registers 3.2 Peripheral Pin Multiplexing Options TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The C672x DSP includes several device-level configuration registers, which are listed in Table 3-1 . These registe[...]

www.ti.com 3.3 Peripheral Pin Multiplexing Control TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 3-3 lists the options for configuring the SPI1, McASP0, and McASP1 pins. Note that there are additional finer grain options when selecting which McASP controls the par[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 3-5. Priority of Control of Data Output on Multiplexed Pins PIN FIRST PRIORITY SECOND PRIORITY THIRD PRIORITY SPI0_SOMI/I2C0_SDA SPI0_SOMI I2C0_SDA SPI0_CLK/I2C0_SCL SPI0_CLK I2C0_SCL SPI0_SCS/I2C1_SCL SPI0_[...]

www.ti.com 4 Peripheral and Electrical Specifications 4.1 Electrical Specifications 4.2 Absolute Maximum Ratings (1) (2) 4.3 Recommended Operating Conditions (1) TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 This section provides the absolute maximum ratings and the rec[...]

www.ti.com 4.4 Electrical Characteristics TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Over Operating Case Temperature Range (Unless Otherwise Noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V OH High Level Output Voltage I O = –100 µA DV DD – 0.2 V V OL Low Lev[...]

www.ti.com 4.5 Parameter Information 4.5.1 Parameter Information Device-Specific Information T ransmission Line 4.0 pF 1.85 pF Z0 = 50 Ω (see note) T ester Pin Electronics Data Sheet T iming Reference Point Output Under T est 42 Ω 3.5 nH Device Pin (see note) V ref = 1.5 V V ref = V I L MAX (or V OL MAX) V ref = V I H MIN (or V OH MIN) TMS320C6[...]

www.ti.com 4.6 Timing Parameter Symbology TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Timing parameter symbols used in the timing requirements and switching characteristics tables are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the p[...]

www.ti.com 4.7 Power Supplies 4.7.1 Power-Supply Sequencing 4.7.2 Power-Supply Decoupling TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 For more information regarding TI’s power management products and suggested devices to power TI DSPs, visit www.ti.com/dsppower . Th[...]

www.ti.com 4.8 Reset 4.8.1 Reset Electrical Data/Timing TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 A hardware reset ( RESET) is required to place the DSP into a known good state out of power-up. The RESET signal can be asserted (pulled low) prior to ramping the core [...]

www.ti.com 4.9 Dual Data Movement Accelerator (dMAX) 4.9.1 dMAX Device-Specific Information TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The dMAX is a module designed to perform Data Movement Acceleration. The dMAX controller handles user-programmed data transfers betw[...]

www.ti.com Event Entry #0 Event Entry #k Event Entry #31 T ransfer Entry #0 T ransfer Entry #k T ransfer Entry #7 Reserved Event Entry T able T ransfer Entry T able HiMAX RAM R/W Control R/W HiMAX (MAX0) Event Encoder + Event and Interrupt Registers LoMAX (MAX1) T ransfer Entry T able LoMAX RAM R/W T ransfer Entry #7 T ransfer Entry #k T ransfer En[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The dMAX controller comprises: • Event and interrupt processing registers • Event encoder • High-priority event Parameter RAM (PaRAM) • Low-priority event Parameter RAM (PaRAM) • Address-generation hardw[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-2 lists how the synchronization events are associated with event numbers in the dMAX controller. Table 4-2. dMAX Peripheral Event Input Assignments EVENT NUMBER EVENT ACRONYM EVENT DESCRIPTION 0 DETR[0] Th[...]

www.ti.com 4.9.2 dMAX Peripheral Registers Description(s) TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-3 is a list of the dMAX registers. Table 4-3. dMAX Configuration Registers BYTE ADDRESS REGISTER NAME DESCRIPTION 0x6000 0008 DEPR Event Polarity Register 0x6[...]

www.ti.com 4.10 External Interrupts TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The C672x DSP has no dedicated general-purpose interrupt pins, but the dMAX can be used in combination with a McASP AMUTEIN signal to provide external interrupt capability. There is a mult[...]

www.ti.com 4.11 External Memory Interface (EMIF) 4.11.1 EMIF Device-Specific Information TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The C672x DSP includes an external memory interface (EMIF) for optional SDRAM, NOR FLASH, NAND FLASH, or SRAM. The key features of this[...]

www.ti.com EM_CS[0] EM_CAS EM_RAS EM_WE EM_CLK EM_CKE EM_BA[1:0] EM_A[1 1:0] EM_WE _DQM[0] EM_WE _DQM[1] EM_D[15:0] EM_CS[2] EM_R W EM_OE GPIO (6 Pins) RESET C6726/C6722 DSP EMIF CE CAS RAS WE CLK CKE BA[1:0] A[1 1:0] LDQM UDQM DQ[15:0] 2M x 16 x 4 Bank SDRAM A[18:13] R Y/BY RESET OE WE CE DQ[15:0] 512K x 16 A[0] A[12:1] FLASH EM_BA[1] RESET Any GP[...]

www.ti.com EM_CS[0] EM_CAS EM_RAS EM_WE EM_CLK EM_CKE EM_BA[1:0] EM_A[12:0] EM_WE _DQM[0] EM_WE _DQM[1] EM_D[15:0] EM_WE _DQM[2] GPIO (5 Pins) RESET C6727 DSP EMIF CE CAS RAS WE CLK CKE BA[1:0] A[12:0] LDQM UDQM DQ[15:0] 4M x 16 x 4 Bank SDRAM A[18:14] R Y/BY RESET OE WE CE DQ[15:0] 512K x 16 A[0] A[13:1] FLASH EM_BA[1] RESET Any GPIO-capable pins [...]

www.ti.com 4.11.2 EMIF Peripheral Registers Description(s) TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-4 is a list of the EMIF registers. For more information about these registers, see the TMS320C672x DSP External Memory Interface (EMIF) User's Guide (li[...]

www.ti.com 4.11.3 EMIF Electrical Data/Timing TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-5 through Table 4-8 assume testing over recommended operating conditions (see Figure 4-7 through Figure 4-13 ). Table 4-5. EMIF SDRAM Interface Timing Requirements NO. MI[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-7. EMIF Asynchronous Interface Timing Requirements (1) (2) NO. MIN MAX UNIT Input setup time, read data valid on EM_D[31:0] before EM_CLK 28 t su(EM_DV-EM_CLKH)A 5 ns rising 29 t h(EM_CLKH-EM_DIV)A Input h[...]

www.ti.com EM_CLK EM_BA[1:0] EM_A[12:0] EM_D[31:0] 1 2 2 4 6 8 8 12 14 16 3 5 7 7 1 1 13 15 9 BASIC SDRAM WRITE OPERA TION EM_CS[0] EM_WE _DQM[3:0] EM_RAS EM_CAS EM_WE EM_CLK EM_BA[1:0] EM_A[12:0] EM_D[31:0] 1 2 2 4 6 8 8 12 14 19 20 3 5 7 7 1 1 13 17 18 2 EM_CLK Delay BASIC SDRAM READ OPERA TION EM_CS[0] EM_WE _DQM[3:0] EM_RAS EM_CAS EM_WE TMS320C[...]

www.ti.com EM_CLK EM_BA[1:0] EM_A[12:0] EM_D[31:0] READ DA T A SETUP STROBE HOLD T A 21 22 23 23 25 25 21 22 23 23 28 29 17 18 ASYNCHRONOUS READ WE STROBE MODE ADDRESS ADDRESS EM_CS[2] EM_WE _DQM[3:0] EM_OE EM_WE EM_R W EM_CLK EM_BA[1:0] EM_A[12:0] EM_D[31:0] READ DA T A SETUP STROBE HOLD T A 22 23 23 25 25 22 23 23 28 29 21 21 17 18 BYTE LANE ENAB[...]

www.ti.com EM_CLK EM_BA[1:0] EM_A[12:0] EM_D[31:0] SETUP STROBE HOLD 21 22 23 23 32 32 21 22 23 23 22 26 26 24 27 ASYNCHRONOUS WRITE WE STROBE MODE ADDRESS ADDRESS WRITE DA T A 22 BYTE WRITE STROBES EM_CS[2] EM_WE _DQM[3:0] EM_OE EM_WE EM_R W EM_CLK EM_BA[1:0] EM_A[12:0] EM_D[31:0] SETUP STROBE HOLD 22 23 23 32 32 23 23 26 26 24 22 21 21 27 ASYNCHR[...]

www.ti.com EM_CLK EM_W AIT ASSERTED DEASSERTED SETUP HOLD STROBE STROBE EXTENDED W AIT ST A TES 34 35 30 31 33 33 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 4-13. EM_WAIT Timing Requirements 54 Peripheral and Electrical Specifications Submit Documentation Feed[...]

www.ti.com 4.12 Universal Host-Port Interface (UHPI) [C6727 Only] 4.12.1 UHPI Device-Specific Information UHPI_HDS[2] UHPI_HDS[1] UHPI_HCS UHPI_HRDY Internal HSTROBE Internal HRDY TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The C672x DSP includes a flexible universal [...]

www.ti.com EM_D[31:16]/UHPI_HA[15:0] (A) UHPI_HCNTL[1:0] UHPI_HD[15:0] UHPI_HD[16]/HHWIL UHPI_HD[31:17] UHPI_HAS (B) UHPI_HBE[1:0] (C) UHPI_HR W UHPI_HDS[2] (G) UHPI_HDS[1] (G) UHPI_HCS UHPI_HRDY AMUTE2/HINT NC or GPIO NC A[x:y] (D) D[15:0] A[1] (E) BE[1:0] (F) R/W WE (G) RD (G) CS RDY INTERRUPT DSP External Host MCU TMS320C6727, TMS320C6726, TMS32[...]

www.ti.com EM_D[31:16]/UHPI_HA[15:0] (A) UHPI_HCNTL[1:0] UHPI_HD[15:0] UHPI_HD[16]/HHWIL UHPI_HD[31:17] UHPI_HAS (B) UHPI_HBE[3:0] UHPI_HR W UHPI_HDS[2] UHPI_HDS[1] UHPI_HCS UHPI_HRDY AMUTE2/HINT NC A[x:y] (C) D[15:0] D[16] BE[3:0 ] (D) R/W WE (E) RD (E) CS RDY INTERRUPT DSP External Host MCU D[31:17] TMS320C6727, TMS320C6726, TMS320C6722 Floating-[...]

www.ti.com EM_D[31:16]/UHPI_HA[15:0] UHPI_HCNTL[1:0] UHPI_HD[15:0] UHPI_HD[16]/HHWIL UHPI_HD[31:17] UHPI_HAS (B) UHPI_HBE[3:0] UHPI_HR W UHPI_HDS[2] UHPI_HDS[1] UHPI_HCS UHPI_HRDY AMUTE2/HINT A[x:y] (A) D[15:0] D[16] BE[3:0] (C) R/W WE (D ) RD (D) CS RDY INTERRUPT DSP External Host MCU D[31:17] A[17:2] TMS320C6727, TMS320C6726, TMS320C6722 Floating[...]

www.ti.com 4.12.2 UHPI Peripheral Registers Description(s) TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-11 is a list of the UHPI registers. Table 4-11. UHPI Configuration Registers BYTE ADDRESS REGISTER NAME DESCRIPTION Device-Level Configuration Registers Cont[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The UHPI has several device-level configuration registers which affect its behavior. Figure 4-18 , Figure 4-19 , and Figure 4-20 show the bit layout of these registers. Table 4-12 , Table 4-13 , and Table 4-14 con[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 31 8 Reserved 7 0 HPIAMSB R/W, 0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Figure 4-19. CFGHPIAMSB Register Bit Layout (0x4000 000C) Table 4-13. CFGHPIAMSB Register Bit Field Description (0x[...]

www.ti.com 4.12.3 UHPI Electrical Data/Timing TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.12.3.1 Universal Host-Port Interface (UHPI) Read and Write Timing Table 4-15 and Table 4-16 assume testing over recommended operating conditions (see Figure 4-21 through Figure[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-16. UHPI Read and Write Switching Characteristics (1) (2) NO. PARAMETER MIN MAX UNIT Case 1. HPIC or HPIA read 1 15 Case 2. HPID read with no 9 * 2H + 20 (3) auto-increment Case 3. HPID read with 1 t d(DSL[...]

www.ti.com 13 14 13 15 16 15 16 1 3 2 7 4 17 18 34 5 UHPI_HCS UHPI_HDSx UHPI_HR W UHPI_HA[15:0] UHPI_HD[31:0] (Read) UHPI_HD[31:0] (W rite) UHPI_HRDY V alid V alid Read data W rite data Read W rite 37 37 6 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 A. Depending on th[...]

www.ti.com UHPI_HCS UHPI_HAS UHPI_HR W UHPI_HHWIL HSTROBE (A ) UHPI_HD[15:0] UHPI_HRDY 2 3 1 37 9 10 14 2 38 12 1 1 12 1 1 12 1 1 13 7 6 1 3 13 37 9 10 36 UHPI_HCNTL[1:0] 12 1 1 12 1 1 12 1 1 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 A. See Figure 4-14 . B. Dependin[...]

www.ti.com UHPI_HCS UHPI_HAS UHPI_HCNTL[1:0] UHPI_HR W UHPI_HHWIL HSTROBE (A ) UHPI_HD[15:0] UHPI_HRDY 16 15 37 13 14 16 15 37 13 3 1 2 3 1 2 38 7 4 6 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 A. See Figure 4-14 . B. Depending on the type of write or read operation [...]

www.ti.com UHPI_HCS UHPI_HAS UHPI_HCNTL[1:0] UHPI_HR W UHPI_HHWIL HSTROBE (A ) UHPI_HD[15:0] UHPI_HRDY 34 5 17 18 17 18 34 5 4 38 37 13 16 15 14 13 16 15 37 35 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 A. See Figure 4-14 . B. Depending on the type of write or read o[...]

www.ti.com 4.13 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2) Receive Logic Clock/Frame Generator State Machine Clock Check and Serializer 0 Serializer 1 Serializer y GIO Control DIT RAM 384 C 384 U Optional T ransmit Formatter Receive Formatter T ransmit Logic Clock/Frame Generator State Machine McASPx (x = 0, 1, 2) Peripheral Confi[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The three McASPs on C672x have different configurations (see Table 4-17 ). NOTE: McASP2 is not available on the C6722. Table 4-17. McASP Configurations on C672x DSP McASP DIT CLOCK PINS DATA PINS COMMENTS McASP0 N[...]

www.ti.com 4.13.1 McASP Peripheral Registers Description(s) TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-18 is a list of the McASP registers. For more information about these registers, see the TMS320C672x DSP Multichannel Audio Serial Port (McASP) Reference Gu[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-18. McASP Registers Accessed Through Peripheral Configuration Bus (continued) McASP0 McASP1 McASP2 REGISTER BYTE BYTE BYTE DESCRIPTION NAME ADDRESS ADDRESS ADDRESS 0x4400 00C8 0x4500 00C8 0x4600 00C8 XCLKC[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-18. McASP Registers Accessed Through Peripheral Configuration Bus (continued) McASP0 McASP1 McASP2 REGISTER BYTE BYTE BYTE DESCRIPTION NAME ADDRESS ADDRESS ADDRESS 0x4400 020C 0x4500 020C – XBUF3 (1) Tra[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 4-26 shows the bit layout of the CFGMCASP0 register and Table 4-19 contains a description of the bits. 31 8 Reserved 7 3 2 0 Reserved AMUTEIN0 R/W, 0 LEGEND: R/W = Read/Write; R = Read only; - n = value aft[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 4-27 shows the bit layout of the CFGMCASP1 register and Table 4-20 contains a description of the bits. 31 8 Reserved 7 3 2 0 Reserved AMUTEIN1 R/W, 0 LEGEND: R/W = Read/Write; R = Read only; - n = value aft[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 4-28 shows the bit layout of the CFGMCASP2 register and Table 4-21 contains a description of the bits. 31 8 Reserved 7 3 2 0 Reserved AMUTEIN2 R/W, 0 LEGEND: R/W = Read/Write; R = Read only; - n = value aft[...]

www.ti.com 4.13.2 McASP Electrical Data/Timing TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.13.2.1 Multichannel Audio Serial Port (McASP) Timing Table 4-22 and Table 4-23 assume testing over recommended operating conditions (see Figure 4-29 and Figure 4-30 ). Table 4[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-23. McASP Switching Characteristics (1) NO. PARAMETER MIN MAX UNIT Cycle time, AHCLKR internal, AHCLKR output 20 Cycle time, AHCLKR external, AHCLKR output 20 9 t c(AHCKRX) ns Cycle time, AHCLKX internal, [...]

www.ti.com 8 7 4 4 3 2 2 1 A0 A1 B0 B1 A30 A31 B30 B31 C0 C1 C2 C3 C31 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) AXR[n] (Data In/Rec[...]

www.ti.com 15 14 13 13 13 13 13 13 13 12 12 1 1 10 10 9 A0 A1 B0 B1 A30 A31 B30 B31 C0 C1 C2 C3 C31 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 B[...]

www.ti.com 4.14 Serial Peripheral Interface Ports (SPI0, SPI1) 4.14.1 SPI Device-Specific Information Peripheral Configuration Bus Interrupt and DMA Requests 16-Bit Shift Register 16-Bit Buffer 16-Bit Emulation Buffer C672x SPI Module GPIO Control (all pins) State Machine Clock Control SPIx_SIMO SPIx_SOMI SPIx_ENA SPIx_SCS SPIx_CLK TMS320C6727, TMS[...]

www.ti.com Optional − Slave Chip Select Optional Enable (Ready) SLA VE SPI MASTER SPI SPIx_SIMO SPIx_SIMO SPIx_SOMI SPIx_SOMI SPIx_CLK SPIx_CLK SPIx_ENA SPIx_ENA SPIx_SCS SPIx_SCS TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 4-32. Illustration of SPI Master-to[...]

www.ti.com 4.14.2 SPI Peripheral Registers Description(s) TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-24 is a list of the SPI registers. Table 4-24. SPIx Configuration Registers SPI0 SPI1 REGISTER NAME DESCRIPTION BYTE ADDRESS BYTE ADDRESS 0x4700 0000 0x4800 0[...]

www.ti.com 4.14.3 SPI Electrical Data/Timing TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.14.3.1 Serial Peripheral Interface (SPI) Timing Table 4-25 through Table 4-32 assume testing over recommended operating conditions (see Figure 4-33 through Figure 4-36 ). Table [...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-26. General Timing Requirements for SPIx Slave Modes (1) NO. MIN MAX UNIT greater of 8P or 9 t c(SPC)S Cycle Time, SPIx_CLK, All Slave Modes 256P ns 100 ns greater of 4P or 10 t w(SPCH)S Pulse Width High, [...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-27. Additional (1) SPI Master Timings, 4-Pin Enable Option (2) (3) NO. MIN MAX UNIT Polarity = 0, Phase = 0, 3P + 15 to SPIx_CLK rising Polarity = 0, Phase = 1, 0.5t c(SPC)M + 3P + 15 Delay from slave asse[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-29. Additional (1) SPI Master Timings, 5-Pin Option (2) (3) NO. MIN MAX UNIT Polarity = 0, Phase = 0, 0.5t c(SPC)M from SPIx_CLK falling Max delay for slave to Polarity = 0, Phase = 1, deassert SPIx_ENA af[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-30. Additional (1) SPI Slave Timings, 4-Pin Enable Option (2) (3) NO. MIN MAX UNIT Polarity = 0, Phase = 0, P – 10 3P + 15 from SPIx_CLK falling Polarity = 0, Phase = 1, 0.5t c(SPC)M + P – 10 0.5t c(SP[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-32. Additional (1) SPI Slave Timings, 5-Pin Option (2) (3) NO. MIN MAX UNIT Required delay from SPIx_SCS asserted at slave to first 25 t d(SCSL_SPC)S P ns SPIx_CLK edge at slave. Polarity = 0, Phase = 0, 0[...]

www.ti.com SPIx_CLK SPI_SIMO SPI_SOMI SPIx_CLK SPI_SIMO SPI_SOMI SPIx_CLK SPI_SIMO SPI_SOMI SPIx_CLK SPI_SIMO SPI_SOMI MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) 6 6 7 7[...]

www.ti.com SPIx_CLK SPI_SIMO SPI_SOMI SPIx_CLK SPI_SIMO SPI_SOMI SPIx_CLK SPI_SIMO SPI_SOMI SPIx_CLK SPI_SIMO SPI_SOMI SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) 14 14 1[...]

www.ti.com MASTER MODE 4 PIN WITH CHIP SELECT SPIx_CLK SPI_SIMO SPI_SOMI SPIx_ENA SPIx_CLK SPI_SIMO SPI_SOMI SPIx_SCS SPIx_CLK SPI_SIMO SPI_SOMI SPIx_ENA SPIx_SCS MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) 17 19 21 22 23 20 1[...]

www.ti.com 27 SPIx_CLK SPI_SOMI SPI_SIMO SPIx_ENA SPIx_CLK SPI_SOMI SPI_SIMO SPIx_SCS SPIx_CLK SPI_SOMI SPI_SIMO SPIx_ENA SPIx_SCS SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) 24 26 28 26 30 28 25 25 27 29 SLA VE MODE 4 PIN WIT[...]

www.ti.com 4.15 Inter-Integrated Circuit Serial Ports (I2C0, I2C1) 4.15.1 I2C Device-Specific Information Peripheral Configuration Bus Noise Filter Noise Filter Clock Prescaler I2CPSCx Prescaler Register Bit Clock Generator I2CCLKHx Clock Divide High Register I2CCLKLx Clock Divide Low Register Control I2CCOARx Own Address Register I2CSARx Slave Add[...]

www.ti.com 4.15.2 I2C Peripheral Registers Description(s) TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-33 is a list of the I2C registers. Table 4-33. I2Cx Configuration Registers I2C0 I2C1 REGISTER NAME DESCRIPTION BYTE ADDRESS BYTE ADDRESS 0x4900 0000 0x4A00 0[...]

www.ti.com 4.15.3 I2C Electrical Data/Timing TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.15.3.1 Inter-Integrated Circuit (I2C) Timing Table 4-34 and Table 4-35 assume testing over recommended operating conditions (see Figure 4-38 and Figure 4-39 ). Table 4-34. I2C I[...]

www.ti.com 10 8 4 3 7 12 5 6 14 2 3 13 Stop Start Repeated Start Stop I2Cx_SDA I2Cx_SCL 1 1 1 9 25 23 19 18 22 27 20 21 17 18 28 Stop Start Repeated Start Stop I2Cx_SDA I2Cx_SCL 16 26 24 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-35. I2C Switching Characteris[...]

www.ti.com 4.16 Real-Time Interrupt (RTI) Timer With Digital Watchdog 4.16.1 RTI/Digital Watchdog Device-Specific Information McASP0,1,2 T ransmit/Receive DMA Events McASP0,1,2 T ransmit/Receive DMA Events Counter 0 32-Bit + 32-Bit Prescale (Used by DSP BIOS) Capture 0 32-Bit + 32-Bit Prescale Counter 1 32-Bit + 32-Bit Prescale Capture 1 32-Bit + 3[...]

www.ti.com 4.16.2 RTI/Digital Watchdog Registers Description(s) TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The digital watchdog is disabled by default. Once enabled, a sequence of two 16-bit key values (0xE51A followed by 0xA35C in two separate writes) must be contin[...]

www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-36. RTI Registers (continued) BYTE ADDRESS REGISTER NAME DESCRIPTION 0x4200 0088 RTIINTFLAG Interrupt Flags. Interrupt pending bits. 0x4200 0090 RTIDWDCTRL Digital Watchdog Control. Enables the Digital Wat[...]

www.ti.com 4.17 External Clock Input From Oscillator or CLKIN Pin OSCV DD C 5 C 7 C 8 X 1 R S R B OSCIN OSCOUT C 6 OSCV SS CLKIN Clock Input From OSCIN to PLL On-Chip 1.2-V Oscillator (a) External 3.3-V L VCMOS-Compatible Clock Source (b) OSCV DD OSCIN OSCOUT OSCV SS CLKIN Clock Input From CLKIN to PLL CV DD (1.2 V) NC TMS320C6727, TMS320C6726, TMS[...]

www.ti.com 4.17.1 Clock Electrical Data/Timing TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-39 assumes testing over recommended operating conditions. Table 4-39. CLKIN Timing Requirements NO. MIN MAX UNIT 1 f osc Oscillator frequency range (OSCIN/OSCOUT) 12 25 [...]

www.ti.com 4.18 Phase-Locked Loop (PLL) 4.18.1 PLL Device-Specific Information 1 0 PLLEN (PLL_CSR[0]) Divider D0 (/1 to /32) PLLREF PLL x4 to x25 PLLOUT Divider D1 (/1 to /32) SYSCLK1 CPU and Memory Divider D2 (/1 to /32) SYSCLK2 Peripherals and dMAX Divider D3 (/1 to /32) SYSCLK3 EMIF AUXCLK McASP0,1,2 Clock Input from CLKIN or OSCIN TMS320C6727, [...]

www.ti.com BOARD DV DD (3.3 V) EMI Filter 10 m F 0.1 m F PLLHV Place Filter and Capacitors as Close to DSP as Possible EMI Filter: TDK ACF451832−333, −223, −153, or −103, Panasonic EXCCET103U, or Equivalent + TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4[...]

www.ti.com 4.18.2 PLL Registers Description(s) TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-41 is a list of the PLL registers. For more information about these registers, see the TMS320C672x DSP Software-Programmable Phase-Locked Loop (PLL) Controller Reference[...]

www.ti.com 5 Application Example 256K Bytes RAM Bytes ROM 384K Memory Controller C67x+ DSP Core Program Cache Crossbar Switch EMIF UHPI dMAX McASP0 SPI1 McASP1 I2C0 I2C1 RTI SPIO McASP2 PLL OSC ASYNC FLASH 100 MHz SDRAM DSP Host Microprocessor Audio Zone 1 SPI or I2C Control (optional) Audio Zone 2 Audio Zone 3 CODEC, DIR, ADC, DAC, DSD, Network Ne[...]

www.ti.com 6 Revision History TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 This data sheet revision history highlights the technical changes made to the SPRS268D device-specific data sheet to make it an SPRS268E revision. Scope: Corrected addresses of the XGBLCTL regis[...]

www.ti.com 7 Mechanical Data 7.1 Package Thermal Resistance Characteristics TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 7-1 and Table 7-2 provide the thermal characteristics for the recommended package types used on the TMS320C672x DSP. Table 7-1. Thermal Charac[...]

www.ti.com 7.2 Supplementary Information About the 144-Pin RFP PowerPAD™ Package 7.2.1 Standoff Height Standoff Height TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 This section highlights a few important details about the 144-pin RFP PowerPAD™ package. Texas Instru[...]

www.ti.com 7.2.2 PowerPAD™ PCB Footprint Thermal Pad on T op Copper should be as large as Possible. Soldermask opening should be smaller and match the size of the thermal pad on the DSP . 7.3 Packaging Information TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 Texas In[...]

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PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TMX320C6722RFP OBSOLETE HTQFP RFP 144 TBD Call TI Call TI TMX320C6726RFP OBSOLETE HTQFP RFP 144 TBD Call TI Call TI TMX320C6727GDH OBSOLETE BGA GDH 256 TBD Call TI Call TI TMX320C6727ZDH OBSOLETE BGA ZDH 25[...]

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