Texas Instruments TMS320DM643x manuale d’uso

TMS320DM643x DMP DSP Subsystem Reference Guide Literature Number: SPRU978E March 2008[...]

2 SPRU978E – March 2008 Submit Documentation Feedback[...]

Contents Preface ............................................................................................................................... 9 1 Introduction ............................................................................................................. 11 1.1 Introduction ..........................................................[...]

5.3.2 Steps for Changing PLL2 Frequency .................................................................. 44 5.4 PLL Controller Registers ......................................................................................... 48 5.4.1 Peripheral ID Register (PID) ............................................................................ 49 5.4[...]

7.3.1 Module Clock ON/OFF .................................................................................. 79 7.3.2 Module Clock Frequency Scaling ...................................................................... 79 7.3.3 PLL Bypass and Power Down .......................................................................... 79 7.4 DSP Sleep Mod[...]

List of Figures 1-1 TMS320DM643x DMP Block Diagram .................................................................................. 12 2-1 TMS320C64x+ Megamodule Block Diagram ........................................................................... 17 2-2 C64x+ Cache Memory Architecture .........................................................[...]

List of Tables 4-1 System Clock Modes and Fixed Ratios for Core Clock Domains .................................................... 30 4-2 Example PLL1 Frequencies and Dividers (27 MHZ Clock Input) .................................................... 32 4-3 Example PLL2 Frequencies (Core Voltage = 1.2V) ..............................................[...]

List of Tables 8 SPRU978E – March 2008 Submit Documentation Feedback[...]

Preface SPRU978E – March 2008 Read This First About This Manual This document describes the DSP subsystem in the TMS320DM643x Digital Media Processor (DMP). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h[...]

TMS320C6000, C6000 are trademarks of Texas Instruments. Read This First 10 SPRU978E – March 2008 Submit Documentation Feedback[...]

Chapter 1 SPRU978E – March 2008 Introduction Topic .................................................................................................. Page 1.1 Introduction .............................................................................. 12 1.2 Block Diagram .......................................................................... 1[...]

www.ti.com 1.1 Introduction 1.2 Block Diagram JT AG Interface System Control PLLs/Clock Generator Input Clock(s) Power/Sleep Controller Pin Multiplexing DSP Subsystem C64x+ t DSP CPU 32 KB L1 Pgm 128 KB L2 RAM 80 KB L1 Data BT .656, Y/C, Raw (Bayer) Video Processing Subsystem (VPSS) CCD Controller Video Interface Front End Resizer Histogram/ 3A Pre[...]

www.ti.com 1.3 DSP Subsystem in TMS320DM643x DMP 1.3.1 Components of the DSP Subsystem DSP Subsystem in TMS320DM643x DMP In the DM643x DMP, the DSP subsystem is responsible for performing digital signal processing for digital media applications. In addition, the DSP subsystem acts as the overall system controller, responsible for handling many syst[...]

Introduction 14 SPRU978E – March 2008 Submit Documentation Feedback[...]

Chapter 2 SPRU978E – March 2008 TMS320C64x+ Megamodule Topic .................................................................................................. Page 2.1 Introduction .............................................................................. 16 2.2 TMS320C64x+ CPU ................................................................[...]

www.ti.com 2.1 Introduction 2.2 TMS320C64x+ CPU Introduction The C64x+ Megamodule ( Figure 2-1 ) consists of the following components: • TMS320C64x+ CPU • Internal memory controllers: – Level-1 program memory controller (L1P controller) – Level-1 data memory controller (L1D controller) – Level-2 unified memory controller (L2 controller) ?[...]

www.ti.com Cache control Memory protect Bandwidth mgmt L1P RAM/ cache 256 Bandwidth mgmt Memory protect Cache control 256 L2 256 RAM/ Cache ROM 256 Instruction fetch file A file B C64x+ CPU 256 Cache control Memory protect Bandwidth mgmt L1D 128 128 8 x 32 IDMA 256 256 128 256 Power down Interrupt controller CFG MDMA SDMA EMC 256 32 Chip registers [...]

www.ti.com 2.3 Memory Controllers 2.3.1 L1P Controller Memory Controllers The C64x+ Megamodule implements a two-level internal cache-based memory architecture with external memory support. Level 1 memory is split into separate program memory (L1P memory) and data memory (L1D memory). Figure 2-2 shows a diagram of the memory architecture. L1P and L1[...]

www.ti.com C64x+ CPU Fetch Path Data Path W rite Buf fer L1D Cache L1D SRAM L1 Data L1P Cache L1P SRAM L1 Program L2 Cache L2 SRAM L2 Unified Data/Program Memory External Memory 64 bit 256 bit 128 bit 256 bit 256 bit 2 x 64 bit Legend: addressable memory cache memory data paths managed by cache controller 256 bit Memory Controllers Figure 2-2. C64x[...]

www.ti.com 2.3.2 L1D Controller 2.3.3 L2 Controller Memory Controllers The L1D controller is the hardware interface between level 1 data memory (L1D memory) and the other components in the C64x+ Megamodule (for example, C64x+ CPU, L2 controller, and EMC). The L1D controller responds to data requests from the C64x+ CPU and manages transfer operation[...]

www.ti.com 2.3.4 External Memory Controller (EMC) 2.3.5 Internal DMA (IDMA) Memory Controllers The external memory controller (EMC) is the hardware interface between the external memory map (external memory and external registers) and the other controllers in the C64x+ Megamodule (for example, L1P controller, L1D controller, and L2 controller). The[...]

www.ti.com 2.4 Internal Peripherals 2.4.1 Interrupt Controller (INTC) 2.4.2 Power-Down Controller (PDC) Internal Peripherals This C64x+ Megamodule includes the following internal peripherals: • Interrupt controller (INTC) • Power-down controller (PDC) This section briefly describes the INTC and PDC. For more information on these peripherals, se[...]

www.ti.com 2.4.3 Bandwidth Manager Internal Peripherals The bandwidth manager provides a programmable interface for optimizing bandwidth among the requesters for resources, which include the following: • EDMA-initiated DMA transfers (and resulting coherency operations) • IDMA-initiated transfers (and resulting coherency operations) • Programm[...]

TMS320C64x+ Megamodule 24 SPRU978E – March 2008 Submit Documentation Feedback[...]

Chapter 3 SPRU978E – March 2008 System Memory Topic .................................................................................................. Page 3.1 Memory Map ............................................................................. 26 3.2 Memory Interfaces Overview ...................................................... 27 SPRU978[...]

www.ti.com 3.1 Memory Map 3.1.1 DSP Internal Memory (L1P, L1D, L2) 3.1.2 External Memory 3.1.3 Internal Peripherals 3.1.4 Device Peripherals Memory Map Refer to your device-specific data manual for memory-map information. This section describes the configuration of the DSP internal memory in the DM643x DMP that consists of L1P, L1D, and L2. In the [...]

www.ti.com 3.2 Memory Interfaces Overview 3.2.1 DDR2 External Memory Interface 3.2.2 External Memory Interface 3.2.2.1 Asynchronous EMIF Interface 3.2.2.2 NAND Interface Memory Interfaces Overview This section describes the different memory interfaces of DM643x DMP. The DM643x DMP supports several memory and external device interfaces, including th[...]

System Memory 28 SPRU978E – March 2008 Submit Documentation Feedback[...]

Chapter 4 SPRU978E – March 2008 Device Clocking Topic .................................................................................................. Page 4.1 Overview .................................................................................. 30 4.2 Clock Domains .........................................................................[...]

www.ti.com 4.1 Overview 4.2 Clock Domains 4.2.1 Core Domains Overview The DM643x DMP requires one primary reference clock. The primary reference clock can be either crystal input or driven by external oscillators. A 27 MHZ crystal at the MXI/CLKIN pin is recommended for the system PLLs, which generate the clocks for the DSP, peripherals, DMA, and i[...]

www.ti.com DSP Subsystem SYSCLK1 SYSCLK3 SCR EDMA VPFE VPBE DACs DDR2 PHY DDR2 VTP DDR2 Memory controller PLLDIV2 (/10) PLLDIV1 (/2) BPDIV PLL Controller 2 PLL Controller 1 PLLDIV2 (/3) PLLDIV3 (/6) PLLDIV1 (/1) SYSCLK2 UAR T s (x2) I2C T imers (x3) PWMs (x3) EMAC EMIF A VL YNQ HPI McASP0 McBSP0 GPIO McBSP1 PCI MXI/CLKIN (27 MHz) PCLK VPBECLK OSCDI[...]

www.ti.com 4.2.2 Core Frequency Flexibility Clock Domains The core frequency domain clocks are supplied by the PLL controller 1 (PLLC1). These domain clocks are flexible, to a degree, within the limitations specified in the device-specific data manual. All of the following frequency ranges and multiplier/divider ratios in the data manual must be ad[...]

www.ti.com 4.2.3 DDR2/EMIF Clock Clock Domains The DDR2 interface has a dedicated clock driven from PLL2. This is a separate clock system from the PLL1 clocks provided to other components of the system. This dedicated clock allows the reduction of the core clock rates to save power while maintaining the required minimum clock rate (125 MHZ) for DDR[...]

www.ti.com 4.2.4 I/O Domains Clock Domains The I/O domains refer to the frequencies of the peripherals that communicate through device pins. In many cases, there are frequency requirements for a peripheral pin interface that are set by an outside standard and must be met. It is not necessarily possible to obtain these frequencies from the on-chip c[...]

www.ti.com 4.2.5 Video Processing Back End 3 2 0 1 0 1 2 PLLDIV2 CLK54 PLL2 DDR_CLKx2 PCLK VPBECLK MXI CLK_VENC CLK_DAC 1 0 venc_sclk_enc CG OSD VENC DACs venc_div2 venc_sclk_osd VPSS VPSS_CLKCTL.MUXSEL CLK54 CLK_VENC CLK_DAC 0 27 MHz Of f 27 MHz 1h 54 54 MHz 54 MHz 2h Of f VPBECLK VPBECLK 3h Of f PCLK Off PLLDIV1 PLLC1 SYSCLKBP VPSS_CLKCTL.MUXSEL [...]

www.ti.com Clock Domains Table 4-6. Possible Clocking Modes VPSS_CLKCTL.MUXSEL Bit Clocking Mode Description 0 MXI mode Both the VENC and the DAC get their clock from PLLC1 SYSCLKBP, which defaults to the MXI 27 MHZ crystal input divide by 1. 1h PLL2 mode The PLL2 (divided-down) generates a 54 MHZ clock. Both the DAC and the VENC receive the 54 MHZ[...]

Chapter 5 SPRU978E – March 2008 PLL Controller Topic .................................................................................................. Page 5.1 PLL Module .............................................................................. 38 5.2 PLL1 Control ............................................................................ [...]

www.ti.com 5.1 PLL Module 5.2 PLL1 Control PLL Module The DM643x DMP has two PLLs (PLL1 and PLL2) that provide clocks to different parts of the system. PLL1 provides clocks (though various dividers) to most of the components of the DM643x DMP. PLL2 is dedicated to the DDR2 port and components for the video processing subsystem (VPSS). The typical r[...]

www.ti.com PLLDIV1(/1) PLLDIV3(/6) PLLDIV2(/3) SYSCLK1 (CLKDIV1Domain) SYSCLK3 (CLKDIV6Domain) SYSCLK2 (CLKDIV3Domain) 1 0 PLLM PLL 0 1 BPDIV CLKMODE CLKIN OSCIN PLLEN SYSCLKBP (VPSS-VPBR ClockSource) OBSCLK (CLKOUT0Pin) PLLOUT AUXCLK (CLKINDomain) OSCDIV1 5.2.1 Device Clock Generation 5.2.2 Steps for Changing PLL1/Core D[...]

www.ti.com 5.2.2.1 Initialization to PLL Mode from PLL Power Down PLL1 Control If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), you must follow the procedure below to change PLL1 frequencies. The recommendation is to stop all peripheral operation before changing the PLL1 frequency, with the exception of the C64x+ DSP and DDR2. The C[...]

www.ti.com 5.2.2.2 Changing PLL Multiplier PLL1 Control If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0) and the PLL stabilization time is previously met (step 7 in Section 5.2.2.1 ), follow this procedure to change PLL1 multiplier. The recommendation is to stop all peripheral operation before changing the PLL multiplier, wit[...]

www.ti.com 5.2.2.3 Changing SYSCLK Dividers PLL1 Control This section discusses the software sequence to change the SYSCLK dividers. The SYSCLK divider change sequence is also referred to as GO operation, as it involves hitting the GO bit (GOSET bit in PLLCMD) to initiate the divider change. The recommendation is to stop all peripheral operation be[...]

www.ti.com 5.3 PLL2 Control PLLDIV2 (/10) PLLDIV1 (/2) 1 0 PLLM PLL 0 1 BPDIV CLKMODE CLKIN OSCIN PLLEN PLL2_SYSCLK2 (VPSS−VPBE) PLL2_SYSCLK1 (DDR2 PHY) PLL2_SYSCLKBP (DDR2 VTP) PLLOUT 5.3.1 Device Clock Generation PLL2 Control PLL2 provides the clock from which the DDR2 memory controller and optional VPBE clocks are derived. The DDR PLL controll[...]

www.ti.com 5.3.2 Steps for Changing PLL2 Frequency 5.3.2.1 DDR2 Considerations When Modifying PLL2 Frequency 5.3.2.1.1 PLL2 Frequency Change Steps When DDR2 Memory Controller is In Reset 5.3.2.1.2 PLL2 Frequency Change Steps When DDR2 Memory Controller is Out of Reset PLL2 Control The PLLC2 is programmed similarly to the PLLC1. Refer to the appropr[...]

www.ti.com 5.3.2.2 Initialization to PLL Mode from PLL Power Down PLL2 Control If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), you must follow the procedure below to change PLL2 frequencies. 1. Select the clock mode by programming the CLKMODE bit in PLLCTL. 2. Before changing the PLL frequency, switch to PLL bypass mode: a. Clear t[...]

www.ti.com 5.3.2.3 Changing PLL Multiplier PLL2 Control If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0) and the PLL stabilization time is previously met (step 7 in Section 5.3.2.2 ), follow this procedure to change PLL2 multiplier. 1. Before changing the PLL frequency, switch to PLL bypass mode: a. Clear the PLLENSRC bit in [...]

www.ti.com 5.3.2.4 Changing SYSCLK Dividers PLL2 Control This section discusses the software sequence to change the SYSCLK dividers. The SYSCLK divider change sequence is also referred to as GO operation, as it involves hitting the GO bit (GOSET bit in PLLCMD) to initiate the divider change. 1. Check for the GOSTAT bit in PLLSTAT to clear to 0 to i[...]

www.ti.com 5.4 PLL Controller Registers PLL Controller Registers Table 5-3 lists the base address and end address for the PLL controllers. Table 5-4 lists the memory-mapped registers for the PLL and reset controller. See the device-specific data manual for the memory address of these registers. Table 5-3. PLL and Reset Controller List PLL and Reset[...]

www.ti.com 5.4.1 Peripheral ID Register (PID) 5.4.2 Reset Type Status Register (RSTYPE) PLL Controller Registers The peripheral ID register (PID) is shown in Figure 5-3 and described in Table 5-5 . Figure 5-3. Peripheral ID Register (PID) 31 24 23 16 Reserved TYPE R-0 R-1h 15 8 7 0 CLASS REV R-8h R-Dh LEGEND: R = Read only; - n = value after reset [...]

www.ti.com 5.4.3 PLL Control Register (PLLCTL) PLL Controller Registers The PLL control register (PLLCTL) is shown in Figure 5-5 and described in Table 5-7 . Figure 5-5. PLL Control Register (PLLCTL) 31 16 Reserved R-0 15 9 8 7 6 5 4 3 2 1 0 Reserved CLKMODE Reserved PLLENSRC PLLDIS PLLRST Rsvd PLLPWRDN PLLEN R-0 R/W-0 R-1h R/W-1 R/W-1 R/W-0 R-0 R/[...]

www.ti.com 5.4.4 PLL Multiplier Control Register (PLLM) 5.4.5 PLL Controller Divider 1 Register (PLLDIV1) PLL Controller Registers The PLL multiplier control register (PLLM) is shown in Figure 5-6 and described in Table 5-8 . Figure 5-6. PLL Multiplier Control Register (PLLM) 31 16 Reserved R-0 15 5 4 0 Reserved PLLM R-0 R/W-10h or 13h (1) LEGEND: [...]

www.ti.com 5.4.6 PLL Controller Divider 2 Register (PLLDIV2) 5.4.7 PLL Controller Divider 3 Register (PLLDIV3) PLL Controller Registers The PLL controller divider 2 register (PLLDIV2) is shown in Figure 5-8 and described in Table 5-10 . Divider 2 controls divider for SYSCLK2. Figure 5-8. PLL Controller Divider 2 Register (PLLDIV2) 31 16 Reserved R-[...]

www.ti.com 5.4.8 Oscillator Divider 1 Register (OSCDIV1) PLL Controller Registers The oscillator divider 1 register (OSCDIV1) is shown in Figure 5-10 and described in Table 5-12 . The oscillator divider 1 controls divider for OBSCLK, dividing down from the MXI/CLKIN clock. For PLLC1, the OBSCLK is connected to CLKOUT0 pin. OSCDIV1 only applies to P[...]

www.ti.com 5.4.9 Bypass Divider Register (BPDIV) PLL Controller Registers The bypass divider register (BPDIV) is shown in Figure 5-11 and described in Table 5-13 . Bypass divider controls divider for SYSCLKBP, dividing down from the MXI/CLKIN clock. Figure 5-11. Bypass Divider Register (BPDIV) 31 16 Reserved R-0 15 14 5 4 0 BPDEN Reserved RATIO R/W[...]

www.ti.com 5.4.10 PLL Controller Command Register (PLLCMD) 5.4.11 PLL Controller Status Register (PLLSTAT) PLL Controller Registers The PLL controller command register (PLLCMD) is shown in Figure 5-12 and described in Table 5-14 . PLLCMD contains the command bit for the GO operation. Writes of 1 initiate command. Writes of 0 clear the bit, but have[...]

www.ti.com 5.4.12 PLL Controller Clock Align Control Register (ALNCTL) PLL Controller Registers The PLL controller clock align control register (ALNCTL) is shown in Figure 5-14 and described in Table 5-16 . ALNCTL indicates which SYSCLKs need to be aligned for proper device operation. You should not modify ALNCTL from its default settings. Figure 5[...]

www.ti.com 5.4.13 PLLDIV Ratio Change Status Register (DCHANGE) PLL Controller Registers The PLLDIV ratio change status register (DCHANGE) is shown in Figure 5-15 and described in Table 5-17 . DCHANGE indicates if the SYSCLK divide ratio has been modified. Figure 5-15. PLLDIV Ratio Change Status Register (DCHANGE) 31 16 Reserved R-0 15 3 2 1 0 Rese[...]

www.ti.com 5.4.14 Clock Enable Control Register (CKEN) PLL Controller Registers The clock enable control register (CKEN) is shown in Figure 5-16 and described in Table 5-18 . CKEN provides clock enable control for miscellaneous output clocks. CKEN is only applicable to PLLC1, not PLLC2. Figure 5-16. Clock Enable Control Register (CKEN) 31 16 Reserv[...]

www.ti.com 5.4.15 Clock Status Register (CKSTAT) PLL Controller Registers The clock status register (CKSTAT) is shown in Figure 5-17 and described in Table 5-19 . CKSTAT shows clock status for all clocks, except SYSCLK n . Figure 5-17. Clock Status Register (CKSTAT) 31 16 Reserved R-0 15 4 3 2 1 0 Reserved BPON Rsvd OBSON AUXON R-0 R-1 R-0 R-0 or 1[...]

www.ti.com 5.4.16 SYSCLK Status Register (SYSTAT) PLL Controller Registers The SYSCLK status register (SYSTAT) is shown in Figure 5-18 and described in Table 5-20 . Indicates SYSCLK on/off status. Actual default is determined by actual clock on/off status, which depends on the D[n]EN bit in PLLDIV[n] default. Figure 5-18. SYSCLK Status Register (SY[...]

Chapter 6 SPRU978E – March 2008 Power and Sleep Controller Topic .................................................................................................. Page 6.1 Introduction .............................................................................. 62 6.2 Power Domain and Module Topology .......................................... [...]

www.ti.com 6.1 Introduction dsp local reset dsp module reset dsp clock DSP dsp power peripheral power peripheral module reset MODx peripheral clock Always on domain PSC clks PLLC RESET VDD POR Emulation Introduction The Power and Sleep Controller (PSC) is responsible for managing transitions of system power on/off, clock on/off, and reset. The DM64[...]

www.ti.com 6.2 Power Domain and Module Topology Power Domain and Module Topology The DM643x DMP includes one power domain--the AlwaysOn power domain. The AlwaysOn power domain is always on when the chip is on. The AlwaysOn domain is powered by the V DD pins of the DM643x DMP (see the device-specific data manual). All of the DM643x DMP modules resid[...]

www.ti.com 6.3 Power Domain and Module States 6.3.1 Power Domain States 6.3.2 Module States Power Domain and Module States Note: The effects of DSP local reset and DSP module reset have not been fully validated; therefore, these resets are not supported and should not be used. Instead, the POR or RESET pins should be used to reset the entire DSP. T[...]

www.ti.com 6.3.3 Local Reset 6.4 Executing State Transitions 6.4.1 Power Domain State Transitions 6.4.2 Module State Transitions Executing State Transitions In addition to module reset (described in Section 6.3.2 ), the DSP CPU can be reset using a special local reset. When DSP local reset is asserted, the DSPs internal memories (L1P, L1D, and L2) [...]

www.ti.com 6.5 IcePick Emulation Support in the PSC 6.6 PSC Interrupts 6.6.1 Interrupt Events IcePick Emulation Support in the PSC The PSC supports IcePick commands that allow IcePick aware emulation tools to have some control over the state of power domains and modules. On the DM643x DMP, this IcePick support only applies to the C64x+ CPU (module [...]

www.ti.com 6.6.1.1 Module State Emulation Events 6.6.1.2 Local Reset Emulation Events 6.6.2 Interrupt Registers PSC Interrupts The DM643x DMP is a single-processor device. The C64x+ CPU must not program its own module state. The C64x+ CPU module state can only be programmed by an external host (for example, PCI, HPI). As a result, interrupt events [...]

www.ti.com 6.6.3 Interrupt Handling 6.7 PSC Registers PSC Registers Handle the PSC interrupts as described in the following procedure: First, enable the interrupt. 1. Set the EMUIHBIE bit and the EMURSTIE bit in MDCTL39 to enable the interrupt events that you want. Note: The PSC interrupt PSCINT is sent to the DSP interrupt controller when at least[...]

www.ti.com 6.7.1 Peripheral Revision and Class Information Register (PID) 6.7.2 Interrupt Evaluation Register (INTEVAL) PSC Registers The peripheral revision and class information (PID) register is shown in Figure 6-2 and described in Table 6-6 . Figure 6-2. Peripheral Revision and Class Information Register (PID) 31 30 29 28 27 16 SCHEME Reserved [...]

www.ti.com 6.7.3 Module Error Pending Register 1 (MERRPR1) 6.7.4 Module Error Clear Register 1 (MERRCR1) PSC Registers The module error pending register 1 (MERRPR1) is shown in Figure 6-4 and described in Table 6-8 . Only the C64x+ CPU (module 39) can have an error condition, as it is the only module with IcePick support. See Section 6.5 for more i[...]

www.ti.com 6.7.5 Power Domain Transition Command Register (PTCMD) 6.7.6 Power Domain Transition Status Register (PTSTAT) PSC Registers The power domain transition command register (PTCMD) is shown in Figure 6-6 and described in Table 6-10 . Figure 6-6. Power Domain Transition Command Register (PTCMD) 31 16 Reserved R-0 15 1 0 Reserved GO[0] R-0 W-0[...]

www.ti.com 6.7.7 Power Domain Status 0 Register (PDSTAT0) PSC Registers The power domain status n register (PDSTAT0) is shown in Figure 6-8 and described in Table 6-12 . PDSTAT0 applies to the AlwaysOn power domain. Figure 6-8. Power Domain Status 0 Register (PDSTAT0) 31 16 Reserved R-0 15 10 9 8 7 5 4 0 Reserved PORDONE POR Reserved STATE R-0 R-1 [...]

www.ti.com 6.7.8 Power Domain Control 0 Register (PDCTL0) PSC Registers The power domain control n register (PDCTL0) is shown in Figure 6-9 and described in Table 6-13 . PDCTL0 applies to the AlwaysOn power domain. Figure 6-9. Power Domain Control 0 Register (PDCTL0) 31 16 Reserved R-0 15 1 0 Reserved NEXT R-0 R/W-1 LEGEND: R/W = Read/Write; R = Re[...]

www.ti.com 6.7.9 Module Status n Register (MDSTATn) PSC Registers The module status n register (MDSTAT0-MDSTAT39) is shown in Figure 6-10 and described in Table 6-14 . Figure 6-10. Module Status n Register (MDSTAT n ) 31 18 17 16 Reserved EMUIHB EMURST R-0 R-0 R-0 15 13 12 11 10 9 8 7 6 5 0 Reserved MCKOUT Reserved MRST LRSTDONE LRST Reserved STATE[...]

www.ti.com 6.7.10 Module Control n Register (MDCTLn) PSC Registers The module control n register (MDCTL0-MDCTL39) is shown in Figure 6-11 and described in Table 6-15 . Figure 6-11. Module Control n Register (MDCTL n ) 31 16 Reserved R-0 15 11 10 9 8 7 3 2 0 Reserved EMUIHBIE EMURSTIE LRST Reserved NEXT R-0 R/W-0 R/W-0 R/W-1 R-0 R/W-0 LEGEND: R/W = [...]

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Chapter 7 SPRU978E – March 2008 Power Management Topic .................................................................................................. Page 7.1 Overview .................................................................................. 78 7.2 PSC and PLLC Overview ............................................................ 78 [...]

www.ti.com 7.1 Overview 7.2 PSC and PLLC Overview Overview In many applications, there may be specific requirements to minimize power consumption for both power supply (or battery) and thermal considerations. There are two components to power consumption: active power and leakage power. Active power is the power consumed to perform work and scales [...]

www.ti.com 7.3 Clock Management 7.3.1 Module Clock ON/OFF 7.3.2 Module Clock Frequency Scaling 7.3.3 PLL Bypass and Power Down Clock Management The module clock on/off feature allows software to disable clocks to module individually, in order to reduce the module's active power consumption to 0. The DM643x DMP is designed in full static CMOS; [...]

www.ti.com 7.4 DSP Sleep Mode Management 7.4.1 DSP Sleep Modes 7.4.2 DSP Module Clock ON/OFF 7.4.2.1 DSP Module Clock ON DSP Sleep Mode Management The C64x+ DSP supports sleep mode management to reduce power: • DSP clock can be completely shut off • C64x+ Megamodule can be put in sleep mode – C64x+ CPU can be put in sleep mode On the DM643x D[...]

www.ti.com 7.4.2.2 DSP Module Clock Off 7.5 3.3 V I/O Power Down 7.6 Video DAC Power Down 3.3 V I/O Power Down In the clock Disable state, the DSP’s module clock is disabled, while DSP reset remains de-asserted. This state is typically used to disable the DSP clock to save power. As mentioned in Section 7.4.2 , the DSP cannot put itself in Disabl[...]

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Chapter 8 SPRU978E – March 2008 Interrupt Controller The C64x+ Megamodule includes an interrupt controller (INTC) to manage CPU interrupts. The interrupt controller interfaces the system events to the CPU's interrupt and exception inputs. The interrupt controller supports up to 128 system events, and it maps these system events to the 12 CPU[...]

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Chapter 9 SPRU978E – March 2008 System Module Topic .................................................................................................. Page 9.1 Overview .................................................................................. 86 9.2 Device Identification .................................................................. [...]

www.ti.com 9.1 Overview 9.2 Device Identification 9.3 Device Configuration 9.3.1 Pin Multiplexing Control 9.3.2 Device Boot Configuration Status Overview The TMS320DM643x DMP System Module is a system-level module containing status and top-level control logic required by the device. The System Module consists of a set of status and control register[...]

www.ti.com 9.4 3.3 V I/O Power-Down Control 9.5 Peripheral Status and Control 9.5.1 Timer Control 9.5.2 VPSS Clock and DAC Control 9.5.3 DDR2 VTP Control 9.5.4 HPI Control 3.3 V I/O Power-Down Control The VDD3P3V_PWDN register controls power to the 3.3 V I/O cells. Some 3.3 V I/Os default to power down for power saving. See device-specific data man[...]

www.ti.com 9.6 Bandwidth Management 9.6.1 Bus Master DMA Priority Control Bandwidth Management In order to determine allowed connections between masters and slaves, each master request source must have a unique master ID (mstid) associated with it. The master ID for each DM643x DMP master is shown in Table 9-1 . Table 9-1. TMS320DM643x DMP Master I[...]

www.ti.com 9.6.2 EDMA Transfer Controller Configuration 9.7 Boot Control Boot Control Each switched central resource (SCR) performs prioritization based on the priority level of the master that sends the command. Each bus master's priority is programmed in the chip-level Bus Master Priority Control Registers (MSTPRI0 or MSTPRI1). The default p[...]

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Chapter 10 SPRU978E – March 2008 Reset Topic .................................................................................................. Page 10.1 Overview .................................................................................. 92 10.2 Reset Pins ................................................................................ 92[...]

www.ti.com 10.1 Overview 10.2 Reset Pins 10.3 Device Configurations at Reset Overview There are different types of reset in the TMS320DM643x DMP. The types of reset differ by how they are initiated and/or by their effect on the chip. Each type is briefly described in Table 10-1 . Refer to the device-specific data manual for more details on each of [...]

www.ti.com 10.4 DSP Reset 10.4.1 DSP Local Reset 10.4.2 DSP Module Reset 10.4.2.1 Software Reset Disable (SwRstDisable) DSP Reset Note: The effects of DSP local reset and DSP module reset have not been fully validated; therefore, these resets are not supported and should not be used. Instead, the POR or RESET pins should be used to reset the entire[...]

www.ti.com 10.4.2.2 Synchronous Reset (SyncReset) DSP Reset • Host: Assert the DSP local reset (Optional) – Clear the LRST bit in MDCTL39 to 0. This step is optional. This step asserts the DSP local reset, and is included here so that the DSP does not start running immediately upon it is subsequently enable by the host. Typically, the host only[...]

Chapter 11 SPRU978E – March 2008 Boot Modes The TMS320DM643x DMP can boot from either asynchronous EMIF/NOR Flash directly or from internal boot ROM, as determined by the setting of the device boot and configuration pins. The input states of the boot and configuration pins are sampled and latched into the BOOTCFG register when device reset is dea[...]

Boot Modes 96 SPRU978E – March 2008 Submit Documentation Feedback[...]

Appendix A SPRU978E – March 2008 Revision History Table A-1 lists the changes made since the previous version of this document. Table A-1. Document Revision History Reference Additions/Modifications/Deletions Figure 6-1 Added Note. Section 6.3 Added Note. Section 10.4 Added Note. SPRU978E – March 2008 Revision History 97 Submit Documentation Fe[...]

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