Texas Instruments TMS320DM643x DMP manuale d’uso

TMS320DM643x DMP Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module User's Guide Literature Number: SPRU941A April 2007[...]

2 SPRU941A – April 2007 Submit Documentation Feedback[...]

Contents Preface .............................................................................................................................. 10 1 Introduction .............................................................................................................. 11 1.1 Purpose of the Peripheral ............................................[...]

5.1 Transmit Identification and Version Register (TXIDVER) ................................................. 71 5.2 Transmit Control Register (TXCONTROL) .................................................................. 71 5.3 Transmit Teardown Register (TXTEARDOWN) ............................................................ 72 5.4 Receive Identi[...]

Appendix A Glossary ...................................................................................................... 117 Appendix B Revision History ............................................................................................ 119 SPRU941A – April 2007 Contents 5 Submit Documentation Feedback[...]

List of Figures 1 EMAC and MDIO Block Diagram ........................................................................................ 12 2 Typical Ethernet Configuration ........................................................................................... 14 3 Ethernet Frame Format ............................................................[...]

53 Receive Channel n Free Buffer Count Register (RX n FREEBUFFER) .............................................. 93 54 MAC Control Register (MACCONTROL) ................................................................................ 94 55 MAC Status Register (MACSTATUS) ..............................................................................[...]

List of Tables 1 EMAC and MDIO Signals ................................................................................................. 14 2 Ethernet Frame Description ............................................................................................... 15 3 Basic Descriptor Description ...................................................[...]

50 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions ......... 92 51 Receive Channel n Flow Control Threshold Register (RX n FLOWTHRESH) Field Descriptions ................ 92 52 Receive Channel n Free Buffer Count Register (RX n FREEBUFFER) Field Descriptions ....................... 93 53 MAC Control Regis[...]

Preface SPRU941A – April 2007 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the TMS320DM643x Digital Media Processor (DMP). Included are the features of the EMAC and MDIO modul[...]

1 Introduction 1.1 Purpose of the Peripheral 1.2 Features User's Guide SPRU941A – April 2007 Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module int[...]

www.ti.com 1.3 Functional Block Diagram Configuration bus DMA memory transfer controller Peripheral bus EMAC control module EMAC module MDIO module MII bus MDIO bus EMAC/MDIO interrupt DSP interrupt controller Introduction Figure 1 shows the three main functional modules of the EMAC/MDIO peripheral: • EMAC control module • EMAC module • MDIO [...]

www.ti.com 1.4 Industry Standard(s) Compliance Statement 2 Peripheral Architecture 2.1 Clock Control 2.2 Memory Map 2.3 Signal Descriptions Peripheral Architecture The EMAC peripheral conforms to the IEEE 802.3 standard, describing the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer specifications. [...]

www.ti.com MTCLK MTXD(3−0) MTXEN MCOL MCRS MRCLK MRXD(3−0) MRXDV MRXER MDCLK MDIO Physical layer device (PHY) System core Transformer 2.5 MHz or 25 MHz RJ−45 EMAC MDIO Peripheral Architecture Figure 2. Typical Ethernet Configuration Table 1. EMAC and MDIO Signals Signal Type Description MTCLK I Transmit clock (MTCLK). The transmit clock is a [...]

www.ti.com 2.4 Ethernet Protocol Overview 2.4.1 Ethernet Frame Format Preamble SFD Destination Source Len Data 7 1 6 6 2 46−1500 4 FCS Number of bytes Legend: SFD=Start Frame Delimeter; FCS=Frame Check Sequence (CRC) Peripheral Architecture A brief overview of the Ethernet protocol is given in the following subsections. For in-depth information o[...]

www.ti.com 2.4.2 Ethernet’s Multiple Access Protocol 2.5 Programming Interface 2.5.1 Packet Buffer Descriptors Peripheral Architecture Nodes in an Ethernet Local Area Network are interconnected by a broadcast channel, as a result, when an EMAC port transmits a frame, all the adapters on the local network receive the frame. Carrier Sense Multiple [...]

www.ti.com SOP | EOP 60 0 60 pBuf fer pNext Packet A 60 bytes 0 SOP Fragment 1 Packet B 512 1514 pBuf fer pNext 512 bytes EOP 0 0 −−− Packet B Fragment 3 500 bytes 502 pBuf fer −−− 500 pNext −−− pBuf fer pNext Packet B Fragment 2 502 bytes SOP | EOP 0 1514 bytes Packet C 1514 pBuf fer pNext (NULL) 1514 Peripheral Architecture Tabl[...]

www.ti.com 2.5.2 Transmit and Receive Descriptor Queues Peripheral Architecture The EMAC module processes descriptors in linked list chains as discussed in Section 2.5.1 . The lists controlled by the EMAC are maintained by the application software through the use of the head descriptor pointer registers (HDP). Since the EMAC supports eight channels[...]

www.ti.com 2.5.3 Transmit and Receive EMAC Interrupts Peripheral Architecture The EMAC processes descriptors in linked list chains as discussed in Section 2.5.1 , using the linked list queue mechanism discussed in Section 2.5.2 . The EMAC synchronizes descriptor list processing through the use of interrupts to the software application. The interrup[...]

www.ti.com 2.5.4 Transmit Buffer Descriptor Format Peripheral Architecture A transmit (TX) buffer descriptor ( Figure 6 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 1 shows the transmit buffer descriptor described by a C structure. Figure 6. Transmit Buffer Desc[...]

www.ti.com 2.5.4.1 Next Descriptor Pointer 2.5.4.2 Buffer Pointer 2.5.4.3 Buffer Offset 2.5.4.4 Buffer Length 2.5.4.5 Packet Length 2.5.4.6 Start of Packet (SOP) Flag Peripheral Architecture The next descriptor pointer points to the 32-bit word aligned memory address of the next buffer descriptor in the transmit queue. This pointer is used to creat[...]

www.ti.com 2.5.4.7 End of Packet (EOP) Flag 2.5.4.8 Ownership (OWNER) Flag 2.5.4.9 End of Queue (EOQ) Flag 2.5.4.10 Teardown Complete (TDOWNCMPLT) Flag 2.5.4.11 Pass CRC (PASSCRC) Flag Peripheral Architecture When set, this flag indicates that the descriptor points to a packet buffer that is last for a given packet. In the case of a single fragment[...]

www.ti.com 2.5.5 Receive Buffer Descriptor Format 2.5.5.1 Next Descriptor Pointer 2.5.5.2 Buffer Pointer Peripheral Architecture A receive (RX) buffer descriptor ( Figure 7 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 2 shows the receive buffer descriptor descri[...]

www.ti.com 2.5.5.3 Buffer Offset Peripheral Architecture Example 2. Receive Buffer Descriptor in C Structure Format /* // EMAC Descriptor // // The following is the format of a single buffer descriptor // on the EMAC. */ typedef struct _EMAC_Desc { struct _EMAC_Desc *pNext; /* Pointer to next descriptor in chain */ Uint8 *pBuffer; /* Pointer to dat[...]

www.ti.com 2.5.5.4 Buffer Length 2.5.5.5 Packet Length 2.5.5.6 Start of Packet (SOP) Flag 2.5.5.7 End of Packet (EOP) Flag 2.5.5.8 Ownership (OWNER) Flag 2.5.5.9 End of Queue (EOQ) Flag Peripheral Architecture This 16-bit field is used for two purposes: • Before the descriptor is first placed on the receive queue by the application software, the [...]

www.ti.com 2.5.5.10 Teardown Complete (TDOWNCMPLT) Flag 2.5.5.11 Pass CRC (PASSCRC) Flag 2.5.5.12 Jabber Flag 2.5.5.13 Oversize Flag 2.5.5.14 Fragment Flag 2.5.5.15 Undersized Flag 2.5.5.16 Control Flag 2.5.5.17 Overrun Flag 2.5.5.18 Code Error (CODEERROR) Flag 2.5.5.19 Alignment Error (ALIGNERROR) Flag 2.5.5.20 CRC Error (CRCERROR) Flag Peripheral[...]

www.ti.com 2.5.5.21 No Match (NOMATCH) Flag 2.6 EMAC Control Module Arbiter and bus switches CPU DMA Controllers 8K byte descriptor memory Configuration registers Interrupt logic Single interrupt to CPU EMAC interrupts MDIO interrupts Configuration bus T ransmit and Receive 2.6.1 Internal Memory 2.6.2 Bus Arbiter Peripheral Architecture This flag i[...]

www.ti.com 2.6.3 Interrupt Control 2.7 MDIO Module 2.7.1 MDIO Module Components Peripheral Architecture The EMAC control module combines multiple interrupt conditions generated by the EMAC and MDIO modules into a single interrupt signal that is mapped to a CPU interrupt via the CPU interrupt controller. The control module uses two registers to cont[...]

www.ti.com EMAC control module Control registers and logic PHY monitoring Peripheral clock MDIO clock generator USERINT MDIO interface polling PHY MDCLK MDIO LINKINT Configuration bus 2.7.1.1 MDIO Clock Generator 2.7.1.2 Global PHY Detection and Link State Monitoring 2.7.1.3 Active PHY Monitoring 2.7.1.4 PHY Register User Access Peripheral Architec[...]

www.ti.com 2.7.2 MDIO Module Operational Overview Peripheral Architecture The MDIO module implements the 802.3 serial management interface to interrogate and control an Ethernet PHY, using a shared two-wired bus. It separately performs autodetection and records the current link status of up to 32 PHYs, polling all 32 MDIO addresses. Application sof[...]

www.ti.com 2.7.2.1 Initializing the MDIO Module 2.7.2.2 Writing Data To a PHY Register 2.7.2.3 Reading Data From a PHY Register Peripheral Architecture The following steps are performed by the application software or device driver to initialize the MDIO device: 1. Configure the PREAMBLE and CLKDIV bits in the MDIO control register (CONTROL). 2. Ena[...]

www.ti.com 2.7.2.4 Example of MDIO Register Access Code Peripheral Architecture The MDIO module uses the MDIO user access register (USERACCESS n ) to access the PHY control registers. Software functions that implement the access process may simply be the following four macros: • PHYREG_read( regadr, phyadr ) Start the process of reading a PHY reg[...]

www.ti.com 2.8 EMAC Module 2.8.1 EMAC Module Components Clock and reset logic Receive DMA engine Interrupt controller Transmit DMA engine Control registers Configuration bus EMAC control module Configuration bus RAM State FIFO Receive FIFO Transmit MAC transmitter Statistics receiver MAC SYNC MII address Receive 2.8.1.1 Receive DMA Engine 2.8.1.2 R[...]

www.ti.com 2.8.1.4 Transmit DMA Engine 2.8.1.5 Transmit FIFO 2.8.1.6 MAC Transmitter 2.8.1.7 Statistics Logic 2.8.1.8 State RAM 2.8.1.9 EMAC Interrupt Controller 2.8.1.10 Control Registers and Logic 2.8.1.11 Clock and Reset Logic 2.8.2 EMAC Module Operational Overview Peripheral Architecture The transmit DMA engine is the interface between the tran[...]

www.ti.com 2.9 Media Independent Interface (MII) 2.9.1 Data Reception 2.9.1.1 Receive Control 2.9.1.2 Receive Inter-Frame Interval 2.9.1.3 Receive Flow Control Peripheral Architecture The EMAC module operates independently of the CPU. It is configured and controlled by its register set mapped into device memory. Information about data packets is co[...]

www.ti.com Peripheral Architecture In either case, receive flow control prevents frame reception by issuing the flow control appropriate for the current mode of operation. Receive flow control prevents reception of frames on the EMAC until all of the triggering conditions clear, at which time frames may again be received by the EMAC. Receive flow c[...]

www.ti.com 2.9.2 Data Transmission 2.9.2.1 Transmit Control 2.9.2.2 CRC Insertion 2.9.2.3 Adaptive Performance Optimization (APO) 2.9.2.4 Interpacket-Gap (IPG) Enforcement 2.9.2.5 Back Off Peripheral Architecture The EMAC passes data to the PHY from the transmit FIFO (when enabled). Data is synchronized to the transmit clock rate. Transmission begi[...]

www.ti.com 2.9.2.6 Transmit Flow Control 2.9.2.7 Speed, Duplex, and Pause Frame Support Peripheral Architecture Incoming pause frames are acted upon, when enabled, to prevent the EMAC from transmitting any further frames. Incoming pause frames are only acted upon when the FULLDUPLEX and TXFLOWEN bits in the MAC control register (MACCONTROL) are set[...]

www.ti.com 2.10 Packet Receive Operation 2.10.1 Receive DMA Host Configuration 2.10.2 Receive Channel Enabling 2.10.3 Receive Address Matching Peripheral Architecture To configure the receive DMA for operation the host must: • Initialize the receive addresses. • Initialize the receive channel n DMA head descriptor pointer registers (RX n HDP) t[...]

www.ti.com 2.10.4 Hardware Receive QOS Support 2.10.5 Host Free Buffer Tracking 2.10.6 Receive Channel Teardown Peripheral Architecture Hardware receive quality of service (QOS) is supported, when enabled, by the Tag Protocol Identifier format and the associated Tag Control Information (TCI) format priority field. When the incoming frame length/typ[...]

www.ti.com 2.10.7 Receive Frame Classification 2.10.8 Promiscuous Receive Mode Peripheral Architecture Received frames are proper (good) frames, if they are between 64 bytes and the value in the receive maximum length register (RXMAXLEN) bytes in length (inclusive) and contain no code, align, or CRC errors. Received frames are long frames, if their[...]

www.ti.com Peripheral Architecture Table 4. Receive Frame Treatment Summary Address Match RXCAFEN RXCEFEN RXCMFEN RXCSFEN Receive Frame Treatment 0 0 X X X No frames transferred. 0 1 0 0 0 Proper frames transferred to promiscuous channel. 0 1 0 0 1 Proper/undersized data frames transferred to promiscuous channel. 0 1 0 1 0 Proper data and control f[...]

www.ti.com 2.10.9 Receive Overrun Peripheral Architecture The types of receive overrun are: • FIFO start of frame overrun (FIFO_SOF) • FIFO middle of frame overrun (FIFO_MOF) • DMA start of frame overrun (DMA_SOF) • DMA middle of frame overrun (DMA_MOF) The statistics counters used to track these types of receive overrun are: • Receive st[...]

www.ti.com 2.11 Packet Transmit Operation 2.11.1 Transmit DMA Host Configuration 2.11.2 Transmit Channel Teardown 2.12 Receive and Transmit Latency Peripheral Architecture The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed or round-robin as selected by the TXPTYPE bit in the MAC control register (M[...]

www.ti.com 2.13 Transfer Node Priority 2.14 Reset Considerations 2.14.1 Software Reset Considerations Peripheral Architecture Latency to system’s internal and external RAM can be controlled through the use of the transfer node priority allocation register available at the device level. Latency to descriptor RAM is low because RAM is local to the [...]

www.ti.com 2.14.2 Hardware Reset Considerations 2.15 Initialization 2.15.1 Enabling the EMAC/MDIO Peripheral 2.15.2 EMAC Control Module Initialization Peripheral Architecture When a hardware reset occurs, the EMAC peripheral has its register values reset and all the components return to their default state. After the hardware reset, the EMAC needs [...]

www.ti.com 2.15.3 MDIO Module Initialization Peripheral Architecture Example 4. EMAC Control Module Initialization Code Uint32 tmpval ; /* // Globally disable EMAC/MDIO interrupts in the control module */ CSL_FINST( ECTL_REGS->EWCTL, ECTL_EWCTL_INTEN, DISABLE ) ; /* Wait about 100 cycles */ for( I=0; i<5; I++ ) tmpval = ECTL_REGS->EWCTL ; [...]

www.ti.com 2.15.4 EMAC Module Initialization Peripheral Architecture The EMAC module is used to send and receive data packets over the network. This is done by maintaining up to eight transmit and receive descriptor queues. The EMAC module configuration must also be kept up-to-date based on PHY negotiation results returned from the MDIO module. Mos[...]

www.ti.com 2.16 Interrupt Support 2.16.1 EMAC Module Interrupt Events and Requests 2.16.1.1 Transmit Packet Completion Interrupts 2.16.1.2 Receive Packet Completion Interrupts Peripheral Architecture The EMAC module generates 18 interrupt events: • TXPEND n : Transmit packet completion interrupt for transmit channels 0 through 7 • RXPEND n : Re[...]

www.ti.com 2.16.1.3 Statistics Interrupt 2.16.1.4 Host Error Interrupt Peripheral Architecture Upon interrupt reception, the CPU processes one or more packets from the buffer chain and then acknowledges one or more interrupt(s) by writing the address of the last buffer descriptor processed to the queue's associated receive completion pointer i[...]

www.ti.com 2.16.2 MDIO Module Interrupt Events and Requests 2.16.2.1 Link Change Interrupt 2.16.2.2 User Access Completion Interrupt 2.16.3 Proper Interrupt Processing 2.16.4 Interrupt Multiplexing Peripheral Architecture The MDIO module generates two interrupt events: • LINKINT: Serial interface link change interrupt. Indicates a change in the s[...]

www.ti.com 2.17 Power Management 2.18 Emulation Considerations Peripheral Architecture Each of the three main components of the EMAC peripheral can independently be placed in reduced-power modes to conserve power during periods of low activity. The power management of the EMAC peripheral is controlled by the processor Power and Sleep Controller (PS[...]

www.ti.com 3 EMAC Control Module Registers 3.1 EMAC Control Module Interrupt Control Register (EWCTL) EMAC Control Module Registers Table 7 lists the memory-mapped registers for the EMAC control module. See the device-specific data manual for the memory address of these registers. Table 7. EMAC Control Module Registers Offset Acronym Register Descr[...]

www.ti.com 3.2 EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) EMAC Control Module Registers The EMAC control module interrupt timer count register (EWINTTCNT) is used to control the generation of back-to-back interrupts from the EMAC and MDIO modules. The value of this timer count is loaded into an internal counter every time interr[...]

www.ti.com 4 MDIO Registers 4.1 MDIO Version Register (VERSION) MDIO Registers Table 10 lists the memory-mapped registers for the MDIO module. See the device-specific data manual for the memory address of these registers. Table 10. Management Data Input/Output (MDIO) Registers Offset Acronym Register Description Section 0h VERSION MDIO Version Regi[...]

www.ti.com 4.2 MDIO Control Register (CONTROL) MDIO Registers The MDIO control register (CONTROL) is shown in Figure 14 and described in Table 12 . Figure 14. MDIO Control Register (CONTROL) 31 30 29 28 24 23 21 20 19 18 17 16 IDLE ENABLE Rsvd HIGHEST_USER_CHANNEL Reserved PREAMBLE FAULT FAULTENB Reserved R-1 R/W-0 R-0 R-1 R-0 R/W-0 R/WC-0 R/W-0 R-[...]

www.ti.com 4.3 PHY Acknowledge Status Register (ALIVE) 4.4 PHY Link Status Register (LINK) MDIO Registers The PHY acknowledge status register (ALIVE) is shown in Figure 15 and described in Table 13 . Figure 15. PHY Acknowledge Status Register (ALIVE) 31 16 ALIVE R/WC-0 15 0 ALIVE R/WC-0 LEGEND: R/W = Read/Write; WC = Write 1 to clear; - n = value a[...]

www.ti.com 4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) MDIO Registers The MDIO link status change interrupt (unmasked) register (LINKINTRAW) is shown in Figure 17 and described in Table 15 . Figure 17. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) 31 16 Reserved R-0 15 2 1 0 Reserved LINKINTRAW R-0 R/[...]

www.ti.com 4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) MDIO Registers The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in Figure 18 and described in Table 16 . Figure 18. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) 31 16 Reserved R-0 15 2 1 0 Reserved LINKINTMASKED [...]

www.ti.com 4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) MDIO Registers The MDIO user command complete interrupt (unmasked) register (USERINTRAW) is shown in Figure 19 and described in Table 17 . Figure 19. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) 31 16 Reserved R-0 15 2 1 0 Reserved USERINTR[...]

www.ti.com 4.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) MDIO Registers The MDIO user command complete interrupt (masked) register (USERINTMASKED) is shown in Figure 20 and described in Table 18 . Figure 20. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) 31 16 Reserved R-0 15 2 1 0 Reserved USERI[...]

www.ti.com 4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) MDIO Registers The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in Figure 21 and described in Table 19 . Figure 21. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) 31 16 Reserved R-0 15 2 1 0 Reserved US[...]

www.ti.com 4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) MDIO Registers The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 22 and described in Table 20 . Figure 22. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) 31 16 Reserved R-0 15 2 1 [...]

www.ti.com 4.11 MDIO User Access Register 0 (USERACCESS0) MDIO Registers The MDIO user access register 0 (USERACCESS0) is shown in Figure 23 and described in Table 21 . Figure 23. MDIO User Access Register 0 (USERACCESS0) 31 30 29 28 26 25 21 20 16 GO WRITE ACK Reserved REGADR PHYADR R/WS-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R = Re[...]

www.ti.com 4.12 MDIO User PHY Select Register 0 (USERPHYSEL0) MDIO Registers The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 24 and described in Table 22 . Figure 24. MDIO User PHY Select Register 0 (USERPHYSEL0) 31 16 Reserved R-0 15 8 7 6 5 4 0 Reserved LINKSEL LINKINTENB Rsvd PHYADRMON R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R/W =[...]

www.ti.com 4.13 MDIO User Access Register 1 (USERACCESS1) MDIO Registers The MDIO user access register 1 (USERACCESS1) is shown in Figure 25 and described in Table 23 . Figure 25. MDIO User Access Register 1 (USERACCESS1) 31 30 29 28 26 25 21 20 16 GO WRITE ACK Reserved REGADR PHYADR R/WS-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R = Re[...]

www.ti.com 4.14 MDIO User PHY Select Register 1 (USERPHYSEL1) MDIO Registers The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 26 and described in Table 24 . Figure 26. MDIO User PHY Select Register 1 (USERPHYSEL1) 31 16 Reserved R-0 15 8 7 6 5 4 0 Reserved LINKSEL LINKINTENB Rsvd PHYADRMON R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R/W =[...]

www.ti.com 5 Ethernet Media Access Controller (EMAC) Registers Ethernet Media Access Controller (EMAC) Registers Table 25 lists the memory-mapped registers for the EMAC. See the device-specific data manual for the memory address of these registers. Table 25. Ethernet Media Access Controller (EMAC) Registers Offset Acronym Register Description Secti[...]

www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 25. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description Section 168h EMCONTROL Emulation Control Register Section 5.30 16Ch FIFOCONTROL FIFO Control Register Section 5.31 170h MACCONFIG MAC Configuration Register Section 5.32 174h SOFTRE[...]

www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 25. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description Section 67Ch RX7CP Receive Channel 7 Completion Pointer Register Section 5.48 Network Statistics Registers 200h RXGOODFRAMES Good Receive Frames Register Section 5.49.1 204h RXBCAST[...]

www.ti.com 5.1 Transmit Identification and Version Register (TXIDVER) 5.2 Transmit Control Register (TXCONTROL) Ethernet Media Access Controller (EMAC) Registers The transmit identification and version register (TXIDVER) is shown in Figure 27 and described in Table 26 . Figure 27. Transmit Identification and Version Register (TXIDVER) 31 16 TXIDENT[...]

www.ti.com 5.3 Transmit Teardown Register (TXTEARDOWN) Ethernet Media Access Controller (EMAC) Registers The transmit teardown register (TXTEARDOWN) is shown in Figure 29 and described in Table 28 . Figure 29. Transmit Teardown Register (TXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved TXTDNCH R-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; - n [...]

www.ti.com 5.4 Receive Identification and Version Register (RXIDVER) 5.5 Receive Control Register (RXCONTROL) Ethernet Media Access Controller (EMAC) Registers The receive identification and version register (RXIDVER) is shown in Figure 30 and described in Table 29 . Figure 30. Receive Identification and Version Register (RXIDVER) 31 16 RXIDENT R-0[...]

www.ti.com 5.6 Receive Teardown Register (RXTEARDOWN) Ethernet Media Access Controller (EMAC) Registers The receive teardown register (RXTEARDOWN) is shown in Figure 32 and described in Table 31 . Figure 32. Receive Teardown Register (RXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved RXTDNCH R-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; - n = v[...]

www.ti.com 5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Ethernet Media Access Controller (EMAC) Registers The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in Figure 33 and described in Table 32 . Figure 33. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) 31 16 Reserved R-0 15 8 Reserved R-0 [...]

www.ti.com 5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Ethernet Media Access Controller (EMAC) Registers The transmit interrupt status (masked) register (TXINTSTATMASKED) is shown in Figure 34 and described in Table 33 . Figure 34. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) 31 16 Reserved R-0 15 8 Reserved R[...]

www.ti.com 5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) Ethernet Media Access Controller (EMAC) Registers The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 35 and described in Table 34 . Figure 35. Transmit Interrupt Mask Set Register (TXINTMASKSET) 31 16 Reserved R-0 15 8 Reserved R-0 76543210 TX7MASK TX6MASK TX[...]

www.ti.com 5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Ethernet Media Access Controller (EMAC) Registers The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in Figure 36 and described in Table 35 . Figure 36. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) 31 16 Reserved R-0 15 8 Reserved R-0 76543210 TX7MA[...]

www.ti.com 5.11 MAC Input Vector Register (MACINVECTOR) Ethernet Media Access Controller (EMAC) Registers The MAC input vector register (MACINVECTOR) is shown in Figure 37 and described in Table 36 . Figure 37. MAC Input Vector Register (MACINVECTOR) 31 30 29 18 17 16 USERINT LINKINT Reserved HOSTPEND STATPEND R-0 R-0 R-0 R-0 R-0 15 8 7 0 RXPEND TX[...]

www.ti.com 5.12 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Ethernet Media Access Controller (EMAC) Registers The receive interrupt status (unmasked) register (RXINTSTATRAW) is shown in Figure 38 and described in Table 37 . Figure 38. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) 31 16 Reserved R-0 15 8 Reserved R-0 76[...]

www.ti.com 5.13 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Ethernet Media Access Controller (EMAC) Registers The receive interrupt status (masked) register (RXINTSTATMASKED) is shown in Figure 39 and described in Table 38 . Figure 39. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) 31 16 Reserved R-0 15 8 Reserved R-0[...]

www.ti.com 5.14 Receive Interrupt Mask Set Register (RXINTMASKSET) Ethernet Media Access Controller (EMAC) Registers The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 40 and described in Table 39 . Figure 40. Receive Interrupt Mask Set Register (RXINTMASKSET) 31 16 Reserved R-0 15 8 Reserved R-0 76543210 RX7MASK RX6MASK RX5M[...]

www.ti.com 5.15 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Ethernet Media Access Controller (EMAC) Registers The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 41 and described in Table 40 . Figure 41. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) 31 16 Reserved R-0 15 8 Reserved R-0 76543210 RX7MASK [...]

www.ti.com 5.16 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) 5.17 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Ethernet Media Access Controller (EMAC) Registers The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Figure 42 and described in Table 41 . Figure 42. MAC Interrupt Status (Unmasked) Register ([...]

www.ti.com 5.18 MAC Interrupt Mask Set Register (MACINTMASKSET) 5.19 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Ethernet Media Access Controller (EMAC) Registers The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 44 and described in Table 43 . Figure 44. MAC Interrupt Mask Set Register (MACINTMASKSET) 31 16 Reserved R-0[...]

www.ti.com 5.20 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Ethernet Media Access Controller (EMAC) Registers The receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) is shown in Figure 46 and described in Table 45 . Figure 46. Receive Multicast/Broadcast/Promiscuous Channel Enable Register[...]

www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 45. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field Value Description 22 RXCEFEN Receive copy error frames enable bit. Enables frames containing errors to be transferred to memory. The appropriate error bit will [...]

www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 45. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field Value Description 2-0 RXMULTCH 0-7h Receive multicast channel select 0 Select channel 0 to receive multicast frames 1h Select channel 1 to receive multicast fra[...]

www.ti.com 5.21 Receive Unicast Enable Set Register (RXUNICASTSET) Ethernet Media Access Controller (EMAC) Registers The receive unicast enable set register (RXUNICASTSET) is shown in Figure 47 and described in Table 46 . Figure 47. Receive Unicast Enable Set Register (RXUNICASTSET) 31 16 Reserved R-0 15 8 Reserved R-0 76543210 RXCH7EN RXCH6EN RXCH[...]

www.ti.com 5.22 Receive Unicast Clear Register (RXUNICASTCLEAR) Ethernet Media Access Controller (EMAC) Registers The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 48 and described in Table 47 . Figure 48. Receive Unicast Clear Register (RXUNICASTCLEAR) 31 16 Reserved R-0 15 8 Reserved R-0 76543210 RXCH7EN RXCH6EN RXCH5EN RXCH4[...]

www.ti.com 5.23 Receive Maximum Length Register (RXMAXLEN) 5.24 Receive Buffer Offset Register (RXBUFFEROFFSET) Ethernet Media Access Controller (EMAC) Registers The receive maximum length register (RXMAXLEN) is shown in Figure 49 and described in Table 48 . Figure 49. Receive Maximum Length Register (RXMAXLEN) 31 16 Reserved R-0 15 0 RXMAXLEN R/W-[...]

www.ti.com 5.25 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) 5.26 Receive Channel 0-7 Flow Control Threshold Register (RX nFLOWTHRESH) Ethernet Media Access Controller (EMAC) Registers The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in Figure 51 and described in Table 50 . Figure 51.[...]

www.ti.com 5.27 Receive Channel 0-7 Free Buffer Count Register (RX nFREEBUFFER) Ethernet Media Access Controller (EMAC) Registers The receive channel 0-7 free buffer count register (RX n FREEBUFFER) is shown in Figure 53 and described in Table 52 . Figure 53. Receive Channel n Free Buffer Count Register (RX n FREEBUFFER) 31 16 Reserved R-0 15 0 RX [...]

www.ti.com 5.28 MAC Control Register (MACCONTROL) Ethernet Media Access Controller (EMAC) Registers The MAC control register (MACCONTROL) is shown in Figure 54 and described in Table 53 . Figure 54. MAC Control Register (MACCONTROL) 31 16 Reserved R-0 15 14 13 12 11 10 9 8 Reserved RXOFFLENBLOCK RXOWNERSHIP Reserved CMDIDLE Reserved TXPTYPE Reserve[...]

www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 53. MAC Control Register (MACCONTROL) Field Descriptions (continued) Bit Field Value Description 3 RXBUFFERFLOWEN Receive buffer flow control enable bit 0 Receive flow control is disabled. Half-duplex mode: no flow control generated collisions are sent. Full-duplex mode: no outgoing[...]

www.ti.com 5.29 MAC Status Register (MACSTATUS) Ethernet Media Access Controller (EMAC) Registers The MAC status register (MACSTATUS) is shown in Figure 55 and described in Table 54 . Figure 55. MAC Status Register (MACSTATUS) 31 30 24 23 20 19 18 16 IDLE Reserved TXERRCODE Rsvd TXERRCH R-0 R-0 R-0 R-0 R-0 15 12 11 10 8 RXERRCODE Reserved RXERRCH R[...]

www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 54. MAC Status Register (MACSTATUS) Field Descriptions (continued) Bit Field Value Description 10-8 RXERRCH 0-3h Receive host error channel. These bits indicate which receive channel the host error occurred on. This field is cleared to 0 on a host read. 0 The host error occurred on [...]

www.ti.com 5.30 Emulation Control Register (EMCONTROL) 5.31 FIFO Control Register (FIFOCONTROL) Ethernet Media Access Controller (EMAC) Registers The emulation control register (EMCONTROL) is shown in Figure 56 and described in Table 55 . Figure 56. Emulation Control Register (EMCONTROL) 31 16 Reserved R-0 15 2 1 0 Reserved SOFT FREE R-0 R/W-0 R/W-[...]

www.ti.com 5.32 MAC Configuration Register (MACCONFIG) 5.33 Soft Reset Register (SOFTRESET) Ethernet Media Access Controller (EMAC) Registers The MAC configuration register (MACCONFIG) is shown in Figure 58 and described in Table 57 . Figure 58. MAC Configuration Register (MACCONFIG) 31 24 23 16 TXCELLDEPTH RXCELLDEPTH R-3h R-3h 15 8 7 0 ADDRESSTYP[...]

www.ti.com 5.34 MAC Source Address Low Bytes Register (MACSRCADDRLO) 5.35 MAC Source Address High Bytes Register (MACSRCADDRHI) Ethernet Media Access Controller (EMAC) Registers The MAC source address low bytes register (MACSRCADDRLO) is shown in Figure 60 and described in Table 59 . Figure 60. MAC Source Address Low Bytes Register (MACSRCADDRLO) 3[...]

www.ti.com 5.36 MAC Hash Address Register 1 (MACHASH1) 5.37 MAC Hash Address Register 2 (MACHASH2) Ethernet Media Access Controller (EMAC) Registers The MAC hash registers allow group addressed frames to be accepted on the basis of a hash function of the address. The hash function creates a 6-bit data value (Hash_fun) from the 48-bit destination ad[...]

www.ti.com 5.38 Back Off Test Register (BOFFTEST) 5.39 Transmit Pacing Algorithm Test Register (TPACETEST) Ethernet Media Access Controller (EMAC) Registers The back off test register (BOFFTEST) is shown in Figure 64 and described in Table 63 . Figure 64. Back Off Random Number Generator Test Register (BOFFTEST) 31 26 25 16 Reserved RNDNUM R-0 R-0 [...]

www.ti.com 5.40 Receive Pause Timer Register (RXPAUSE) 5.41 Transmit Pause Timer Register (TXPAUSE) Ethernet Media Access Controller (EMAC) Registers The receive pause timer register (RXPAUSE) is shown in Figure 66 and described in Table 65 . Figure 66. Receive Pause Timer Register (RXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read o[...]

www.ti.com 5.42 MAC Address Low Bytes Register (MACADDRLO) 5.43 MAC Address High Bytes Register (MACADDRHI) Ethernet Media Access Controller (EMAC) Registers The MAC address low bytes register used in address matching (MACADDRLO), is shown in Figure 68 and described in Table 67 . Figure 68. MAC Address Low Bytes Register (MACADDRLO) 31 16 Reserved [...]

www.ti.com 5.44 MAC Index Register (MACINDEX) Ethernet Media Access Controller (EMAC) Registers The MAC index register (MACINDEX) is shown in Figure 70 and described in Table 69 . Figure 70. MAC Index Register (MACINDEX) 31 16 Reserved R-0 15 3 2 0 Reserved MACINDEX R-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; - n = value after reset Table 69[...]

www.ti.com 5.45 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TX nHDP) 5.46 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RX nHDP) Ethernet Media Access Controller (EMAC) Registers The transmit channel 0-7 DMA head descriptor pointer register (TX n HDP) is shown in Figure 71 and described in Table 70 . Figure 71. Transmit C[...]

www.ti.com 5.47 Transmit Channel 0-7 Completion Pointer Register (TX nCP) 5.48 Receive Channel 0-7 Completion Pointer Register (RX nCP) Ethernet Media Access Controller (EMAC) Registers The transmit channel 0-7 completion pointer register (TX n CP) is shown in Figure 73 and described in Table 72 . Figure 73. Transmit Channel n Completion Pointer Re[...]

www.ti.com 5.49 Network Statistics Registers 5.49.1 Good Receive Frames Register (RXGOODFRAMES) 5.49.2 Broadcast Receive Frames Register (RXBCASTFRAMES) 5.49.3 Multicast Receive Frames Register (RXMCASTFRAMES) Ethernet Media Access Controller (EMAC) Registers The EMAC has a set of statistics that record events associated with frame traffic. The sta[...]

www.ti.com 5.49.4 Pause Receive Frames Register (RXPAUSEFRAMES) 5.49.5 Receive CRC Errors Register (RXCRCERRORS) 5.49.6 Receive Alignment/Code Errors Register (RXALIGNCODEERRORS) 5.49.7 Receive Oversized Frames Register (RXOVERSIZED) Ethernet Media Access Controller (EMAC) Registers The total number of IEEE 802.3X pause frames received by the EMAC [...]

www.ti.com 5.49.8 Receive Jabber Frames Register (RXJABBER) 5.49.9 Receive Undersized Frames Register (RXUNDERSIZED) 5.49.10 Receive Frame Fragments Register (RXFRAGMENTS) 5.49.11 Filtered Receive Frames Register (RXFILTERED) Ethernet Media Access Controller (EMAC) Registers See Section 2.5.5 for definitions of alignment, code, and CRC errors. Over[...]

www.ti.com 5.49.12 Receive QOS Filtered Frames Register (RXQOSFILTERED) 5.49.13 Receive Octet Frames Register (RXOCTETS) 5.49.14 Good Transmit Frames Register (TXGOODFRAMES) Ethernet Media Access Controller (EMAC) Registers To determine the number of receive frames discarded by the EMAC for any reason, sum the following statistics (promiscuous mode[...]

www.ti.com 5.49.15 Broadcast Transmit Frames Register (TXBCASTFRAMES) 5.49.16 Multicast Transmit Frames Register (TXMCASTFRAMES) 5.49.17 Pause Transmit Frames Register (TXPAUSEFRAMES) 5.49.18 Deferred Transmit Frames Register (TXDEFERRED) 5.49.19 Transmit Collision Frames Register (TXCOLLISION) Ethernet Media Access Controller (EMAC) Registers The [...]

www.ti.com 5.49.20 Transmit Single Collision Frames Register (TXSINGLECOLL) 5.49.21 Transmit Multiple Collision Frames Register (TXMULTICOLL) 5.49.22 Transmit Excessive Collision Frames Register (TXEXCESSIVECOLL) 5.49.23 Transmit Late Collision Frames Register (TXLATECOLL) 5.49.24 Transmit Underrun Error Register (TXUNDERRUN) Ethernet Media Access [...]

www.ti.com 5.49.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE) 5.49.26 Transmit Octet Frames Register (TXOCTETS) 5.49.27 Transmit and Receive 64 Octet Frames Register (FRAME64) 5.49.28 Transmit and Receive 65 to 127 Octet Frames Register (FRAME65T127) 5.49.29 Transmit and Receive 128 to 255 Octet Frames Register (FRAME128T255) Ethernet [...]

www.ti.com 5.49.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511) 5.49.31 Transmit and Receive 512 to 1023 Octet Frames Register (FRAME512T1023) 5.49.32 Transmit and Receive 1024 to RXMAXLEN Octet Frames Register (FRAME1024TUP) 5.49.33 Network Octet Frames Register (NETOCTETS) Ethernet Media Access Controller (EMAC) Registers [...]

www.ti.com 5.49.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS) 5.49.35 Receive FIFO or DMA Middle of Frame Overruns Register (RXMOFOVERRUNS) 5.49.36 Receive DMA Overruns Register (RXDMAOVERRUNS) Ethernet Media Access Controller (EMAC) Registers The total number of frames received on the EMAC that had either a FIFO or DMA st[...]

www.ti.com Appendix A Glossary Broadcast MAC Address — A special Ethernet MAC address used to send data to all Ethernet devices on the local network. The broadcast address is FFh-FFh-FFh-FFh-FFh-FFh. The LSB of the first byte is odd, qualifying it as a group address; however, its value is reserved for broadcast. It is classified separately by the[...]

www.ti.com Appendix A Link — The transmission path between any two instances of generic cabling. Multicast MAC Address — A class of MAC address that sends a packet to potentially more than one recipient. A group address is specified by setting the LSB of the first MAC address byte to 1. Thus, 01h-02h-03h-04h-05h-06h is a valid multicast address[...]

www.ti.com Appendix B Revision History Table B-1 lists the changes made since the previous version of this document. Table B-1. Document Revision History Reference Additions/Modifications/Deletions Section 2.4.1 Changed last sentence. Table 2 Changed Data field Bytes and Description. Table 25 Changed Register Description for FRAME1024TUP. Section 5[...]

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