Texas Instruments TNETE211 manuale d’uso

Programmer ’ s Guide October 1996 Network Business Products[...]

Printed in U.S.A., October 1996 L41 1001–9761 revision A SPWU013A[...]

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ThunderLAN Programmer ’ s Guide TNETE100A, TNETE1 10A, TNETE21 1 Literature Number: SPWU013A Manufacturing Part Number: L41 1001-9761 revision A October 1996[...]

Running Title—Attribute Reference ii IMPORT ANT NOTICE T exas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify , before placing orders, that the information being relied[...]

iii Preface Read This First About This Manual The ThunderLAN Programmer ’ s Guide assists you in using the following implementations of ThunderLAN networking hardware: TNETE100A Ethernet controller TNETE1 10A Ethernet controller TNETE21 1 100 VG-AnyLAN physical media interface (PMI) How to Use This Manual The goal of this book is to assist you in[...]

Notational Conventions iv Notational Conventions This document uses the following conventions: Program listings, program examples, and interactive displays are shown in a special font. Examples use a bold version of the special font for emphasis. Here is a sample program listing: 11 0005 0001 .field 1, 2 12 0005 0003 .field 3, 4 13 0005 0006 .field[...]

If Y ou Need Assistance / T rademarks v Read This First If Y ou Need Assistance. . . World-W ide Web Sites TI Online http://www .ti.com Semiconductor PIC http://www .ti.com/sc/docs/pic/home.htm Networking Home Page http://www .ti.com/sc/docs/network/nbuhomex.htm North America, South America, Central America Product Information Center (PIC) (972) 64[...]

T rademarks vi Trademarks Ethernet is a trademark of Xerox Corporation. ThunderLAN and Adaptive Performance Optimization are trademarks of T exas Instruments Incorporated.[...]

Contents vii Contents 1 ThunderLAN Overview 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 ThunderLAN Architecture 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Networking Protocols 1-3 . . . . . . . . . .[...]

Contents viii 4.4.1 No Interrupt (Invalid Code). Int_type = 000b 4-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.2 Tx EOF Interrupt. Int_type = 001b 4-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.3 Statistics Overflow Interrupt. Int_type = 010b 4-8 . . . . . . . . . . . . . . . . . . . . . . . . [...]

Contents ix Contents A.1.13 PCI Memory Base Address Register (@ 14h) A-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . A.1.14 PCI BIOS ROM Base Address Register (@ 30h) A-8 . . . . . . . . . . . . . . . . . . . . . . . . A.1.15 PCI NVRAM Register (@ 34h) A-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.1[...]

Contents x B TNETE21 1 100VG-AnyLAN Demand Priority Physical Media Independent (PMI) Interface B-1 B.1 100VG-AnyLAN T raining B-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.2 TNETE21 1 Register Descriptions B-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

Figures xi Contents Figures 1–1 The ThunderLAN Controller 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 PCI Bus Byte Assignment 1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 How ThunderLAN Registers are Addre[...]

T ables xii T ables 2–1 ThunderLAN EEPROM Map 2-30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1 Adapter Check Bit Definitions 4-1 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 Adapter Check Failure Codes 4-12 . . . . . . . . [...]

T ables xiii Contents A–25 ThunderLAN PHY Status Register Bits A-50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1 PHY Generic Control Register Bits B-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–2 PHY Generic Status Register Bits B-8 . . . . . . . . .[...]

xiv[...]

Running Title—Attribute Reference 1-1 Chapter Title—Attribute Reference ThunderLAN Overview The ThunderLAN family consists of highly integrated, single-chip networking hardware. It uses a high-speed architecture that provides a complete peripher- al component interconnect (PCI)- to-10Base-T/AUI (adapter unit interface) Ethernet solution. It all[...]

ThunderLAN Architecture 1-2 1.1 ThunderLAN Architecture Figure 1–1. The ThunderLAN Controller PCI Bus PCI controller FIFO registers Multiplexed SRAM LAN controller PHY LAN 802.3 100M-bps MII An integrated PHY provides interface functions for 10Base-T carrier sense multiple access/collision detect (CSMA/CD) (Ethernet). A MII is used to com- munica[...]

Networking Protocols 1-3 ThunderLAN Overview 1.2 Networking Protocols The MII also allows freedom in choosing a networking protocol. It allows the use of standard 100M bps CSMA/CD PHY chips. ThunderLAN uses these sig- nal lines to interface to an external 100M bps demand priority PHY . This gives ThunderLAN the flexibility necessary to handle 10Bas[...]

PCI Interface 1-4 1.3 PCI Interface The PCI local bus is a high-performance, 32- or 64-bit bus with multiplexed ad- dress and data lines. The bus is designed to be a medium between highly inte- grated peripheral controller components such as ThunderLAN, add-in boards, and processor/memory systems. 1.3.1 PCI Cycles ThunderLAN executes the following [...]

PCI Interface 1-5 ThunderLAN Overview 1.3.2 Byte Ordering ThunderLAN follows the PCI Local Bus Specification convention when trans- ferring data on the PCI bus. The PCI bus data is transferred on the P AD[31::0] lines. P AD31 is the most significant bit, and P AD0 is the least significant bit. The 32 data lines are enough to transfer four bytes per[...]

1-6[...]

2-1 ThunderLAN Registers ThunderLAN uses a variety of registers to perform its networking functions. These include peripheral component interface (PCI) registers, host registers, internal direct input /output (DIO) registers, media independent interface (MII) registers, and physical interface (PHY) registers. Access to these is a require- ment for [...]

Register Addresses 2-2 2.1 Register Addresses The following figure shows the various register spaces provided by Thunder- LAN. It also shows how a driver uses ThunderLAN’s registers to interface to external devices such as PHYs, BIOS ROMs, and EEPROMs. Figure 2–1. How ThunderLAN Registers are Addressed Host registers HOST CMD CH P ARM HOST INT [...]

Register Addresses 2-3 ThunderLAN Registers and PCI configuration registers to make control of the system possible through the one PCI interface. An EEPROM, required by the PCI, can be written to at manufacture time through the PCI_NVRAM register , which is located in the host register space. The EEPROM can also be accessed through the NetSio regis[...]

PCI Configuration Space 2-4 2.2 PCI Configuration Space Figure 2–2. The PCI Configuration Space Registers read only read/write read/write read/write read/write read/write read/write read only read/write read only Byte 0 Byte 1 Byte 2 Byte 3 0 31 FFh 44h 40h 3Ch 38h 34h 30h 28h 18h 14h 10h 0Ch 08h 04h 00h Reset control Interrupt line Int pin(01h) [...]

PCI Configuration Space 2-5 ThunderLAN Registers Set up the PCI bus. Several PCI bus options can be selected through these registers, including latency and grant. (Refer to PCI Local Bus Spec- ification, subsection 3.5) Map a BIOS ROM using the BIOS ROM base address register Many of the registers in the PCI configuration space are accessed with PCI[...]

PCI Configuration Space 2-6 Normally , access to the configuration space is limited to the operating system. On power-up, the vendor ID, device ID, revision, subclass, Min_Gnt, and Max_Lat registers are loaded with default values. V endor-specific data is loaded into these registers by placing the data into the EEPROM, which is read at the end of r[...]

PCI Configuration Space 2-7 ThunderLAN Registers r.h.ah = PCI_FUNCTION_ID; r.h.al = FIND_PCI_DEVICE; r.x.cx = DeviceID; r.x.dx = VendorID; r.x.si = Index; int86(PCI_INT, &r, &r); *pDev = (WORD)r.x.bx; return (int)r.h.ah; } This code returns the function ID that is used to request reads and writes to the ThunderLAN PCI configuration space; t[...]

PCI Configuration Space 2-8 r.x.di = addr; int86(PCI_INT, &r, &r); /* PCI_INT 0x1A */ return (r.x.cx & 0xFF); } Normally , the constants in this routine (the values assigned to ah, al, and the opcode for the int86 call) are assigned in the header file for the C code. Their values are inserted as comments to enable the reader to resolve [...]

Host Registers 2-9 ThunderLAN Registers 2.3 Host Registers Figure 2–4. Host Registers offset Base address +12 +8 +4 +0 DIO_DA T A DIO_ADR HOST_INT CH_P ARM HOST_CMD 0 15 16 31 ThunderLAN implements the host registers shown above. These are the pri- mary control points for ThunderLAN. Through the host registers, a driver can: Reset the ThunderLAN [...]

Host Registers 2-10 T o enable reads of adjacent addresses without reposting the address, bit 15 of the DIO_ADR register can be set, which causes the address to be post-in- cremented by 4 after each access of the DIO_DA T A register . This function is useful when reading the statistics or reading the internal SRAM. Autoincre- menting while reading [...]

Internal Registers 2-1 1 ThunderLAN Registers 2.4 Internal Registers Figure 2–5. Internal Registers DIO address 0x44 0x40 0x3C 0x38 0x34 0x30 0x2C 0x28 0x24 0x20 0x1C 0x18 0x14 0x10 0x0C 0x08 0x04 0x00 LEDreg BSIZEreg MaxRx collisions Excessive collisions Late errors Carrier loss Acommit Multicollision Tx frames Single collision Tx frames frames [...]

Internal Registers 2-12 Setting commit levels and PCI burst levels Interfacing via the management interface to the PHY registers Determining status interrupts Setting eight bytes of default PCI configuration data if the EEPROM checksum is bad Setting the various unicast and multicast addresses Providing network statistics Setting the LEDs and imple[...]

Internal Registers 2-13 ThunderLAN Registers is used to set the network transmit commit level. The BSIZEreg register is used to set the bus burst size on both Tx and Rx frames. The internal registers are accessed via the DIO_DA T A and DIO_ADR host registers. DIO_ADR holds the DIO address of the register . The data is then read from or written to D[...]

Internal Registers 2-14 //–––––––––––––––––––––––––––––––––––––––––––––––––––––––– // DioRdDword() – read 32 bits from internal TLAN register // // Parameters: // base_addr WORD base address of TLAN internal registers // addr WORD addre[...]

MII PHY Registers 2-15 ThunderLAN Registers 2.5 MII PHY Registers Figure 2–6. MII PHY Registers Register V endor-specific registers Reserved by IEEE 802.3 Autonegotiation next page transmit Autonegotiation expansion Autonegotiation link-partner ability Autonegotiation advertisement PHY generic identifier (low) PHY generic identifier (high) PHY ge[...]

MII PHY Registers 2-16 The status register (GEN_sts in ThunderLAN products) includes bits to identify the technology supported by the PHY . This technology includes protocol and duplex abilities. It indicates link, jabber , and autoconfiguration completion. Bit 0 of the status register also indicates whether the extended register set is sup- ported[...]

MII PHY Registers 2-17 ThunderLAN Registers is 0x1F . When the internal PHY for 10Base-T is used in a standalone mode, that is, when run from another controller through the MII pins, it is at address 0x00. These are the only two addresses allowed for the internal PHY . The 100VG-AnyLAN PMI device, the TNETE21 1, is used to attach 802.12 physical me[...]

MII PHY Registers 2-18 up resistor , which is recommended to be attached to this line. The MII devices should see 1s. An alternate way to give the PHYs a series of 1s, is to: set(MDATA) set(MTXEN) clr(MCLK); //delay here DioRdByte(base_addr,Net_Sio); set(MCLK); Where MCLK is a constant for the third LSB (in the internal NetSio register) and is defi[...]

MII PHY Registers 2-19 ThunderLAN Registers After synchronization, one could use code like the following to read a PHY reg- ister: //–––––––––––––––––––––––––––––––––––––––––––––––––––––––– // MiiRdWord() – Read word from Phy MII, place[...]

MII PHY Registers 2-20 Interrupts are turned off with the CritOn() macro. This macro leaves a value that can be sampled to see if it has been invoked. CritOn can be defined as follows: #define CritOn() if (CritLevel == 0) { _asm { cli } } CritLevel++ The NetSio register must be reached indirectly using the host registers. This sets the address [...]

MII PHY Registers 2-21 ThunderLAN Registers This samples data on the rising edge of the MCLK bit. T ake the first bit into the PHY MII as follows: b &= ~MCLK; outp(diodata,b); b |= MDATA; outp(diodata,b); b |= MCLK; outp(diodata,b); //1 data bit out This concludes writing out the start delimiter bits. The data can be changed before the clock is[...]

MII PHY Registers 2-22 to NetSio. Then the clock is cycled for each bit. The loop effectively cycles five times. // Send the register number MSB first // Send the device number Internal=31(0x1f), External=0(0x00) for (i = 0x10;i;i >>= 1) { if (i&addr) b |= MDATA; else b &= ~MDATA; outp(diodata,b); //togLH b &= ~MCLK; outp(diodata,[...]

MII PHY Registers 2-23 ThunderLAN Registers After the addresses have been clocked out on a read cycle, there is a cycle where neither side drives the data pin. If the PHY is synced and ready to re- spond, it should drive a 0 next, followed by the 16 bits of data. The data is avail- able up to 300 ns after the rising edge of the clock, so the softwa[...]

MII PHY Registers 2-24 { for (i = 0;i < 17;i++) togLH(MCLK); tmp = 0xffff; } //togLH b &= ~MCLK; outp(diodata,b); b |= MCLK; outp(diodata,b); b = inp(diodata); This is the quiescent cycle following data transmission. Since this is a read op- eration, ThunderLAN does not drive the line and the PHY turns off during this cycle. If the quiescent[...]

External Devices 2-25 ThunderLAN Registers 2.6 External Devices This following section discusses the manner in which the ThunderLAN control- ler interfaces to external devices. These devices include: A BIOS ROM Light emitting diodes (LEDs) A serial EEPROM Any devices (PMIs/PMDs) attached to the MDIO/MDCLK serial interface of the MII 2.6.1 BIOS ROM [...]

External Devices 2-26 reserves the following two LED locations for its drivers. The bit numbers refer to their locations in LEDreg. Bit 0 (LSB) displays link status. Bit 4 displays activity . 2.6.3 EEPROM The implementation-specific configuration information is read or written into the EEPROM from two sources. Control of the two-wire serial bus to [...]

External Devices 2-27 ThunderLAN Registers Writing to the NetSio register involves writing a >000 to the host register DIO_ADR, then writing to the DIO_DA T A host register . Control of the EEPROM interface shifts to the bits in NetSio when a write takes place to the DIO_DA T A host register . Following is an example of how one might read a byte[...]

External Devices 2-28 Set and clear are macros for a read/modify/write routine for individual bits in the NetSio register . The NetSio byte is read indirectly from the internal register block with the host register address and data pointers, the bit passed as a constant (really a bit mask) is ANDed to 0 (clear), or ORed to a 1 (set). The pattern of[...]

External Devices 2-29 ThunderLAN Registers When the EEPROM address is shipped out, another special pattern of control signal movements must take place to signal the start of the data transfer . // send device ID, address and read command to EEPROM sel(base_addr, READ); // EEPROM should have acked if (!ack(base_addr)) return (0); //clock bits in fro[...]

External Devices 2-30 2.6.4 ThunderLAN EEPROM Map ThunderLAN uses the following EEPROM map. Note that these values may be used in several applications and systems including: ThunderLAN hardware A host running T exas Instruments ThunderLAN drivers T exas Instruments diagnostic routines T able 2–1. ThunderLAN EEPROM Map Address Default Binary Bits [...]

External Devices 2-31 ThunderLAN Registers T able 2–1. ThunderLAN EEPROM Map (Continued) Address Description Binary Bits Default 0x79 0x04 WxSHRAFI PHY and test control modes W – PHY wrap request S – Skip training request H – HiPriority transmit frames request R – Don’t copy short frame request A – Don’t copy all frames request F ?[...]

External Devices 2-32 T able 2–1. ThunderLAN EEPROM Map (Continued) Address Description Binary Bits Default 0x82 0x00 0x83 Ethernet address 0x84 Ethernet address 0x85 Ethernet address 0x87 Ethernet address 0x88 Ethernet address 0x86 Ethernet address 0x89 0xff Checksum 0x8a 0xff Checksum 0x8b 0x83 0x8c 0x08 0x8d 0x00 0x8e T oken ring address 0x8f [...]

External Devices 2-33 ThunderLAN Registers T able 2–1. ThunderLAN EEPROM Map (Continued) Address Description Binary Bits Default 0x9c Ethernet address 0x9d Ethernet address 0x9e Ethernet address 0x9f 0xff Checksum 0xa0 0xff Checksum 0xa1 0x83 0xa2 0x08 0xa3 0x00 0xa4 T oken ring address 0xa5 T oken ring address 0xa6 T oken ring address 0xa7 T oke[...]

External Devices 2-34 T able 2–1. ThunderLAN EEPROM Map (Continued) Address Description Binary Bits Default 0xb6 0xff Checksum 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 V endor ID register LSbyte 0xc1 V endor ID MSbyte 0xc2 Device ID LSbyte 0xc3 Device ID MSbyte 0xc4 Revision 0xc5 Subclass 0xc6 Min_Gnt 0xc7 Max_Lat 0xc8 Checksum[...]

3-1 Initializing and Resetting This chapter describes the steps necessary to get a ThunderLAN device ready to transmit and receive frames. It provides examples of the necessary code, beginning with configuration of the ThunderLAN device on a peripheral com- ponent interconnect (PCI) system. The chapter also defines the steps needed for both hardwar[...]

Initializing 3-2 3.1 Initializing T o initialize or to set the starting values for ThunderLAN, the device must pro- ceed through a specific sequence of steps. This procedure assumes that the autoconfiguration step of loading from the EEPROM to the PCI configuration registers has already taken place. 3.1.1 Finding the Network Interface Card (NIC) A [...]

Initializing 3-3 Initializing and Resetting WORD PciFindDevice( WORD DeviceID, WORD VendorID, WORD Index, WORD *pDev) { union REGS r; r.h.ah = PCI_FUNCTION_ID; r.h.al = FIND_PCI_DEVICE; r.x.cx = DeviceID; r.x.dx = VendorID; r.x.si = Index; int86(PCI_INT, &r, &r); *pDev = (WORD)r.x.bx; return (int)r.h.ah; } When the BIOS call is finished, th[...]

Initializing 3-4 3.1.2 Finding the Controller in Memory and I/O Space T o access the host registers, the I/O base address must be determined. This I/O base is needed, since the host registers are accessed as I/O ports. The I/O base address register in the ThunderLAN controller has the LSB hardwired to high. This code does an O/S call to read a 32-b[...]

Initializing 3-5 Initializing and Resetting 3.1.3 Finding Which Interrupt was Assigned When the base register is established, the driver needs to find out what inter- rupt was assigned to the card. The next code segment from GetPciConfig be- low retrieves the PCI_INTLINE which in x86-based PCs refers to the interrupt request (IRQ) numbers (0 – 15[...]

Initializing 3-6 3.1.4 T urning on the I/O Port and Memory Address Decode The next step in the GetPciConfig section of the code is responsible for turning on the ThunderLAN controller by enabling the decode of memory and I/O port addresses. Without this step, there is no access to the host registers and there- fore, to the internal registers or the[...]

Initializing 3-7 Initializing and Resetting 3.1.5 Recovering the Silicon Revision V alue At this point, the sample program needs to know what the default silicon revi- sion for the controller is. There is a revision byte in the configuration space that can be read with a PciRdxxxx command. This configuration byte is loaded with EEPROM data to signa[...]

Resetting 3-8 3.2 Resetting Resetting ThunderLAN is required when conditions such as an incorrect pow- er-up cause the register value in the device to deviate from that needed for proper operation. T o perform either a software or hardware reset, the program- mer must complete the steps indicated. 3.2.1 Hardware Reset The IEEE 802.3 specification d[...]

Resetting 3-9 Initializing and Resetting 3.2.2 Software Reset The driver needs to reset ThunderLAN at startup when an adapter check inter- rupt occurs or when an upper layer requires the driver to do so. ThunderLAN may only need to be reinitialized when link is lost. T o reset ThunderLAN the driver must: 1) Clear the statistics by reading the stati[...]

3-10[...]

4-1 Interrupt Handling ThunderLAN and its host device indicate communication with each other by sending and receiving interrupts to the bus data stream. This chapter provides information on setting up code which recognizes, prioritizes, and acknowl- edges these interrupts. It defines specific interrupt codes and describes what happens when these oc[...]

Loading and Unloading an Interrupt Service Routine (ISR) 4-2 4.1 Loading and Unloading an Interrupt Service Routine (ISR) Before the ThunderLAN controller can be allowed to generate an interrupt to the host, it is necessary to install code for the host to handle the interrupt. The driver also relies on other host services that are interrupt-driven,[...]

Loading and Unloading an Interrupt Service Routine (ISR) 4-3 Interrupt Handling This routine converts either the eight low hardware interrupts, or the eight high interrupts, or a software interrupt higher than 0xF to the vector table, then makes an O/S call to get the old vector and slips in the new . It returns the pre- vious contents of that tabl[...]

Loading and Unloading an Interrupt Service Routine (ISR) 4-4 Cleanup uses the same HwSetIntV ector routine to restore the old value. This time, the parameter is the old value and the interim value returned by the func- tion is ignored. Only the three interrupts that were asserted are restored, and only if the structure for the NIC instance has had [...]

Prioritizing Adapter Interrupts 4-5 Interrupt Handling 4.2 Prioritizing Adapter Interrupts All (non-PCI) adapter interrupts are governed by the interrupt pacing timer . The interrupt pacing timer is started whenever the HOST_CMD register Ack bit is written as a 1. When this timer expires and if any interrupt sources are active, a PCI interrupt is a[...]

Acknowledging Interrupts (Acking) 4-6 4.3 Acknowledging Interrupts (Acking) The ThunderLAN controllers have been designed to minimize the code neces- sary to acknowledge interrupts. This is accomplished by matching the HOST_INT register ’s bits to the corresponding bits in the HOST_CMD regis- ter . Also, the HOST_INT’ s two LSBs are set to 0 so[...]

Interrupt T ype Codes 4-7 Interrupt Handling 4.4 Interrupt T ype Codes The following subsections define specific interrupt codes which may occur during ThunderLAN operation. It describes the conditions that result from the occurrence of interrupts, and corrective actions to overcome these conditions. 4.4.1 No Interrupt (Invalid Code). Int_type = 00[...]

Interrupt T ype Codes 4-8 4.4.3 Statistics Overflow Interrupt. Int_type = 010b This interrupt is given when one of the network statistics registers is halfway filled. The driver: Reads all the statistics registers, thereby clearing them Acknowledges the interrupt, then exits When reading the statistics registers, it is a good idea to use the Adr_In[...]

Interrupt T ype Codes 4-9 Interrupt Handling 4.4.6 Tx EOC Interrupt. Int_type = 101b A Tx EOC interrupt occurs when ThunderLAN encounters a forward pointer of 0 in the Tx list structure or when the Ld_Thr bit is loaded with 0. In this routine the driver: Gets the pointer to the Tx buffer queue Checks the list CST A T to see if a frame has been tran[...]

Interrupt T ype Codes 4-10 4.4.8 Adapter Check Interrupt. Int_type = 1 10b and Int_V ec ≠ 00h An adapter check interrupt occurs when ThunderLAN enters an unrecover- able state and must be reset. This unrecoverable condition occurs when ThunderLAN does not agree with the parameters given to it by the driver or when it does not agree with the exter[...]

Interrupt T ype Codes 4-1 1 Interrupt Handling Figure 4–1. Adapter Check Interrupt Fields Failure code 0 0 0 0 0 0 0 0 0 0 R/W R/T L/D Channel 0 0 0 Byte 0 Byte 1 Byte 2 Byte 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 T able 4–1. Adapter Check Bit Definitions Bit Name Function 28 – 21 Channel This [...]

Interrupt T ype Codes 4-12 T able 4–2. Adapter Check Failure Codes Bit Name Function 00h 01h DataPar Data parity error: Indicates that during bus master operations, ThunderLAN has de- tected a PCI bus data parity error , and parity error checking was enabled (the P AR_En bit in the PCI command register is set). 02h AdrsPar Address parity error: I[...]

Interrupt T ype Codes 4-13 Interrupt Handling The error status bits are only relevant for some adapter check failure codes, as indicated by the following table: T able 4–3. Relevance of Error Status Bits for Adapter Check Failure Codes Bit Name Channel List/Data Receive/T ransmit Read/Write 01h DataPar Y Y Y Y 02h AdrsPar N N N N 03h Mabort Y Y Y[...]

4-14[...]

5-1 List Structures ThunderLAN controllers use a list processing method to move data in and out of the host’s memory . A list is a structure in host memory which is composed of pointers to data. The list contains information telling ThunderLAN where in the host memory to look for the data to be transmitted or where the receive buffer is located. [...]

List Management 5-2 5.1 List Management Some of the more commonly used list management terms are defined here: List A list is a structure in host memory which is composed of pointers to data. The list includes information on the location of a frame, its size, and its transmission/receive status. A list can represent only one frame, but lists can be[...]

List Management 5-3 List Structures can keep the transmit and receive channels continuously open by freeing up buffers and relinking lists faster than frames are transferred by ThunderLAN. This is important in receive operations where the Rx channel must be open continuously to avoid losing frames from the network. All list processing and managemen[...]

List Management 5-4 A driver is not limited in the number of lists it can manage as long as there is memory to put them in. The question then arises as to how many lists are ap- propriate for a certain application. The number of lists allocated should be just enough to allow the driver to use the full wire bandwidth on Tx and to handle the Rx data [...]

CST A T Field Bit Requirements 5-5 List Structures 5.2 CST A T Field Bit Requirements T exas Instruments specifies that some bits in the CST A T field should be set to 1, but tells you to ignore them. This is because these bits are ignored by the adapter . The ThunderLAN CST A T is very much like that in TI380 products. Bit 12 in ThunderLAN corresp[...]

One-Fragment Mode 5-6 5.3 One-Fragment Mode When the GO command is given on either transmit or receive, ThunderLAN DMAs the whole list, even though the driver only uses a limited number of frag- ments on that list. In the case of a receive list, the driver has the option to force ThunderLAN to DMA a one-fragment list. This is accomplished by settin[...]

Receive List Format 5-7 List Structures 5.4 Receive List Format Figure 5–3. Receive List Format – One_Frag = 0 List offset 0x54 0x50 0x4C 0x48 0x44 0x40 0x3C 0x38 0x34 0x30 0x2C 0x28 0x24 0x20 0x1C 0x18 0x14 0x10 0x0C 0x08 0x04 0x00 Data count Data address Data count Data count Data address Data address Data count Data address Data count Data c[...]

Receive List Format 5-8 T able 5–1. Receive Parameter List Fields Field Definition Forward pointer This full 32-bit field contains a pointer to the next receive parameter list in the chain. The three LSBs of this field are ignored, as lists must always be on an eight-byte address boundary . When the pointer is 0, the current receive parameter lis[...]

Receive List Format 5-9 List Structures Figure 5–5. Receive CST A T Request Fields LSB MSB 000 0 0 0 000 0 0 0 1 1 0 Cmp Frm 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 T able 5–2. Receive CST A T Request Bits Bit Name Function 15 0 Ignored by adapter . Set to 0 14 Frm_Cmp 0 Frame complete: Ignored by adapter . Set to 0. Setting the Frm_Cmp bit to [...]

Receive List Format 5-10 Figure 5–6. Receive CST A T Complete Fields LSB MSB DP 0 Rx RX EOC 1 1 1 Cmp Frm 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Error pr Reserved T able 5–3. Receive CST A T Complete Bits Bit Name Function 15 0 Same value as previously set by the host in CST A T request field 14 Frm_Cmp 1 Frame complete: Set to 1 by the adapte[...]

T ransmit List Format 5-1 1 List Structures 5.5 T ransmit List Format Figure 5–7. T ransmit List Format . . . through 0x55 User-specific information List offset 0x54 0x50 0x4C 0x48 0x44 0x40 0x3C 0x38 0x34 0x30 0x2C 0x28 0x24 0x20 0x1C 0x18 0x14 0x10 0x0C 0x08 0x04 0x00 Data count Data address Data count Data count Data address Data address Data [...]

T ransmit List Format 5-12 T able 5–4. T ransmit Parameter List Fields Field Definition Forward pointer This 32-bit field contains a pointer to the next transmit parameter list in the chain. The three LSBs of this field are ignored, as lists must always be on an eight-byte address boundary . When the forward pointer is 0, the current transmit par[...]

T ransmit List Format 5-13 List Structures Figure 5–8. T ransmit CST A T Request Fields LSB MSB Reserved Network priority 0 Pass CRC 0 0 1 1 0 Cmp Frm 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 T able 5–5. T ransmit CST A T Request Bits Bit Name Function 15 x Ignored by adapter . The value in this bit is a don’t care. 14 Frm_Cmp 0 Frame complete[...]

T ransmit List Format 5-14 Figure 5–9. T ransmit CST A T Complete Fields LSB MSB 0 Pass TX EOC 1 1 1 Cmp Frm 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CRC Reserved 0 Network priority T able 5–6. T ransmit CST A T Complete Bits Bit Name Function 15 x Same value as previously set by the host in the CST A T request field 14 Frm_Cmp 1 Frame complete:[...]

6-1 T ransmitting and Receiving Frames This chapter describes the structure and format for transmitting and receiving frames using ThunderLAN. Frames are units of data that are transmitted on a network. These must appear in a consistent, logical format to be recognized. The chapter also describes the method you must use to create a linked list stru[...]

Frame Format 6-2 6.1 Frame Format The following describes the configuration of the data units which ThunderLAN transmits and receives. ThunderLAN looks for this format to create the linked structures it uses in transmitting and receiving data (see subsection 6.2, GO Command). 6.1.1 Receive (Rx) Frame Format The adapter receive channels are used to [...]

Frame Format 6-3 T ransmitting and Receiving Frames 6.1.2 T ransmit (Tx) Frame Format The adapter transmit channels are used to transmit frames to other nodes on the network. The ThunderLAN adapter allows transmitted frame data to be fragmented into up to ten pieces. However , the adapter expects the conca- tenation of these fragments to be in a co[...]

GO Command 6-4 6.2 GO Command T o transmit and receive data, the ThunderLAN driver must create a linked list of frames. This subsection describes the steps to create such a linked list, and the process for initiating transfer by using a GO command. 6.2.1 Starting Frame Reception (Rx GO Command) T o create a linked receive list structure the driver:[...]

GO Command 6-5 T ransmitting and Receiving Frames forward pointer point to the next available list. The last list should have a for- ward pointer of 0. Y ou must then initialize the CST A T fields in the lists. Opening a receive channel works in much the same way as opening a transmit channel. Y ou must first write the address of the beginning of t[...]

GO Command 6-6 The HOST_CMD register can be written in a single, 32-bit operation. This im- plies that several commands can be combined in one operation. An Rx EOC interrupt can be acknowledged and Rx GO commands can be reissued in a single operation. 6.2.2 Starting Frame T ransmission (Tx GO Command) T o create a linked transmit list structure the[...]

GO Command 6-7 T ransmitting and Receiving Frames 8) Gives the TX GO command by writing the address of the first available list to the CH_P ARM register 9) Writes a 1 to the GO bit of the HOST_CMD register , with the transmit chan- nel selected This assumes the transmit interrupt threshold has been initialized. If not, write to HOST_CMD with the Ld[...]

GO Command 6-8 Depending on the value loaded into the Ld_Thr bit in the HOST_CMD register , ThunderLAN gives a Tx EOF interrupt after processing the number of frames specified. In this case, the driver acknowledges the number of frames that it has processed. Again, the driver has to look into the Frm_Cmp bit of the CST A T field to determine the nu[...]

7-1 Physical Interface (PHY) This chapter describes ThunderLAN support for all IEEE 802.3-compliant de- vices through its media independent interface (MII). These include the internal 10Base-T physical interface (PHY) and any MII-compliant networking PHYs. It also discusses IEEE 802.12-compliant devices which are supported when ThunderLAN is used i[...]

MII-Enhanced Interrupt Event Feature 7-2 7.1 MII-Enhanced Interrupt Event Feature ThunderLAN can connect to an external PMI device through its industry stan- dard MII interface. A full description of the MII can be found in the 802.3u stan- dard. The ThunderLAN MII is enhanced in two ways: The ThunderLAN MII can be shifted through software into a m[...]

MII-Enhanced Interrupt Event Feature 7-3 Physical Interface (PHY) ThunderLAN implements the 19-signal MII shown in T able 7–1: T able 7–1. ThunderLAN MII Pins (100M-bps CSMA /CD) Name T ype Function MTCLK In T ransmit clock: T ransmit clock source from the attached PHY device MTXD0 MTXD1 MTXD2 MTXD3 Out T ransmit data: Nibble transmit data from[...]

MII-Enhanced Interrupt Event Feature 7-4 Figure 7–3. MII Frame Format: Write Start delimiter Operation code PHY address Register address T urn- around Data 01 01 AAAAA RRRRR 10 DDDD DDDD DDDD DDDD The clock cycle at the end of a transaction is used to disable the PMI from driv- ing the MDIO pin after a register read (the quiescent cycle). Thunder[...]

MII-Enhanced Interrupt Event Feature 7-5 Physical Interface (PHY) PHY interrupt function. The INTEN bit is used to enable and disable the PHY interrupt function. Setting the INTEN bit enables the PHY internal event sys- tem to generate interrupts; clearing the INTEN bit disables the PHY from gen- erating interrupts. Interrupts from the PHY are usua[...]

MII-Enhanced Interrupt Event Feature 7-6 generated under host software control and is used to latch the MDIO pin on the rising edge. The ThunderLAN architecture expands the use of these two pins to allow the attached PHY to interrupt the host using ThunderLAN. The clock cycle at the end of a transaction on the MDIO signal is used to disable the PMI[...]

Nonmanaged Mll Devices 7-7 Physical Interface (PHY) 7.2 Nonmanaged MII Devices Nonmanaged MII devices do not have a management interface (MDIO and MDCLK). As such, they do not have any registers. The driver must have a key- word that denotes that the PHY used is nonmanaged.[...]

Bit-Rate Devices 7-8 7.3 Bit-Rate Devices ThunderLAN supports bit-rate devices by asserting the BIT rate bit in the Net- Config register . The MII is then converted into an Ethernet serial network inter- face (SNI). The pin conversion for this mode is: MRXD0 → RXD (receive data) MRCLK → RXC (receive clock) MRCLK → RXC (receive clock) MCRS →[...]

PHY Initialization 7-9 Physical Interface (PHY) 7.4 PHY Initialization The driver initializes each MII-attached PHY . Since there may be more than one PHY attached to the MII, proper initialization ensures that one and only one PHY is active and driving the MII. (The condition where more than one PHY drives the MII at the same time is termed conten[...]

7-10[...]

A-1 Appendix A Register Definitions This appendix contains register definitions for the TNETE100A, TNETE1 10A, and TNETE21 1 ThunderLAN implementations. ThunderLAN uses these reg- isters to store information on its internal status and its communication with the host. This appendix describes the purpose and function of each register and provides bit[...]

PCI Configuration Registers A-2 A.1 PCI Configuration Registers The PCI specification requires all PCI devices to support a configuration regis- ter space to allow jumperless autoconfiguration. The configuration space is 256 bytes in length, of which the first 64-byte header region is explicitly defined by the PCI standard. Registers in this addres[...]

PCI Configuration Registers A-3 Register Definitions Figure A–1. PCI Configuration Register Address Map read only read/write read/write read/write read/write read/write read/write read only read/write read only Byte 0 Byte 1 Byte 2 Byte 3 0 31 FFh 44h 40h 3Ch 38h 34h 30h 2Ch 18h 14h 10h 0Ch 08h 04h 00h Reset control Interrupt line Interrupt Pin(0[...]

PCI Configuration Registers A-4 The first bit written to or read from the EEPROM is the most significant bit of the byte, such as data(7). Therefore, writing the address C0h is accomplished by writing a 1 and six 0s. ThunderLAN expects data to be stored in the EEPROM in a specific format. Nine bytes in the EEPROM are reserved for use by the adapter[...]

PCI Configuration Registers A-5 Register Definitions Should autoconfiguration fail (bad checksum), this register is loaded with the ThunderLAN device ID of 0500h. A.1.4 PCI Command Register (@ 04h) En I/O En Mem En BM Reserved En Par En SER Reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Res T able A–1. PCI Command Register Bits Bit Name Function [...]

PCI Configuration Registers A-6 A.1.5 PCI Status Register (@ 06h) cap FBB det DP (01b) DEVSEL Res ab RT ab RM err SS err DP Reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 T able A–2. PCI Status Register Bits Bit Name Function 15 DP_err Detected parity error: Indicates that the adapter has detected a parity error . This bit is set even if the pari[...]

PCI Configuration Registers A-7 Register Definitions A.1.6 PCI Base Class Register (@ 0Bh) This register is hardwired with the network controller code of 0x02h. A.1.7 PCI Subclass Register (@ 0Ah) This register holds the adapter PCI subclass. This register is loaded from an external serial EEPROM on the falling edge of PCI reset, during autoconfi- [...]

PCI Configuration Registers A-8 This register holds the base address for ThunderLAN’s register set in I/O space. Bit 0 of this register is hardwired to a 1 to indicate that this is a memory- mapped base address. Bits 1 through 3 are hardwired to 0 to indicate that the register set occupies four 32-bit words. A.1.13 PCI Memory Base Address Registe[...]

PCI Configuration Registers A-9 Register Definitions pins. On reset (software or hardware), control of the interface is given to the PCI NVRAM register . 0 1 2 3 4 5 6 7 CLOCK CDIR Reserved Reserved DA T A DDIR Reserved NVPR Byte 0 T able A–3. PCI NVRAM Register Bits Bit Name Function 7 NVPR Nonvolatile RAM present: When this bit is set to a 1, i[...]

PCI Configuration Registers A-10 A.1.18 PCI Min_Gnt (@ 3Eh) and Max_Lat (@ 3Fh) Registers These byte registers are used to specify the adapter ’s desired settings for la- tency timers. For both registers, the value specifies a period of time in units of 250 ns (quarter microsecond). These registers are loaded from an external serial EEPROM on the[...]

PCI Configuration Registers A-1 1 Register Definitions A.1.20 CardBus CIS Pointer (@ 28h) This register is used by those devices that want to share silicon between Card- Bus and PCI. The field is used to point to the Card Information Structure (CIS) for the CardBus card. On ThunderLAN this register is hardwired to a value of 10000107h which indicat[...]

Adapter Host Registers A-12 A.2 Adapter Host Registers Host command registers contain bits which are toggled to tell the channel to use receive or transmit FIFOs. ThunderLAN’s adapter host registers include the adapter internal registers (see section A.3, Adapter Internal Registers). The following subsections describe the functions of each host r[...]

Adapter Host Registers A-13 Register Definitions T able A–5. Host _ CMD Register Bits (Continued) Bit Function Name 30 Stop Channel stop: This command bit only affects the network channels. if R / T = 0 (Tx Stop): Writing a 1 to this bit stops frame transmission on all transmit channels immediately . All transmit FIFO control logic and the networ[...]

Adapter Host Registers A-14 T able A–5. Host _ CMD Register Bits (Continued) Bit Function Name 29 Ack Interrupt acknowledge: Writing a 1 to this bit acknowledges the interrupt indicated by the Nes, EOC, Ch_Sel, and R / T fields. if Nes = 0, EOC = 1, and R / T = 1 (Status Ack): Writing a 1 to this bit acknowledges and clears the status interrupt. [...]

Adapter Host Registers A-15 Register Definitions T able A–5. Host _ CMD Register Bits (Continued) Bit Function Name 20 EOC End of channel select: This read/write bit is used to select between the EOC, EOF , and command bit operations. If this bit is set to a 1, then end of channel operations are se- lected. If set to a 0, EOF operations are selec[...]

Adapter Host Registers A-16 T able A–5. Host _ CMD Register Bits (Continued) Bit Function Name 14 Ld_Tmr Load interrupt timer 4 : W riting a 1 to this bit causes the interrupt holdoff timer to be loaded from the Ack Count field. Ack Count indicates the time-out period in 4- µ s units (based on a 33-MHz PCI clock). The interrupt holdoff timer is [...]

Adapter Host Registers A-17 Register Definitions A.2.2 Channel Parameter Register – CH_P ARM @ Base_Address + 4 (Host) This is used to pass parameter information for HOST_CMD register com- mands as follows: GO (Tx GO): Load CH_P ARM with the address of the first transmit list be- fore issuing the command. The list must be located on an 8-byte add[...]

Adapter Host Registers A-18 A.2.3 Host Interrupt Register – HOST_INT @ Base_Address + 10 (Host) 0 0 Int T ype Int V ec 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 T able A–6. HOST_INT Register Bits Bit Name Function 15 – 13 0 These bits are always read as 0s. 12 – 5 Int_V ec Interrupt vector: This field indicates the highest active interrup[...]

Adapter Host Registers A-19 Register Definitions and Nes bits. This allows the value read from the interrupt register to be written to the HOST_CMD register to directly select the appropriate channel. If no in- terrupts are active, the interrupt pacing timer is running, or the PCI interrupt has been disabled (by writing a nonzero value to this regi[...]

Adapter Host Registers A-20 If ADR_SEL[1::0] = 00, the 32 LSBs of the 68-bit word are accessed. If ADR_SEL[1::0] = 01, the middle 32 bits of the 68-bit word are accessed. If ADR_SEL[1::0] = 1X, the four MSBs of the 68-bit word are accessed (in the four LSBs of DIO_DA T A). PCI bus-byte enables are honored in writes to the internal RAM; individual b[...]

Adapter Internal Registers A-21 Register Definitions A.3 Adapter Internal Registers The adapter ’s internal registers are indirectly accessible from the PCI bus through the DIO_ADR and DIO_DA T A registers. These are usually referred to as DIO. ThunderLAN has an internal 32-bit bus that is used for DIO accesses to the registers and the SRAM. PCI [...]

Adapter Internal Registers A-22 Figure A–4. ADAPTER Internal Register Map DIO Address Byte 3 Byte 2 Byte 1 Byte 0 NetMask NetSts NetSio NetCmd 0x00 ManT est NetConfig 0x04 Default device ID MSbyte Default device ID LSbyte Default vendor ID MSbyte Default vendor ID LSbyte 0x08 Default Max_Lat Default Min_Gnt Default subclass Default revision reg 0[...]

Adapter Internal Registers A-23 Register Definitions A.3.1 Network Command Register – NetCmd @ 0x00 (DIO) All bits in this register are set to 0 on an Ad_Rst or when PRST# is asserted. 0 1 2 3 4 5 6 7 TXP ACE TRFRAM DUPLEX NOBRX CAF CSF NWRAP NRESET Byte 0 T able A–8. Network Command Register Bits Bit Name Function 7 NRESET ThunderLAN controlle[...]

Adapter Internal Registers A-24 T able A–8. Network Command Register Bits (Continued) Bit Name Function 0 TXP ACE Transmit pacing (CSMA/CD): This bit allows pacing of transmitted CSMA/CD frames to improve network utilization of network file servers. When this bit is set, the pacing algo- rithm is enabled. When this bit is cleared, the pacing algo[...]

Adapter Internal Registers A-25 Register Definitions T able A–9. Network Serial I/O Register Bits (Continued) Bit Name Function 12 EDA T A EEPROM SIO data: This bit is used to read or write the state of the EDIO pin. When ETXEN is set to 1, EDIO is driven with the value in this bit. When ETXEN is set to 0, this bit is loaded with the value on the[...]

Adapter Internal Registers A-26 T able A–10. Network Status Register Bits (Continued) Bit Name Function 20 RXSTOP Receiver stopped: This bit indicates the completion of a receive ST OP command. This bit is cleared by writing a 1 to its bit position. Writing a 0 has no ef fect. 19 – 16 Reserved A.3.4 Network Status Mask Register – NetMask @ 0x[...]

Adapter Internal Registers A-27 Register Definitions A.3.5 Network Configuration Register – NetConfig @ 0x04 (DIO) This 16-bit register is used for ThunderLAN’s controller configuration. This register is only writable while the ThunderLAN controller is in reset. (NRESET = 0). All bits in this register are set to 0 on an Ad_Rst or when PRST# is [...]

Adapter Internal Registers A-28 T able A–12. Network Configuration Register Bits (Continued) Bit Name Function 12 RxCRC Receive CRC: When this bit is set to 1, the ThunderLAN controller transfers frame CRC to the host for received frames and includes it in the reported frame length. The value in the MaxRx register must be large enough to accommod[...]

Adapter Internal Registers A-29 Register Definitions T able A–13. MAC Protocol Selection Codes Code MAC Protocol Selected 0xb0000000b CSMA/CD (802.3 -10/100M bps) 0b0000001b External protocol: Enhanced 802.3u interface for 802.12 – 100M bps 100VG-AnyLAN interface, with decreased priority determined by channel Tx start-up timing hardwired at 50 [...]

Adapter Internal Registers A-30 A.3.8 General Address Registers – Areg_0-3 @ 0x10 – 0x24 (DIO) The four general-purpose address registers, Areg_0 through Areg_3, are used to hold the adapter ’s specific and group addresses. Each of the four reg- isters can be used to hold any 48-bit IEEE 802 address (specific or group, local or universal). Ea[...]

Adapter Internal Registers A-31 Register Definitions mode, functional addressing is supported through the general address regis- ters. If any address register contains a functional address (group/specific = 1; local/universal = 1; group/functional = 0), that register ’s two MSbytes are compared normally , but its 31 LSBs are compared on a functio[...]

Adapter Internal Registers A-32 A.3.10 Network Statistics Registers – @ 0x30 – 0x40 (DIO) The network statistics registers gather frame error information. Registers vary in size, depending on the frequency with which they increment, and may be 8, 16, or 24 bits wide. Reading a statistics register clears its contents after the read. Byte reads t[...]

Adapter Internal Registers A-33 Register Definitions T able A–14. Ethernet Error Counters Counter Definition Good Tx frames are without errors. This is a 24-bit counter . Good frames are transmitted more frequently than errored frames. Tx frames are aborted during transmission, due to frame data not being available (due to host bus latencies). Th[...]

Adapter Internal Registers A-34 Figure A–7. Demand Priority Error Counters DIO Address Byte 3 Byte 2 Byte 1 Byte 0 0x30 Rx overrun Good Rx frames 0x34 Tx underrun Good Tx frames 0x38 Code error frames CRC error frames Deferred Tx frames 0x3C 0x40 T able A–15. Demand Priority Error Counters Counter Definition Good Tx frames are transmitted witho[...]

Adapter Internal Registers A-35 Register Definitions T able A–16. Adapter Commit Register Bits Bit Name Function 31 – 28 Tx commit level T ransmit commit level: This nibble code indicates the commit size in use by the adapter transmitter . The code indicates the number of bytes that must be in a channel’s FIFO before network transmission is s[...]

Adapter Internal Registers A-36 A.3.13 Burst Size Register – BSIZEreg @ 0x44 (DIO) (Byte 1) This register is used to set the receive and transmit burst sizes to be used by the adapter . This register is only writable while the ThunderLAN controller is in reset. (NRESET = 0). This register is set to 0x22 on an Ad_Rst or when PRST# is asserted. 8 9[...]

Adapter Internal Registers A-37 Register Definitions A.3.14 Maximum Rx Frame Size Register – MaxRx @ 0x44 (DIO) (Bytes 2 + 3) Byte 3 Byte 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Maximum Rx frame size (in units of 8 bits) This register is used to set the maximum size of received network frames. Frames larger than this size are not copied[...]

Adapter Internal Registers A-38 A.3.15 Interrupt Disable Register - INTDIS @ 0x48 (DIO) (BYTE 0) This register is used to disable RX EOC, RX EOF and TX EOC interrupts. TX EOF can be disabled by setting to Tx interrupt threshold value to a zero. This register is only written to while the ThunderLAN Controller is reset. (NRE- SET=0) 0 1 2 3 4 5 6 7 R[...]

10Base-T PHY Registers A-39 Register Definitions A.4 10Base-T PHY Registers The 10Base-T PHY registers are indirectly accessible through the MII. This is a low-speed serial interface which is supported on ThunderLAN through the NetSio register in adapter DIO space. A host software program uses the MCLK, MTXEN, and MDA T A bits in this register to i[...]

10Base-T PHY Registers A-40 A.4.1 PHY Generic Control Register – GEN_ctl @ 0x0 Byte 0 Byte 1 Reserved COL TEST DUPLEX AUTO RSRT ISOLA TE PDOWN 0 LOOPBK RESET 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 AUTO ENB T able A–19. PHY Generic Control Register Bits Bit Name Function 15 RESET PHY reset: Writing a 1 to this bit causes the PHY to be reset. This[...]

10Base-T PHY Registers A-41 Register Definitions T able A–19. PHY Generic Control Register Bits (Continued) Bit Name Function 10 ISOLA TE Isolate: When this bit is set (default), the PHY electrically isolates its data paths from the MII. In this state, it does not respond to the MTXD0–3, MTXEN, and MTXER pin inputs, and presents a high impedanc[...]

10Base-T PHY Registers A-42 A.4.2 PHY Generic Status Register – GEN_sts @ 0x1 1 JABBER LINK 1 RFL T AUTOCOMPL T 1 1 0 0 0 Byte 0 Byte 1 Reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 T able A–20. PHY Generic Status Register Bits Bit Name Function 15 0 100Base-T4 capable: Not supported 14 0 100Base-Tx full-duplex capable: Not supported 13 0 100B[...]

10Base-T PHY Registers A-43 Register Definitions T able A–20. PHY Generic Status Register Bits (Continued) Bit Name Function 1 JABBER Jabber detect: When read as 1 this bit indicates a 10Base-T jabber condition has been detected. A jabber condition is latched (held) until the register is read. This bit has no meaning if the AUI interface is selec[...]

10Base-T PHY Registers A-44 A.4.3 PHY Generic Identifier – GEN_id_hi/GEN_id_lo @ 0x2/0x3 Revision number Manufacturer ’s model number OUI cont. Organizationally unique identifier (OUI) Byte 0 Byte 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 These two hardwired 16-bit registers contain an identifier code for the TLAN 10Base-T PHY . GEN_id_hi contain[...]

10Base-T PHY Registers A-45 Register Definitions A.4.4 Autonegotiation Advertisement Register – AN_adv @ 0x4 Selector field T echnology ability field TLRFL T Reserved 0 Byte 0 Byte 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 T able A–21. Autonegotiation Advertisement Register Bits Bit Name Function 15 0 Autonegotiation next page: Reception / transm[...]

10Base-T PHY Registers A-46 A.4.5 Autonegotiation Link Partner Ability Register – AN_lpa @ 0x5 selector field Link partner technology ability field Link partner LPRFL T Reserved LPNXTP AGE Byte 0 Byte 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 T able A–22. Autonegotiation Link Partner Ability Register Bits Bit Name Function 15 LPNXTP AGE Link part[...]

10Base-T PHY Registers A-47 Register Definitions A.4.6 Autonegotiation Expansion Register – AN_exp @ 0x6 LP ANABLE P AGERX 0 LPNP ABLE P ARDETFL T Reserved Byte 0 Byte 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 T able A–23. Autonegotiation Expansion Register Bits Bit Name Function 15 – 5 Reserved Read as 0 4 P ARDETFL T Parallel detection fault:[...]

10Base-T PHY Registers A-48 A.4.7 ThunderLAN PHY Identifier High/Low – TLPHY_id @ 0x10 This hardwired 16-bit register contains a TI assigned identifier code for the ThunderLAN PHY/PMIs. An additional identifier is required to identify non-802.3 PHY/PMIs, which are not otherwise supported by the 802.3u MII specification. The identifier code for th[...]

10Base-T PHY Registers A-49 Register Definitions A.4.8 ThunderLAN PHY Control Register – TLPHY_ctl @ 0x1 1 TINT INTEN NFEW MTEST SQEEN AUISEL SW APOL IGLINK Reserved Byte 0 Byte 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 T able A–24. ThunderLAN PHY Control Register Bits Bit Name Function 15 IGLINK Ignore link: When this bit is set to 0, the 10Base[...]

10Base-T PHY Registers A-50 T able A–24. ThunderLAN PHY Control Register Bits (Continued) Bit Name Function 1 INTEN Interrupt enable: Writing a 1 to this bit allows the PHY to generate interrupts on the MII if the MINT bit is set. Writing a 0 to this bit prevents the PHY from generating any MII interrupts. This bit does not disable test interrupt[...]

10Base-T PHY Registers A-51 Register Definitions T able A–25. ThunderLAN PHY Status Register Bits (Continued) Bit Name Function 13 POLOK † Polarity OK: When this bit is high (default), the 10Base-T PHY receives valid (nonin- verted) link pulses. If this bit goes low , it indicates that a sequence of seven consecutive inverted link pulses has be[...]

A-52[...]

B-1 Appendix A TNETE21 1 100VG-AnyLAN Demand Priority Physical Media Independent (PMI) Interface This appendix contains register definitions for the TNETE21 1 100VG-AnyLAN PMI interface. ThunderLAN uses these registers to store information on its in- ternal status and its communication with the host. This appendix describes the purpose and function[...]

100VG-AnyLAN T raining B-2 B.1 100VG-AnyLAN T raining The algorithm used to open ThunderLAN to the network depends on the net- work protocol in use. The demand priority protocol specified in IEEE 802.12 goes through a training process to open onto the wire. T o open the controller the driver must: Enter VG training; the network protocol is demand p[...]

100VG-AnyLAN T raining B-3 TNETE21 1 100VG-AnyLAN Demand Priority Physical Media Independent (PMI) Interface The following describes what the driver must do to successfully train: 1) Assert the INTEN bit in the TLPHY_ctl register to enable MII interrupts to ThunderLAN from the voice grade (VG) PHY 2) Ensure that ThunderLAN is not in copy all frames[...]

100VG-AnyLAN T raining B-4 8) The driver now waits for a status interrupt. The MASK7 bit in the NetMask register must be set for the status interrupt to reach ThunderLAN. 9) When this interrupt arrives, perform frame exchange T raining involves the exchange of 24 consecutive training frames between the client and the hub. The client begins by sendi[...]

100VG-AnyLAN T raining B-5 TNETE21 1 100VG-AnyLAN Demand Priority Physical Media Independent (PMI) Interface If the training frame passes these criteria, it is valid. The driver updates a counter showing the number of consecutive valid training frames passed. The driver also keeps a separate counter showing how many frames are left in the training [...]

TNETE21 1 Register Descriptions B-6 B.2 TNETE21 1 Register Descriptions This document is a specification for ThunderLAN’s TNETE21 1 PMI device, which interfaces the ThunderLAN MII and the PMD device. It is responsible for converting the nibble stream of data from the MII to the four-pair category-3 cabling, and from the four-pair category-3 cabli[...]

TNETE21 1 Register Descriptions B-7 TNETE21 1 100VG-AnyLAN Demand Priority Physical Media Independent (PMI) Interface Figure B–3. TNETE21 1 Registers TLPHY_sts TLPHY_ctl TLPHY_id GEN_id_lo GEN_id_hi GEN_sts GEN_ctl Reserved Reserved Reserved AN reserved AN far end ability AN advertisement Not implemented Not implemented ThunderLAN PHY status regi[...]

TNETE21 1 Register Descriptions B-8 T able B–1. PHY Generic Control Register Bits (Continued) Bit Name Function 11 PDOWN Power down: When this bit is set (default), the PHY is placed in a low-power consump- tion state. This bit resets the 802.12 MAC state machine to MAC0. It stops the Tx and Rx functions and disables the oscillator by deasserting[...]

TNETE21 1 Register Descriptions B-9 TNETE21 1 100VG-AnyLAN Demand Priority Physical Media Independent (PMI) Interface T able B–2. PHY Generic Status Register Bits (Continued) Bit Name Function 4 RFL T Remote fault: When this bit is set, it indicates that a remote fault condition has been detected. This bit is autoclearing, and a remote fault cond[...]

TNETE21 1 Register Descriptions B-10 T able B–3. ThunderLAN PHY Control Register Bits Bit Name Function 15 IGLINK Ignore link: When this bit is set to 0, the 100VG-AnyLAN Demand Priority PHY expects to receive link pulses from the hub, and sets the LINK bit in the GEN_sts register to 0 if they are not present. When this bit is set to 1, link puls[...]

TNETE21 1 Register Descriptions B-1 1 TNETE21 1 100VG-AnyLAN Demand Priority Physical Media Independent (PMI) Interface B.2.6 ThunderLAN PHY Status Register – TLPHY_sts @ 0x12 LSIL LRCV RTRIDL TRFRT O LST A TE RETRAIN 0 0 0 PHOK MINT Byte 0 Byte 1 CONFIG 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 T able B–4. ThunderLAN PHY Status Register Bits Bit N[...]

TNETE21 1 Register Descriptions B-12 T able B–4. ThunderLAN PHY Status Register Bits (Continued) Bit Name Function 3 TRFRT O T raining frame time out: This bit indicates that the PMI is in training, the training frame has not been received in 273 µ s, and that another training frame should be sent. If the INTEN bit is also set, this causes an MI[...]

C-1 Appendix A TNETE100PM/TNETE1 10PM For information on the TNETE100PM and TNETE1 10PM implementations of ThunderLAN, please contact TLANHOT@micro.ti.com, which is listed on page v of this document. Appendix C[...]

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