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Xilinx 1.8 manuale d’uso - BKManuals
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Xilinx 1.8 manuale d’uso

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Un buon manuale d’uso

Le regole impongono al rivenditore l'obbligo di fornire all'acquirente, insieme alle merci, il manuale d’uso Xilinx 1.8. La mancanza del manuale d’uso o le informazioni errate fornite al consumatore sono la base di una denuncia in caso di inosservanza del dispositivo con il contratto. Secondo la legge, l’inclusione del manuale d’uso in una forma diversa da quella cartacea è permessa, che viene spesso utilizzato recentemente, includendo una forma grafica o elettronica Xilinx 1.8 o video didattici per gli utenti. La condizione è il suo carattere leggibile e comprensibile.

Che cosa è il manuale d’uso?

La parola deriva dal latino "instructio", cioè organizzare. Così, il manuale d’uso Xilinx 1.8 descrive le fasi del procedimento. Lo scopo del manuale d’uso è istruire, facilitare lo avviamento, l'uso di attrezzature o l’esecuzione di determinate azioni. Il manuale è una raccolta di informazioni sull'oggetto/servizio, un suggerimento.

Purtroppo, pochi utenti prendono il tempo di leggere il manuale d’uso, e un buono manuale non solo permette di conoscere una serie di funzionalità aggiuntive del dispositivo acquistato, ma anche evitare la maggioranza dei guasti.

Quindi cosa dovrebbe contenere il manuale perfetto?

Innanzitutto, il manuale d’uso Xilinx 1.8 dovrebbe contenere:
- informazioni sui dati tecnici del dispositivo Xilinx 1.8
- nome del fabbricante e anno di fabbricazione Xilinx 1.8
- istruzioni per l'uso, la regolazione e la manutenzione delle attrezzature Xilinx 1.8
- segnaletica di sicurezza e certificati che confermano la conformità con le norme pertinenti

Perché non leggiamo i manuali d’uso?

Generalmente questo è dovuto alla mancanza di tempo e certezza per quanto riguarda la funzionalità specifica delle attrezzature acquistate. Purtroppo, la connessione e l’avvio Xilinx 1.8 non sono sufficienti. Questo manuale contiene una serie di linee guida per funzionalità specifiche, la sicurezza, metodi di manutenzione (anche i mezzi che dovrebbero essere usati), eventuali difetti Xilinx 1.8 e modi per risolvere i problemi più comuni durante l'uso. Infine, il manuale contiene le coordinate del servizio Xilinx in assenza dell'efficacia delle soluzioni proposte. Attualmente, i manuali d’uso sotto forma di animazioni interessanti e video didattici che sono migliori che la brochure suscitano un interesse considerevole. Questo tipo di manuale permette all'utente di visualizzare tutto il video didattico senza saltare le specifiche e complicate descrizioni tecniche Xilinx 1.8, come nel caso della versione cartacea.

Perché leggere il manuale d’uso?

Prima di tutto, contiene la risposta sulla struttura, le possibilità del dispositivo Xilinx 1.8, l'uso di vari accessori ed una serie di informazioni per sfruttare totalmente tutte le caratteristiche e servizi.

Dopo l'acquisto di successo di attrezzature/dispositivo, prendere un momento per familiarizzare con tutte le parti del manuale d'uso Xilinx 1.8. Attualmente, sono preparati con cura e tradotti per essere comprensibili non solo per gli utenti, ma per svolgere la loro funzione di base di informazioni e di aiuto.

Sommario del manuale d’uso

  • Pagina 1

    R LogiCORE™ IP Endpoint Bloc k Plus v1.8 f or PCI Express® Getting Star ted Guide UG343 J une 27, 2008[...]

  • Pagina 2

    www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Xilinx is disclosing this user gui de, manual, rel ease note, and/or sp ecification (the "Documentation") to y ou solely f or use in the de v elopment of designs to operate with Xilinx hardw are de vices. Y ou may not re produce, distribu te, repub lish, downlo[...]

  • Pagina 3

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com UG343 June 27, 2008 Preface: About This Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

  • Pagina 4

    www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Dual Core Example De sign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Dual Core Directory Structure and Fi le Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 <component name>/example[...]

  • Pagina 5

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 5 UG343 June 27, 2008 R Pr eface About This Guide The Endpoint Block Plus for P CI Ex pres s® Getting Started Gu ide provides information about generating an Endpoint Block Plus for PCI Expr ess (PCIe ® ) cor e, customizing and simulating the cor e using the pr ovided example design, and [...]

  • Pagina 6

    6 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Preface: About This Guide R Online Document The following li nking conventions are used in this document: Italic font Refer ences to other manuals See the User Guide for details. Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol, the two nets [...]

  • Pagina 7

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 7 UG343 June 27, 2008 R Chapter 1 Intr oduction The Endpoint Block Plus for PCI Express is a high-bandwidth , scalable, and r eliable serial interconnect building block for use with V irtex™-5 FPGA devices. This cor e supports V erilog® and VHDL. The example design described in thi s gui[...]

  • Pagina 8

    8 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 1: Introd uction R performance, pipelined FPGA designs using Xilinx implementation softwar e and User Constraints Files (U CF) is recommended. Additional Core Resour ces For detailed informati on and updates about the cor e, see the fol lowing documents, availa[...]

  • Pagina 9

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 9 UG343 June 27, 2008 Feedbac k R Document For comments or suggestions about this do cument, please submit a W ebCase from www .xilinx.com/support . Be sure to include the following information: • Document title • Document number • Page number(s) to which your comments r efer • Expl[...]

  • Pagina 10

    10 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 1: Introd uction R[...]

  • Pagina 11

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 11 UG343 June 27, 2008 R Chapter 2 Licensing the Cor e This chapter provided licensing options for th e E ndpoint Block Plus for PCI Expr ess cor e, which you must do bef ore using the core in your designs. The cor e is pr ovided under the terms of the Xilinx LogiCORE Site License Agre emen[...]

  • Pagina 12

    12 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 2: Licensing the Core R Obtaining Y our License Simulatio n Only Eva luation License The Simulation Only Evalua tion license is pr ovided with the CORE Generator system and requir es no license file. Obtaining a Full License T o obtain a Full license, you must[...]

  • Pagina 13

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 13 UG343 June 27, 2008 R Chapter 3 Quickstart Example Design This chapter provides an overview of the Endpoi nt Block Plus for PCI Ex press example design (both single and dual cor e) and instructio ns for generating the co re. It also includes information about simulati ng and implementing[...]

  • Pagina 14

    14 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quicks tart Example Design R Figure 3-1: Simula tion Example Design Bloc k Diagram Test Program Endpoint DUT for PCI Express PCI Expr ess Fabric Endpoint Core for PCI Expr ess PIO Design dsport usrapp_tx usrapp_com usrapp_r x Output Logs Downstream Port Mod[...]

  • Pagina 15

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 15 UG343 June 27, 2008 Overvie w R Implementation Design Ov er vie w The implementation design consists of a simple PIO example that can accept r ead and write transactions and respond to requests, as illustrated in Figure 3-2 . Sour ce code for the example is provided with the core. For mo[...]

  • Pagina 16

    16 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quicks tart Example Design R Generating the Core T o generate a core using the default values in the CORE Generator Graphical User Interface (GUI), do the following: 1. Start the CORE Generator . For help starting and using the CORE Ge nerator , see the Xil[...]

  • Pagina 17

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 17 UG343 June 27, 2008 Generating the Core R 4. Set the project options: From the Part tab, select the following options: • Family : V irtex5 • Device : xc5vlx50t • Package : ff1 1 36 • Speed Grade : -1 Note : If an unsupported silicon devi ce is sele cted, the core is dimmed (unava[...]

  • Pagina 18

    18 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quicks tart Example Design R Sim ulating the Example Design The example design pr ovides a quick way to si mulate and observe the behavior of the cor e. The simulation environment pr ovided with th e Block Plus cor e performs simple memory access tests on t[...]

  • Pagina 19

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 19 UG343 June 27, 2008 Implementing th e Example Design R 2. Run the script that corresponds to your si mulation tool using one of the following: • VCS : simulate_vcs.sh • Cadence IUS : simulate_ncsim.sh • ModelSim : vsim -do simulate_mti.do Implementing the Example Design After gener[...]

  • Pagina 20

    20 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quicks tart Example Design R • routed.sdf T iming model Sta ndard Delay File. • mapped.mrp Xilinx map report. • routed.par Xilinx place and route r eport. • routed.twr Xilinx timing analysis report. Th e sc ri pt f ile sta rt s fro m an ED IF/ NG C [...]

  • Pagina 21

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 21 UG343 June 27, 2008 Directory Structure and File Conten ts R <project director y> The project dir ectory contains all the CORE Generator project files . <project director y>/<component name> The component name directory contains the re lease notes r eadme file pr ovided[...]

  • Pagina 22

    22 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quicks tart Example Design R <component name>/e xample_design The example design dir ectory contains the ex ample design files pr ovided with the cor e. <component name>/implement The implement directory contains the cor e implementation script [...]

  • Pagina 23

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 23 UG343 June 27, 2008 Directory Structure and File Conten ts R implement/results The results dir ectory is created by the implem ent script, after which the implement script resul ts are placed in the r esults dir ectory . <component name>/simulation The simulation directory contai n[...]

  • Pagina 24

    24 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quicks tart Example Design R simulation/dspor t The dsport dire ctory contains the data stre am simulation scripts provided with the core. simulation/functional The functional directory contains functional simulation scripts pr ovided with the core. T able [...]

  • Pagina 25

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 25 UG343 June 27, 2008 Dual Core Example Design R simulation/tests The tests dir ectory contains test definiti ons for the example te st bench. Dual Core Example Design The dual core example design can be used as a starting point for desi gns with multiple V irtex-5 FPGA PCI Expr ess blocks[...]

  • Pagina 26

    26 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quicks tart Example Design R Dual Core Director y Structure and File Contents W h e n g e n e r a t i n g t h e B l o c k P l u s c o r e w i t h the V irtex-5 FX70T -FF1 136 (XC5VFX70T -FF1 136) FPGA, the PIO example design source files and s cripts are ge[...]

  • Pagina 27

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 27 UG343 June 27, 2008 Dual Core Example Design R <component name>/e xample_design The example design dir ectory includes the du al core example design ucf, which varies based on the device selected . e xample_design/dual_core The dual core dir ectory contains the top-leve l and wrapp[...]

  • Pagina 28

    28 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quicks tart Example Design R simulation/functional The functional directory contains the dual cor e example design simulation scripts. <component name>/implement The implement directory contains the dual co re example design implementation script file[...]

  • Pagina 29

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 29 UG343 June 27, 2008 R Appendix Additional Design Considerations P acka ge Constraints This appendix describes design consi derations specifi c to the Endpoint Block P lus for PCIe core. Ta b l e A - 1 lists the smallest supported devic e an d interface combinations for the Block Plus cor[...]

  • Pagina 30

    30 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Appendix Appendix: Additional Design Considera tions R[...]