Acer Intel Pentium B940 manual

Document Number: 322910 -003 Intel ® Core™ i5-600, i3-500 Desktop Processor Series and Intel ® Pentium ® Desktop Processor 6000 Series Datasheet – Volume 2 January 2011[...]

2 Datasheet, Volume 2 Legal Lines and Disclaime rs INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNE CTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR O THERWISE, TO ANY INTELLECTUAL PROPER TY RIGHTS IS GRANTED BY THIS DOCUMENT . EXCEPT AS PROVIDED IN INTEL 'S TERMS AND CONDIT IONS OF SALE FOR SUCH PRODUCTS, IN TEL A[...]

Datasheet, Volume 2 3 Contents 1I n t r o d u c t i o n ....... ........... ........ ........... ........ ........... ........ ........... ........ ........ ........... ...... 13 2 Processor Configuration Registers ........ .......... ......... .......... ......... .......... ......... .......... 15 2.1 Register Terminolog y ......... ........... .[...]

4 Datasheet, Volume 2 2.7.12 MCHBAR—MCH M emory Mapped Reg ister Range Ba se Register ................ .. 52 2.7.13 GGC—Graphics Control Register ... ............. .......... ........... ........... .......... .. 53 2.7.14 DEVEN—De vice Enable Reg ister ........... ............ ........... .......... ........... ...... 54 2.7.15 DMIBAR—Root[...]

Datasheet, Volume 2 5 2.8.37 SSKPD—Sticky Scratchp ad Data Register . ............. ............ ........... .......... 94 2.8.38 TSC1—Thermal Sen sor Control 1 Register .. ........... .......... ............. .......... 94 2.8.39 TSS1—Thermal Sensor Status 1 Register .. .. ........... ........ ........... ........ ...... 95 2.8.40 TR1—Ther[...]

6 Datasheet, Volume 2 2.10.31 MC—Me ssage Control Register................. .......... ........... .......... ............. 137 2.10.32 MA—Me ssage Address Registe r ............ .......... ........... .......... ........... ...... 138 2.10.33 MD—Me ssage Data Register ... ............. .......... ............. .......... ........... .... 138[...]

Datasheet, Volume 2 7 2.13.8 MLT2—Master L atency Timer Registe r .............. ........... .......... ............. .. 178 2.13.9 HDR2—Head er Type Re gister .................. .......... ........... ............. .......... 178 2.13.10 GTTMMADR—Graphics Translation Table, Memory Mapped Range Address Register ... ........ ......... ........[...]

8 Datasheet, Volume 2 2.16.6 RTADDR_REG—Root-Entry Table Address Re gister .......... .......... ........... .. 231 2.16.7 CCMD_REG—Con text Command Re gister ................... .......... ........... ...... 232 2.16.8 FSTS_REG—Fau lt Status Register ........ .......... ............. .......... ........... .... 234 2.16.9 FECTL_REG—Fault E[...]

Datasheet, Volume 2 9 2.18.27 IVA_REG—Invalid ate Address Reg ister ............... ........... ........... .......... .. 283 2.18.28 IOTLB_REG—IOTLB Invalidate Register ............ ........... ............. .......... .. 284 2.18.29 FRCD _REG—Fault Recording Registers ..... ............... ........ ........... ........ .. 286 2.18.30 VTPO L[...]

10 Datasheet, Volume 2 2.20.5 VC0RCTL—VC0 Resource Control Register ..... ............. .......... ............. .... 331 2.20.6 VC0RSTS—VC0 Resource Status Register .......... ........... ............ ........... .. 332 2.21 Intel ® Trusted Execution Technology (Intel ® TXT) Specific Registers ................ ...... 332 2.21.1 TXT.DID—T X[...]

Datasheet, Volume 2 11 Figures 2-1 System Addre ss Range ..... ........... ............ ........... .......... ........... ........... .......... .... 18 2-2 DOS Lega cy Address Rang e ........... ........ ........... ........ ........... ........ ........... ........ .... 19 2-3 Main Memory Ad dress Range ................... ........... ..........[...]

12 Datasheet, Volume 2 Revision History § Revision Number Description Revision Date -001 Initial release January 2010 -002 • Added the MCSAMPML —Memory Config uration, S ystem Address Map and Pre-allocated Me mory Lock Reg ister . See Section 2.7. 28 . • Added the PEG_TC—PCI Express Completion Timeout Register . See Section 2.11.7 . • Up[...]

Datasheet, Volume 2 13 Introduction 1 Introduction This is V olume 2 of the Datasheet for the Intel ® Core™ i5-600, i3-500 Desktop processor series and Intel ® Pen t iu m ® desktop processor 6000 series. The processor contains one or more PCI devi ces within a single ph ysical component. The configuration registers for these devices are mapped[...]

Introduction 14 Datasheet, Volume 2[...]

Datasheet, Volume 2 15 Processor Configuration Registers 2 Processor Configuration Registers 2.1 Register Terminology Ta b l e 2 - 1 shows the register-related terminology that is used in this chapter . Table 2-1. Register Term inology (Sheet 1 of 2) Item Description RO Read Only bit(s). Writes to these bits ha ve no e ffect. These are static value[...]

Processor Configuration Registers 16 Datasheet, Volume 2 RW- V-L Read/Write/Volatile/Lockable bit(s). These bits can be read and written by software. Hardware may set or clear the bit based upon internal events, possibly sooner than an y subsequent software read could retrieve the value writt en. Additionally , there is a bit (which is marked RW -K[...]

Datasheet, Volume 2 17 Processor Configuration Registers 2.2 System Address Map Note: The processor’s Multi Chip P ackage (MCP) conceptually consists of the processor and the north bridge chipset (GMCH) combined to gether in a single package. Hence, this section will have references to the processor as well as GMCH (or MCH) address mapping. The M[...]

Processor Configuration Registers 18 Datasheet, Volume 2 Figure 2-1 represents system memory address map in a simplified form. Figure 2-1. System Address Range Main Memory Address Range Main Memory Address Range 4G Main Memory Reclaim Address Range 64G RECLAIM BASE RECLAIM LIMIT = RECLAIM BASE + x OS VISIBLE < 4GB PCI Memory Address Range (subtr[...]

Datasheet, Volume 2 19 Processor Configuration Registers 2.2.1 Legacy Add ress Range This area is divided into the following address regions: • 0 – 640 KB — DOS Area • 640 – 768 KB — Legacy Video Buffer Area • 768 – 896 KB in 16 KB sections (total of 8 sections) — Expansion Area • 896 – 960 KB in 16 KB sections (total of 4 sec[...]

Processor Configuration Registers 20 Datasheet, Volume 2 Non-SMM-mode processor accesses to this range are considered to be to the Video Buffer Area as described above. The processor will route these accesses on the non- coherent (NCS or NCB) channels. The processor always positively decodes internally mapped devices, namely the IGD and PCI-Express[...]

Datasheet, Volume 2 21 Processor Configuration Registers 2.2.2 Main Memory Address Range (1MB – TOLUD) This address range extends from 1 MB to the top o f Low Usable physical memory that is permitted to be accessible by the GMCH (as programmed in the T O LUD register). The processor will route all addresses within th is range as HOM accesses, whi[...]

Processor Configuration Registers 22 Datasheet, Volume 2 2.2.2.2 TSEG The TSEG register was moved from the GMCH to the processor . The GMCH will have no direct knowledge of the TSEG size. F or processor initiated transactions, the processor will perform necessary decode and route a ppropriately on HOM (to DRAM) or NCS/NCB. TSEG is below IGD stolen [...]

Datasheet, Volume 2 23 Processor Configuration Registers Once the protected low/high memory region registers are configured, bus master protection to these regions is enabled thro ugh the Protected Memory Enable register . For platforms with multiple DMA -remapp ing hardware units, each of the DMA- remapping hardware units mu st be config ured with[...]

Processor Configuration Registers 24 Datasheet, Volume 2 2.2.2.6.3 S hadow GTT Stolen Space (SGSM) Shadow GSM will be only used once internal GFX and VT -d translations are enabled. The purpose of shadow GSM is to provide a physical space to hardware, where VT -d translation for PTE updates can be made on the fly and re- written back into physical [...]

Datasheet, Volume 2 25 Processor Configuration Registers There are sub-ranges within the PCI Memory address range defined as APIC Configuration Space, MSI Interrupt Spac e, and High BIOS Address R ange. The exceptions listed above for internal graphics and the PCI Express ports MUST NOT overlap with these rang es. Figure 2-4. PCI Memory Address Ran[...]

Processor Configuration Registers 26 Datasheet, Volume 2 2.2.2.9 APIC Configuration Space (FEC0_0000h–F ECF_FFFFh) This range is reserv ed for APIC configuratio n space. The I/O APIC(s) usually reside in the PCH portion of the chipset, but ma y also exist as stand-alone components like PXH. The IOAPIC spaces are used to communicate with IOAPIC in[...]

Datasheet, Volume 2 27 Processor Configuration Registers 2.2.3 Main Memory Address Space (4 GB to TOUUD) The processor will support 36 bit addressing. The maximum main memory size supported is 16 GB total DRAM memory . A hole between TOLU D and 4 GB occurs when main memory size approaches 4 GB or larger . As a result, TOM, an d T OUUD registers and[...]

Processor Configuration Registers 28 Datasheet, Volume 2 2.2.3.1 Programming Model The memory boundaries of interest are: • Bottom of Logical Address Remap Window defined by the REMAPBASE register , which is calculated and loaded by BIOS . • T op of Logical Address Remap Window defined by the REMAPLIMIT register , whic h is calculated and loade[...]

Datasheet, Volume 2 29 Processor Configuration Registers 2.2.3.1.1 Case 1 — Less than 4 GB of Physical Memory (no remap) • P opulated Physical Memory = 2 GB • Address Space allocated to memory mapped I/O = 1 GB • Remapped Physical Memory = 0 GB • TOM – 020h (2 GB) • ME stolen size – 00001b (1 MB) • T OUUD – 07FFh (2 GB minus 1 M[...]

Processor Configuration Registers 30 Datasheet, Volume 2 2.2.3.1.2 C ase 2 — Greater than 4 GB of Physical Memory Note: Internal graphics is not supported on the Intel X eon processor L3406 . In this case the amount of memory rema pped is the range between TOLUD and 4 GB. This physical memory will be mapped to the logical address range defined be[...]

Datasheet, Volume 2 31 Processor Configuration Registers 2.2.3.1.3 Case 3 — 4 GB or less of Physical Memory Note: Internal gr aphics is not supported on the Intel Xeon processor L3406. In this case the amount of memory rema pped is the r ange between T OLUD and TOM minus the ME stolen memory . This physical memory will be mapped to the logical ad[...]

Processor Configuration Registers 32 Datasheet, Volume 2 2.2.3.1.4 C ase 4 — Greater than 4 GB of Physical Memory, Remap Note: Internal graphics is not supported on the Intel X eon processor L3406 . In this case the amount of memory rema pped is the range between TOLUD and 4 GB. This physical memory will be mapped to the logical address range def[...]

Datasheet, Volume 2 33 Processor Configuration Registers 2.2.4 PCI Express* Conf iguration Address Space PCIEXBAR has moved to the processor . The processor now detects memory accesses targeting PCIEXBAR and the processor conv erts that access to QPI configur ation accesses. BIOS must assign this address ra nge such that it will not conflict with a[...]

Processor Configuration Registers 34 Datasheet, Volume 2 2.2.6 Graphics Memo ry Address Ranges The processor can be programmed to direct memory accesses to IGD when addresses are within any of five r anges specified using registers in the processor Device 2 configuration space. 1. The Graphics Memory Aperture Base Register (GMADR) is used to access[...]

Datasheet, Volume 2 35 Processor Configuration Registers 2.2.7 System M anagement Mode ( SMM) The processor handles all SMM mode transaction routing. The processor has no direct knowledge of SMM mode. The processor will never allow I/O devices access to CSEG/TSEG/HSEG ranges. DMI Interface and PCI Express masters ar e not allowed to access the SMM [...]

Processor Configuration Registers 36 Datasheet, Volume 2 locations can be accessed only during I/O address wrap-around when address bit 16 is asserted. Address bit 16 is asserted on the processor bus whenever an I/O access is made to 4 bytes from address 0FFFDh, 0FFFE h, or 0FFFFh. Address bit 16 is also asserted when an I/O access is made to 2 byt[...]

Datasheet, Volume 2 37 Processor Configuration Registers Note that the processor Device 1 I/O address r ange registers defined above are used for all I/O space allocation for any devices requ iring such a window on PCI -Express. The PCICMD1 register can disable the ro uting of I/O cycles to PCI- Express. 2.3 Configuration Process and Registers 2.3.[...]

Processor Configuration Registers 38 Datasheet, Volume 2 2.4 Configuration Mechanisms The GMCH is the originator of configuration cycles. Internal to the GMCH transactions received through both configuration mechan isms are translated to the same format. 2.4.1 Standard PCI Confi gu ration Mechani sm The following is the mechanism for tr anslating G[...]

Datasheet, Volume 2 39 Processor Configuration Registers 2.4.2 PCI Express* Enhanced Configuration Mechanism PCI Express extends the configuration space to 4096 bytes per device/function as compared to 256 bytes allowed by the latest PCI Local Bus Specification . PCI Express configuration space is divided into a PCI 3.0 compatible region, which con[...]

Processor Configuration Registers 40 Datasheet, Volume 2 Just the same as with PCI devices, each device is selected based on decoded address information that is provided as a part of the address portion of Configur ation Request packets. A PCI Express device will decode a ll address information fields (bus, device, function and extended address num[...]

Datasheet, Volume 2 41 Processor Configuration Registers 2.4.4 Internal Device Configuration Accesses The processor decodes the Bus Number (Bits 23:16) and the Device Number fields of the CONFIG_ADDRESS register . If the Bus Numb er field of CONFIG_A DDRESS is 0, the configuration cy cle is targeting a PCI Bus 0 device. If the targeted PCI Bus 0 de[...]

Processor Configuration Registers 42 Datasheet, Volume 2 2.4.5 Bridge Related Co nfi guration Accesses Configuration accesses on PCI Express or DMI are PCI Express Configuration TLPs. • Bus Number [7:0] is Header Byte 8 [7:0] • Device Number [4:0] is Header Byte 9 [7:3] • Function Number [2:0] is Header Byte 9 [2:0] And special fields for thi[...]

Datasheet, Volume 2 43 Processor Configuration Registers 2.4.5.2 DMI Configura tion Accesses Accesses to disabled processor internal devices, bus numbers not claimed by the Host - PCI Express bridge, or PCI Bus 0 devices no t part of the processor will subtr actively decode to the PCH and consequently be fo rwarded over the DMI using a PCI Express [...]

Processor Configuration Registers 44 Datasheet, Volume 2 positions must first be read, merged with the new values for other bit positions and then written back. Note the software does not need to perform read, merge, and write operation for the C onfiguration Address R egister . In addition to reserved bits within a register , the processor contain[...]

Datasheet, Volume 2 45 Processor Configuration Registers 2.7 PCI Express* Device 0 Registers Ta b l e 2 - 4 shows the PCI Express Device 0 register address map. Detailed register bit descriptions follow Ta b l e 2 - 4 . Table 2-4. PCI Express* Devi ce 0 Register Address Map Offset Address Regis ter Symbol Register Name Reset Value Access 0–1h VID[...]

Processor Configuration Registers 46 Datasheet, Volume 2 2.7.1 VID—Vendor Identification Register This register combined with the Device Identification register uniquely identifies any PCI device. 2.7.2 DID—Device Iden tification Register This register combined with the Vendor Identification register uniquely identifies any PCI device. B/D/F/Ty[...]

Datasheet, Volume 2 47 Processor Configuration Registers 2.7.3 PCICMD—PCI Command Register Since processor Device 0 does not physically reside on PCI_A many of the bits are not implemented. B/D/F/Type : 0/0/0/ PCI Address Offset: 4–5h Reset Value: 0006h Access: RO, RW Bit A ttr Reset Value Description 15:10 RO 00h Reserved 9R O 0 b Fast Back-to[...]

Processor Configuration Registers 48 Datasheet, Volume 2 2.7.4 PCISTS—PCI Status Register This status register reports the occurrence of error events on Device 0's PCI interface. Since the processor Device 0 d oes not physically reside on PCI_A, many of the bits are not implemented. B/D/F/Type: 0/0/0/PCI Address Offset: 6–7h Reset Value: 0[...]

Datasheet, Volume 2 49 Processor Configuration Registers 2.7.5 RID—Revision Identification This register contains the revision num ber of the processor . The R evision ID (RID) is a traditional 8-bit R ead Only (RO) register located at offset 08h in the standard PCI header of every PCI/PCI Express compatible device and function. 2.7.6 CC—Class [...]

Processor Configuration Registers 50 Datasheet, Volume 2 2.7.8 HDR—Header Type Register This register identifies the header layout of the configuration space. No physical register exists at this location. 2.7.9 SVID—Subsystem Vendor Identification Register This value is used to identify the vendor of the subsystem. B/D/F/Type: 0/0/0/PCI Address[...]

Datasheet, Volume 2 51 Processor Configuration Registers 2.7.10 SID—Subsystem Id entification Register This value is used to identify a particular subsystem. 2.7.11 PXPEPBAR—PCI Express Egress Port Base Address Register This is the base address for the PCI Express Egress P ort MMIO Configur ation space. There is no physical memory within this 4[...]

Processor Configuration Registers 52 Datasheet, Volume 2 2.7.12 MCHBAR—MCH Memory Ma pped Register Range Base Register This is the base address for the processo r memory mapped configuration space. There is no physical memory within this 16 KB window that can be addressed. The 16 KB reserved by this register does not alias to any PCI 2.3 complian[...]

Datasheet, Volume 2 53 Processor Configuration Registers 2.7.13 GGC—Graphics Control Register All the bits in this register are Intel TXT lockable. B/D/F/Type : 0/0/0/ PCI Address Offset: 52–53h Reset Value: 0030h Access: RW-L, RO Bit A ttr Reset Value Description 15:12 RO 0h Reserved 11:8 RW-L 0h GTT Graphics Memory Siz e (GGMS) This field is [...]

Processor Configuration Registers 54 Datasheet, Volume 2 2.7.14 DEVEN—Device Enable Register This register allows for enabling/disabling of PCI devices and functions that are within the processor. The table below describes the behavior of all combinations of transactions to devices controlled by this register. All the bits in this register are In[...]

Datasheet, Volume 2 55 Processor Configuration Registers 2.7.15 DMIBAR—Root Complex Re gister Range Base Address Register This is the base a ddress for the Root Comp lex configuration space. This window of addresses contains the Root Complex Register set for the PCI Express Hierarchy associated with the processor. There is no physical memory with[...]

Processor Configuration Registers 56 Datasheet, Volume 2 2.7.16 LAC—Legacy Acce ss Control Register This 8-bit register controls steering of MDA cycles. There can only be at most one MDA device in the system. BIOS must not program bits 1:0 to 11b. B/D/F/Type: 0/0/0/PCI Address Offset: 97h Reset Value: 00h Access: RW BIOS Optimal Reset Value 00h B[...]

Datasheet, Volume 2 57 Processor Configuration Registers 0R W 0 b PEG0 MDA Present (MDAP0) This bit works with the VGA Enable bits in the BCTRL register of Device 1 to control the routing o f processor in itiated tr ansactions targeting MDA compatible I/O and memory address ra nges. This bit should not b e set if device 1's VGA Enable bi t is [...]

Processor Configuration Registers 58 Datasheet, Volume 2 2.7.17 TOUUD—Top of Uppe r Usable DRAM Re gister This 16 bit register defines the T op of Upper Usable DRAM. Configuration software must set this value to T OM minus all EP pre-allocated memory if reclaim is disabled. If reclaim is enabled, this v alue must be set to reclaim limit + 1byte, [...]

Datasheet, Volume 2 59 Processor Configuration Registers 2.7.19 BGSM—Base of GTT Pre- allocated Memory Register This register contains the base address of DRAM memory pre-allocated for the GT T . BIOS determines the base of pre-allocated GT T memory by subtracting the GT T grap hics memory pre- allocated size (PCI Dev ice 0, offset 52h, bits 11:8[...]

Processor Configuration Registers 60 Datasheet, Volume 2 2.7.21 TOLUD—Top of Low Usable DRAM Register This 16-bit register defines the T op of Low Usable DRA M. TSEG, GT T Graphics memory , and Memory pre-allocated for graphics are within the usable DRAM space defined. Progra mming Example: C1DRB3 is set to 5 GB BIOS knows the OS requires 1 GB of[...]

Datasheet, Volume 2 61 Processor Configuration Registers 2.7.22 PBFC—Primary Buffer Flush Co ntrol Register 2.7.23 SBFC—Secondary B uffer Flush Control Register B/D/F/Type : 0/0/0/ PCI Address Offset: C0–C3h Reset Value: 0000_0000h Access: RO, W Bit A ttr Reset Value Description 31:1 RO 0h Reserved 0W 0 b Primary CWB Flush Control (PCWBFLSH) [...]

Processor Configuration Registers 62 Datasheet, Volume 2 2.7.24 ERRSTS—Error Status Regi ster This register is used to report v arious error conditions using the SERR DMI messaging mechanism. An SERR DMI message is generated on a zero to one tr ansition of any of these flags (if enabled by the ERRCMD and PCICMD registers). These bits are set rega[...]

Datasheet, Volume 2 63 Processor Configuration Registers 2.7.25 ERRCMD—Error Command Register This register controls the processor responses to v arious system errors. Since the processor does not have an SERR# signal, SERR messages are passed from the processor to the PCH over DMI. When a bit in this register is set, a SERR message will be gener[...]

Processor Configuration Registers 64 Datasheet, Volume 2 2.7.26 SMICMD—SMI Command Register This register enables various errors to gener ate an SMI DMI specia l cycle. When an error flag is set in the ERRSTS register , it can gener ate an SERR, SMI, or SCI DMI special cycle when enabled in the ERRCMD , SMICMD, or SCICMD registers, respectively .[...]

Datasheet, Volume 2 65 Processor Configuration Registers 2.7.28 CAPID0—Capability Identifier Register This register is used to report various processor capabilities. 2.7.29 MCSAMPML—Memory Co nfiguration, System Address Map and Pre-allo cated Memory Lock Register B/D/F/Type : 0/0/0/ PCI Address Offset: E0–EBh Reset Value: SKU dependent Access[...]

Processor Configuration Registers 66 Datasheet, Volume 2 2.8 MCHBAR Registers Table 2-5. MCHBAR Register Address Map (Sheet 1 of 2) Address Offset Register Symbol Register Name Reset Value Access 111h CHDECMISC Channel Decode Misc 00h RW-L, RO 200–201h C0DRB0 Channel 0 DRAM Rank Boundary Address 0 0000h RW-L, RO 202–203h C0DRB1 Channel 0 DRAM R[...]

Datasheet, Volume 2 67 Processor Configuration Registers 1001–1002h TSC1 Thermal Sen sor Control 1 0000h RW-L, RO, RW , AF 1004–1005h TSS1 Thermal Sensor Status 1 0000h RO 1006h TR1 T hermometer Read 1 FFh RO 1007h TOF1 Thermometer Offset 1 00h RW 1008h RTR1 Relative Thermometer R ead 1 00h RO 1010–1013h TSTTP A1 Thermal Sensor T emperature T[...]

Processor Configuration Registers 68 Datasheet, Volume 2 2.8.1 CSZMAP—Channel Size Map ping Register This register indicates the total memory that is mapped to Interleaved and Asymmetric operation respectively (1 MB granularit y) used for Channel address decode. B/D/F/Type: 0/0/0/MCHBAR Address Offset: 100–107h Reset Value: 0000_0000_0000_0000h[...]

Datasheet, Volume 2 69 Processor Configuration Registers 2.8.2 CHDECMISC—Channel Deco de Miscellaneous Regi ster This register provides enhanced addressing configuration bits. B/D/F/Type : 0/0/0/ MCHBAR Address Offset: 111h Reset Value: 00h Access: RW-L, RO BIOS Optimal Reset Value 0h Bit A ttr Reset Value Description 7R W - L 0 b Enhanced Addres[...]

Processor Configuration Registers 70 Datasheet, Volume 2 2.8.3 C0DRB0—Channel 0 DRAM Rank Boundary Address 0 Register The DRAM R ank Boundary R e gisters define th e upper boundary address of each DRAM rank with a granularit y of 64 MB. Each r ank has its own single-word DRB register . These registers are used to determine which chip select will [...]

Datasheet, Volume 2 71 Processor Configuration Registers 2.8.4 C0DRB1—Channel 0 DRAM Rank Boundary Address 1 Register See C0DRB0 register description for details. 2.8.5 C0DRB2—Channel 0 DRAM Rank Boundary Address 2 Register See C0DRB0 register description for details. B/D/F/Type : 0/0/0/ MCHBAR Address Offset: 202–203h Reset Value: 0000h Acce[...]

Processor Configuration Registers 72 Datasheet, Volume 2 2.8.6 C0DRB3—Channel 0 DRAM Rank Boundary Address 3 Register See C0DRB0 register description for details. B/D/F/Type: 0/0/0/MCHBAR Address Offset: 206–207h Reset Value: 0000h Access: RO, RW-L Bit Attr Reset Value Description 15:10 RO 00h Reserved 9:0 RW-L 000h Channel 0 DRAM Rank Boundary[...]

Datasheet, Volume 2 73 Processor Configuration Registers 2.8.7 C0DRA01—Channel 0 DRAM Rank 0,1 Attribute Register The DRAM Rank A ttribute R egisters define th e page sizes/number of banks to be used when accessing different ranks. These registers should be left with their R eset V alue (all zeros) for any r ank that is unpopulated, as determined[...]

Processor Configuration Registers 74 Datasheet, Volume 2 2.8.8 C0DRA23—Channel 0 DRAM Rank 2,3 Attribute Register See C0DRA01 register description for programming details. 2.8.9 C0WRDATACTRL—Channel 0 Write Data Control Register Channel 0 WR Data Control R egisters. B/D/F/Type: 0/0/0/MCHBAR Address Offset: 20A–20Bh Reset Value: 0000h Access: [...]

Datasheet, Volume 2 75 Processor Configuration Registers 2.8.10 C0CYCTRKPCHG—Channel 0 CYCT RK PCHG Register B/D/F/Type : 0/0/0/ MCHBAR Address Offset: 250-251h Reset Value: 0000h Access: RO, RW Bit A ttr Reset Value Description 15:11 RO 00h Reserved 10:6 RW 00h Write To Precharge Delay (C0sd_cr_wr_pchg) This field indicates the minimum allowe d [...]

Processor Configuration Registers 76 Datasheet, Volume 2 2.8.11 C0CYCTRKACT—Channe l 0 CYCTRK ACT Register B/D/F/Type: 0/0/0/MCHBAR Address Offset: 252–255h Reset Value: 0000_0000h Access: RW, RO Bit Attr Reset Value Description 31:30 RO 00b Reserved 29 RW 0b FAW Windowcnt Bug Fi x Dis able (FAWWBF D) This bit disables the CYCTRK F AW windowcnt[...]

Datasheet, Volume 2 77 Processor Configuration Registers 2.8.12 C0CYCTRKWR—Channel 0 CYCTRK WR Register 2.8.13 C0CYCTRKRD—Channel 0 CYCTRK READ Register B/D/F/Type : 0/0/0/ MCHBAR Address Offset: 256–257h Reset Value: 0000h Access: RW Bit A ttr Reset Value Description 15:12 RW 0h Activate To Write Delay (C0sd_cr_act_wr) This field indicates t[...]

Processor Configuration Registers 78 Datasheet, Volume 2 2.8.14 C0CYCTRKREFR—Channel 0 CYCTRK REFR Register This register provides Channel 0 CYCTRK R efresh control. 2.8.15 C0PWLRCTRL—Channel 0 Part ial Write Line Read Control Register This register configures the DRAM controller partial write policies. B/D/F/Type: 0/0/0/MCHBAR Address Offset: [...]

Datasheet, Volume 2 79 Processor Configuration Registers 2.8.16 C0REFRCTRL—Channel 0 DRAM Refresh Control Register This register provides settings to configure the DRAM refresh controller . B/D/F/Type : 0/0/0/ MCHBAR Address Offset: 269–26Eh Reset Value: 241830000C30h Access: RW, RO Bit A ttr Reset Value Description 47 RO 0b Reserved 46:44 RW 0[...]

Processor Configuration Registers 80 Datasheet, Volume 2 21:20 RW 00b DRAM Refresh Hysterisis (REFHYSTERISIS) Hysterisis level — useful for dref_high watermark cas es. The dref_high flag is set when the dr ef_high watermark level is exceeded, and is cleared when the refresh count is less than the h ysterisis leve l. This bit should be set to a v [...]

Datasheet, Volume 2 81 Processor Configuration Registers 2.8.17 C0JEDEC—Channel 0 JEDEC Control Register This is the Channel 0 JEDEC Control Register . B/D/F/Type : 0/0/0/ MCHBAR Address Offset: 271h Reset Value: 00h Access: RW, RO Bit A ttr Reset Value Description 7R W 0 b Functional Loopback Mode Enable (FLME) This configur ation setting indica[...]

Processor Configuration Registers 82 Datasheet, Volume 2 2.8.18 C0ODT—Channel 0 ODT Matrix Register This is an ODT related configur ation register . It is BIOS responsibility to program these bits to turn on/off the DRAM OD T signals according to how the system is populated; that is, 2r/2r , 2r/1r , 1r/2r , 1r/1r , 2r/nc, nc/2r , 1r/nc, nc/1r . T[...]

Datasheet, Volume 2 83 Processor Configuration Registers 9R W 0 b DODTRD0R1 (sd0_cr_rdrank0_r1odt) Assert ra nk1 ODT du ring Reads from RA NK0. 1 = ON 0 = OFF 8R W 0 b DODTRD0R0 (sd0_cr_rdrank0_r0odt) Assert ra nk0 ODT du ring Reads from RA NK0. 1 = ON 0 = OFF 7R W 0 b DODTWR1R3 (sd0_cr_wrrank1_r3odt) Assert rank3 OD T during Writes to RANK1. 1 = O[...]

Processor Configuration Registers 84 Datasheet, Volume 2 2.8.19 C0ODTCTRL—Channel 0 ODT Control Register 2.8.20 C0DTC—Channel 0 DRAM Throttling Control Register Programmable Event weights are input into the a veraging filter . Each Ev ent weight is an normalized 8 bit v alue that the BIOS must progr am. The BIOS must account for burst length an[...]

Datasheet, Volume 2 85 Processor Configuration Registers 2.8.21 C0RSTCTL—Channel 0 Reset Controls Register This register contains all the res e t controls for the DDR IO buffers. 18:16 RW-L 000b Time Constant (TC) 000 = 2^28 Clocks 001 = 2^29 Clocks 010 = 2^30 Clocks 011 = 2^31 Clocks Others = Re served 15:8 RW-L 00h Weighted Average Bandwidth Li[...]

Processor Configuration Registers 86 Datasheet, Volume 2 2.8.22 C1DRB0—Channel 1 DRAM Rank Boundary Address 0 Register The operation of this register is detailed in the description for register C0DRB0. 2.8.23 C1DRB1—Channel 1 DRAM Rank Boundary Address 1 Register The operation of this register is detailed in the description for register C0DRB0.[...]

Datasheet, Volume 2 87 Processor Configuration Registers 2.8.25 C1DRB3—Channel 1 DRAM Rank Boundary Address 3 Register The operation of this register is detaile d in the description for register C0DRB0. 2.8.26 C1DRA01—Channel 1 DRAM Rank 0,1 Attributes Register The operation of this register is detailed in the description for register C0DRA01. [...]

Processor Configuration Registers 88 Datasheet, Volume 2 2.8.28 C1WRDATACTRL—Channel 1 Write Data Control Register This register provides Channel 1 W rite Data Control. 2.8.29 C1CYCTRKPCHG—Channel 1 CYCTRK PCHG Register This register provides Channel 1 CYCTRK Precharge control. B/D/F/Type: 0/0/0/MCHBAR Address Offset: 64D–64Fh Reset Value: 00[...]

Datasheet, Volume 2 89 Processor Configuration Registers 2.8.30 C1CYCTRKACT—Channel 1 CYCTRK ACT Register This register provides Channel 1 CYCTRK ACT control. B/D/F/Type : 0/0/0/ MCHBAR Address Offset: 652–655h Reset Value: 0000_0000h Access: RW, RO Bit A ttr Reset Value Description 31:30 RO 0h Reserved 29 RW 0b FAW Window cnt Bug Fix Dis able [...]

Processor Configuration Registers 90 Datasheet, Volume 2 2.8.31 C1CYCTRKWR—Channel 1 CYCTRK WR Register This register provides Channel 1 CYCTRK WR control. 2.8.32 C1CYCTRKRD—Channel 1 CYCTRK READ Register This register is for Channel 1 CYCTRK READ control. B/D/F/Type: 0/0/0/MCHBAR Address Offset: 656–657h Reset Value: 0000h Access: RW Bit Att[...]

Datasheet, Volume 2 91 Processor Configuration Registers 2.8.33 C1CKECTRL—Channel 1 CKE Control Register This register provides Channel 1 CKE Control. B/D/F/Type : 0/0/0/ MCHBAR Address Offset: 660–663h Reset Value: 0000_0800h Access: RW, RW-L, RO Bit A ttr Reset Value Description 31:28 RO 0h Reserved 27 RW 0b start the self-refresh exit sequen[...]

Processor Configuration Registers 92 Datasheet, Volume 2 2.8.34 C1PWLRCTRL—Channel 1 Part ial Write Line Read Control Register This register is to configure the DRAM controller's partial write policies. 2.8.35 C1ODTCTRL—Channel 1 ODT Control Register This register provides ODT contro ls. B/D/F/Type: 0/0/0/MCHBAR Address Offset: 665–666h [...]

Datasheet, Volume 2 93 Processor Configuration Registers 2.8.36 C1DTC—Channel 1 DRAM Throttling Control Register Programmable Ev ent weights are input into the averaging filter . Each Event weight is an normalized 8 bit value that the BIOS must program. The BIOS must account for burst length and 1N/2N rule considerations. It is also possible for [...]

Processor Configuration Registers 94 Datasheet, Volume 2 2.8.37 SSKPD—Sticky Scra tchpad Data Re gister This register holds 64 writable bits with no functionality behind them. It is f or the convenience of BIOS and gr aphics drivers. 2.8.38 TSC1—Thermal Sens or Contro l 1 Register This register controls the operation of the internal thermal sen[...]

Datasheet, Volume 2 95 Processor Configuration Registers 2.8.39 TSS1—Thermal Sensor Status 1 R egister This read only register provides trip point and other status of the thermal sensor . 2.8.40 TR1—Thermometer Read 1 Register This register generally provides the unca libr ated counter value from the thermometer circuit when the Thermometer mod[...]

Processor Configuration Registers 96 Datasheet, Volume 2 2.8.41 TOF1—Thermometer Offset 1 Register This register is used for programming the thermometer offset. 2.8.42 RTR1—Relative Ther mometer Read 1 Re gister This register contains the relative temperature. B/D/F/Type: 0/0/0/MCHBAR Address Offset: 1007h Reset Value: 00h Access: RW Bit Attr R[...]

Datasheet, Volume 2 97 Processor Configuration Registers 2.8.43 TSTTPA1—Thermal Sensor Temperature Trip Point A1 Register This register sets the target values for so me of the trip points in thermometer mode. See also TST [Direct DAC Connect Test Enable]. This register also reports the relative thermal sensor te mperature. See also TSTTPB. B/D/F/[...]

Processor Configuration Registers 98 Datasheet, Volume 2 2.8.44 TSTTPB1—Thermal Sensor Temperature Trip Point B1 Register This register sets the target values for so me of the trip points in the Thermo meter mode. See also T STTPA1. 2.8.45 TS10BITMCTRL—Thermal Sensor 10-bit Mode Control Register B/D/F/Type: 0/0/0/MCHBAR Address Offset: 1014–1[...]

Datasheet, Volume 2 99 Processor Configuration Registers 2.8.46 HWTHROTCTRL1—Hardware Throttle Control 1 Register B/D/F/Type : 0/0/0/ MCHBAR Address Offset: 101Ch Reset Value: 00h Access: RW-L, RO, RW-O Bit A ttr Reset Value Description 7R W - L 0 b Internal Thermal Hardware Throttling Enable (ITHTE ) This bit is a master enable for inte rnal the[...]

Processor Configuration Registers 100 Datasheet, Volume 2 2.8.47 TIS1—Thermal Inte rrupt Status 1 Register This register is used to report which specific error condition resulted in the D2F0 or D2F1 ERRSTS[Thermal Sensor ev ent for SMI/SCI/SERR] or memory mapped IIR Thermal Event. Softw are can examine the current state of the thermal zones by ex[...]

Datasheet, Volume 2 101 Processor Configuration Registers 3R W 1 C 0 b Aux 3 Thermal Sensor Interrupt Event (A3TSIE) 1 = Aux 3 Thermal Sensor trip eve nt occurred based on a l ower to higher temperature trans ition through the trip point. 0 = No trip for this event. Software must write a 1 to clear this status bit . 2R W 1 C 0 b Aux 2 Thermal Senso[...]

Processor Configuration Registers 102 Datasheet, Volume 2 2.8.48 TERATE—Thermometer Mode Enable and Rate Register This common register helps select between the analog and the therm ometer mode and also helps select the DAC settling timer . B/D/F/Type: 0/0/0/MCHBAR Address Offset: 1070h Reset Value: 00h Access: RO, RW Bit Attr Reset Value Descript[...]

Datasheet, Volume 2 103 Processor Configuration Registers 2.8.49 TERRCMD—Ther mal Error Command Register This register select which errors are generate a SERR DMI interface special cycle, as enabled by ERRCMD [SERR Thermal Sensor event]. The SERR and SCI must not be enabled at the same time for the thermal sensor event. B/D/F/Type : 0/0/0/ MCHBAR[...]

Processor Configuration Registers 104 Datasheet, Volume 2 2.8.50 TSMICMD—Thermal SMI Command Register This register selects specific errors to gene r ate a SMI DMI cycle, as enabled by the SMI Error Command R egister[SMI on Thermal Sensor T rip]. B/D/F/Type: 0/0/0/MCHBAR Address Offset: 10E5h Reset Value: 00h Access: RO, RW Bit Attr Reset Value D[...]

Datasheet, Volume 2 105 Processor Configuration Registers 2.8.51 TSCICMD—Thermal SCI Command Register This register selects specific errors to gene rate a SCI DMI cycle, as enabled by the SCI Error Command R egister[SCI on Thermal Sens or T rip]. The SCI and SERR must not be enabled at the same time for the thermal sensor event. B/D/F/Type : 0/0/[...]

Processor Configuration Registers 106 Datasheet, Volume 2 2.8.52 TINTRCMD—Thermal INTR Command Regi ster This register selects specific errors to generate a INT DMI cycle. B/D/F/Type: 0/0/0/MCHBAR Address Offset: 10E7h Reset Value: 00h Access: RO, RW Bit Attr Reset Value Description 7:6 RO 00b Reserved 5R W 0 b INTR on Catastrophic Thermal Sensor[...]

Datasheet, Volume 2 107 Processor Configuration Registers 2.8.53 EXTTSCS—External Thermal Sensor Control and Status Register B/D/F/Type : 0/0/0/ MCHBAR Address Offset: 10EC–10EDh Reset Value: 0000h Access: RO, RW-O, RW-L Bit A ttr Reset Value Description 15 RW-O 0b External Sensor Enable (ESE) Setting this bit to 1 locks the lockable bi ts in t[...]

Processor Configuration Registers 108 Datasheet, Volume 2 6R W - L 0 b Throttling Type Select (TTS) Lockable by EXT TSCS [External Sensor Enable]. If E xternal Thermal Sensor Enable = 1, then 0 = DRAM throttling based on the settings in the Device 0 MCHBAR DRAM Throttling Control register 1 = processor throttling, base d on the settings in the Devi[...]

Datasheet, Volume 2 109 Processor Configuration Registers 2.8.54 DDRMPLL1—DDR PLL BIOS Register This register is for DDR PLL register progr amming. B/D/F/Type : 0/0/0/ MCHBAR Address Offset: 2C20–2C22h Reset Value: 00000Ch Access: RO, RW, RW-S Bit A ttr Reset Value Description 23:12 RO 00b Reserved 11 RW -S 0b Alternative VCO Select (VCOSEL) 0 [...]

Processor Configuration Registers 110 Datasheet, Volume 2 2.9 EPBAR Registers 2.9.1 EPPVCCAP1—EP Port VC Capability Reg ister 1 This register describes the configuration of PCI Express Virtual Ch annels associated with this port. 2.9.2 EPPVCCTL—EP Port VC Control Register B/D/F/Type: 0/0/0/PXPEPBAR Address Offset: 4–7h Reset Value: 0000_0001h[...]

Datasheet, Volume 2 111 Processor Configuration Registers 2.9.3 EPVC0RCTL—EP VC 0 Resource Control Reg ister This register controls the resources associated with Egress P ort Virtual Channel 0. B/D/F/Type : 0/0/0/ PXPEPBAR Address Offset: 14–17h Reset Value: 8000_00FFh Access: RO, RW Bit A ttr Reset Value Description 31 RO 1b VC0 Enable (VC0E) [...]

Processor Configuration Registers 112 Datasheet, Volume 2 2.9.4 EPVC0RCAP—EP VC 0 Reso urce Capability Register B/D/F/Type: 0/0/0/PXPEPBAR Address Offset: 10–13h Reset Value: 0000_0001h Access: RO Bit Attr Reset Value Description 31:24 RO 00h Reserved for Port Arbitrat ion T able Offset No VC0 port arbitr ation necessary . 23 RO 0b Reserved 22:[...]

Datasheet, Volume 2 113 Processor Configuration Registers 2.9.5 EPVC1RCTL—EP VC 1 Resource Control Reg ister This register controls the resources associated with PCI Express Virtual Channel 1. B B/D/F/Typ e: 0/0/0/PXPE PBAR Address Offset: 20–23h Reset Value: 0100_0000h Access: RW, RO Bit A ttr Reset Value Description 31 RW 0b VC1 Enable (VC1E)[...]

Processor Configuration Registers 114 Datasheet, Volume 2 2.9.6 EPVC1RSTS—EP VC 1 Resource Status Register B/D/F/Type: 0/0/0/PXPEPBAR Address Offset: 26–27h Reset Value: 0000h Access: RO Bit Attr Reset Value Description 15:2 RO 0000h Reserved and zero 1R O 0 b VC1 Negotiation Pending (VC1NP) 0 = The VC negotiat ion is complete. 1 = The VC resou[...]

Datasheet, Volume 2 115 Processor Configuration Registers 2.10 PCI Device 1 Registers Table 2-7. PCI Express* Devi ce 1 Register Address Map Address Offset Register Symbol Register Name Reset Value Access 0–1h VID1 V endor Identification 8086h RO 2–3h DID1 Device Identification 0041h RO 4–5h PCICMD1 PCI Command 0000h RO, RW 6–7h P CISTS1 PC[...]

Processor Configuration Registers 116 Datasheet, Volume 2 A8–A9h DCTL Device Control 0000h RO, RW AA– ABh DSTS Device Status 0000h RO, RW1C AC– AFh LCAP Link Capabilities 02214D02h RO, RW -O B0–B1h LCTL Link Control 0000h RO, RW , RW-SC B2–B3h LSTS Link Status 1000h RW1C, RO B4–B7h SLOT CAP Slot Capabilities 00040000h RW-O , RO B8–B9h[...]

Datasheet, Volume 2 117 Processor Configuration Registers 2.10.1 VID1—Vendor Identification Register This register combined with the Device Identification regi ster uniquely identify any PCI device. 2.10.2 DID1—Device Identification Register This register combined with the V endor Identification register uniquely identifies any PCI device. 2.10[...]

Processor Configuration Registers 118 Datasheet, Volume 2 8R W 0 b SERR# Message Enable (SERRE1) This bit controls De vice 1 SERR# messaging. The processo r communicates the SERR# condition by sending an SERR message to the PCH. This bit, when set, enables reporting of non-fatal and fa tal errors detected by the device to the R oot Comple x. Note t[...]

Datasheet, Volume 2 119 Processor Configuration Registers 2.10.4 PCISTS1—PCI Status Register This register reports the occurrence of error conditions associated with primary side of the "virtual" Host-PCI Express brid ge embedded within the processor . B/D/F/Type : 0/1/0/ PCI Address Offset: 6–7h Reset Value: 0010h Access: RO, RW1C Bi[...]

Processor Configuration Registers 120 Datasheet, Volume 2 2.10.5 RID1—Revision Id entification Register This register contains the revision number of the processor device 1. These bits are read only and writes to this register hav e no effect. This register contains the revision number of the processor . The Re vision ID (RID) is a traditional 8-[...]

Datasheet, Volume 2 121 Processor Configuration Registers 2.10.7 CL1—Cache Li ne Size Regi ster 2.10.8 HDR1—Header Type Register This registe r identifies the header la yout of the config uration space. No physical register exists at this location. 2.10.9 PBUSN1—Primary Bus Number Register This register identifies that this "virtual"[...]

Processor Configuration Registers 122 Datasheet, Volume 2 2.10.10 SBUSN1—Secondary Bus Number Register This register identifies the bus number assigned to the second bus side of the "virtual" bridge (that is, to PCI Express-G). This number is programmed by the PCI configur ation software to allow mapping of configur ation cycles to PCI [...]

Datasheet, Volume 2 123 Processor Configuration Registers 2.10.12 IOBASE1—I/O Ba se Address Register This register controls the processor to PCI Express-G I/O access routing based on th e following formula: IO_BASE  address  IO_LIMIT Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are treated [...]

Processor Configuration Registers 124 Datasheet, Volume 2 2.10.14 SSTS1—Secondary Status Register SSTS1 is a 16-bit status register that reports the occurrence of error con ditions associated with secondary side (that is, PC I Express-G side) of the "virtual" PCI-PCI bridge embedded within processor . B/D/F/Type: 0/1/0/PCI Address Offse[...]

Datasheet, Volume 2 125 Processor Configuration Registers 2.10.15 MBASE1—Mem ory Base Address Register This register controls the processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE  address  MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12[...]

Processor Configuration Registers 126 Datasheet, Volume 2 2.10.16 MLIMIT1—Memory Limit Address Register This register controls the processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE  address  MEMORY_LIMIT The upper 12 bits of the register are re ad/write and correspond to the upper [...]

Datasheet, Volume 2 127 Processor Configuration Registers 2.10.17 PMBASE1 —Prefetchable Memory Base Address Regi ster This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express-G pr efetchable memory access routing based on the following formula: PREFETCH ABLE_MEMOR Y_BASE  address [...]

Processor Configuration Registers 128 Datasheet, Volume 2 2.10.18 PMLIMIT1—Prefetchable Me mory Limit Address Register This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express-G prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE  address  [...]

Datasheet, Volume 2 129 Processor Configuration Registers 2.10.20 PMLIMITU1—Prefetchable Memory Limit Address Upper Register The functionality associated with this register is present in the PEG design implementation. This register in conjunction with the correspon ding Upper Limit Address register controls the processor to PCI Express-G pr efetc[...]

Processor Configuration Registers 130 Datasheet, Volume 2 2.10.22 INTRLINE1—Interrupt Line Register This register contains interrupt line routing information. The device itself does not use this value, r ather it is used by device drivers and oper ating systems to determine priority and vector information. 2.10.23 INTRPIN1—Inte rrupt Pi n Regis[...]

Datasheet, Volume 2 131 Processor Configuration Registers 2.10.24 BCTRL1—Bridge Control Register This register provides extensions to the PC ICMD1 register that are specific to PCI-PCI bridges. The BCTRL provides additional cont rol for the secondary interface (that is, PCI Express-G) as well as some bits that affect the over all behavior of the [...]

Processor Configuration Registers 132 Datasheet, Volume 2 2.10.25 MSAC—Multi Size Ap erture Control Register This register determines the size of the gr aphics memory aperture in function 0 and in the trusted space. Only the system BIOS w ill write this register based on pre- boot address allocation efforts, but the gr aphics may read this regist[...]

Datasheet, Volume 2 133 Processor Configuration Registers 2.10.26 PM_CAPID1—Power Manage ment Capabilities Register B/D/F/Type: 0/1/0/PCI Address Offset: 80–83h Reset Value: C8039001h Access: RO Bit A ttr Reset Value Description 31:27 RO 19h PME Suppo rt (PMES) This field indicates the po wer states in which this device may indicate PME wake us[...]

Processor Configuration Registers 134 Datasheet, Volume 2 2.10.27 PM_CS1—Power Manageme nt Control/Stat us Register B/D/F/Type: 0/1/0/PCI Address Offset: 84–87h Reset Value: 0000_0008h Access: RO, RW-S, RW Bit Attr Reset Value Description 31:16 RO 0000h Reserved Not Applicable or Impleme nted. Hardwired to 0. 15 RO 0b PME Status (PMEST S) Indic[...]

Datasheet, Volume 2 135 Processor Configuration Registers 2.10.28 SS_CAPID—Subsystem ID and Vendor ID Capabilities Register This capability is used to uniquely identify the subsystem where the PCI device resides. Because this device is an integrated part of the system and not an add-in device, it is anticipated that this capability will never be [...]

Processor Configuration Registers 136 Datasheet, Volume 2 2.10.30 MSI_CAPID—Message Signal ed Interrupts Capability ID Register When a device supports MSI, it can generate an interrupt request to the processor by writing a predefined data item (a message) to a predefined memory address. The reporting of the existence of this ca pability can be di[...]

Datasheet, Volume 2 137 Processor Configuration Registers 2.10.31 MC—Message Control Register System softw are can modify bits in this register , but the device is prohibited from doing so. If the device writes the same message mult iple times, only one of those messages is ensured to be serviced. If all of them must be serviced, th e device must[...]

Processor Configuration Registers 138 Datasheet, Volume 2 2.10.32 MA—Message Address Register 2.10.33 MD—Message Data Register 2.10.34 PEG_CAPL—PCI Express- G Capability List Register This register enumerates the PCI Express capability structure. B/D/F/Type : 0/1/0/ PCI Address Offset: 94–97h Reset Value: 0000_0000h Access: RW, RO Bit Attr [...]

Datasheet, Volume 2 139 Processor Configuration Registers 2.10.35 PEG_CAP—PCI Express-G Capabilities Register This register indicates PCI Express device capabilities. 2.10.36 DCAP—Device Capabilities Register This register indicates PCI Express device capabilities. B/D/F/Type : 0/1/0/ PCI Address Offset: A2–A3h Reset Value: 0142h Access: RO, [...]

Processor Configuration Registers 140 Datasheet, Volume 2 2.10.37 DCTL—Device Control Register This register provides control for PCI Express device specific capabilities. The error reporting enable bits are in refere nce to errors detected by this device, not error messages received across the link. Th e reporting of error messages (ERR_CORR, ER[...]

Datasheet, Volume 2 141 Processor Configuration Registers 2.10.38 DSTS—Device Status Register This register reflects status corresponding to controls in the Device Control register . The error reporting bits are in reference to errors detected by this device, not errors messages received across the link. B/D/F/Type : 0/1/0/ PCI Address Offset: AA[...]

Processor Configuration Registers 142 Datasheet, Volume 2 2.10.39 LCAP—Link Capa bilities Register This register indicates PCI Express device specific capabilities. B/D/F/Type: 0/1/0/PCI Address Offset: AC–AFh Reset Value: 02214D02h Access: RO, RW-O Bit Attr Reset Value Description 31:24 RO 02h Port Number (PN) This bit indicates the PCI Expres[...]

Datasheet, Volume 2 143 Processor Configuration Registers 14:12 RO 100b L0s Exit Latency (L0SELAT) This field indicates the length of time this P ort requires to complete the transition from L0s to L0. 000 = Less than 64 ns 001 = 64ns to less than 128ns 010 = 128ns to less than 256 ns 011 = 256ns to less than 512ns 100 = 512ns to less than 1us 101 [...]

Processor Configuration Registers 144 Datasheet, Volume 2 2.10.40 CTL—Link Control Register This register allows control of PCI Express link. B/D/F/Type: 0/1/0/PCI Address Offset: B0–B1h Reset Value: 0000h Access: RO, RW, RW-SC Bit Attr Reset Value Description 15:12 RO 0000b Reserved 11 RW 0b Link Autonomous Bandwidth Interrupt Enable (LABIE) L[...]

Datasheet, Volume 2 145 Processor Configuration Registers 5R W - S C 0 b Retrain Link (RL) 0 = Normal operation. 1 = Full Link retraining is initiated by directing the Ph ysical Layer L TS SM from L0, L0s, or L1 states to the R ecovery state. This bit always returns 0 when read. This bit is cleared automatically (no need to write a 0). 4R W 0 b Lin[...]

Processor Configuration Registers 146 Datasheet, Volume 2 2.10.41 LSTS—Link Status Register This register indicates PCI Express link status. B/D/F/Type: 0/1/0/PCI Address Offset: B2–B3h Reset Value: 1000h Access: RW1C, RO Bit Attr Reset Value Description 15 RW1C 0b Link Autonomous Bandwidth Status (LABWS) This bit is set to 1b by hardware to in[...]

Datasheet, Volume 2 147 Processor Configuration Registers 9:4 RO 00h Negotiated Link Width (NLW) This field indicate s negotiated link widt h. This field is valid only when the link is in the L0, L0s, or L1 states (after link width negotiation is successfully completed). 00h = Reserved 01h = X1 02h = X2 04h = X4 08h = X8 10h = X16 All other encodin[...]

Processor Configuration Registers 148 Datasheet, Volume 2 2.10.42 SLOTCAP—Slot Capabilities Register Note: Hot Plug is not supported on the platform. B/D/F/Type: 0/1/0/PCI Address Offset: B4–B7h Reset Value: 00040000h Access: RW-O, RO Bit Attr Reset Value Description 31:19 RW-O 0000h Physical Slot Number (PSN) Indicates the physical slot number[...]

Datasheet, Volume 2 149 Processor Configuration Registers 2.10.43 SLOTCTL—Slot Control Register Note: Hot Plug is not supported on the platform. B/D/F/Type : 0/1/0/ PCI Address Offset: B8–B9h Reset Value: 0000h Access: RO, RW Bit A ttr Reset Value Description 15:13 RO 000b Res erved 12 RO 0b Reserved for Data Link Layer State Changed Enable (D [...]

Processor Configuration Registers 150 Datasheet, Volume 2 7:6 RO 00b Reserved for Attention Indicator Control (AIC) If an Attention Indicator i s implemented, writes to this field set the Attention Indicator to the written state. R eads of this field must reflect the value from the late st write, even if t he co rresp onding hot -plug command is no[...]

Datasheet, Volume 2 151 Processor Configuration Registers 2.10.44 SLOTSTS—Slot Status Register Note: Hot Plug is not supported on the platform. B/D/F/Type : 0/1/0/ PCI Address Offset: BA– BBh Reset Value: 0000h Access: RO, RW1C Bit A ttr Reset Value Description 15:9 RO 0000000b Reserved and Zero: R eserved for future R/WC/S implementati ons; so[...]

Processor Configuration Registers 152 Datasheet, Volume 2 2R O 0 b Reserved for MRL Sensor Changed (MSC) If an MRL sensor is implemented, this bit is set when a MRL Sensor state c h a ng e i s d e t e c t e d . I f a n M R L s e n s o r i s not implemented, this bit must not be set. 1R O 0 b Reserved for Power Fault Detected (PFD) If a Power Contro[...]

Datasheet, Volume 2 153 Processor Configuration Registers 2.10.45 R CTL—Root Control Regi ster Allows control of PCI Express R oot Comple x specific parameters. The system error control bits in this register determine if corresponding SERRs are gener ated when our device detects an error (reported in this device's Device Status register) or [...]

Processor Configuration Registers 154 Datasheet, Volume 2 2.10.46 RSTS—Root Status Register This register provides information about PCI Express R oot Complex specific parameters. 2.10.47 LCTL2—Link Control 2 Register B/D/F/Type: 0/1/0/PCI Address Offset: C0–C3h Reset Value: 0000_0000h Access: RO, RW1C Bit Attr Reset Value Description 31:18 R[...]

Datasheet, Volume 2 155 Processor Configuration Registers 2.10.48 LSTS2—Link Status 2 Register 2.10.49 PEGLC—PCI Express* Legacy Control Register This register controls functionality that is needed by Legacy (non-PCI Express aware) OS's during run time. B/D/F/Type : 0/1/0/ PCI Address Offset: D2–D 3h Reset Value: 0000h Access: RO Bit A t[...]

Processor Configuration Registers 156 Datasheet, Volume 2 2.11 Device 1 Extended Configuration Registers 2.11.1 PVCCAP1—Port VC Capability Register 1 This register describes the configuration of PCI Express Virtual Ch annels associated with this port. Table 2-8. Device 1 Extended Configuration Register Address Map Address Offset Register Symbol R[...]

Datasheet, Volume 2 157 Processor Configuration Registers 2.11.2 PVCCAP2—Port VC Capability Register 2 This register describes the configuration of PCI Express Virtual Channels associated with this port. 2.11.3 PVCCTL—Port VC Control Register B/D/F/Type : 0/1/0/ MMR Address Offset: 108–10Bh Reset Value: 0000_0000h Access: RO Bit A ttr Reset V[...]

Processor Configuration Registers 158 Datasheet, Volume 2 2.11.4 VC0RCAP—VC0 Resour ce Capability Register 2.11.5 VC0RCTL—VC0 Reso urce Control Register This register controls the resources associated with PCI Express Virtual Channel 0. B/D/F/Type: 0/1/0/MMR Address Offset: 110–113h Reset Value: 0000_0001h Access: RO Bit Attr Reset Value Desc[...]

Datasheet, Volume 2 159 Processor Configuration Registers 2.11.6 VC0RSTS—VC0 Reso urce Status Registe r This register reports the Virtual Channe l specific status. 15:8 RO 00h Reserved 7:1 RW 7Fh TC/VC0 Map (TCVC0M) This field indicates the TCs (T raffic Classes) that are mapped to the VC resource. Bit location s within this field co rrespond to [...]

Processor Configuration Registers 160 Datasheet, Volume 2 2.11.7 PEG_TC—PCI Express Co mpletion Timeout Register This register reports PCI Express configur ation control of PCI Express Completion Timeout related parameters that are not re quired by the PCI Express specificaiton. B/D/F/Type: 0/1/0/MMR Address Offset: 204h Reset Value: 0000_0C00h A[...]

Datasheet, Volume 2 161 Processor Configuration Registers 2.12 DMIBAR Registers 2.12.1 DMIVCECH—DMI Virtual Ch annel Enhanced Capability Register This register indicates DMI Virtual Channel capabilities. Table 2-9. DMI Register Address Map Offset Address Register Symbol Register Name Reset Value Access 0–3h DMIVCECH DMI Virtual Channel Enhanced[...]

Processor Configuration Registers 162 Datasheet, Volume 2 2.12.2 DMIPVCCAP1—DMI Port VC Capability Register 1 Describes the configuration of PCI Express Virtual Channels associated with this port. 2.12.3 DMIPVCCAP2—DMI Port VC Capability Register 2 This register describes the configuration of PCI Express Virtual Ch annels associated with this p[...]

Datasheet, Volume 2 163 Processor Configuration Registers 2.12.4 DMIPVCCTL—DMI Port VC Control Register 2.12.5 DMIVC0RCAP—DMI VC0 Re source Capability Register B/D/F/Type : 0/0/0/ DMIBAR Address Offset: C–Dh Reset Value: 0000h Access: RO, RW Bit A ttr Reset Value Description 15:4 RO 000h Reserved 3:1 RW 000b VC Arbitration Select (VCAS) This [...]

Processor Configuration Registers 164 Datasheet, Volume 2 2.12.6 DMIVC0RCTL0—DMI VC0 Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 0. B/D/F/Type: 0/0/0/DMIBAR Address Offset: 14–17h Reset Value: 8000_00FFh Access: RW, RO Bit Attr Reset Value Description 31 RO 1b Virtual Channel 0 Enab[...]

Datasheet, Volume 2 165 Processor Configuration Registers 2.12.7 DMIVC0RSTS—DMI VC0 Resour ce Status Register This register reports the Virtual Channe l specific status. 2.12.8 DMIVC1RCAP—DMI VC1 Re source Capability Register B/D/F/Type : 0/0/0/ DMIBAR Address Offset: 1A– 1Bh Reset Value: 0002h Access: RO Bit A ttr Reset Value Description 15:[...]

Processor Configuration Registers 166 Datasheet, Volume 2 2.12.9 DMIVC1RCTL1—DMI VC1 Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 1. B/D/F/Type: 0/0/0/DMIBAR Address Offset: 20–23h Reset Value: 0100_0000h Access: RO, RW Bit Attr Reset Value Description 31 RW 0b Virtual Channel Enable[...]

Datasheet, Volume 2 167 Processor Configuration Registers 2.12.10 DMIVC1RSTS—DMI VC1 Resou rce Status Register This register reports the Virtual Channe l specific status. B/D/F/Type : 0/0/0/ DMIBAR Address Offset: 26–27h Reset Value: 0002h Access: RO Bit A ttr Reset Value Description 15:2 RO 0000h Res erved 1R O 1 b Virtual Channel 1 Negotiatio[...]

Processor Configuration Registers 168 Datasheet, Volume 2 2.12.11 DMIVCPRCTL—DMI VCp Reso urce Control Register This register controls the resources associated with the DMI Priv ate Channel. B/D/F/Type: 0/0/0/DMIBAR Address Offset: 2C–2Fh Reset Value: 0000_0000h Access: RW, RO Bit Attr Reset Value Description 31 RW 0b Virtual Channel Enable (VC[...]

Datasheet, Volume 2 169 Processor Configuration Registers 2.12.12 DMIVCPRSTS—DMI VCp Resource Status Register This register reports the Virtual Channe l specific status. 2.12.13 DMIESD—DMI Element Self Description Register This register provides information about the root complex element contai ning this Link Declaration Capability . B/D/F/Type[...]

Processor Configuration Registers 170 Datasheet, Volume 2 2.12.14 DMILE1D—DMI Link En try 1 Description Register This register provides the first part of a Li nk Entry which declares an internal link to another R oot Complex Element. 2.12.15 DMILE1A—DMI Link Entry 1 Address Register This field provides th e second part of a Li nk Entry which de[...]

Datasheet, Volume 2 171 Processor Configuration Registers 2.12.16 DMILE2D—DMI Link En try 2 Description Register This register provides the first part of a Link Entry which declares an internal link to another R oot Complex E lement. 2.12.17 DMILE2A—DMI Link Entry 2 Address Register This register provides the second part of a Link Entry which d[...]

Processor Configuration Registers 172 Datasheet, Volume 2 2.12.18 DMILCAP—DMI Link Capabilities Register This field indicates DMI specific capabilities. B/D/F/Type: 0/0/0/DMIBAR Address Offset: 84–87h Reset Value: 00012C41h Access: RO, RW-O Bit Attr Reset Value Description 31:18 RO 0000h Reserved 17:15 RW-O 010b L1 Exit Latency (L1SELAT) This f[...]

Datasheet, Volume 2 173 Processor Configuration Registers 2.12.19 DMILCTL—DMI Link Control Register This register allows control of DMI. 2.12.20 DMILSTS—DMI Link Status Register B/D/F/Type : 0/0/0/ DMIBAR Address Offset: 88–89h Reset Value: 0000h Access: RO, RW Bit A ttr Reset Value Description 15:8 RO 00h Reserved 7R W 0 b Extended Synch (EX[...]

Processor Configuration Registers 174 Datasheet, Volume 2 2.13 PCI Device 2, F unction 0 Registers 2.13.1 VID2—Vendor Iden tification Register This register combined with the Device Identification register uniquely identifies any PCI device. Table 2-10. PCI (Device 2, Fun c tion 0) Register Address Map Address Offset Register Symbol Register Name[...]

Datasheet, Volume 2 175 Processor Configuration Registers 2.13.2 DID2—Device Identification Register This register combined with the V endor Identification register uniquely identifies any PCI device. 2.13.3 PCICMD2—PCI Command Register This 16-bit register provides basic control over the IGD ability to respond to PCI cycles. The PCICMD R egist[...]

Processor Configuration Registers 176 Datasheet, Volume 2 2.13.4 PCISTS2—PCI Status Register PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and PCI compliant target abort. PCISTS also indicates the DEVSEL# ti mi ng that has been set by the IGD . B/D/F/Type: 0/2/0/PCI Address Offset: 6–7h Reset Val[...]

Datasheet, Volume 2 177 Processor Configuration Registers 2.13.5 RID2—Revision Identification Register This register contains the revision number for Dev ice 2, Functions 0 and 1. This register contains the revision num ber of the processor . The R evision ID (RID) is a traditional 8-bit R ead Only (RO) register located at offset 08h in the stand[...]

Processor Configuration Registers 178 Datasheet, Volume 2 2.13.7 CLS—Cache Line Size Register The IGD does not support this register as a PCI slave. 2.13.8 MLT2—Master La tency Ti mer Register The IGD does not support the progr ammability of the master latency timer because it does not perform bursts. 2.13.9 HDR2—Header Type Register This reg[...]

Datasheet, Volume 2 179 Processor Configuration Registers 2.13.10 GTTMMADR—Graphics Transl ation Table, Memory Mapped Range Address Register This register requests allocation for the combined Gr aphics T ranslation T able Modification Range and Memory Mapped R ange. The range requires 4 MB combined for MMIO and Global GT T aperture, with 512K of [...]

Processor Configuration Registers 180 Datasheet, Volume 2 2.13.11 GMADR—Graphics Memo ry Range Address Register The IGD graphics memory base addre ss is specified in this re gister . Software must not change the value in MS AC[1:0] (offset 62h) after writing to the GMADR register . B/D/F/Type: 0/2/0/PCI Address Offset: 18–1Fh Reset Value: 0000_[...]

Datasheet, Volume 2 181 Processor Configuration Registers 2.13.12 IOBAR—I/O Base Address Register This register provides the Base offset of the I/O registers within Device 2. Bits 15:3 are programmable allowing the I/O Base to be located anywhere in 16bit I/O Address Space. Bits 2:1 are fixed and return zero , bit 0 is hardwired to a one indicati[...]

Processor Configuration Registers 182 Datasheet, Volume 2 2.13.14 SID2—Subsystem Identification Register 2.13.15 ROMADR—Video BIOS ROM Base Address Regist er The IGD doe s not use a separ ate BIOS ROM, therefore this registe r is hardwi red to 0s. 2.13.16 INTRPIN—Inte rrupt Pin Register B/D/F/Type: 0/2/0/PCI Address Offset: 2E–2Fh Reset Val[...]

Datasheet, Volume 2 183 Processor Configuration Registers 2.13.17 MINGNT—Minimum Grant Register 2.13.18 M AXLAT—Maximu m Latency Register 2.14 Device 2 I/O Registers B/D/F/Type : 0/2/0/ PCI Address Offset: 3Eh Reset Value: 00h Access: RO Bit A ttr Reset Value Description 7:0 RO 00h Minimum Grant Value (MGV) The IGD does not burst as a PCI compl[...]

Processor Configuration Registers 184 Datasheet, Volume 2 2.14.1 Index—MMIO Address Register A 32 bit I/O write to this port loads the offset of the MMIO register or offset into the GT T that needs to be accessed. An I/O R ead returns the current value of this register . An 8/16 bit I/O write to this register is completed by the processor but doe[...]

Datasheet, Volume 2 185 Processor Configuration Registers 2.15 DMI and PEG VC0/VCp Remap Registers Table 2-11. MMI and PEG VC0/VCp Remap Register Address Map (Sheet 1 of 2) Address Offset Register Symbol Register Name Reset Value Access 0–3h VER_REG V ersion 0000_0010h RO 8–Fh CAP_REG Capability 00C90080206302 72h RO 10–17h ECAP_REG Extended [...]

Processor Configuration Registers 186 Datasheet, Volume 2 2.15.1 VER_REG—Version Register This register reports the architecture vers ion supported. Backw ard compatibility for the architecture is maintained with new revisi on numbers, allowing softw are to load DMA - remapping drivers written for prior architecture versions. 200–20Fh FRCD_REG [...]

Datasheet, Volume 2 187 Processor Configuration Registers 2.15.2 CAP_REG—Capability Register This register reports gener al DMA remapping hardware capabilities. B/D/F/Type : 0/0/0/ VC0PREMAP Address Offset: 8–Fh Reset Value: 00C9008020630272h Access: RO Bit A ttr Reset Value Description 63:56 RO 00h Reserved 55 RO 1b DMA Read Draining ( DRD) 0 [...]

Processor Configuration Registers 188 Datasheet, Volume 2 23 RO 0b Isochrony (Isoch) 0 = Indicates this DMA-remapping hard ware unit has no critical isoc hronous requesters in its scope. 1 = Indicates this DMA-re mapping hardware unit has one or more critical isochronous reque sters in its scope. T o ensure isochronous performance, software must en[...]

Datasheet, Volume 2 189 Processor Configuration Registers 6R O 1 b Protected High-Memory Region (PHMR) 0 = Indicates protected hig h-memory region not supp orted. 1 = Indicate s protected high -memory re gion is suppor ted. DMA-remapp ing hardware implementat ions on Intel TXT platforms supporting main memory abo ve 4 GB are required to support pro[...]

Processor Configuration Registers 190 Datasheet, Volume 2 2.15.3 ECAP_REG—Extended Capability Register This register reports DMA-remapping hardw are extended capabilities. B/D/F/Type: 0/0/0/VC0PREMAP Address Offset: 10–17h Reset Value: 0000000000001000h Access: RO Bit Attr Reset Value Description 63:32 RO 00000000 h Reserved 31:24 RO 00h Number[...]

Datasheet, Volume 2 191 Processor Configuration Registers 2.15.4 GCMD_REG—Global Command Register This register controls DMA-remapping hardw are. If multiple control fields in this register need to be modified, software must serialize through multiple writes to this register . 2R O 0 b Device IOTLB Sup port (DI) 0 = Hardware does not support devi[...]

Processor Configuration Registers 192 Datasheet, Volume 2 30 WO 0b Set Root Table Pointer (SRTP) Software sets this field to set/update the root -entry table pointer used by hardware. The root-entr y table pointer is sp ecified through the Root -entry T able Address regi ster . Hardware reports the statu s of the root t able point er set operation [...]

Datasheet, Volume 2 193 Processor Configuration Registers 26 W 0b Queued Invalidation Enable (QIE) This field is valid only for implementa tions supporting queued inv alidations. Software writes to this field to en able or disable queued in validations. 0 = Disable queued invalidations. 1 = Enable use of queued in validation s. Hardware repo rts th[...]

Processor Configuration Registers 194 Datasheet, Volume 2 2.15.5 GSTS_REG—Global Status Register This register reports general DMA -remapping hardware status. B/D/F/Type: 0/0/0/VC0PREMAP Address Offset: 1C–1Fh Reset Value: 00000000h Access: RO Bit Attr Reset Value Description 31 RO 0b Translation Enable Status (TES) This field indicates the sta[...]

Datasheet, Volume 2 195 Processor Configuration Registers 2.15.6 RTADDR_REG—Roo t-Entry Table Address Register This register provides the base address of root-entry table. 23 RO 0b Compatibility Format Interrupt Status (CFIS) This field indicates the status of Compatibility fo rmat interrupts on Intel 64 implementations support ing interrupt -rem[...]

Processor Configuration Registers 196 Datasheet, Volume 2 2.15.7 CCMD_REG—Contex t Command Register Register to manage context cache. The ac t of writing the uppermost byte of the CCMD_REG with ICC field set causes the hardware to perform the context-cache invalidation. B/D/F/Type: 0/0/0/VC0PREMAP Address Offset: 28–2Fh Reset Value: 00000000000[...]

Datasheet, Volume 2 197 Processor Configuration Registers 60:59 RO 0h Context Actual Invalidation Granularity (CAIG) Hardware reports the g ranularity at wh ich an inval idation request was processed throu gh the CAIG field at the time of repo rting invalidation completion (by clearing th e ICC field). The following are the encodings for the CAIG f[...]

Processor Configuration Registers 198 Datasheet, Volume 2 2.15.8 FSTS_REG—Fault Status Register This register indicates the primary fault lo gging status. The VTd specification describes hardware behavior for primary fault logging. B/D/F/Type : 0/0/0/ VC0PREMAP Address Offset: 34–37h Reset Value: 00000000h Access: RO, RO-V-S, RW1C-S Bit Attr Re[...]

Datasheet, Volume 2 199 Processor Configuration Registers 2.15.9 FECTL_REG—Fault Event Cont rol Register This register specifies the fault event interrupt message contro l bits. The VTd specification describes hardware handling of fault events. B/D/F/Type : 0/0/0/ VC0PREMAP Address Offset: 38–3Bh Reset Value: 80000000h Access: RW, RO Bit A ttr [...]

Processor Configuration Registers 200 Datasheet, Volume 2 2.15.10 FEDATA_REG—Fault Event Data Register This register specifies the interrupt message data. 2.15.11 FEADDR_REG—Fault Event Address Register This register specifies the interrupt message address. 2.15.12 FEUADDR_REG—Fault Ev ent Upper Address Register This register specifies the in[...]

Datasheet, Volume 2 201 Processor Configuration Registers 2.15.13 AFLOG_REG—Advan ced Fault Log Register This register specifies the base addre ss of memory -resident fault-log region. This register is treated as read-only (0) for implementations not supporting adva nced translation fault logging (AFL field reported as 0 in the Capability registe[...]

Processor Configuration Registers 202 Datasheet, Volume 2 2.15.14 PMEM_REG—Protected Memory Enable Register This register enables the DMA protected me mory regions setup through the PLMBASE , PLMLIMT , PHMBAS E, PHMLIMIT register s. When L T .CMD.LOC K.PMRC command is invoked, this register is locked (treated RO). When L T .CMD.UNLOCK.PMRC comman[...]

Datasheet, Volume 2 203 Processor Configuration Registers 2.15.15 PLMBASE_REG—Protected Low-Memory Base Register This register is used to setup the base address of DMA protected low-memory region. The register must be setup before enablin g protected memory through PM EN_REG, and must not be updated when protected memory regions are enabled. When[...]

Processor Configuration Registers 204 Datasheet, Volume 2 2.15.16 PLMLIMIT_REG—Protected Low-Memory Limit Register Register to setup the limit address of DMA protected low-memory region. This register must be setup before enabling protected me mory through PMEN_REG, and must not be updated when protected memory regions are en abled. When L T .CMD[...]

Datasheet, Volume 2 205 Processor Configuration Registers 2.15.17 PHMBASE_REG—Protected High-Memory Base Register This register is used to setup the base address of DMA protected high-memory region. This register must be setup before en abling protected memory through PMEN_REG , and must not be updated when protecte d memory regions are enabled. [...]

Processor Configuration Registers 206 Datasheet, Volume 2 2.15.18 PHMLIMIT_REG—Protected High-Memory Limit Register Register to setup the limit address of DMA protected high-memory region. This re gister must be setup before enabling protected me mory through PMEN_REG, and must not be updated when protected memory regions are en abled. When L T .[...]

Datasheet, Volume 2 207 Processor Configuration Registers 2.15.20 IQT_REG—Invalidation Queue Tail Regist er R egister indicating the inv alidation tail head. This register is treated as reserved by implementations reporting Queued Inv alidatio n (QI) as not supported in the Extended Capability register . 2.15.21 IQA_REG—Invalidation Queue Addre[...]

Processor Configuration Registers 208 Datasheet, Volume 2 2.15.22 ICS_REG—Invalidation Completion Status Register This register reports the completion status of inv alidation wait descriptor with Interrupt Flag (IF) Set. This register is treated as reserved by implementations reporting Queued Invalidation (QI) as not supported in the Extended Cap[...]

Datasheet, Volume 2 209 Processor Configuration Registers 2.15.24 IEDATA_REG—Invalidat ion Event Data Register R egister specifying the Inv alidation Event interrupt message data. This register is treated as reserved by implementations r e porting Queued Inv alidation (QI) as not supported in the Extended Capability register . 2.15.25 IEADDR_ REG[...]

Processor Configuration Registers 210 Datasheet, Volume 2 2.15.26 IEUADDR_REG—I nvalidation Event Upper Address Register This register specifies the Invalidation Ev ent interrupt message upper address. This register is treated as reserved by implem entations reporting both Queued Inv alidation (QI) and Extended Interrupt Mode (EIM) as not support[...]

Datasheet, Volume 2 211 Processor Configuration Registers 2.15.28 IVA_REG—Invalidate Addr ess Register This register provides the DMA address whose corresponding IOTLB entry needs to be inv alidated through the corresponding IOTLB In validate register . This register is a write-only register . V alue returned on reads of this register is undefine[...]

Processor Configuration Registers 212 Datasheet, Volume 2 2.15.29 IOTLB_REG—IOTLB Invalidate Register Register to control page-table entry caching. The act of writing the upper byte of the IOTLB_REG with IVT field set causes the hardw are to perform the IO TLB invalidation. There is an IOTLB_REG for each IO TLB Invalidation unit supported by hard[...]

Datasheet, Volume 2 213 Processor Configuration Registers 59:57 RO 0h IOTLB Actual Invalidation Granularity (IAIG) Hardware reports the gr anularity at which an in validation r equest was processed throug h this field at the time of reporting in validation completion (by cleari ng the IVT fiel d). The following are the encodings for the IAIG field.[...]

Processor Configuration Registers 214 Datasheet, Volume 2 2.15.30 FRCD_REG—Fault Recording Registers This registers records DMA-remapping fault information when primary fault logging is active. Hardware reports the number and loca tion of fault recording registers through the Capability register . This register is relevant only for primary fault [...]

Datasheet, Volume 2 215 Processor Configuration Registers 2.15.31 VTCMPLRESR—VT Completion Resourc e Dedication This register provides a programmable in terface to dedicate the DMI Completion T racking Queue resources to DMI VC0 Read, DMI VC0 W rite, DMI VC1 and DMI VCp VT fetch and PEG Completion T r acking Queue resources to PEG VC 0 read and P[...]

Processor Configuration Registers 216 Datasheet, Volume 2 2.15.32 VTFTCHARBCTL—VC0/VCp VTd Fetch Arbiter Control This register controls the relative grant co unt given to each of the DMI VC0, DMI VC1, and PEG VC0 VT fetch requests. 3:0 RW- L 0h DMI VC0 Read VT Completion Tracking Queue Resource Threshold (DMIVC0RDCTQRT) This field provides a 1-ba[...]

Datasheet, Volume 2 217 Processor Configuration Registers 2.15.33 PEGVTCMPLRESR—PEG VT Completion Resource Dedication This register provides a programmable in terface to dedicate the PEG0 and PEG1 Completion T racking Queue resources to PEG0 VC0 read, PEG0 VC0 write, PEG1 VC0 read and PEG1 VC0 write VT fetch. B/D/F/Type : 0/0/0/ VC0PREMAP Address[...]

Processor Configuration Registers 218 Datasheet, Volume 2 14:10 RO 10000b PEG0 VT Completion Tracking Queue Resource Available (PEG0VTCTRA) Number of entri es av ailable in PEG0 VT Completion T racking Queue. 1-base d. The v alues pr ogramm ed in the f ields below must not be greater than the value advertised i n this field. Note: If device 6 is al[...]

Datasheet, Volume 2 219 Processor Configuration Registers 2.15.34 VTPOLICY—DMA Rema p Engine Policy Control This registers contains all the policy bits rel ated to the DMA remap engine. B/D/F/Type : 0/0/0/ VC0PREMAP Address Offset: FFC–FFFh Reset Value: 00000000h Access: RW-L Bit A ttr Reset Value Description 31 RW-L 0b DMA Remap Engine Policy [...]

Processor Configuration Registers 220 Datasheet, Volume 2 12 RW-L 0b PEG1 L3 TLBR (P EG1L3TLB R) This is a TLBR policy bit for PEG1VC0 L3 Cache 11 RW-L 0b PEG1 TLB Disable (PEG1TLB DIS) 1 = PEG1VC0 TLBs are disabled and each GPA request wil l result in a miss and a root walk will be requested from VTd Dispatcher 0 = Normal mode (default), PEG1VC0 T[...]

Datasheet, Volume 2 221 Processor Configuration Registers 2.16 DMI VC1 REMAP Registers Table 2-12. DMI VC1 Rema p Register Address Map Address Offset Register Symbol Register Name Reset Value Access 0–3h VER_REG Version R egister 00000010h RO 8–Fh CAP_REG Capability Regi ster 00C9008020E30272h RO 10–17h ECAP_REG Extended Capability Register 0[...]

Processor Configuration Registers 222 Datasheet, Volume 2 2.16.1 VER_REG—Version Register This register reports the architecture vers ion supported. Backw ard compatibility for the architecture is maintained with new revisi on numbers, allowing softw are to load DMA - remapping drivers written for prior architecture versions. B/D/F/Type: 0/0/0/DM[...]

Datasheet, Volume 2 223 Processor Configuration Registers 2.16.2 CAP_REG—Capability Register This register reports gener al DMA remapping hardware capabilities. B/D/F/Type : 0/0/0/D MIVC1REMAP Address Offset: 8–Fh Reset Value: 00C9008020E30272h Access: RO Bit A ttr Reset Value Description 63:56 RO 00h Reserved 55 RO 1b DMA Read Draining ( DRD) [...]

Processor Configuration Registers 224 Datasheet, Volume 2 23 RO 1b Isochrony (Isoch) 0 = Indicates this DMA-remapping hard ware unit has no critical isoc hronous requesters in its scope. 1 = Indicates this DMA-re mapping hardware unit has one or more critical isochronous reque sters in its scope. T o ensure isochronous performance, software must en[...]

Datasheet, Volume 2 225 Processor Configuration Registers 2.16.3 ECAP_REG—Extended Capability Register This register reports DMA -remapping hardware extended capabilities. 6R O 1 b Protected High-Memory Region (PHMR) 0 = Protected high-memory region not supp orted. 1 = Protected high-memory region is supp orted. 5R O 1 b Protected Low-Memory Regi[...]

Processor Configuration Registers 226 Datasheet, Volume 2 17:8 RO 010h Invalidation Unit Offset (IVO) This field specifies the location to the first IO TLB registers relative to the register base address of this DMA-remap ping hardware unit. If the register base address is X, and the value rep orted in this field is Y , the address for the first IO[...]

Datasheet, Volume 2 227 Processor Configuration Registers 2.16.4 GCMD_REG—Global Command Register This register controls DMA-remapping hardw are. If multiple control fields in this register need to be modified, software must serialize the modifications through multiple writes to this register . B/D/F/Type : 0/0/0/D MIVC1REMAP Address Offset: 18?[...]

Processor Configuration Registers 228 Datasheet, Volume 2 28 W 0b Enable Advanced Fault Logging (EAFL) This field is valid only for implementa tions su pporting adv anced fault logging . Software writes to this field to re quest hardware to enable or disable advanced fault logging. 0 = Disable advanced fault logging. In this case, translatio n faul[...]

Datasheet, Volume 2 229 Processor Configuration Registers 24 RO 0b Set Interrupt Remap Table Pointer (SIRTP) This field is valid only for implemen tations supporting interrupt-remapping. Software sets this field to set/update the inte rrupt remapping table poin ter used by hard ware. The inter rupt remapp ing table pointer is specified through the [...]

Processor Configuration Registers 230 Datasheet, Volume 2 2.16.5 GSTS_REG—Global Status Register This register reports general DMA -remapping hardware status. B/D/F/Type: 0/0/0/DMIVC1REMAP Address Offset: 1C–1Fh Reset Value: 00000000h Access: RO Bit Attr Reset Value Description 31 RO 0b Translation Enable Status (TES) This field indicates the s[...]

Datasheet, Volume 2 231 Processor Configuration Registers 2.16.6 RTADDR_REG—Roo t-Entry Table Address Register This register provides the b ase address of the root-entry table. B/D/F/Type : 0/0/0/D MIVC1REMAP Address Offset: 20–27h Reset Value: 0000000000000000h Access: RW, RO Bit A ttr Reset Value Description 63:12 RW 00000000 00000h Root Tabl[...]

Processor Configuration Registers 232 Datasheet, Volume 2 2.16.7 CCMD_REG—Contex t Command Register This register manages context cache. The act of writing th e uppermost byte of the CCMD_REG with ICC field set causes the hardware to perform the context -cache invalidation. B/D/F/Type: 0/0/0/DMIVC1REMAP Address Offset: 28–2Fh Reset Value: 00000[...]

Datasheet, Volume 2 233 Processor Configuration Registers 60:59 RO 00b Context Actual Invalidation Granularity (CAIG) Hardware reports the g ranularity at wh ich an inval idation request was processed throu gh the CAIG field at the time of repo rting invalidation completion (by clearing the ICC field). The following are the encodings for the CAIG f[...]

Processor Configuration Registers 234 Datasheet, Volume 2 2.16.8 FSTS_REG—Fault Status Register This register indicates the various error status. B/D/F/Type: 0/0/0/DMIVC1REMAP Address Offset: 34–37h Reset Value: 00000000h Access: RW1C-S, RO-V-S, RO Bit Attr Reset Value Descriptio n 31:16 RO 0000h Reserved 15:8 RO-V- S 00h Fault Record Index (FR[...]

Datasheet, Volume 2 235 Processor Configuration Registers 2.16.9 FECTL_REG—Fault Event Cont rol Register This register specifies the fault event interrupt message contro l bits. The VTd specification describes hardware handling of fault events. B/D/F/Type : 0/0/0/D MIVC1REMAP Address Offset: 38-3Bh Reset Value: 80000000h Access: RW, RO Bit A ttr [...]

Processor Configuration Registers 236 Datasheet, Volume 2 2.16.10 FEDATA_REG—Fault Event Data Register This register specifies the interrupt message data. 2.16.11 FEADDR_REG—Fault Event Address Register This Register specifies the interrupt message address. B/D/F/Type: 0/0/0/DMIVC1REMAP Address Offset: 3C–3Fh Reset Value: 00000000h Access: RO[...]

Datasheet, Volume 2 237 Processor Configuration Registers 2.16.12 FEUADDR_REG—Fault Event Upper Address Register This register specifies the interrupt message upper address. The register is treated as reserv ed by implem entations re porting Extended In terrupt Mode (EIM) as not supported in the Extended Capability register . 2.16.13 AFLOG_REG—[...]

Processor Configuration Registers 238 Datasheet, Volume 2 2.16.14 PMEN_REG—Protected Memory Enable Register This register enables the DMA-protected me mory regions set up through the PLMBASE, PLMLIMT , PHMBASE, PHMLIMIT registers. This register is trea ted as RO for implementations not supporting protected memory regions (PL MR and PHMR fields re[...]

Datasheet, Volume 2 239 Processor Configuration Registers 2.16.15 PLMBASE_REG—Protected Low-Memory Base Register This register is used to set up the base address of DMA-protected low-memory region below 4 GB. This register must be set up before enabling protected memory throug h PMEN_REG, and must not be updated when protected memory re gions are[...]

Processor Configuration Registers 240 Datasheet, Volume 2 2.16.16 PLMLIMIT_REG—Protected Low-Memory Limit Register This register is used to setup the lim it address of DMA pr otected low-memory region below 4 GB. This register must be setup before enabling protected memory throug h PMEN_REG, and must not be updated when protected memory reg ions [...]

Datasheet, Volume 2 241 Processor Configuration Registers 2.16.17 PHMBASE_REG—Protected High-Memory Base Register This register is used to set up the base address of DMA -protected high-memory region. This register must be set up before enabling protected memory throug h PMEN_REG, and must not be u pdated when protecte d memory regions are enable[...]

Processor Configuration Registers 242 Datasheet, Volume 2 2.16.18 PHMLIMIT_REG—Protected High-Memory Limit Register This register is used to setup the lim it address of DMA protected high-memory region. This register must be setup before enabling protected memory through PMEN_REG, and must not be updated when protected memory re gions are enabled[...]

Datasheet, Volume 2 243 Processor Configuration Registers 2.16.19 IQH_REG—Invali dation Queue Head Register This register indicates the invalidation queue head. This register is treated as reserved by implementations reporting Queued Inv a lidation (QI) as not s upported in the Extended Capability register . 2.16.20 IQT_REG—Invalidation Queue T[...]

Processor Configuration Registers 244 Datasheet, Volume 2 2.16.21 IQA_REG—Invalidation Queue Addr ess Register This register is used to configure the base address and size of the in validation queue. The register is treated as reserved by implementations reporting Queued Inv alidation (QI) as not supported in the Extended Capability register . Wh[...]

Datasheet, Volume 2 245 Processor Configuration Registers 2.16.23 IECTL_REG—Invalidation Event Control Register This register specifies the invalidation ev ent interrupt control bits. This register is treated as reserved by implementations r e porting Queued Inv alidation (QI) as not supported in the Extended Capability register . B/D/F/Type : 0/[...]

Processor Configuration Registers 246 Datasheet, Volume 2 2.16.24 IEDATA_REG—Invalidat ion Event Data Register This register specifies the Invalidation Ev ent interrupt message data. This register is treated as reserv ed by impl ementations reporting Q ueued In valid ation (QI) as not supported in the Extended Capability register . 2.16.25 IEADDR[...]

Datasheet, Volume 2 247 Processor Configuration Registers 2.16.26 IEUADDR_REG—Invalid ation Event Upper Address Register This register specifies the Invalidation Ev ent interr upt message upper address. This register is treated as reserved by implementations repo rting both Queued In validation (QI) and Extended Interrupt Mode (EIM) as not suppor[...]

Processor Configuration Registers 248 Datasheet, Volume 2 2.16.28 IVA_REG—Invalidate Address Register This register provides the DMA address wh ose corresponding IOTLB entry needs to be invalidated through the corresp onding IO TLB Invalidate register . The register is a write- only register . V alue returned on re ads of this register is un defi[...]

Datasheet, Volume 2 249 Processor Configuration Registers 2.16.29 IOTLB_REG—IOTLB Invalidate Register This register is used to inv alidate IOTLB. The act of writing the upper byte of the IOTLB_REG with IVT field set causes the ha rdware to perform the IO TLB inv alidation. B/D/F/Type : 0/0/0/D MIVC1REMAP Address Offset: 108–10Fh Reset Value: 00[...]

Processor Configuration Registers 250 Datasheet, Volume 2 59:57 RO 000b IOTLB Actual Invalidation Granularity (IAIG) Hardware reports the gr anularity at which an in validat ion request was processed through this field at the time of reporting inv a lidation completion (by clearing th e IVT field) . The following are the encodings for the IAIG fiel[...]

Datasheet, Volume 2 251 Processor Configuration Registers 2.16.30 FRCD_REG —Fault Recording Registers These R egisters record fault information when primary fault logging is active. Hardware reports the number and location of fault recording registers through the Capability register . This register is relevant only for pr imary fault logging. The[...]

Processor Configuration Registers 252 Datasheet, Volume 2 2.16.31 VTPOLICY—DMA Remap Engine Policy Control This registers contains all the policy bits related to the DMA remap engine. B/D/F/Type: 0/0/0/DMIVC1REMAP Address Offset: FFC–FFFh Reset Value: 00000000h Access: RO, RW-L-K, RW-L Bit Attr Reset Value Description 31 RW-L -K 0b DMA Remap En[...]

Datasheet, Volume 2 253 Processor Configuration Registers 2.17 Graphics Control Registers 2.17.1 MGGC—Graphics Control Regist er All the Bits in this register are Intel TXT lockable. B/D/F/Type : 0/2/0/ PCI Address Offset: 52–53h Reset Value: 0030h Access: RO Bit A ttr Reset Value Description 15:12 RO 0h Reserved 11:8 RO 0h GTT Graphics Memory [...]

Processor Configuration Registers 254 Datasheet, Volume 2 2.17.2 GFXPLL1—GFX PLL BIOS This is the GFX PLL BIOS register . See la test BIOS specification for more details. 1R O 0 b IGD VGA Disable (IVD) 0 = Enable. Device 2 (IGD) claims VGA memory and IO cycles, the Sub- Class Code within Device 2 Class Code regis ter is 00. 1 = Disable. Device 2 [...]

Datasheet, Volume 2 255 Processor Configuration Registers 2.18 GFXVTBAR Registers Table 2-13. GFXVTBAR Register Address Map Address Offset Register Symbol Register Name Reset Value A ccess 0–3h VER_REG Version R egister 00000010h RO 8–Fh CAP_REG Capability Re gister 00C00000202 30272h RO 10–17h ECAP_REG Extended Capability Register 0000000000[...]

Processor Configuration Registers 256 Datasheet, Volume 2 2.18.1 VER_REG—Version Register This register reports the architecture vers ion supported. Backw ard compatibility for the architecture is maintained with new revisi on numbers, allowing softw are to load DMA - remapping drivers written for prior architecture versions. B/D/F/Type: 0/2/0/GF[...]

Datasheet, Volume 2 257 Processor Configuration Registers 2.18.2 CAP_REG—Capability Register This register reports gener al DMA remapping hardware capabilities. B/D/F/Type : 0/2/0/ GFXVTBAR Address Offset: 8–Fh Reset Value: 00C0000020230272h Access: RO Bit A ttr Reset Value Description 63:56 RO 00h Reserved 55 RO 1b DMA Read Draining ( DRD) 0 =[...]

Processor Configuration Registers 258 Datasheet, Volume 2 23 RO 0b Isochrony (ISOCH) 0 = Indicates this DMA-remapping hard ware unit has no critical isoc hronous requesters in its scope. 1 = Indicates this DMA-re mapping hardware unit has one or more critical isochronous reque sters in its scope. T o ensure isochronous performance, software must en[...]

Datasheet, Volume 2 259 Processor Configuration Registers 6R O 1 b Protected High-Memory Region (PHMR) 0 = Indicates protected hig h-memory region is not supp orted. 1 = Indicate s protected high -memory re gion is suppor ted. DMA-remapp ing hardware implementat ions on Intel TXT platforms supporting main memory abo ve 4 GB are required to support [...]

Processor Configuration Registers 260 Datasheet, Volume 2 2.18.3 ECAP_REG—Extended Capability Register This register reports DMA-remapping hardw are extended capabilities. B/D/F/Type: 0/2/0/GFXVTBAR Address Offset: 10–17h Reset Value: 0000000000001000h Access: RO Bit Attr Reset Value Description 63:24 RO 0h Reserved 23:20 RO 0h Maximum Handle M[...]

Datasheet, Volume 2 261 Processor Configuration Registers 2.18.4 GCMD_REG—Global Command Register This register to controls remapping hardware. If multiple control fields in this register need to be modified, software must serializ e the modifications through multiple writes to this register . 0R O 0 b Coherency (C) This field indicates if hardwa[...]

Processor Configuration Registers 262 Datasheet, Volume 2 30 W 0b Set Root Table Pointer (SRTP) Software sets this field to set/ update the root-entry table pointer used by hardware. The root-entry tab le pointer is spec ified through the R oot -entry T able Address regist er . Hardware reports the status o f the “root table pointer set” operat[...]

Datasheet, Volume 2 263 Processor Configuration Registers 26 RO 0b Queued Invalidation Enable (QIE) This field is valid only for implementa tions supporting queued invalidations. Software writes to this field to enable or disable queued in validations. 0 = Disable queued invalidations. 1 = Enable use of queued invalidations. Hardware repo rts the s[...]

Processor Configuration Registers 264 Datasheet, Volume 2 2.18.5 GSTS_REG—Global Status Register This register reports general remapping hardwar e status. 23 RO 0b Compatibility Format Interrupt (CFI) This field is valid only for Intel 64 implementations s upporting interrupt- remapping. Software writes to this field to en able or disable Compati[...]

Datasheet, Volume 2 265 Processor Configuration Registers 27 RO 0b Write Buffer Flush Status (WBFS) This field is valid only for implemen tations requiring write buffer flushing. This field indicates th e status of the write buffer flush command. It is Set by hardware when software sets the WBF field in th e Global Command register . Cleared by har[...]

Processor Configuration Registers 266 Datasheet, Volume 2 2.18.6 RTADDR_REG—Root-Entr y Table Address Register This register provides the base address of root-entry table. 2.18.7 CCMD_REG—Contex t Command Register This register manages context cache. The act of writing th e uppermost byte of the CCMD_REG with the ICC field set causes the hardwa[...]

Datasheet, Volume 2 267 Processor Configuration Registers 62:61 RW 00b Context Invalidation Request Granularity (CIRG) Software provides the requested invalid ation granularit y through this field when setting the ICC field: 00 = R es erved. 01 = Global In validation request. 10 = Domain-selective invalidati on requ est. The tar get domain-id must [...]

Processor Configuration Registers 268 Datasheet, Volume 2 2.18.8 FSTS_REG—Fault Status Register This register indicates the various error statuses. B/D/F/Type: 0/2/0/GFXVTBAR Address Offset: 34–37h Reset Value: 00000000h Access: RO, RW1C-S, RO-V-S Bit Attr Reset Value Description 31:16 RO 0000h Reserved 15:8 RO-V -S 00 h Fault Record Index (FRI[...]

Datasheet, Volume 2 269 Processor Configuration Registers 1R O - V - S 0 b Primary Pending Fault (PPF) This field indicates if there are one or more pending faults logged in the fault recording register s. Hardware c omputes this field as the logical OR of F ault (F) fields across all the faul t recording registers of this remapping hardware unit. [...]

Processor Configuration Registers 270 Datasheet, Volume 2 2.18.9 FECTL_REG—Fault Event Control Register This register specifies the fault event interrupt message control bits. The VTd specification describes hardware handling of fault events. B/D/F/Type: 0/2/0/GFXVTBAR Address Offset: 38–3Bh Reset Value: 80000000h Access: RO, RW Bit Attr Reset [...]

Datasheet, Volume 2 271 Processor Configuration Registers 2.18.10 FEDATA_REG —Faul t Event Data Register This register specifies the interrupt message data. 2.18.11 FEADDR_REG—Fault Event Address Register This register specifies the i nterrupt message address. 2.18.12 FEUADDR_REG—Fault Event Upper Address Register This register specifies the [...]

Processor Configuration Registers 272 Datasheet, Volume 2 2.18.13 AFLOG_REG—Advanc ed Fault Log Register This register specifies the base addres s of memory-resident faul t-log region. This register is treated as read-only (0) for implem entations not supporting adv anced translation fault logging (AFL field reported as 0 in the Capabilit y regis[...]

Datasheet, Volume 2 273 Processor Configuration Registers 2.18.14 PMEN_REG—Protected Memory Enable Register This regist er enables the DMA- protected me mo ry regions set up through the PLMBASE, PLMLIMT , PHMBASE, PHMLIMIT registers. This register is always treated as RO (0) for implementations not supporting protected memory regions (PLMR and PH[...]

Processor Configuration Registers 274 Datasheet, Volume 2 2.18.15 PLMBASE_REG—Protected Low Memory Base Register This register is used to set up the base address of DMA -protected low-memory region below 4 GB. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory reg ions are[...]

Datasheet, Volume 2 275 Processor Configuration Registers 2.18.16 PLMLIMIT_REG—Protecte d Lo w Memory Limit Register This register is used to set up the limit address of DMA -protect ed low-memory region below 4 GB. The register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory re gion[...]

Processor Configuration Registers 276 Datasheet, Volume 2 2.18.17 PHMBASE_REG—Protected High M emory Base Re gister This register is used to set up the base address of DMA -protected high-memory region. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory re gions are enable[...]

Datasheet, Volume 2 277 Processor Configuration Registers 2.18.18 PHMLIMIT_REG—Protected Hi gh Memory Limit Register This register is used to set up the limit address of D MA-protected high-memory region. The register must be set up before en abling protected memory through PMEN_RE G, and must not be u pdated when protecte d memory regions are en[...]

Processor Configuration Registers 278 Datasheet, Volume 2 2.18.19 IQH_REG—Invalidati on Queue Head Register This register indicates the invalidation queue head. The register is treated as reserved by implementations reporting Queued Inva lidation (QI) as not supported in the Extended Capability register . 2.18.20 IQT_REG—Invalidati on Queue Tai[...]

Datasheet, Volume 2 279 Processor Configuration Registers 2.18.21 IQA_REG—Invalidation Queue Address Register This register is used to configure the base address and size of the inv alidation queue. The register is treated as reserved by implementations reporting Queued Inv alidation (QI) as not supported in the Extended Capability register . Whe[...]

Processor Configuration Registers 280 Datasheet, Volume 2 2.18.23 IECTL_REG—Invalidation Completion Event Co ntrol Register This register specifies the invalidation even t interrupt con trol bits. The register is treated as reserv ed by impl ementations reporting Q ueued In valid ation (QI) as not supported in the Extended Capability register . B[...]

Datasheet, Volume 2 281 Processor Configuration Registers 2.18.24 IEDATA_REG—Invalidation Completion Event Data Register This register specifies the Invalidation Event interrupt message data. The register is treated as reserved by implementations r e porting Queued Inv alidation (QI) as not supported in the Extended Capability register . 2.18.25 [...]

Processor Configuration Registers 282 Datasheet, Volume 2 2.18.26 IRTA_REG—Interrupt Rema pping Table A ddress Register This register provides the base address of Interrupt remapping table. The register is treated as reserved by implementations reporting Interrupt Remapping (IR) as not supported in the Extended Capability register . B/D/F/Type: 0[...]

Datasheet, Volume 2 283 Processor Configuration Registers 2.18.27 IVA_REG—Invalidate Addr ess Register This register provides the DMA address whose corresponding IOTLB entry needs to be inv alidated through the corresponding IOTLB In validate register . The register is a write- only register . A v alue returned on a re ad of this register is unde[...]

Processor Configuration Registers 284 Datasheet, Volume 2 2.18.28 IOTLB_REG—IOTLB Invalidate Register This register is used to inv alidate IOTLB . The act of writing the uppe r byte of the IOTLB_REG with the IVT field Set causes the hardwa re to perform the IO TLB invalidation. B/D/F/Type: 0/2/0/GFXVTBAR Address Offset: 108–10Fh Reset Value: 02[...]

Datasheet, Volume 2 285 Processor Configuration Registers 56:50 RO 00h Reserved 49 RW 0b Drain Reads (DR) This field is ignored by hardw are if th e DRD field is report ed as clear in the Capability register . When DRD field is reported as set in the Capabi lity reg i ster , the following encodings are suppo rted for this field: 0 = Hardware may co[...]

Processor Configuration Registers 286 Datasheet, Volume 2 2.18.29 FRCD_REG—Fault Recording Registers Registers to record fault information when primary fault logging is active. Hardware reports the number and location of fault recording registers through the Capability register . This register is relevant only for primary fault logging. These reg[...]

Datasheet, Volume 2 287 Processor Configuration Registers 2.18.30 VTPOLICY—VT Policy Register B/D/F/Type : 0/2/0/ GFXVTBAR Address Offset: FFC–FFFh Reset Value: 4000_0000h Access: RW-L, RW-O, RO Bit A ttr Reset Value Description 31 RW-O 0b DMA Remap Engine Policy Lock-Down (DMAR_LCKDN) This register bit protects all th e DMA remap engine specif[...]

Processor Configuration Registers 288 Datasheet, Volume 2 2.19 PCI Device 6 Registers Note: Device 6 is not supported on all SKUs. Table 2-14. PCI Device 6 Regist er Address Map (Sheet 1 of 2) Address Offset Register Symbol Register Name Reset Value Access 0–1h VID6 V endor Identification 8086h RO 2–3h DID6 Device Identification 0043h RO 4–5h[...]

Datasheet, Volume 2 289 Processor Configuration Registers 2.19.1 VID6—Vendor Identification Register This register , combined with the Device Iden tification register , uniquely identify any PCI device. A4–A7h DCAP Device Capabilities 00008000h RO A8–A9h DCTL Device Control 0000h RW , RO AA– ABh DSTS Device Status 0000h RO, RW1C AC– AFh L[...]

Processor Configuration Registers 290 Datasheet, Volume 2 2.19.2 DID6—Device Identification Register This register combined with the V end or Iden tification register uniquely identifies any PCI device. 2.19.3 PCICMD6—PCI Co mmand Register B/D/F/Type: 0/6/0/PCI Address Offset: 2–3h Reset Value: 0043h Access: RO Bit Attr Reset Value Descriptio[...]

Datasheet, Volume 2 291 Processor Configuration Registers 7R O 0 b Reserved Not Applicable or Implem ented. Hardwired to 0. 6R W 0 b Parity Error Respons e Enable (PERRE) Controls whether or not th e Master Data Pari ty Error bit in the PCI Stat us registe r can bet set. 0 = Master Data Parity Error bit in PCI Status register can NOT be set. 1 = Ma[...]

Processor Configuration Registers 292 Datasheet, Volume 2 2.19.4 PCISTS6—PCI Status Register This register reports the occurrence of error conditions associate d with primary side of the "virtual" Host -PCI Express br idge embedded within the GMCH. B/D/F/Type: 0/6/0/PCI Address Offset: 6–7h Reset Value: 0010h Access: RO, RW1C Bit Attr[...]

Datasheet, Volume 2 293 Processor Configuration Registers 2.19.5 RID6—Revision Identification Register This register contains the revision num ber of the processor . The R evision ID (RID) is a traditional 8-bit R ead Only (RO) register located at offset 08h in the standard PCI header of every PCI/PCI Express compatible device and function. This [...]

Processor Configuration Registers 294 Datasheet, Volume 2 2.19.7 CL6—Cache Li ne Size Register 2.19.8 HDR6—Header Type Register This register identifies the header layout of the configur ation space . No physical register exists at this location. 2.19.9 PBUSN6—Primary Bus Number Register This register identifies that this "virtual" [...]

Datasheet, Volume 2 295 Processor Configuration Registers 2.19.10 SBUSN6—Secondary Bus Number Register This register identifies the bus number assigned to the second bus side of the "virtual" bridge (that is, to PCI Express-G). T his num ber is programmed by the PCI configur ation software to allow mapping of configur ation cycles to PC[...]

Processor Configuration Registers 296 Datasheet, Volume 2 2.19.12 IOBASE6—I/O Base Address Register This register controls the processor to PC I Express-G I/O access routing based on the following formula: IO_BASE  address  IO_LIMIT Only upper 4 bits are programmable. F or the purpose of address decode, address bits A[11:0] are treated as 0[...]

Datasheet, Volume 2 297 Processor Configuration Registers 2.19.14 SSTS6—Secondary Status Register SSTS6 is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (that is, PCI Express-G side) of the "virtual" PCI -PCI bridge embedded within GMCH. B/D/F/Type : 0/6/0/ PCI Address Offset: 1E[...]

Processor Configuration Registers 298 Datasheet, Volume 2 2.19.15 MBASE6—Memory Ba se Address Register This register controls the processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE  address  MEMORY_LIMIT The upper 12 bits of the register are re ad/write and correspond to the upper 1[...]

Datasheet, Volume 2 299 Processor Configuration Registers 2.19.16 MLIMIT6—Memory Limit Address Register This register controls the processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE  address  MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 1[...]

Processor Configuration Registers 300 Datasheet, Volume 2 2.19.17 PMBASE6—Prefetchable Me mory Base Address Register This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express-G prefetchable memory access routing based on the following formula: PREFETCH ABLE_MEMOR Y_BASE  address  P[...]

Datasheet, Volume 2 301 Processor Configuration Registers 2.19.18 PMLIMIT6—Prefetchable Memory L imit Address Register This register in conjunction with the correspon ding Upper Limit Address register controls the processor to PCI Express-G pr efetchable memory access routing based on the following formula: PREFET CHABLE_MEMORY_BASE  address ?[...]

Processor Configuration Registers 302 Datasheet, Volume 2 2.19.19 PMBASEU6—Prefe tchable Memory Base Address Upper Register The functionality associated with this register is present in the PEG design implemen tation. This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express-G prefetchab[...]

Datasheet, Volume 2 303 Processor Configuration Registers 2.19.20 PMLIMITU6—Prefetchable Memory Limit Address Upper Register The functionality associated with this register is present in the PEG design implementation. This register in conjunction with the correspon ding Upper Limit Address register controls the processor to PCI Express-G pr efetc[...]

Processor Configuration Registers 304 Datasheet, Volume 2 2.19.22 INTRLINE6—Interrupt Line Register This register contains interrupt line routing information. The device itself does not use this value, r ather it is used by device drivers and oper ating systems to determine priority and vector information. 2.19.23 INTRPIN6—Inte rrupt Pi n Regis[...]

Datasheet, Volume 2 305 Processor Configuration Registers 9R O 0 b Secondary Discard Timer (SDT) Not Applicable or Implem ented. Hardwired to 0. 8R O 0 b Primary Discard Timer (PDT) Not Applicable or Implem ented. Hardwired to 0. 7R O 0 b Fast Back-to-Back Enable (F B2BEN) Not Applicable or Implem ented. Hardwired to 0. 6R W 0 b Secondary Bus Reset[...]

Processor Configuration Registers 306 Datasheet, Volume 2 2.19.25 PM_CAPID6—Powe r Mana gement Capabi lities Register B/D/F/Type: 0/6/0/PCI Address Offset: 80–83h Reset Value: C8039001h Access: RO Bit Attr Reset Value Description 31:27 RO 19h PME Support (PMES) This field indicates the power states in which this device may indicate PME wake usi[...]

Datasheet, Volume 2 307 Processor Configuration Registers 2.19.26 PM_CS6—Power Management Control/Status Register B/D/F/Type : 0/6/0/ PCI Address Offset: 84–87h Reset Value: 00000008h Access: RO, RW, RW-S Bit A ttr Reset Value Description 31:16 RO 0000h Reserved Not Applicable or Implem ented. Hardwired to 0. 15 RO 0b PME Status (PMESTS) Indica[...]

Processor Configuration Registers 308 Datasheet, Volume 2 2.19.27 SS_CAPID—Subsystem ID and Ven dor ID Capabilities Register This capability is used to uniquely identify the subsystem where the PCI device resides. Because this device is an integrated part of the system and not an add-in device, it is anticipated that this capability will never be[...]

Datasheet, Volume 2 309 Processor Configuration Registers 2.19.29 MSI_CAPID—Message Signal ed Interrupts Ca pability ID Register When a device supports MSI it can generate an interrupt request to the processor by writing a predefined data item (a message) to a predefined memory address. The reporting of the existence of this ca pability can be di[...]

Processor Configuration Registers 310 Datasheet, Volume 2 2.19.30 MC—Message Control Register System software can modify bits in this register , but the device is prohibited from doing so. If the device writes the same message multiple times, only one of those messages is ensured to be serviced. If all of them must be serviced, the device must no[...]

Datasheet, Volume 2 311 Processor Configuration Registers 2.19.31 M A—Message Addres s Register 2.19.32 MD—Message Data Register 2.19.33 PEG_CAPL—PCI Express- G Capability List Register This register enumerates the PCI Express capability structure. B/D/F/Type : 0/6/0/ PCI Address Offset: 94–97h Reset Value: 00000000h Access: RW, RO Bit A tt[...]

Processor Configuration Registers 312 Datasheet, Volume 2 2.19.34 PEG_CAP—PCI Expres s-G Capabilities Register This register indicates PCI Express device capabilities. 2.19.35 DCAP—Device Capabilities Register This register indicates PCI Express device capabilities. B/D/F/Type: 0/6/0/PCI Address Offset: A2–A3h Reset Value: 0142h Access: RO, R[...]

Datasheet, Volume 2 313 Processor Configuration Registers 2.19.36 DCTL—Device Control Register This register provides control for PCI Express device specific capabilities. The error reporting enable bits are in refere nce to errors detected by this device, not error messages received across the link. The reporting of error messages (ERR_CORR, ERR[...]

Processor Configuration Registers 314 Datasheet, Volume 2 2.19.37 DSTS—Device Status Register This register reflects status corresponding to controls in the Device Control register . The error reporting bits are in reference to errors detected by this device, not errors messages received across the link. B/D/F/Type: 0/6/0/PCI Address Offset: AA?[...]

Datasheet, Volume 2 315 Processor Configuration Registers 2.19.38 LCAP—Link Capabilities Register This register indicates PCI Express device specific capabilities. B/D/F/Type : 0/6/0/ PCI Address Offset: AC–A Fh Reset Value: 03214C82h Access: RO, RW-O Bit A ttr Reset Value Description 31:24 RO 03h Port Number (PN) This field indicates th e PCI [...]

Processor Configuration Registers 316 Datasheet, Volume 2 14:12 RO 100b L0s Exit Latency (L0SELAT) This field indicates the length of time this P ort requires to complete the transiti on from L0s to L0. 000 =Less than 64 ns 001 =64 ns to less than 128 ns 010 =128 ns to less than 256 ns 011 =256 ns to less than 512 ns 100 =512 ns to less than 1 us 1[...]

Datasheet, Volume 2 317 Processor Configuration Registers 2.19.39 L CTL—Link Control Regi ster This register allows control of PCI Express link. B/D/F/Type : 0/6/0/ PCI Address Offset: B0–B1h Reset Value: 0000h Access: RW, RO, RW-SC Bit A ttr Reset Value Description 15:12 RO 0000b Reserved 11 RW 0b Link Autonomous Bandwidth Interrupt Enable (LA[...]

Processor Configuration Registers 318 Datasheet, Volume 2 5R W - S C 0 b Retrain Link (RL) 0 = Normal operation. 1 = Full Link retraining is initiated by directing the Physical L ayer L TSSM from L0, L0s, or L1 states to the Reco very state. This bit always returns 0 when read. This bit is cleared automatically (no need to write a 0). It is permitt[...]

Datasheet, Volume 2 319 Processor Configuration Registers 2.19.40 LSTS—Link Status Register This register indicates PCI Express link status. B/D/F/Type : 0/6/0/ PCI Address Offset: B2–B3h Reset Value: 1000h Access: RO, RW1C Bit A ttr Reset Value Description 15 RW1C 0b Link Autonomous Bandwidth Status (LABWS) This bit is set to 1b by h ardware t[...]

Processor Configuration Registers 320 Datasheet, Volume 2 2.19.41 SLOTCAP—Slot Capabilities Register Note: Hot Plug is not supported on the platform. 3:0 RO 0h Current Link Speed (CLS) This field indicates the negotiated Link speed of the give n PCI Express Link. Defined encodings ar e: 0001b = 2.5 GT/s PCI Express Link 0010b = 5.0 GT/s PCI Expre[...]

Datasheet, Volume 2 321 Processor Configuration Registers 5R O 0 b Reserved for Hot-plug Surprise (HPS) When set to 1, this bit indicates that an adapter present in this slot might be removed from the system without any prio r notification. This is a form factor specific capability . This bit is an indi cation to the oper ating system to allow for [...]

Processor Configuration Registers 322 Datasheet, Volume 2 2.19.42 SLOTCTL—Slot Control Register Note: Hot Plug is not supported on the platforms. B/D/F/Type: 0/6/0/PCI Address Offset: B8–B9h Reset Value: 0000h Access: RO, RW Bit Attr Reset Value Description 15:13 RO 000b Reserved 12 RO 0b Reserved for Data Link Layer State Changed Enable (DLLSC[...]

Datasheet, Volume 2 323 Processor Configuration Registers 7:6 RO 00b Reserved for Attention Indicator Control (AIC) If an Attention Indicator is implemented, writes to this field set the Attenti on Indicator to the written state. R eads of this field must reflect the v alue from the latest write, even if the c orresponding hot-plug comman d is not [...]

Processor Configuration Registers 324 Datasheet, Volume 2 2.19.43 SLOTSTS—Slot Status Register Note: Hot Plug is not supported on the platform. B/D/F/Type: 0/6/0/PCI Address Offset: BA–BB h Reset Value: 0000h Access: RO, RW1C Bit Attr Reset Value Description 15:9 RO 0000000b Reserved. MBZ For futur e R/WC/S implementations; software must use 0 [...]

Datasheet, Volume 2 325 Processor Configuration Registers 2R O 0 b Reserved for MRL Sensor Changed (MSC) If an MRL sensor is implemented, this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented, this bit must not be set. 1R O 0 b Reserved for Power Fault Detected (PFD) If a Power Con troller that supports pow[...]

Processor Configuration Registers 326 Datasheet, Volume 2 2.19.44 RCTL—Root Control Register This register allows control of PCI Express Root Complex specific parameters. The system error control bits in this regist er determine if corresponding SERRs are generated when our device detects an error (reported in this device's Device Status reg[...]

Datasheet, Volume 2 327 Processor Configuration Registers 2.19.45 RSTS—Root Status This register provides information ab out PCI Express Root Complex specific parameters. 2.19.46 PEGLC—PCI Express-G Legacy Control Register This register controls functionality that is needed by Legacy (non-PCI Express aware) OSs during run time. B/D/F/Type : 0/6[...]

Processor Configuration Registers 328 Datasheet, Volume 2 2.20 Device 6 Extended Configuration Registers Note: Device 6 is not supported on all SKUs. 2.20.1 PVCCAP1—Port VC Capability Register 1 This register describes the configuration of PCI Express Virtual Ch annels associated with this port. Table 2-15. Device 6 Extended Configuration Regist [...]

Datasheet, Volume 2 329 Processor Configuration Registers 2.20.2 PVCCAP2—Port VC Capability Register 2 This register describes the configuration of PCI Express Virtual Channels associated with this port. 2.20.3 PVCCTL—Port VC Control Register B/D/F/Type : 0/6/0/ MMR Address Offset: 108–10Bh Reset Value: 0000_0000h Access: RO Bit A ttr Reset V[...]

Processor Configuration Registers 330 Datasheet, Volume 2 2.20.4 VC0RCAP—VC0 Resour ce Capability Register B/D/F/Type: 0/6/0/MMR Address Offset: 110–113h Reset Value: 0000_0001h Access: RO Bit Attr Reset Value Description 31:24 RO 00h Reserved for Port Arbitration Table Offset 23 RO 0b Reserved 22:16 RO 00h Reserved for Maximum Time Slots 15 RO[...]

Datasheet, Volume 2 331 Processor Configuration Registers 2.20.5 VC0RCTL—VC0 Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 0. B/D/F/Type : 0/6/0/ MMR Address Offset: 114–117h Reset Value: 800000FFh Access: RO, RW Bit A ttr Reset Value Description 31 RO 1b VC0 Enable (VC0E) For VC0 thi[...]

Processor Configuration Registers 332 Datasheet, Volume 2 2.20.6 VC0RSTS—VC0 Resource Status Register 2.21 Intel ® Trusted Execution Technology (Intel ® TXT) Specific Registers Intel TXT configuration registers are a subset of chipset registers. These registers are mapped into two regions of memory , representing the public and priv ate config [...]

Datasheet, Volume 2 333 Processor Configuration Registers 2.21.1 TXT.DID—TXT De vice ID Register This register contains the TXT ID for the processor . 2.21.2 TXT.DPR—DMA Prot ected Range Register This is the DMA protected range register . B/D/F/Type: 0/0/0/TXT Specific Address Offset: 110–117h Reset Value: 00000003A0008086h Access: RO Bit A t[...]

Processor Configuration Registers 334 Datasheet, Volume 2 2.21.3 TXT.PUBLIC.KEY.LOWER—TX T Processor P ublic Key Hash Lower Half Register These registers hold the hash of the processor's public key . It is 256 bits (32 Bytes). 2.21.4 TXT.PUBLIC.KEY.UPPER—TX T Processor Public Key Hash Upper Half Register § § B/D/F/Type: 0/0/0/TXT Specifi[...]

Datasheet, Volume 2 335 Intel ® QuickPath Architecture System Ad dress Decode Register Description 3 Intel ® QuickPath Architecture System Address Decode Register Description The processor supports PCI configuration space accesses using the mechanism denoted as Configuration Mechanism in the PCI spec ification as defined in the PCI Local Bus Spec[...]

Intel ® QuickPath Architect ure System Ad dress Decode Register Description 336 Datasheet, Volume 2 RWO Read/Write Once. A register bit with this attribute can be written to only once after power u p. After the first write, the bit becomes read only . This attribute is applied on a bit by bit basis. For example, if the RWO attribute is applied to [...]

Datasheet, Volume 2 337 Intel ® QuickPath Architecture System Ad dress Decode Register Description 3.2 Platform Configuration Structure The processor contains PCI devices within a single physical component. The configuration registers for these devices are mapped as devices residing on the PCI bus assigned for the processor socket. Bus nu mber is [...]

Intel ® QuickPath Architect ure System Ad dress Decode Register Description 338 Datasheet, Volume 2 3.3 Detailed Configuration Space Maps Table 3-3. Device 0, Function 0 — Gene ric Non-core Registers DID VID 00h 80h PCISTS PCICMD 04h 84h CCR RID 08h 88h HDR 0Ch 8Ch 10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h A0h 24h A4h 28h A8h SID SVID 2Ch ACh 30h B0h [...]

Datasheet, Volume 2 339 Intel ® QuickPath Architecture System Ad dress Decode Register Description Table 3-4. Device 0, Function 1 — System Address Decoder Registers DID VID 00h SAD_DRAM_RULE_0 80h PCISTS PCICMD 04h SAD_DRAM_RULE_1 84h CCR RID 08h SAD_DRAM_RULE_2 88h HDR 0Ch S AD_DRAM_RULE_3 8Ch 10h SAD_DRAM_RULE_4 90h 14h SAD_DRAM_RULE_5 94h 18[...]

Intel ® QuickPath Architect ure System Ad dress Decode Register Description 340 Datasheet, Volume 2 Table 3-5. Device 2, Function 0 — Inte l ® QPI Link 0 Regist ers DID VID 00h 80h PCISTS PCICMD 04h 84h CCR RID 08h 88h HDR 0Ch 8Ch 10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h A0h 24h A4h 28h A8h SID SVID 2Ch ACh 30h B0h 34h B4h 38h B8h 3Ch BCh 40h C0h 44[...]

Datasheet, Volume 2 341 Intel ® QuickPath Architecture System Ad dress Decode Register Description Table 3-6. Device 2, Function 1 — Intel ® QPI Physical 0 Regi sters DID VID 00h QPI_0_PH_PIS 80h PCISTS PCICMD 04h 84h CCR RID 08h 88h HDR 0Ch 8Ch 10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h A0h 24h A4h 28h A8h SID SVID 2Ch ACh 30h B0h 34h B4h 38h B8h 3Ch[...]

Intel ® QuickPath Architect ure System Ad dress Decode Register Description 342 Datasheet, Volume 2 3.4 PCI Standard Registers These registers appear in every function for every device. 3.4.1 VID—Vendor Identification Register The VID Register contains the v endor identification number . This 16-bit register , combined with the Device Identifica[...]

Datasheet, Volume 2 343 Intel ® QuickPath Architecture System Ad dress Decode Register Description 3.4.3 RID—Revision Identification Register This register contains the revision num ber of the processor . The R evision ID (RID) is a traditional 8-bit R ead Only (RO) register located at offset 08h in the standard PCI header of every PCI/PCI Expre[...]

Intel ® QuickPath Architect ure System Ad dress Decode Register Description 344 Datasheet, Volume 2 3.4.4 CCR—Class Code Register This register contains the Class Code for the device. W rite s to this register have no effect. Device: 0 Function: 0–1 Offset: 09h Device: 2 Function: 0–1 Offset: 09h Bit Type Reset Value Description 23:16 RO 06h[...]

Datasheet, Volume 2 345 Intel ® QuickPath Architecture System Ad dress Decode Register Description 3.4.5 HDR—Header Type Register This registe r identifies the header layout of the co nfiguration space. 3.4.6 SID/SVID—Subsys tem Identity/Subsys tem Vendor Identification Register This regis ter identifi es the manufactu rer of the sys tem. This[...]

Intel ® QuickPath Architect ure System Ad dress Decode Register Description 346 Datasheet, Volume 2 3.4.7 PCICM D—Command Regi ster This register defines the PCI 3.0 compatible command register values applicable to PCI Express space. Device: 0 Function: 0–1 Offset: 04h Device: 2 Function: 0–1 Offset: 04h Bit Type Reset Value Descriptio n 15:[...]

Datasheet, Volume 2 347 Intel ® QuickPath Architecture System Ad dress Decode Register Description 3.4.8 PCISTS—PCI Status Register The PCI Status register is a 16-b it status re gister that reports the occurrence of various error events on this device's PCI interface. Device: 0 Function: 0–1 Offset: 06h Device: 2 Function: 0–1 Offset: [...]

Intel ® QuickPath Architect ure System Ad dress Decode Register Description 348 Datasheet, Volume 2 4R O 0 Capability List (CLIST) This bit is hard wired to 1 to indica te to the configur ation software that this device/function implements a list of new capabilities. A list of new capabilities is accessed using regi sters CAPPTR at the configur at[...]

Datasheet, Volume 2 349 Intel ® QuickPath Architecture System Ad dress Decode Register Description 3.5 Generic Non-core Registers 3.5.1 MAX_RTIDS Maximum number of R T IDs other homes have. How many requests can this caching agent send to the other home agents. This number is one m ore than the highest numbered R TID to use. Note that these v alue[...]

Intel ® QuickPath Architect ure System Ad dress Decode Register Description 350 Datasheet, Volume 2 25:24 RW 0 PAM3_LOENABLE. 0D0000h–0D3FFFh Attribute (LOE NABLE) This field contro ls the steering o f read and write cycles that address the BIOS area from 0D0000h to 0D3FFFh. 00 = DRAM Disabled: All accesses are d irected to ESI. 01 = Read Only: [...]

Datasheet, Volume 2 351 Intel ® QuickPath Architecture System Ad dress Decode Register Description 3.6.2 SAD_PAM456 This register is for legacy Device 0, Function 0 94h–97h address space. Device: 0 Function: 1 Offset: 44h Access as a Dword Bit Type Reset Value Description 31:22 RV 0 Rese rved 21:20 RW 0 PAM6_HIENABLE. 0EC000h–0EFFFFh A ttribut[...]

Intel ® QuickPath Architect ure System Ad dress Decode Register Description 352 Datasheet, Volume 2 3.6.3 SAD_HEN This register is for legacy Hole Enable. Device: 0 Function: 1 Offset: 48h Access as a Dword Bit Type Reset Value Description 31:8 RV 0 Reserved 7R W 0 HEN This bit enables a memory hole in DRAM space. The DRAM that lies "behind&q[...]

Datasheet, Volume 2 353 Intel ® QuickPath Architecture System Ad dress Decode Register Description 3.6.4 SAD_SM RAM This register is for legacy 9 Dh address space. Note: This register must be programmed consistently with any other registers controlling access to SMM space within the system, such as on IOH devices if present. Device: 0 Function: 1 [...]

Intel ® QuickPath Architect ure System Ad dress Decode Register Description 354 Datasheet, Volume 2 3.6.5 SAD_PCIEXBAR This is the Global register for PCIEXBAR address space. Device: 0 Function: 1 Offset: 50h Access as a QWord Bit Type Reset Value Description 63:40 RV 0 Reserved 39:20 RW 0 ADDRESS This field contains the Base address of PCIEXBAR. [...]

Datasheet, Volume 2 355 Intel ® QuickPath Architecture System Ad dress Decode Register Description 3.6.6 SAD_DRAM_RULE_0, SAD_DRAM_RULE_1, SAD_DRAM_RULE_2, SAD_DRAM_RULE_3, SAD_DRAM_RULE_4, SAD_DRAM_RULE_5, SAD_DRAM_RULE_6, SAD_DRAM_RULE_7 This register provides the SAD DRAM rule s. Address Map for package determination. Device: 0 Function: 1 Offs[...]

Intel ® QuickPath Architect ure System Ad dress Decode Register Description 356 Datasheet, Volume 2 3.7 I ntel ® QPI Link Registers 3.7.1 QPI_QPILCL_L0, QPI_QPILCL_L1 This register provides Intel QPI Link Control. Device: 2 Function: 0 Offset: 48h Access as a Dword Bit Type Reset Value Description 31:22 RV 0 Reserved 21 RW 0 L1_MASTER This bit in[...]

Datasheet, Volume 2 357 Intel ® QuickPath Architecture System Ad dress Decode Register Description 3.8 Intel ® QPI Physical Layer Registers 3.8.1 QPI_0_PH_CPR, QPI_1_PH_CPR This is the Intel QPI Physical Layer Capability R egister . Device: 2 Function: 1 Offset: 68h Access as a Dword Bit Ty pe Reset Value Description 31:30 RV – Reserved 29 RO ?[...]

Intel ® QuickPath Architect ure System Ad dress Decode Register Description 358 Datasheet, Volume 2 3.8.2 QPI_0_PH_CTR, QPI_1_PH_CTR This is the Intel QPI Physical Layer Control R egister . Device: 2 Function: 1 Offset: 6Ch Access as a Dword Bit Type Reset Value Description 31:28 RV 0 Reserved 27 RW 0 LA_LOAD_DISABLE This bit disables the loading [...]

Datasheet, Volume 2 359 Intel ® QuickPath Architecture System Ad dress Decode Register Description 3.8.3 QPI_0_PH_PIS, QPI_1_PH_PIS This is an Intel QPI Physical Layer Initialization Status R egister . § § Device: 2 Function: 1 Offset: 80h Access as a Dword Bit Ty pe Reset Value Description 31:30 RV – Reserved 29 RO – GLOBAL_ERROR Set upon a[...]

Intel ® QuickPath Architect ure System Ad dress Decode Register Description 360 Datasheet, Volume 2[...]