Adaptec AIC-6915 manual

Document Title: ABA-1030 D VB Satellite Receiver Stock Number : 512130-00 , Re v . A Cov er-1 Print Spec N umber : 497767-00 , Re v . AA Current Date: 1 0/10/98 Pr ogra mme r’ s Man ual AIC-69 15 Ethernet LAN Co ntr oller R[...]

Document Title: ABA-1030 D VB Satellite Receiver Stock Number : 512130-00 , Re v . A Cov er-2 Print Spec N umber : 497767-00 , Re v . AA Current Date: 1 0/10/98 Adaptec, Inc. 691 Sout h Milpi t as Boul e vard Milpitas, CA 95035 © 1998, Adaptec, Inc. All rights reserved . Adaptec and the Adaptec logo are r eg ister ed trademarks of Adaptec, Inc. Pr[...]

Do cument Title: Document Title Stock Nu mber: xxxxxx- xx Rev. x Page: F ro n t Matter-i Print S pec Numb e r: xxx xxx-xx Rev. x Cu rrent Date: 10/10/98 ECN Dat e: xx/xx/xx ▼ ▼ ▼ ▼ ▼ AIC-6915 Ethernet LAN Contr oller Pr ogrammer’ s Manual R[...]

ii Document Titl e: Document Titl e Stock Number: x xxxxx-xx Rev. x Page: Front Matte r-ii Print Sp ec Number: xxxxx x-xx Rev. x Current Date: 10/10/98 ECN Date: xx/x x/xx Copyri ght © 1998 Adaptec, I n c. All rights r eserved. No part o f this publ ication may be r eproduced, stored in a r etrieval system, or tran sm itted in an y for m or by any[...]

iii Document Title: AIC-6915 Ethe r net LAN Control ler Progra mmer’ s Manu al Stoc k Number: xxxxx x-xx Re v . x P age: F ront Matter -iii Print Spe c Number: xxxxxx-x x Re v . x Current Date: 1 0 /10/98 ECN Date: xx/xx/ xx ▼ ▼ ▼ ▼ Contents 1 Intr odu ction Feature s 1-2 Genera l 1-2 Ethernet 1- 2 DMA 1-2 Intern al Buffe r Managem en t 1[...]

iv AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual 4 PCI Module Arc hitectur e Feature s 4-1 PCI Bl ock D iagra m 4-3 PCI Mast er Module 4-4 64-bit PCI Bus Master 4-5 Arbi tratio n 4-6 PCI T arget Module 4-6 Po wer Management 4-8 CardBus 4-9 Retry Func tion 4-9 Response t o PCI Commands 4-9 Conf iguration Ad dress Spac e 4-11 I/O Addres [...]

v Cont ents Document Title: AIC-6915 Ethe r net LAN Control ler Progra mmer’ s Manu al Stoc k Number: xxxxx x-xx Re v . x P age: F ront Matt er-v Print Spe c Number: xxxxxx-x x Re v . x Current Date: 1 0 /10/98 ECN Date: xx/xx/ xx 7 Register Descriptio ns Over view 7-1 AIC-6915 Addr ess Space 7-2 AIC-6915 PCI Address Map 7-2 T erminol ogy 7-4 AIC[...]

vi AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual T ransmit Buf fer Descript or T ypes 8-18 T wo T ransmit Queues 8-20 T ransmit Produ cer -Consumer Model 8-20 T ran smit Initia li zatio n 8-21 T ransmit Ha ndling 8-25 T ransmit Compl etion Interr upt Handling 8-27 AIC-6915 DDK Fea t ures 8-29 DDK De velopment En vironment 8-30[...]

vii Document Title: Docume nt Title Stoc k Number: xxxxxx-x x Re v . x P age: F ront Matter-v ii Print Spe c Number: xxxxxx- xx Re v . x Current Date: 1 0 /10/98 ECN Date: xx/xx/ xx Figure ▼ ▼ ▼ ▼ Figures 1-1 AIC-6915 Block Diagram 1-5 2-1 The AIC-6915 Recei ve Data Structures 2-2 3-1 T r an smit Host Commu ni cation Data Structure 3 -4 4-1[...]

Document Title: Docume nt Title Stoc k Number: xxxxx x-xx Re v . x P age: F ront M atter- viii Print Spe c Number: xxxxxx- xx Re v . x Current Date: 1 0 /10/98 ECN Date: xx/xx/ xx[...]

ix Document Title: AIC-6915 Ethe r net LAN Control ler Progra mmer’ s Manu al Stoc k Number: xxxxx x-xx Re v . x P age: F ront Matter -ix Print Spe c Number: xxxxxx-x x Re v . x Current Date: 1 0 /10/98 ECN Date: xx/xx/ xx Table ▼ ▼ ▼ ▼ Ta b l e s 2-1 Receive Buffer Descriptor ( One-size, 32-bit Addressing) 2-4 2-2 Receive Buffer Descript[...]

x AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual Document Title: AIC-6915 Ethe r net LAN Control ler Progra mmer’ s Manu al Stoc k Number: xxxxx x-xx Re v . x P age: F ront Matt er-x Print Spe c Number: xxxxxx-x x Re v . x Current Date: 1 0 /10/98 ECN Date: xx/xx/ xx Table 7-10 Bas eClas s R egiste r 7-10 7-11 Cache Line Size Register[...]

xi Ta b l e s Document Title: AIC-6915 Ethe r net LAN Control ler Progra mmer’ s Manu al Stoc k Number: xxxxx x-xx Re v . x P age: F ront Matter -xi Print Spe c Number: xxxxxx-x x Re v . x Current Date: 1 0 /10/98 ECN Date: xx/xx/ xx Table 7-53 TxDmaS tatus2 Reg ister 7-42 7-54 TransmitFrameControlStatus Register 7-42 7-55 Co m pQueu e HighA dd r[...]

xii AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual Document Title: AIC-6915 Ethe r net LAN Control ler Progra mmer’ s Manu al Stoc k Number: xxxxxx-x x Re v . x P age: F ront Matter-x ii Print Spe c Number: xxxxxx- xx Re v . x Current Date: 1 0 /10/98 ECN Date: xx/xx/ xx Table 7-97 TxNi bbleCnt Regi ster 7- 76 7-98 TxByteCnt R egister[...]

1-1 1 ▼▼▼▼ Intr oduction The Adaptec AIC-6 915, PCI 10/100 Et hernet LAN Contr oller pro vide s advanced Etherne t adapter featur es in a single chip optimized for high-performance and cost effective Ethernet NICs (Network Interface C ar ds). The AIC-6915 integrates all the f unctions nec essary for an E thernet PCI adapter to dir ectly con[...]

1-2 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual Features General ■ Supports four general purpose I/Os that can be pr ogrammed separately as inputs, outputs, o pen-drain outputs or , interrupt inputs ■ Interface to a n external, 8-bit Boot ROM wi t h a maxim um size of 256-K Byte ■ Supports dynami c system bus (PCI) clo ck where[...]

1-3 Int roducti on ■ Supports 32- and 6 4-bit addr essing of Host DMA buf fers and DMA descriptor queues ■ Big/Little endian support for data and des criptors ■ Special output pin to indica te high-priority P CI re quest Inte rnal Buf fer Man ag e ment ■ Lar g e, 8 KByte DMA FIFO (default - 4KByte for transmit, 4-KByte for r eceive) ■ Pro[...]

1-4 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual – Memory W rit e And Invalidate ■ Supports PCI bus address an d data parity generation and checking ■ Supports PCI PERR and SERR req uirem ents ■ Supports 8-bit, 256-KByte, external Mem ory port for interface with external Bo ot ROM or devices/re g isters ■ Supports externa l [...]

1-5 Int roducti on Bloc k Dia gra m Figure 1- 1 is a blo ck diagram of the A IC-6915. 8 KByte SRAM Comb ined Tx/Rx FIFO PCI BusAcce ssContro l SlaveA ccess , system registers ( Sla ve) (Master) MA C ( T rans mit ) ( Receive ) Data (8) Status Status (32 bits ) (64 bits) PCI Bus (64-b its) EPROM Serial Po r t EPROM DMA Bus (64-bi ts ) FIFO Bus (32-bi[...]

1-6 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual Modules The AIC-6915 con tains the following major mo dules: ■ PCI - Contr ols access to the PCI bus and contains PCI-specific r egis ters. ■ BusAccessControl - Arbitrates master accesses to the PCI bus fr om internal modules, and accesses the F IFO fr om the PCI side. ■ SlaveAcce[...]

2-1 2 ▼▼▼▼ Receive Ar chitectur e Features The host-r elated Receive Architectur e features ar e ■ Interrupts may be delayed so that onl y one interrupt is generated when a g r oup of frames is received ■ Choice of shar ed or separate completion lists for r eceive and transmit. An optional second completion list can be u sed for high-pr[...]

2-2 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual ■ VLAN support: – Addr es s filtering based on VLAN – Ability to delete VLA N tag and number from frame returned to the host ■ Optional second buf fer list for allocating two diff erent buffer s izes Host Data St ructures Figure 2-1 illus trates the AIC-69 1 5 r eceive dat a str[...]

2-3 Receive Architecture A pro grammable number of word s can be skipped between buf fer descriptors. This allows the driver to store data related to a buf fer . When using 64-bit addr essi ng, all descriptor and com pl etion q ueues must be con tained in the same 32-bit addr ess space. Descriptor queues must be align ed to a 256-byte boundary . Wh[...]

2-4 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual 32-bit Ad dressing Mod e 64-bit Ad dressing Mode Descriptor Fields: ■ Addre ss - Th e ad dress of the b uffer . ■ LowAddress - Least-significant 3 2-bits of addr ess. ■ HighAddress - Mos t-significant 3 2-b i ts of address. ■ E / End - This bit is set to indicate the last descri[...]

2-5 Receive Architecture Acceptin g fram es The AIC-6915 uses two cr iteria when deciding whether to accept a frame: Fr ame addr ess and frame qua lity . Wh en receiving a frame, the Station A ddress block eval uates a frame’s address to de term i ne if this stat i on sh ould rece ive t h e fra me. A ddres s filt e rin g is accomplished by the ti[...]

2-6 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual T able 2-3. Shor t (T yp e 0) C om ple tion E ntr y 31 24 23 1 6 15 8 7 0 01 S t a t u s 1 E n d I n d e x L e n g t h T ab le 2-4. Basic (T ype 1) Comple tion Descriptor 31 2 4 23 1 6 15 8 7 0 01 S t a t u s 1 E n d I n d e x L e n g t h Stat u s 2 VLA N ID T able 2 -5. Check sum (T yp[...]

2-7 Receive Architecture T able 2 -7. Receiv e Complet ion Descriptor (W ord 0) Bit( s) Description/Fu nction St atus1 field 29 OK - The frame is good. There were no CRC error s, dribble nibble, illegal lengths, or re c eive code violations . In ISL mode, the ISL and Et hernet c hecksums must b oth be valid. T his does no t include the TCP/UDP chec[...]

2-8 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual T able 2 -8. Receiv e Complet ion Descriptor (W ord 1) Bit(s) Descriptio n/Function Status2 fiel d 31 Perfect - destination a ddress mat c hes on e of the 16 pr edefined “perfe c t” addresses . 30 Hash - hashed des tinatio n addr ess mat ches a bit s et in the ha sh table 29 CRC Err[...]

2-9 Receive Architecture The AIC-6915 pr ovides address filters that h ave an ef fect on which re ceive frames ar e accepted and how they are pr oces sed. For mor e information on address filtering, refer to Address Filte ring Reg i st ers on pag e 7-82 . ❒ T able 2 -9. Receiv e Complet ion Descriptor (W ord 2) Bit( s) Description/Fu nction P art[...]

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3-1 3 ▼▼▼▼ T ransmit Ar chitectur e Features The main fe atur es of T ransmit Ar chitecture ar e ■ T wo Buff er Descriptor Queues in the Host Memory . One for h i gh-priority packets and one for low- priority packets. ■ Driver notifies the transm it blo ck to start transmi tting packets by writin g the “Pro ducer Index” of descripto[...]

3-2 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual ■ Ther e are thr ee kinds of interrupts generated by the transmit DMA engine. A “TxDmaDoneInt” is generated when the entire packet is DMA-transferr ed. A “TxFrameCompleteInterr upt” is generated when an entir e packet is transmitted. Ther e are two con trol bits, DisableTxDmaC[...]

3-3 T ransmit Architecture ■ When the amoun t of packet data in the FIFO exceeds the “T ransmit Thr eshold,” or when the end of packet is alr eady in the FIFO, the “T ransmit Frame” state machine signals the MAC to start transm itting the packet. The transmit frame block han dles reading packets from the FIFO, MAC interface and FIFO link [...]

3-4 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual T ransmit Data Struct ure Figure 3-1 illustrates the T ransmit D ata Structur e Pkt 2 Buf3 CI PI Buff er Descriptors f or Hi-P r ior ity Buff er Descriptors f or Lo-P r ior ity P acket Data Buff ers Completion Queue Status CI Host Memory the AIC-6 915 High-Prior ity CI PI Low-Priority C[...]

3-5 T ransmit Architecture T ransmit Registe r Set The following is a list of transmit param eters program m ed by the driver d uring initializ ation. ■ T ransmit descriptor queue size and base addr ess. ■ Completion queue size and base addr ess. ■ Descriptor type, minimum spacing, and skip field size. ■ FIFO size (4KBy tes). ■ PCI cache [...]

3-6 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual ■ ID : 4 bits. This field is used by the software/debugger to identify the start o f a descriptor . If a transmit DMA operation does not see a matched ID in this field, it aborts the DM A operation and sets an interrupt sta tus bit. ■ Number of Fragments : 8 bits. Defines the number[...]

3-7 T ransmit Architecture ■ INTR : Ca uses s etting of the interrupt status bits (TxDm aDoneInt and/or TxFrameCompleteInt) after complete tran smis sion of the entir e packet. The appropriate interrupt status bit is set based on two control bits that the software programs at the initializat ion phase. Given ‘ INTR ’ is set the following tabl[...]

3-8 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual ■ T otal Packet Length : This 16-bit field defines the total packet length. If this field is zer o, it is ignored and the t otal packet length is equal to the sum of all the buf fers. If this field is nonzer o, it is defined a s the total packet length. Note: In Nove ll TCB/ECB bl ock[...]

3-9 T ransmit Architecture T ype 3, 32-bi t Addressing Mode (Frame Descriptor) This mode is curr ently not supported in the AIC-6915. T ype 4, 32-bit Add r essing Mode (Frame Descriptor) T ype 4 enables the driver to execute a simple and fast copy of DOS and O S2 data structur e (given by the upper layer softwar e as a frame descriptor) to the desc[...]

3-10 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual T ransmit Completi o n Queue Ent ry T ransm it Completion Q ueue entries consist of two types: DMA Com p lete Entry a nd T ransmit Complete Entry , d if feren tiated by the MSB of the entry . Thr ee bits are defined in the “T ype” field because the A IC-6915 always returns a nonzer[...]

3-11 T ransmit Architecture If the AIC-6915 is programmed to transmit two wo r d s (8 bytes), the second word (bit 63- 32) is the InterruptStatus register content. ■ Ty p e -3 bit. Always 3’b101 for T ransmit Complete Entry . ■ T ransmit Status - 13 bits. The bits are d efined as Bit 12: T ransmit previously paused. Bit 1 1: Pause control fra[...]

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4-1 4 ▼▼▼▼ PCI Module Ar chitectur e Features ■ Complian t with PCI Local Bus Specifica tio n, Revision 2.1 ■ Complian t with Intel PCI Bus Po wer Ma nagement Interf ace S pecification Rev 1 .00 and Micr osoft Device Class Power Management Ref erence Specification (OnNow) ■ PC 97 rea dy . Implements all har dwar e features r equired b[...]

4-2 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual ■ Supports PCI PERR and SERR r equirements. ■ Supports 8-bit, 256-KByte, external Memory port for interfa ce with external Boot ROM or devices/re g isters. ■ Supports external Boot R OM access fr om mem ory or Expansion ROM addr ess spa ce. ■ Supports an external I 2 C serial EE[...]

4-3 PCI Module Architecture PCI Bloc k Diagram Figure 4-1 is a PCI block diag ram . TGTDPU TGTCTL DECODER PCI Module BAC Bus A ccess PCIM ST Pcimas ter Logic Data path Lo gic control logi c Addres s Dec ode r PCI_P ADS PCI_T OP BUFOUTFLOPS / OUTFLOPS PCIT GT Control Serial EPR OM Memory P or t Interf ace EEPROM CNTL BOO TRO M CTL SA C Sla ve Access[...]

4-4 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual PCI Master Modu le The PCI master transfers da ta to/fr om system memory . Theref or e, the AIC-691 5 never generates PCI transactions for In terrupt Acknowledge, Special Cycle, I/ O space, or Configuration space. The PCI ma ster generates all Memory space comma nds, and uses the option[...]

4-5 PCI Module Architecture 64-bit PCI Bus M as ter The AIC-6915 supports a 64 -bit P CI bus master and perform s 64-bit data transfers with a 64-bit tar get. If the r esponding target is a 3 2-bit device, the lower 32-bit of addr ess bus is used. The RE Q64_ signal is used to determine whether the system supports a 64 -bit data path. A pull-up re [...]

4-6 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual Arbitrat ion The AIC-6915 drives AD[3 1:00] during 32 -bit tran sfers an d AD[6 3:0] during 64-bit transfers. CBE[3:0] _ are asserted on the first PCLK when GNT_ is sampled asserted and the PCI bus idle. PA R and PA R 6 4 ar e asserted one PCLK later . The AIC-6915 also asserts FRAME _ [...]

4-7 PCI Module Architecture The value of BR_A1 pin is sampled when PCI reset is active to determin e if the serial EPROM data ( BR_ A1 =1) or the defa ult values ( BR_A1 =0) should be used fo r ■ V endor ID [7:0 ] ■ V endor I D [15: 8] ■ Device ID [7:0] ■ Device ID [15: 8] ■ Sub Class [7:0] ■ Base Class [7:0] ■ SubSystem V endor ID [7[...]

4-8 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual P ower Management The PCI bus power management defined f o ur power states. D0 indicates the “On” state, D3 indicates the “Of f” state, and D1 and D2 r epresent power managed states. In the AIC-6915, thr ee states are supported. D 0 and D3 ar e requir ed states and D2 is an opti[...]

4-9 PCI Module Architecture CardBus Card Bu s is the interface between a PC car d and a portable device which has 32-bit bus mastering capabilit y . The CardBus interface is based on the PCI interf ace with lower po wer consumption, additional signals and r egisters supp orted. Ther e ar e four 32-bit Car dBus registers. The fo llowing events must [...]

4-10 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual T able 4-2 lists a ll 1 6 PCI commands and the corresponding AIC-6915 response. T able 4 -2. T arget Res ponse to PCI Com m ands CBE[3:0]_ Com mand Abbrev . AIC-6915 Resp onse to Com mand 0000 Int errupt Ackno wledge Ignored 0001 Special Cycle Ignor ed 0010 I/O Read IORD Supports IORD [...]

4-11 PCI Module Architecture Configura tion Addre ss Space The AIC-6915, as a si ngle function tar get, supports type 0 addr ess space accesses with a single configuration space. As a tar get, the AIC-6915 uses positive addr ess decoding over AD[07: 02] al ong with CBE [3:0]_ (command is CRDC o r CWRC), IDSEL, AD[01:00] = 0 H an d FRAME_ to validat[...]

4-12 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual Expansion ROM Ad d ress Space When in t arg et mode, t he AIC-6915 allows access to an 8-bit ROM/EEPROM (connected to the External M emory Interface po rt) through the expan sion ROM addr ess space. Th e AIC-6915 uses positive addr ess decoding over EXROMCTL register (stor ed value), A[...]

4-13 PCI Module Architecture PERR_ The AI C-6915 asserts PERR_ for detected data parity err ors only if PERRESPEN is asserted. As a tar get device, t he AIC-6915 as serts PERR_ and sets the DPE bit active ( ST A TUS register in PCI Configuration header) for write cycles in which it detects a data parity erro r , only if it claims the access and ass[...]

4-14 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual Illegal Behavior As a tar get, when the AIC-6915 accepts a cycle (I/O, memory , configuration) which is addr ess ed to it and drives DEVSEL_ , it che cks the legality of the transaction a n d aborts under any of the f ollowing conditions: ■ The combinat ion of CBE[3: 0]_ in an I/O cy[...]

5-1 5 ▼▼▼▼ Frame Pr ocessor Ar chitectur e Features ■ Calculate the TCP and UDP checksum ■ Decode fra me type (TCP , UDP , ARP , RARP , IPX, W ake-up, VLAN 802 .1q, Ipv4, Ipv6, ICMP , Ethernet 2, IEEE 80 2/803) ■ Process Eth ernet 2, 802, IPv4, IPv6, TCP and UDP hea ders ■ Process r eceive data on-the-fly . The maximum r eceive buff[...]

5-2 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual ■ LC= 0, 1 o r 2, and E XC O N C LOCK is set, or ■ Read/W rite instruction is executed and the Input IOR EADY is sampled asserted. Note: E XC O N C LOCK is a bit in the instruct ion . The loop counter is decr emented by 2 every clock cycle if E XC O N C LO CK =1, or if D ATA V ALID [...]

5-3 Frame Processor Ar chitecture GFP Address Space A total of 25 6 addr ess locations can be accessed by the GFP executing Rea d/W rite instructions. The tar get addr ess is presented in the B RANCH A DD [7:0] field of the instruction. When executing a rea d or wr ite instruction, the GFP asserts G IFP R D /G FP W R , and drives G FP A DD [7:0 ] ,[...]

5-4 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual External Regis ters The external registers are used as a standard way to comm unicate with other modules. All defined external r e gist ers are write- only (from the GFPs point of view). They are used for pro vi ding information to external devices. The follo wing external addr ess es a[...]

5-5 Frame Processor Ar chitecture Bloc k Dia gra m Figure 5-1 is a block diagram of the Data P r ocess ing Unit. WR2[15:0] 8 Input Mux Barrel Sh ifter WR3[15: 0] Simple A LU: Mask Contro l Adder , Comparator ALU-Out[ 31:0] Instruct ion Loop Counte r WR1 WR 2 WR3 WR4 LC Input1 In put2 WR1[ 31:0] WR 4[15:0] Flag 8 Inpu t Mux Branch Logi c Instruct io[...]

5-6 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual Instru ction Format s T able 5-2 describes the Instruction Formats. T able 5-2. Inst ruc tion F or mats Name Bit Number Descriptio n Opcode 0 3:0 Exec ute - Execute i n struction as s pec ified by cont rol fie lds Opcode 1 3:0 BrT oIm mIfT rue - Branch to im m ediate address s pecified [...]

5-7 Frame Processor Ar chitecture Opcode A 3:0 CheckI pv6NextHea der - Special instruction for checking the Next Header field. T he GFP recogni z es 8 types of extensi on headers implemented in har dware, iden tified by th e followin g Next Header ident ification number: T cpProtocolI d = 8'd 6; UdpPro tocolId = 8 ' d17; HopByHopPr ot oco[...]

5-8 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual Opcode E 3:0 Return - Return to main pro gram. When branching from the main progr am, the next instruction pointer value of the main program is saved in a special r egister . When executing this command, the information stor ed in the special r egister is used as t h e next instruc t io[...]

5-9 Frame Processor Ar chitecture ❒ MuxSelInput1 [29:17] Controls the 8 input mux operation at ALU input 1 ‘ 0 ’ - Dat a ‘ 1 ’ - WR1[15:0 ] ‘ 2 ’ - WR2 ‘ 3 ’ - WR3 ‘ 4 ’ - Statu s[31:16 ] ‘ 5 ’ - Statu s[15:0] ‘ 6 ’ - Fram eC nt ‘ 7 ’ - WR1[31:1 5] AluCt rl [23:2 0] ‘ 0 ’ - NOP (Out put=Inpu t2, Fl ag=F alse) ?[...]

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6-1 6 ▼▼▼▼ AIC-6915 Internal Registers Summary For the follo wing registers, the ‘Byte A ddr ess’ indicates each registers lo cation in mem ory space given as a byte of fset address fr om the start of the memory space dedicated for internal registers - 0x50 000h. PCI Config uration Header Reg is ters Summary The PCI configuration regist[...]

6-2 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual AIC-6915 Fu nctional Re gisters Summar y Mapped to addr ess range 0x50040-0x5 00FF in memory space, addr ess 0x40-0xFF in configuration space a n d address 0x40 -0xFF in I/O space. Th ese r eg isters ar e read/write and can be accessed using Memory , I/O, and Con fig uration comman ds. [...]

6-3 AIC-6915 Int ernal Registers Summar y 00B4 CompletionQueueHighAddr Completion queue contr ol and configuration reg is te r s 00B8 TxCompletionQueueCt rl 00BC RxCompletionQueue1Ctrl 00C0 RxCompletionQueue2Ctrl 00C4 CompletionQueueConsumerIndex 00C8 CompletionQueuePr oducerIndex 00CC RxHiPrCompletionPt rs 00D0 RxDmaCt rl Receive DMA control, conf[...]

6-4 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual Ad dit ional PCI Register s Summary Mapped to addr ess range 0x50FFF-0x50100 in Memory space. These registers can be accessed using memory or indire ct I/O commands. Ad dit ional Ethern et Reg isters Summa ry Mapped to addr ess range 0x52000-0x5 4FFF in memor y space. These ar e read/wr[...]

6-5 AIC-6915 Int ernal Registers Summar y ❒ 500C No nBkT oBk IPG 5010 ColR etry 5014 Ma xLength 5018 TxN ibb leCnt 501C TxB yteCnt 5020 Re TxCn t 5024 Ra ndomNumGe n 5028 Msk RandomNu m 502C-5 033 Reserved 5034 T otalT xCnt 5040 RxB yteCnt 5060 TxPauseT imer W riting to this r egister will ca use a flow-cont rol frame to be tran smitted with the [...]

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7-1 7 ▼▼▼▼ Register Descriptions Overview This section includes a ll the r e g isters r equired for contr olling, programming , and operating the AIC-6915. All r egisters throughout this section subscribe to the following format. T able 7- 1. Shad e Lege nds These bit s or fields a re un der softwar e contr ol. They may be pr ogrammed by so[...]

7-2 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual AIC-6915 Ad dress Space A device on a PCI bus can be accessed using di f feren t PCI comm and t ypes. The AI C-6 915 can be accessed using Memory , I/O and Conf i guration comm ands. The 512-KByte address space is mapped to a base address defined by the operating system at boot time. Th[...]

7-3 Register Des criptions (E)EPRO M R/W Inter nal registers Exter nal regist ers 0x00000 0x40000 (64KByte words (256KBytes)) (~16K words ( ~64KBytes)) (16K words ( 64KBytes)) 0x50000 0x60 000 0x7FFFF (PCI cloc k domain) (PCI clock doma in) Reser ved Memor y Mapped and Indirect I/O Mapped Memor y /Config/ 512K PCI Address Map 64K I nternal Regist e[...]

7-4 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual T erm in ology Thr o ughout this chapter , data values are d efined as follows: ■ Byte = 8 bits ■ Halfword = 16 bits ■ W or d = 32 bits ■ Doubleword = 64 bits AIC-6915 I nternal Reg i ster s These r eg isters ar e used by the software driver for configuration, control, and r etr[...]

7-5 Register Des criptions PCI Registers PCI Configuration Head er Registers At the deassertion edge of the PCI r eset, the AIC-6915 starts r eading the serial EPROM. At the same time, the BR_A 1 input is sampled. If the boar d has a pull-up on this pin, the AIC-6915 r eplaces the default value of the following PCI configuration h e ader registers:[...]

7-6 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual PCI Comm and Regis t er T ype: R/W Internal Registers Subgr o up: PCI Configuration Header Byt e Ad dres s: 04h - 05h T able 7 -5. PCI Command Register Bit (s) rw Reset V alue De scription/Function 15: 10 r 0 Alwa ys r ead as 0. 9r 0 MFBTBEN: Ma ster Fa st Back-T o-Back Enable. When act[...]

7-7 Register Des criptions PCI Status Re gister T ype: R/W Internal Registers Subgr o up: PCI Configu ration Header Byte Addres s: 06 h - 07h The ST A T US register is used to recor d status information for PCI bus related events. Read transactions of the ST A TUS register access the curr ently stored s tatus informatio n. W rit e transactions to t[...]

7-8 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual 11 r / w 0 ST A: Signal T arget Ab ort is set by the tar get of a PCI bus trans action if it is unable to r espond due to a fatal err or conditio n. ST A is set ina ctive during and after assertion of PCI_PCIRST_ or by a wri te to th e ST A TUS r egister with bit 1 1 (=1). T he AIC-691 [...]

7-9 Register Des criptions PCI DEVREVID (Device Revision ID) Register T ype: R Internal Registers Subgr o up: PCI Configu ration Header Byte Addres s: 08 h PCI Proginfc (Program Interface) Register T ype: R Internal Registers Subgr o up: PCI Configu ration Header Byt e Ad dres s: 09h PCI Subclass Registe r T ype: R Internal Registers Subgr o up: PC[...]

7-10 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual PCI Baseclass Register T ype: R Internal Registers Subgr o up: PCI Configu ration Header Byte Addres s: 0B h PCI Cachesiz e (Cache Line Siz e) Registe r T ype: R/W Internal Registers Subgr o up: PCI Configu ration Header Byte Addres s: 0C h The Cache Size register specifies the system [...]

7-11 Register Des criptions PCI Hdr type (H eader T ype) Regist er T ype: R Internal Registers Subgr o up: PCI Configu ration Header Byte Addres s: 0E h BIST (Built -in Self T est) Re gister T ype: R Internal Registers Subgr o up: PCI Configu ration Header Byte Addres s: 0F h PCI LowB ASEADR 0 (Base Addr ess 0) Regist er T ype: R/W Internal Registe[...]

7-12 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual PCI HighBASEADR0 (Base Address 0) Register T ype: R/W Internal Registers Subgr o up: PCI Configu ration Header Byte Addres s: 14 h - 17h Note : When an access is made to an addr ess that is mapped and enabled in both the BASEADR0 and EXR OMCTL registers, the PCI responds with a t ar g [...]

7-13 Register Des criptions PCI Su bSys temV e ndor ID Re giste r T ype: R Internal Registers Subgr o up: PCI Configu ration Header Byte Addres s: 2C h - 2 D h PCI SubSystem ID Regis ter T ype: R Internal Registers Subgr o up: PCI Configu ration Header Byte Addres s: 2E h - 2 Fh PCI EXPROMC TL (Expansi on RO M Control) Register T ype: R/W Internal [...]

7-14 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual PCI CapPtr (Capabiliti es List P ointer) Register T ype: R/W Internal Registers Subgr o up: PCI Configu ration Header Byte Addres s: 34 h PCI INTLINSEL (Interru pt Line Select) Register T ype: R/W Byte Addres s: 3C h T ab le 7-21. Expan sion R OM Control Regi ster Bit(s) rw Reset V alu[...]

7-15 Register Des criptions PCI INTPINSEL (Interrupt Pin Select ) Register T ype: R Internal Registers Subgr o up: PCI Configu ration Header Byte Addres s: 3D h PCI MINGNT (Minim um Grant) Register T ype: R Internal Registers Subgr o up: PCI Configu ration Header Byte Addres s: 3E h T ab le 7-24. Interrupt Pin Se lect Regis ter Bit(s) rw Reset V al[...]

7-16 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual PCI MAXLA T (Maximum Latency) Register T ype: R Internal Registers Subgr o up: PCI Configu ration Header Byte Addres s: 3F h T able 7- 26. Maxim um Latency Reg ister Bit(s) rw Reset V alu e Desc ripti on/Fu nctio n 7:0 r 06h MAXLA T[7:0]: Always read as 06 h. The M aximum La tency reg [...]

7-17 Register Des criptions PCI Functional Registers Definition The following re g isters ar e accessible from PCI con f igu ration, memory and di r ect I/O space. PCIDeviceConfig Register T ype: R/W Internal Regi sters S ubgroup: PCI Functio nal Registers Byte Addres s: 40 h - 43h T able 7-27 . PCID e vic eConf ig Re giste r Bit(s) rw Reset V alue[...]

7-18 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual 18:1 6 r /w 000 EpromCsW idth: Indicates the width of t he EPROM chip-select. ‘000’ - 8 PC I cl ocks ‘1 1 1 ’ - 7 PCI clocks ‘1 10’ - 6 PCI cloc ks ‘101’ - 5 PC I cl ocks ‘100’ - 4 PC I cl ocks ‘01 1’ - 3 PCI cloc ks All other comb inations a re res erved. 15 r/[...]

7-19 Register Des criptions 6r / w0 StopOnPe rr: Specifies the beha vior of the PCI master when a data parity error is en c ountered dur ing an active DMA ope ration. If the bit is asserted, the PC I master stops the transfer as soon as it detects/r eceives a data parity er r or . The PCIMstDmaEn , TxDmaEn and Rx DmaEn bits ar e r eset, and dri ver[...]

7-20 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual BacControl Re gister T ype: R/W Internal Regi sters S ubgroup: PCI Functio nal Registers Byt e Ad dres s: 44h - 47h This re g ister pr o vides the softwa r e driver a way to configur e and contro l BAC DMA operation. T able 7-28 . Bac Cont rol Re giste r Bit(s) rw Reset V alue Descript[...]

7-21 Register Des criptions PCIMonitor1 Reg ister T ype: R Internal Regi sters S ubgroup: PCI Functio nal Registers Byte Addres s: 48 h - 4Bh 1r / w0 P REFER R X D MA R EQ : Controls B A C’ s arbitration alg o rithm. If the bit is set and P REFER T X D MA R EQ is cleared, the rece ive DMA request has priority over transmit DMA data request, othe [...]

7-22 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual PCIMonitor2 Reg ister T ype: R Internal Regi sters S ubgroup: PCI Functio nal Registers Byte Addres s: 4C h - 4 Fh PMC (P ower Managem ent Capabiliti es) Register T ype: R/W Internal Regi sters S ubgroup: PCI Functio nal Registers Byte Addres s: 50 h - 53h T able 7 -30. PCI Monitor2 Re[...]

7-23 Register Des criptions PMC SR (P owe r Mana gement Contr ol/Sta tus) Regi ster T ype: R/W Internal Regi sters S ubgroup: PCI Functio nal Registers Byte Addres s: 54 h - 57h 18:1 6 r 1h PMV ersion : This fiel d indicates that t h ere ar e 4 byte s of Ge neral Purpose Power Ma nagement r egisters implemented as described in r evision 1. 0 of the[...]

7-24 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual PME Event Register T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byte Addres s: 58 h- 5B h Serial EEPROMC ontr olStatu s Register T ype: R/W Internal Regi sters S ubgroup: PCI Functio nal Registers Byte Addres s: 60 h - 63h T able 7-33. PM E Ev ent Register Bi[...]

7-25 Register Des criptions EEPRO M Memory Definition T ab le 7-35. EEPROM Memor y Definiti on Byte Address Descriptio n/Function V alue 0 V endor ID [7:0] 04 1 V en dor ID [ 15:8] 90 2 Device ID [7:0] 15 3 Device ID [15:8] 69 4 SubClass [7:0] 00 5 Bas e Class [7:0] 02 6 SubSystem V endor ID [7:0] 04 7 S ubSystem V endor I D [15:8] 90 8 SubSystem D[...]

7-26 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual PCIComplianceT estin g Register T ype: R/W Internal Regi sters S ubgroup: PCI Functio nal Registers Byte Addres s: 64 h - 67h This r egister is used for PCI compliance checker testing purposes only and has no meanin g to the AIC-6915 .. IndirectIoAddress R egister T ype: R/W Internal R[...]

7-27 Register Des criptions Ethernet Registers The following re g isters ar e accessible from PCI con f igu ration, memory , and dir e ct I/O space. They ar e all synchro nized to the Ethernet T ransmit clock. General Ethernet Fu nctional Registers Gener alEt her netCtrl Regi ster T ype: R/W Internal Registers Subgr o up: Ethernet Functional Regist[...]

7-28 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual Tim ersC on trol Reg is ter T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byte Addres s: 74 h - 77h T ab le 7-40. TimersContro l Register Bit(s) rw Reset value Description/Funct ion 31 r/w 0 EarlyRxQ1IntDe layDisable: Wh en set, the in terrupt ma sking timer h[...]

7-29 Register Des criptions 12 r/w 0 RxHiPrBypa ss : I f this bi t is set, by pass the inte rrupt mas king timer when g enerating RxDoneInt aft er DMA-tran sferring the completion des criptor of a hig h-priority frame. 11 r / w 0 Ti m e r 1 0 X : Enables the softwar e to easi ly scale th e T imerClock period by a fac tor of 10 to ma tch a 10 Mb its[...]

7-30 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual The following interrupts are affe cted by the mask ing time: ■ RxQ1Don eInt ■ EarlyRxQ1Int ■ RxQ2Don eInt ■ EarlyRxQ2Int ■ TxDmaD oneInt ■ TxQueueDoneInt ■ TxFrameCompleteInt CurrentTime Reg ister T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byt[...]

7-31 Register Des criptions InterruptStatus Re gister T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byt e Ad dres s: 80h - 83h This register stores the interrupt vector which indicates th e interrupt source . Some of the bits in the register are clear ed on a read, while others mus t be cleared at the source. All ‘cleare[...]

7-32 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual 19 r/w 0 DmaErrInt: This b it is set on a DMA err or . The DMA err ors ar e: T arget abort, Mas ter abort, Data parity err or (with S TOP O N P AR E RR bit set) , and bad de scripto r . This bit i s cleared on a read, or by writin g a ‘1’. 18 r/w 0 TxDataLowIn t: This b it is set w[...]

7-33 Register Des criptions 10 r/w 0 EarlyR xQ1I nt: This bit is s et after the DM A tra nsfer of a programmable numbe r of bytes of a received fr a me. The programmabl e numb er is defi ned by RxEarlyIntThreshold. No stat us is D MA- transfe rred at t his time. T he Rx Q1Done Int inte rrup t is genera ted when the whole frame is DMA-transferred. A[...]

7-34 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual ShadowInterruptStatus Regi ster T ype: R Internal Registers Subgr o up: Ethernet Functional Registers Byt e Ad dres s: 84h - 87h This r egister is used for r eading the Interrupt Status r egister in read-only mode. I n this mode the interrupt status bits that ar e defined as ‘clear e[...]

7-35 Register Des criptions Inte rruptEn R egister T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byt e Ad dres s: 88h - 8Bh Specifies if the corresponding bi t in I NTERRUPT S TATUS register is enabl ed, causing an external PCI interrupt. The PCI interr upt bi t must be enabled in the PCID EVICE C ONFIG register . T ab le [...]

7-36 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual GPIO Register T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byt e Ad dres s: 8C - 8F h The GPIO r egis ter pr ovides for ho s t softwar e control of the GP IO[3:0 ] pins. T able 7 -45. GPIO Registe r Bit(s) rw Re set V alue Description/Function 31:28 r 0 Reser[...]

7-37 Register Des criptions T ransmit Register s TxDescQueueCtrl Register T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byt e Ad dres s: 90h - 93h T able 7-46 . Tx D escQue ueCt rl Regist er Bit(s) rw Reset V alue Description/ Function 31:2 4 r /w 2 TxHighPriorityFifoThre s hold: Spe c ifies a pr ogrammable thr eshold. Whe[...]

7-38 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual Note: Maximum transmit descriptor que ue length 16-K Bytes for the high-priority queue and 16-KBytes for the lo w-priority queue. Priorities cannot be mixed within the same queue. Overall queue size is programmable by setting the “ E ND ” bit in the appr opriate descriptor field. 6[...]

7-39 Register Des criptions HiPrTxDescQueu eBaseAddr Register T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byt e Ad dres s: 94h - 97h LoPrTxDescQueueBaseAddr Reg ister T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byte Addr es s: 98h - 9Bh T ab le 7-47. HiPrTxD escQueue BaseAddress Re gister Bit([...]

7-40 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual TxDescQueueH ighAddr Register T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byte Addr es s: 9Ch - 9Fh TxDescQueueProducerIndex Register T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byte Addres s: A0 h- A 3 h T able 7 -49. TxDescQ ueu[...]

7-41 Register Des criptions TxDescQueueCon sumerIndex Register T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byte Addres s: A4 h- A 7h TxDma Stat us1 T ype: R Internal Registers Subgr o up: Ethernet Functional Registers Byte Addres s: A8 h - ABh T able 7-5 1. TxDescQu eueConsumerI ndex R egister Bit(s) rw Reset V alue Desc[...]

7-42 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual TxDma Stat us2 T ype: R Internal Registers Subgr o up: Ethernet Functional Registers Byte Addr es s: ACh- AFh T ransmitFram eCtrl/Status R egister T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byte Addr es s: B0h - B3h T able 7 -53. TxDmaStatus2 Register Bit(s[...]

7-43 Register Des criptions Completion Queue Registe rs Note: All completion queues have a fixed size of 1 K Byte entries. Completi on Queu eHig hAdd r Reg ister T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byte Addr es s: B4h - B7h TxCompletio nQueueCtrl T ype: R/W Internal Registers Subgr o up: Ethernet Functional Regis[...]

7-44 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual RxCompletionQueue1C trl T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byt e Ad dres s: BCh - B Fh 4r / w0 Comm onQueueMode: Whe n this bit i s set, th e r e ceive compl etion queues ar e di sabled and all completi on descri ptor s and genera l chip status ar e[...]

7-45 Register Des criptions RxCompletionQueue2C trl T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byt e Ad dres s: C0h - C 3h 3:0 r/w 0 RxCompletionQ1 Threshold specif ies a thres hold equal to 4*RxCompletion Q1 Threshold . If RxComple tionQ1 ThresholdMode is ‘0’ and the number of empty entries in receive queue 1 is le[...]

7-46 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual Completi onQueueCo nsumerInd ex T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byt e Ad dres s: C4h - C 7h Note: A qu eue i s consi dered e mpt y if bo t h Q UEUE P RODUCER I NDEX and Q UEUE C ONSUM ER I NDE X ar e equal. The queue is consider ed full if the va[...]

7-47 Register Des criptions Completi onQueueProducerIndex T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byt e Ad dres s: C8h - C Bh RxHiPr CompletionPt rs T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byt e Ad dres s: CCh - C Fh T ab le 7-60. Co mpletionQueueP roducerInde x Regis ter Bit(s) rw Res[...]

7-48 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual Receive Register s RxDmaCtr l T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byt e Ad dres s: D0h - D 3h 9:0 r/w 0 RxCompletionQ2 ConsumerIndex: W r itten by softw are driver and r ea d by the AIC-6915. The s oft war e driver incr ements or writes a new ind ex [...]

7-49 Register Des criptions 22:2 0 r /w 0 RxDmaQueueMode[2 :0]: This field determ ines how to selec t the DMA buf fer descriptor queue. The encoding is as foll ows: ‘ 000 ’ - Disa ble buf fer des criptor queue 2. DMA all (good) packets to buf fers taken fr om queue 1. ‘ 001 ’ - DMA all (good) packets t o buf fers taken fr om queue 1. Queue [...]

7-50 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual RxDescQueue1C trl T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byte Addres s: D4 h - D7 h Note : Many of the bits in R X D ESC Q UEUE 1C TRL af fect descriptor queue 2 as well. 11 : 8 r / w 6 h RxHighPrio rityThreshold[3:0]: If more than RxH ighPriorit yThre [...]

7-51 Register Des criptions 13 r/w 0 RxV aria bleSize Queues: Ind icates the Rx descript or mode: ‘ 0 ’ - Fi xed size queue is used. ‘ 1 ’ - V ariab le size queue is us ed. If th e descr ipto r queu e is varia ble si ze, i t st ill ha s a max imum of 256 or 204 8 entrie s dependin g on R X D ESC Q UEUE S IZE . The host can set an END bit in[...]

7-52 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual RxDescQueue2C trl T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byt e Ad dres s: D8h - D Bh RxDescQueueH ighAddress T ype: R/W Intern al Register s Subgro up: Ethe r net Fu nc tiona l Registers Byte Address: DCh - DFh RxDescQueue1LowAddress T ype: R/W Internal[...]

7-53 Register Des criptions RxDescQueue2LowAddress T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byt e Ad dres s: E4h - E 7h RxDescQueue1Pt rs T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byt e Ad dres s: E8h - E Bh 7:0 r 0 Rese rved: Always write 0 T able 7 -67. RxDesc Queue2L owAddress Registe [...]

7-54 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual RxDescQueue2Pt rs T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byte Addres s: E C h - EFh RxDmaStatu s Register T ype: R/W Internal Registers Subgr o up: Ethernet Functional Registers Byt e Ad dres s: F0h - F3h T ab le 7-69. Rx Desc Queue2P trs Register Bit(s[...]

7-55 Register Des criptions RxAddressFiltering Ctrl Register Addr es s filtering, which is contr olled by the R X A DDRESS F ILTERING C TRL register and various addr ess filtering memories, determines which frames ar e accepted by the AIC-6915 a nd passed to the driver . The frame’s destination addr ess is compa red against the following thr ee c[...]

7-56 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual T ab le 7-71. RxAddre ssFilteringCtrl Registe r Bit(s) rw Reset V alue Description/ Function 31:1 6 r /w 0 PerfectAddressPriority[15:0]: Each bit in th is field corr esponds to one “p erfect” addr ess, bit 0 corr esponding t o the first addr ess. In P ERFE CT F ILTERING M ODE (01),[...]

7-57 Register Des criptions 7:6 r/w 0 PerfectFilteringMode[1:0] ‘00’ - Perfect filtering disabled. ‘01’ - 16 p erfect addresse s f ilter ing. Th e AIC-69 15 compares the incomi ng frame d estination addr ess with 1 6 addresses stored in an inter nal SRAM, th en DMA tra nsfers th e frame if th ere is a match. ‘10’ - 1 6 perfect ad dresse[...]

7-58 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual RxFrameT estOu t Register T ype: R Internal Registers Subgr o up: Ethernet Functional Registers Byt e Ad dres s: F8h - FBh T able 7 -72. RxF rame T estOut Regi ster Bit(s) rw Reset V alue Description/ Function 31:2 4 r 0 Rese rved: Alway s read as 0. 23:1 6 r 0 T estRxFr ame: If T estS[...]

7-59 Register Des criptions PCI Diagnostic Registers The following r egisters are accessible fr o m PCI configuration, m emory , and indirect I/O space. They ar e used for diagno s tic purposes only . PCIT argetStat us Register T ype: R/W Internal Registers Subgr o up: PCI Extra Registers Byte Addres s: 01 00h - 010 3h This r egister is for diagnos[...]

7-60 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual PCIMasterSt atus1 Regist er T ype: R Internal Registers Subgr o up: PCI Extra Registers Byte Addres s: 01 04h - 010 7h This r egister is used for diagnostic purposes to r ead the internal status of a DMA operation. T ab le 7-74. PCIM asterStatus1 Registe r Bit(s) rw Reset V alue Descri[...]

7-61 Register Des criptions PCIMasterSt atus2 Regist er T ype: R Internal Registers Subgr o up: PCI Extra Registers Byte Addres s: 01 08h -01 0 B h PCID maLowHo st Addr Re gist er T ype: R Internal Registers Subgr o up: PCI Extra Registers Byte Addres s: 01 0Ch - 010Fh T ab le 7-75. PCIM asterStatus2 Registe r Bit(s) rw Reset V alue Description/ Fu[...]

7-62 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual BacDmaDiagn ostic0 Register T ype: R Internal Registers Subgr o up: PCI Extra Registers Byt e Ad dres s: 01 1 0h - 0 1 13h BacDmaDiagn ostic1 Register T ype: R Internal Registers Subgr o up: PCI Extra Registers Byte Addres s: 01 1 4h - 01 1 7h This r egister provides info rmation about[...]

7-63 Register Des criptions BacDmaDiagn ostic2 Register T ype: R Internal Registers Subgr o up: PCI Extra Registers Byt e Ad dres s: 01 1 8h - 0 1 1Bh This r egister provides info rmation about the current DMA transfer and is used f o r diagnostic purposes only . All values in th e r egister are synchronized to the Ethernet clock. T able 7-7 9. Bac[...]

7-64 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual BacDmaDiagn ostic3 Register T ype: R Internal Regi sters S ubgroup: PCI Functio nal Registers Byte Addres s: 01 1 Ch - 0 1 1Fh T able 7 -80. BA CDMADia gnostic3 Reg ister Bit(s) rw Reset V alue Description/ Function 31:2 5 r 0 Reserved : Always read as 0. 24 r 0 IllegalDmaReq: This bit[...]

7-65 Register Des criptions MacAddr1 Register T ype: R/W Internal Regi sters S ubgroup: PCI Functio nal Registers Byte Addres s: 01 20h - 012 3h NIC’s MAC Addr Byte 5 - -> MacAddr[7:0] (LSB) NIC’s MAC Addr Byte 4 - -> MacAddr[15:8] NIC’s MAC Addr Byte 3 --> MacAddr [23:16] NIC’s MAC Addr Byte 2 --> MacAddr [31:24] MacAddr2 Regis[...]

7-66 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual PCI Car d Bus Reg isters The following re g isters ar e defined in the Car dBus PC Car d Electrical Specification. Their implementation in the AI C-6915 is described her e. For more detailed inf o rmation on the meaning of these bits see the PC Car d specification. The r egi sters ar e[...]

7-67 Register Des criptions Functio nEventMask Re gister T ype: R/W Internal Regi sters S ubgroup: PCI Functio nal Registers Byte Addres s: 01 34h - 013 7h Contr ol s which events cause a status change interrupt. Only bit 15 is implemented, all other bits ar e zer o . Functio nPresentState Reg ister T ype: R Internal Regi sters S ubgroup: PCI Funct[...]

7-68 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual ForceFunction Re gister T ype: R/W Internal Regi sters S ubgroup: PCI Functio nal Registers Byte Addres s: 01 3Ch - 01 3Fh Setting a bit h ere a lso sets a bit in the Fu nctionPresentState register . S ince only the interrupt function is supported, only bit 15 is implemented. T ab le 7[...]

7-69 Register Des criptions Ad dition al Eth ernet Re gister s The following gr oup of registers control access to the MAC, physical device (M II), transmit FP , r eceive FP , and Ethernet FIFO. The r egisters are accessible fr om PCI memory and indire ct I/O space. Th ey are a l l synchr o nized to the Ethernet transmit clock and ar e usually not [...]

7-70 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual T est Mode Register (T BD) T ype: R/W Internal Registers Subgr o up: Ethernet Extra Registers Byte Addres s: 40 00h - 400 3h This r egister contr o ls tes t mode of the chip. RxFrameP rocessorCtrl Register T ype: R/W Internal Registers Subgr o up: Ethernet Extra Registers Byte Addres s[...]

7-71 Register Des criptions MA C Control Registe rs MacConfig 1 Register T ype: R/W Internal Regis ters S ubgr oup: MAC Regist ers Byt e Ad dres s: 5000 h - 50 03h T ab le 7-91. MacCo nfig1 Register Bit(s ) rw Reset V alue Description/Function 31:16 r/w 0 Reserv ed: Always read as 0. 15 r/w 0 Soft Rst: Software r eset to internal MAC logic. This b [...]

7-72 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual For pr oper operation, the internal MAC must be r eset after enabling any of the configuratio n bits in this register by setting bi t 15 ( M AC S OFT R ST ). For example, after setting the T X F LOW E N and R X F LOW E N bits to enable flow control, set bit 15 to reset the internal MAC[...]

7-73 Register Des criptions MacConfig 2 Register T ype: R/W Internal Regis ters S ubgr oup: MAC Regist ers Byt e Ad dres s: 5004 h- 5 007 h T ab le 7-92. MacCo nfig2 R egister Bit(s) rw Reset V alue Description/ Function 31:1 6 r /w 0 Reserv ed: Alw ays read as 0. 15 r 0 TxCRCe rr: T ransm it Ether net CRC error stat us. 14 r 0 TxIslCRCe rr: T rans[...]

7-74 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual For pr oper operation, the internal MAC must be r eset after enabling any of the configuratio n bits in this register by setting bi t 15 ( M AC S OFT R ST ). For example, after setting the T X F LOW E N and R X F LOW E N bits to enable flow control, set bit 15 to reset the internal MAC[...]

7-75 Register Des criptions NonBkT oBkI PG Register T ype: R/W Internal Regis ters S ubgr oup: MAC Regist ers Byt e Ad dres s: 500C h - 50 0Fh ColRetry Reg ister T ype: R/W Internal Regis ters S ubgr oup: MAC Regist ers Byt e Ad dres s: 5010 h- 5 013 h T able 7-9 4. NonBkT oBkIPG Re gister Bit(s) rw Reset V alue Description/ Function 31:1 5 r /w 0 [...]

7-76 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual MaxLength Re gister T ype: R/W Internal Regis ters S ubgr oup: MAC Regist ers Byt e Ad dres s: 5014 h - 50 17h TxNi bbleCnt Regi ster T ype: R/W Internal Regis ters S ubgr oup: MAC Regist ers Byt e Ad dres s: 5018 h- 5 01Bh TxByte Cnt Regi ster T ype: R/W Internal Regis ters S ubgr oup[...]

7-77 Register Des criptions ReTxCn t Regis ter T ype: R/W Internal Regis ters S ubgr oup: MAC Regist ers Byt e Ad dres s: 5020 h- 5 023 h RandomNum Gen Register T ype: R/W Internal Regis ters S ubgr oup: MAC Regist ers Byt e Ad dres s: 5024 h - 50 27h T able 7 -99. ReTxCnt Regi ster Bit(s) rw Reset V alue Description/ Function 31:4 r /w 0 Rese rved[...]

7-78 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual MskRandomNum R egister T ype: R/W Internal Regis ters S ubgr oup: MAC Regist ers Byt e Ad dres s: 5028 h - 50 2Bh T otalTxCnt Reg ister T ype: R/W Internal Regis ters S ubgr oup: MAC Regist ers Byt e Ad dres s: 5034 h- 5 037 h T able 7-101. Ms kRa ndomNum Regis ter Bit(s) rw Reset V al[...]

7-79 Register Des criptions Rx Byt eCn t Regis t er T ype: R/W Internal Regis ters S ubgr oup: MAC Regist ers Byt e Ad dres s: 5040 h- 5 043 h TxP au seT ime r Register T ype: R/W Internal Regis ters S ubgr oup: MAC Regist ers Byt e Ad dres s: 5060 h- 5 063 h VLANT yp e Register T ype: R/W Internal Regis ters S ubgr oup: MAC Regist ers Byt e Ad dre[...]

7-80 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual MIIStatus Reg ister T ype: R/W Internal Registers Subgr o up: MAC Registers Byt e Ad dres s: 5070 h - 50 73h T ab le 7-106. MII Status Regis ter Bit(s) rw Reset value Description/Funct ion 31:5 r 0 Reserved: Al w ays read as 0. 4r0 MIILink Fail: MII Lin k Fail indicator . Setting this [...]

7-81 Register Des criptions Since each external PHY takes up 12 8 bytes (32 x 32 bits), the a ctu al addr ess offset to access each of th em through the AIC-6 915 is: T able 7 -107. External PHY Addre s s Examp les External PHY Byte Address PHY # 0 2000h PHY # 1 2080h PHY # 2 2100h PHY # 3 2180h PHY # 4 2200h PHY # 5 2280h PHY # 6 2300h PHY # 7 238[...]

7-82 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual Address Filtering Registers P erfect Address Memor y Register T ype: R/W Internal Registers Subgr o up: Address Filtering Memory Access Byte Addres s: 60 00h - 6FF F h T able 7-108 starts at byte addr ess 6000h fr om the internal r egi sters base address, of fset 56000h fr om the AIC-6[...]

7-83 Register Des criptions P erfect Addresses The A IC- 69 15 co mpa res t he de stina tio n a ddres s of th e inc o m in g f ram e again st a ll of th e perfect addr esses s tored in mem ory . The comparison is used as one of the criteria fo r accepting a frame. This is indicated by the Perfe ctFilteringMod e field of the R X A DDRESS F ILTERING [...]

7-84 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual MA C Statistic Regist ers T ype: R/W Internal Registers Subgr o up: MAC Statistic Byte Addres s: 70 00h - 7FF F h The following ar e a list of statistics counters tracked by the MAC block. The “Source” field indicates the internal logic block that generates the statistics. The “P[...]

7-85 Register Des criptions 34h Frames Lo st due to Inter nal T ransmit Err ors. (Cann ot recover from FI FO underrun) TX R 32 Count the number of fra mes whic h are lost in tran sm it eng ine be cau se it c ann o t re- transmi t afte r enco untering FIFO u nd erf low er rors . 38h Receive OK Frames MAC (RX) M 32 Count the numb er of fram es succes[...]

7-86 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual Note: Due to the limitation of the SRAM size, Receive Multicast, Br oadcast, and VLAN packets are count ed by software for RM O N usage. 6Ch Receive Packets 12 8 to 255 By tes MAC (RX) RMON 32 Count the number of r e ceive frames w h ose length is betwe en 128 and 2 55 bytes . 70h Rece[...]

7-87 Register Des criptions T ransmit Fram e Pr o cessor - TxGfpMem T ype: R/W Internal Registers Subgr o up: T ransmit Frame Pr ocessor Register Byt e Ad dres s: 8000 h-9 FFF h Receive Fra me Pr o c essor - Rx GfpMem T ype: R/W Internal Registers Subgr o up: Receive Frame Processor Register Byte Addres s: A0 00h -BFF Fh Ethe rnet FI FO T ype: R/W [...]

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8-1 8 ▼▼▼▼ Sample Driver The following sample driver documentation i s intended as a guide for the software developer writing a device driver for the Adaptec A IC-6915 Ethernet Network Co ntroller . It is designed to complement t he driver sour ce code in the D DK and to serve as a basic checklist for driver development. In itialization of [...]

8-2 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual Pr oducer -Consumer Mod el f or the AIC-6915 The AIC-6915 uses the Pr oducer-Consumer model for its operation and in teraction with the driver . One of the entities (AIC-6915 or the d r i ver) "Pr oduces" work items by placing them in a shared queue, the o ther entity "Co[...]

8-3 Sample Driver Basic Regis ter Initiali zat i on and Reset Sequence The first step in the initialization process is NIC r ecognition. The most straightforwar d method of finding th e card is through PCI confi guration spa ce. Operati ng system-speci fic calls may be used to lo cate the device with the A IC-6915 Device ID (6915) an d V endor ID ([...]

8-4 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual 1 PCI C OMMAND R egister (offset 04h) : The PCI Command register must be initialized to enable memory a nd/or I/O r eg ister access, to enable bus master mode, to enable Memory W rite and Invalida t e, and to enable system error r esponse. The Command register does not have to be r eini[...]

8-5 Sample Driver 8 InterruptStatus (offset 80h): The InterruptStatus register should be set to ze r o during initialization. Ther e are two types of status bits - thos e that are clear ed on read o r write, and others that must be clear ed at the sour ce. 9 InterruptEnable (of fset 88h): This r egister indicates which events should trigger an inte[...]

8-6 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual // Other fields in MacConfig1 may remain at the default value AIC6915_WRITE_REG(Adapter->RegisterBaseVa->MacConfig1, MacConfig1Value); // Read MacConfig1 again AIC6915_READ_REG(MacConfig1, MacConfig1Value); // Now do a soft reset to the MAC, separately from the programming step Ma[...]

8-7 Sample Driver // Specify which interrupts we want InterruptEnValue.RxQ1DoneIntEn = 1; // interrupt on receive DMA InterruptEnValue.TxDmaDoneIntEn = 1; // interrupt on transmit DMA // The hardware is now ready to transmit and receive packets! Receive Pr ocess The re ceive pr ocess in the AIC-6915 is based on the use of a r eceive completion queu[...]

8-8 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual T yp e 2 Completion De scriptor The T ype 2 descriptor is a lso known a s the checksum completi on descriptor . It cons ists of two wor d entries. The first wor d is identical to the T ype 0 descriptor . The secon d w or d contains extende d status informa t ion and a partial TCP/UDP ch[...]

8-9 Sample Driver T w o Rec eive Que ues The AIC-6915 of fers the ability to use two Receive Completion Descriptors Queues and two Receive Buf fer Descript or Queues. T wo Receive Buf fer Descriptor Queues are selected through the R X D ESC Q UEUE 2C TRL r egister . Ther e is a corr esponding register , R X C OMPLETION Q UEUE 2C TRL , if two r ecei[...]

8-10 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual 1 R X C OMPLETION Q UEUE 1C TRL (off s et BCh): This r egister is us ed to define the location and type of t he first Receive Comple tion Descri ptor Queue. Required Fields: – RxCo mple tio nQ1Ba se Addres s: Assign th e base ad dress of R eceive Comple tio n Descriptor Queue 1 in ha[...]

8-11 Sample Driver 6 R X D MA C TRL (of fset D0h): This register controls receive DMA operation and frame acceptance criteria. Required Fields: – RxCompletionQ2Enable: En able the second Receive Co mpletion Descriptor Queue if needed. – RxDmaQueueMode: Select the queue sortin g criteria, if a second queue is needed. Sorting may be based on pack[...]

8-12 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual 11 R X D ESC Q UE UE 1P TRS (offset E8h ): This register contains the consumer and producer indices for the first Receive Buffer Descriptor Queue. Initialization of this register depends on the cho ice of the receive model - producer-consumer versus polling. Required Fields: – RxDesc[...]

8-13 Sample Driver // assign the base address of the completion queue (high 24 bits) RxCompletionQueue1CtrlValue.RxCompletionQ1BaseAddress = NdisGetPhysicalAddressLow(RxCompletionQ) >> 8; // Write the value to the AIC-6915 AIC6915_WRITE_REG(Adapter->RegisterBaseVa->RxCompletionQueue1Ctrl, RxCompletionQueue1CtrlValue); // Single completi[...]

8-14 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual // If single queue, use the first queue only // Initialize RxDescQueue1LowAddress // Allocate memory for RxDescQueue1 AIC6915_ALLOC_MEMORY(&Status, &RxDescQ, 4 * 2048); // 4 byte descriptor, //2K fixed size queue RxDescQueue1LowAddressvalue.Reserved = 0; // assign the buffer ad[...]

8-15 Sample Driver Receive Interrupt Handling When a packet is r eceived, the AIC-6915 adds a new entry to the Receive Completion Descriptor Queue and generates either an E ARLY R X Q1I NT (or E ARLY R X Q2I NT ) or a n R X Q1D ONE I NT (or R X Q2D ONE I NT ), depending on which r eceive interrupts have been enabled. When the dr i ver pr ocesses th[...]

8-16 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual // RxBufferRing structure contains pointers to physical and virtual // buffer addresses, and flush buffer address CurrentRxBuffer = Adapter->RxBufferRing[RxDescIndex]; // Indicate the packet to the protocol (operating system specific). NdisMEthIndicateReceive(…CurrentRxBuffer…);[...]

8-17 Sample Driver transmit completi on interrupt which is enabl ed. The T r a nsmit Completion Descript ors ar e described in more detail below . T ransmit Completion D escriptor T ypes DMA Complete T ran smit Completio n Descriptor This four byte descriptor contains an identifier o f 100b, which denotes a DMA complete entry . It also includes a t[...]

8-18 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual of descriptor . These descriptors are outlined below . For a complete description, r efer to the T ransmit A rchitecture section. All har dware ind i ces which r eference a T ransmit Buffer Descriptor ar e incremen ted by a value which is dependen t upon the size of the descriptor . Th[...]

8-19 Sample Driver T ransmit Producer or Consumer index to a softwar e array index. The size of a T ype 1 descriptor in bytes is calculated usin g the formula: (8 + S KIP F IELD B YTES ). For example, assume that a T ype 1 descriptor is in use, with a 16- byte skip field. The size of the descriptor is then 24 bytes. This includes 16 by tes for the [...]

8-20 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual T o convert the har dware T ransmit Pr oducer or Consumer index to a softwar e index, multiply the hardwar e index by 8, a nd then divide by the calculated size of the descriptor . Refer to the T ransmit DMA Buffer Descriptor Q ueue section in the T ransmit Arch it ectur e chapter for [...]

8-21 Sample Driver T ransmit Ini tializa tion The AIC-6915 provides a set of registers which m ust be initialized in preparation for transmitting packets. These registers and the fields which must be initialized in the driver are summarized below . Register bits which are not explicitly described her e may be left at the default r e set value. The [...]

8-22 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual 5 T X D ESC Q UEUE P RODUCER I NDEX (offset A0h): This register conta i ns the producer index for both the high and low priority Transmit Buffer Descriptor Queues. These fields are incremented i n software w henever the d river has prepared a packet for transmission. The producer index[...]

8-23 Sample Driver Required Fields: – RxCompletionQ1ConsumerInd ex = 0: Initialize the Receive Comple tion Descriptor Queue 1 consumer index to zero . Note: this entry is also cover ed in th e Receive Initiali zation section . – TxCompletio nCo ns umerIndex = 0: Initializ e the T ransmit Compl etion Descriptor Queue consumer inde x to zero. 11 [...]

8-24 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual // Set up the low 32 bits of the low priority transmit descriptor queue // base address LoPrTxDescQBaseAddrValue = NdisGetPhysicalAddressLow(Adapter->TxDescRing.AlignedPa); AIC6915_WRITE_REG(LoPrTxDescQBaseAddr, LoPrTxDescQBaseAddrValue); // Set up the high 32 bits of address - it&a[...]

8-25 Sample Driver T ransmit Handling In the code fragmen t below , the operating system has called the tra n smit r ou tine with a packet to be transmitted. The driver mu st set up the T ransmit Buf fer Des criptor(s) for all buffers in this packet, and then instru ct the AIC-6915 controller to transmit the packet. Example: // Windows NT driver ex[...]

8-26 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual Adapter->MapRegisterIndex, TRUE, PhysicalSegmentArray, &BufferPhysicalSegments); // Put each physical segment for this buffer into a Transmit Buffer // Descriptor for (ii = 0 ; ii < BufferPhysicalSegments; ii++) { PhysicalAddressUnit = PhysicalSegmentArray[ii] ; // Get a loca[...]

8-27 Sample Driver &CurrentBuffer); } // while (CurrentBuffer) // We’ve placed all the buffers in this packet into Transmit Buffer // Descriptors. // We’re ready to tell the chip to transmit the packet. // Advance the Tx Producer Index causing the chip to transmit the packet out. // The Producer index is incremented by units of 8 bytes. For[...]

8-28 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual // The index is a multiple of the size of the Transmit Buffer Descriptor. IndexToDescriptor = TxCompletionDesc->ConsumerIndex/ sizeof(AIC6915_TX_DESC); TxDesc = Adapter->TxDesc[IndexToDescriptor]; // Return the packet to the operating system. // This is the packet given to us by [...]

8-29 Sample Driver AIC-6915 DDK Features T able 8-1 is a list of the major featur es available in the AIC-6915 and demonstrated in the DDK. *Additional interrupts no t enabled in DDK driver: GpioInt, StatisticW rapInt, PhyInt, AbNormalInterrupt, Gener a lT imerInt, SoftInt, RxCompletionQueue1Int, TxCompletionQueueInt, P ciInt, DmaErrInt, TxD ataLow[...]

8-30 AIC-6915 Eth ernet LAN Controller Pr ogrammer’ s Ma nual DDK Development En vironment The drivers contained i n the DDK wer e written for the W indows NT envir onment. Ther e is an NDIS 3.0/4.0 driver and an NDIS 5.0 driver in the D DK. They wer e developed using V ersion 5.0 of the Micr osoft V isual C++ compiler . When using this compiler [...]