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AMD 6 manual

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Table of contents for the manual

  • Page 1

    AM D Athlon™ Pr oc essor Model 6 R evision Guide Publication # 24332 Rev: E Issue Date: December 2002 Preliminary Information[...]

  • Page 2

    Preliminary Information T rademarks AMD , the AMD Arr ow logo , AMD Athlon, and comb inations thereof , ar e trademar ks of Adv anced Micr o Devices, Inc. Other product names us ed in this publication are for id entification purposes onl y and ma y be tr ademarks of their r espectiv e companies. © 200 1 , 2002 Advanced Micro Dev ices, Inc. All rig[...]

  • Page 3

    3 24332E— December 2002 AM D Athlon™ Pr ocessor Model 6 Revision Guide Preliminary Information Revision History Date Rev Description December 2002 E Added errata #22–2 4. July 2002 D Added errata #20 and #2 1 . October 200 1 C ■ Added silicon revision A5 information ■ Added erratum #1 8 and #1 9 ■ Added T able 2: Cross-reference of Erra[...]

  • Page 4

    4 AM D Athlon™ Processor Model 6 Revision Guide 24332E— December 2002 Preliminary Information AM D Athlon™ Pr oc essor Model 6 Re vision Guide The pur pose of the AMD Athlon™ Processor Model 6 Revision Guide is to communicate update d product info rmation on the AMD Athlon processor model 6 to designer s of computer systems and softw ar e d[...]

  • Page 5

    5 24332E— December 2002 AM D Athlon™ Pr ocessor Model 6 Revision Guide Preliminary Information 1 Pro du ct Er ra ta T his section documents AMD Athlon ™ Processor Mode l 6 product err ata. T he err ata ar e div ided into categories to assist r efe r encing particular err ata. A unique tr ac king n umber f or eac h err atum has been assigned w[...]

  • Page 6

    6 AM D Athlon™ Processor Model 6 Revision Guide 24332E— December 2002 Preliminary Information T able 2. Cross-Reference of Er ratum to Processor Segments Errata Number W orkstation/Server 1 Desktop 2 Mobile 3 16 XXX 17 X 18 X 19 XXX 20 XXX 21 XXX 22 XXX 23 XXX 24 XXX Notes: 1. The workstation/server segment current ly includes the AMD Athlon™[...]

  • Page 7

    7 24332E— December 2002 AM D Athlon™ Pr ocessor Model 6 Revision Guide Preliminary Information 16 INVLPG Instruction Does Not Flush Entire Four -Megabyte Page Properly with Certain Linear Addresses Products Affected. A0, A2 Normal Specified Operation. After executing an INVLPG instruction the TLB should no t contain an y tr anslations f or any [...]

  • Page 8

    8 AM D Athlon™ Processor Model 6 Revision Guide 24332E— December 2002 Preliminary Information 17 Deadlock May Occur in a Tw o-Processor System in the Pres ence of Prob e to Memory- Mapped I/O Products Affected. A0, A2, A5 Normal Specified Operation. Processor should not hang. Non-conformance. In a multipr ocessor system, if one pr ocessor (A) i[...]

  • Page 9

    9 24332E— December 2002 AM D Athlon™ Pr ocessor Model 6 Revision Guide Preliminary Information 18 Processor May Issue Non-Connect Bus Cycle After FID Special Cycle Products Affected. A0, A2 Normal Specified Operation. The first pr ocessor c ycle after a FID Change special c ycle should be a Connect special c ycle. Non-conformance. I n ra re c i[...]

  • Page 10

    10 AM D Athlon™ Processor Model 6 Revision Guide 24332E— December 2002 Preliminary Information 19 Processor Does Not Support Re liable Microcode Patch Mechanism Products Affected. A5 Normal Specified Operation. The pr ocessor should fu nction properl y after a microcode patch is loaded. Non-conformance. The pr ocessor has the pat ch RAM BIST fu[...]

  • Page 11

    11 24332E— December 2002 AM D Athlon™ Pr ocessor Model 6 Revision Guide Preliminary Information 20 Processor Performance Counters Do Not Count Some x86 Instructions Products Affected. A0, A2, A5 Normal Specified Operation. The pr ocessor should c ount all x8 6 inst ructions when pr ogr ammed to do so . Non-conformance. Ther e ar e tw o types of[...]

  • Page 12

    12 AM D Athlon™ Processor Model 6 Revision Guide 24332E— December 2002 Preliminary Information 21 A Speculative SMC Store F ollowed by an Actual SMC Store May Cause One-Time Stale Execution Products Affected. A0, A2, A5 Normal Specified Operation. Self-modifying code sequ ences should be corr ectl y detected and handled in a manner consistent w[...]

  • Page 13

    13 24332E— December 2002 AM D Athlon™ Pr ocessor Model 6 Revision Guide Preliminary Information 22 Real Mode RDPMC with Illegal ECX May Cause Unpre dictable Operation Products Affected. A0, A2, A5 Normal Specified Operation. Illegal v alues of ECX (that is, ECX>3) f or the RDPMC (Read P er formance Monitor Counter) instruction cause the proc[...]

  • Page 14

    14 AM D Athlon™ Processor Model 6 Revision Guide 24332E— December 2002 Preliminary Information 23 Using Task Gates With Breakpoint s Enabled May Caus e Unexpected Faults Products Affected. A0, A2, A5 Normal Specified Operation. T ask gates should correctl y use the TSS selector out of the task gate for C ALL and JMP instructions. Non-conformanc[...]

  • Page 15

    15 24332E— December 2002 AM D Athlon™ Pr ocessor Model 6 Revision Guide Preliminary Information 24 Single Step Across I/O SMI Skips One Debug Trap Products Affected. A0, A2, A5 Normal Specified Operation. When single stepping (with EFLA GS.TF) across an IN or OUT instructio n that detects an SMI, the processor corr ectl y defer s taking the deb[...]

  • Page 16

    16 AM D Athlon™ Processor Model 6 Revision Guide 24332E— December 2002 Preliminary Information 2 R evision Determination T able 3 sho ws the AMD Athlon™ pr ocessor model 6 identification n umbers r eturned by the CPUID instruction f or each r e vision of the processor . T able 3. CPU I D V alues for the Revisions of the AM D Athlon™ Process[...]

  • Page 17

    17 24332E— December 2002 AM D Athlon™ Pr ocessor Model 6 Revision Guide Preliminary Information 3 T echnical and Documentation Support T he follo wing documents pr o vide additiona l informa tion r egar ding the oper ation of the AMD Athlon™ processor model 6. Please r efer to the data sheets listed in this secti on f or product mar king info[...]