Analog Devices ADSP-21020 manual

FUNCTIONAL BLOCK DIAGRAM EXTERNAL ADDRESS BUSES PROGRAM SEQUENCER EXTERNAL DATA BUSES DATA ADDRESS GENERATORS DAG 1 DAG 2 PROGRAM MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY DATA DATA MEMORY ADDRESS INSTRUCTION CACHE ARITHMETIC UNITS SHIFTER MULTIPLIER ALU REGISTER FILE TIMER JTAG TEST & EMULATION REV. C Information furnished by Analog Devic[...]

ADSP-21020 REV. C –2– • Instruction Cache The ADSP-21020 includes a high performance instruction cache that enables three-bus operation for fetching an instruction and two data values. The cache is selective—only the instructions whose fetches conflict with program memory data accesses are cached. This allows full-speed execution of core, l[...]

ADSP-21020 REV. C –3– the standard IEEE format, whereas the 40-bit IEEE extended- precision format has eight additional LSBs of mantissa for greater accuracy. The multiplier performs floating-point and fixed-point multiplication as well as fixed-point multiply/add and multiply/ subtract operations. Integer products are 64 bits wide, and the acc[...]

ADSP-21020 REV. C –4– in a specified register, either before (premodify) or after (postmodify) the access. To implement automatic modulo addressing for circular buffers, the ADSP-21020 provides buffer length registers that can be associated with each pointer. Base values for pointers allow circular buffers to be placed at arbitrary locations. E[...]

ADSP-21020 REV. C –5– 4 1 × CLOCK CLKIN PMA PMD DMACK DMA DMD ADSP-21010 24 48 32 32 2 PMACK 4 DMPAGE PMPAGE FLAG3-0 JTAG 5 4 RCOMP TIMEXP ADDR DATA PROGRAM MEMORY SELECTS OE WE PMS1-0 PMRD PMWR DMRD DMWR DMTS DATA MEMORY ACK PERIPHERALS ADDR DATA ADDR DATA SELECTS SELECTS OE WE OE WE BR BG RESET IRQ3-0 PMTS DMS3-0 Figure 2. Basic System Confi[...]

ADSP-21020 REV. C –6– Pin Name Type Function DMPAGE O Data Memory Page Boundary. The ADSP- 21020 asserts this pin to signal that a data memory page boundary has been crossed. Memory pages must be defined in the memory control registers. DMTS I/S Data Memory Three-State Control. DMTS places the data memory address, data, selects, and strobes in [...]

ADSP-21020 REV. C –7– COMPUTE AND MOVE OR MODIFY INSTRUCTIONS 1. compute , | DM(Ia, Mb) = dreg1 | , | PM(Ic, Md) = dreg2 | ; | dreg1 = DM(Ia, Mb) || dreg2 = PM(Ic, Md) | 2. IF condition compute; 3a. IF condition compute , | DM(Ia, Mb) | = ureg ; | PM(Ic, Md) | 3b. IF condition compute , | DM(Mb, Ia) | = ureg ; | PM(Md, Ic) | 3c. IF condition co[...]

ADSP-21020 REV. C –8– Table II. Condition and Termination Codes Name Description eq ALU equal to zero ne ALU not equal to zero ge ALU greater than or equal to zero lt ALU less than zero le ALU less than or equal to zero gt ALU greater than zero ac ALU carry not ac Not ALU carry av ALU overflow not av Not ALU overflow mv Multiplier overflow not [...]

ADSP-21020 REV. C –9– Table III. Universal Registers Name Function Register File R15–R0 Register file locations Program Sequencer PC* Program counter; address of instruction cur- rently executing PCSTK Top of PC stack PCSTKP PC stack pointer FADDR* Fetch address DADDR* Decode address LADDR Loop termination address, code; top of loop address s[...]

ADSP-21020 REV. C –10– Table V. Multiplier Compute Operations Rn = Rx * Ry ( SS F ) Fn = Fx * Fy MRF = Rx * Ry ( UUI MRB = Rx * Ry ( UU FR Rn = MRF + Rx * Ry ( SSF ) Rn = MRF – Rx * Ry ( SSF ) Rn = MRB + Rx * Ry ( UUI Rn = MRB = Rx * Ry ( UUI MRF = MRF + Rx * Ry ( U U FR MRF = MRF = Rx * Ry ( UUI FR MRB = MRB MRB = MRB Rn = SAT MRF ( SI ) Rn [...]

ADSP-21020 REV. C –11– Table Vll. Multifunction Compute Operations Fixed-Point Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12 Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 – R15-12 Rm=R3-0 * R7-4 (SSFR), Ra=(R11-8 + R15-12)/2 MRF=MRF + R3-0 * R7-4 (SSF), Ra=R11-8 + R15-12 MRF=MRF + R3-0 * R7-4 (SSF), Ra=R11-8 – R15-12 MRF=MRF + R3-0 * R7-4 (SSF), Ra=(R11-8 + R[...]

RECOMMENDED OPERA TING CONDITIONS K Grade B Grade T Grade Parameter Min Max Min Max Min Max Unit V DD Supply Voltage 4.50 5.50 4.50 5.50 4.50 5.50 V T AMB Ambient Operating Temperature 0 +70 –40 +85 –55 +125 ° C Refer to Environmental Conditions for information on thermal specifications. ELECTRICAL CHARACTERISTICS Parameter Test Conditions Min[...]

ADSP-21020 REV. C –13– TIMING PARAMETERS General Notes See Figure 15 on page 24 for voltage reference levels. Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data[...]

ADSP-21020 REV. C –14– Interrupts K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requirement: t SIR IRQ 3-0 Setup before CLKIN High 38 31 25 23 38 + 3DT/4 ns t HIR IRQ 3-0 Hold after CLKIN High 0 0 0 0 ns t IPW IRQ 3-0 Pulse Width 55 45 [...]

ADSP-21020 REV. C –15– Flags K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requirement: 1 t SFI FLAG3-0 IN Setup before CLKIN High 19 16 14 13 19 + 5DT/16 ns t HFI FLAG3-0 IN Hold after CLKIN High 0 0 0 0 ns t DWRFI FLAG3-0 IN Delay fro[...]

ADSP-21020 REV. C –16– Bus Request/Bus Grant K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requirement: t HBR BR Hold after CLKIN High 0 0 0 0 ns t SBR BR Setup before CLKIN High 18 15 13 12 18 + 5DT/16 ns Switching Characteristic: t DM[...]

ADSP-21020 REV. C –17– External Memory Three-State Control K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requirement: t STS xTS , Setup before CLKIN High 14 50 12 40 10 33 9 30 14 + DT/4 t CK ns t DADTS xTS Delay after Address, Select 2[...]

ADSP-21020 REV. C –18– Memory Read K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependence* Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requirement: t DAD Address, Select to Data Valid 37 27 20 17 37 + DT ns t DRLD xRD Low to Data Valid 24 18 13 11 24 + 5DT/8 ns t HDA Data Hold from Address[...]

ADSP-21020 REV. C –19– CLKIN DATA DMACK, PMACK ADDRESS, SELECT DMPAGE, PMPAGE t DARL t DAP t DAAK t DCKRL t DRAK t SAK t HAK t DAD t DRLD t RWR t HDRH t RW t HDA DMWR, PMWR DMRD, PMRD Figure 10. Memory Read[...]

ADSP-21020 REV. C –20– Memory Write K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requirement: 12 t DAAK xACK Delay from Address, Select 27 18 6 9 27 + 7DT/8 ns t DWAK xACK Delay from xWR Low 15 10 10 5 15 + DT/2 ns t SAK xACK Setup bef[...]

ADSP-21020 REV. C –21– CLKIN DATA DMACK, PMACK ADDRESS, SELECT DMPAGE, PMPAGE t DAWL t DAP t DAAK t DCKWL t DWAK t SAK t HAK t WDE t DWHA t WWR t DDWR t DDWH t WW t DAWH t HDWH DMWR, PMWR DMRD, PMRD Figure 11. Memory Write[...]

ADSP-21020 REV. C –22– IEEE 1149.1 Test Access Port K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requirement: t TCK TCK Period 50 40 33 30 t CK ns t STAP TDI, TMS Setup before TCK High 5 5 5 5 ns t HTAP TDI, TMS Hold after TCK High 6 6[...]

ADSP-21020 REV. C –23– TCK TMS,TDI TDO SYSTEM INPUTS SYSTEM OUTPUTS t STAP t HTAP t DTDO t SSYS t HSYS t DSYS t TCK Figure 12. IEEE 1149.1 Test Access Port[...]

ADSP-21020 REV. C –24– TEST CONDITIONS Output Disable Time Output pins are considered to be disabled when they stop driving, go into a high-impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by ∆ V is dependent on the capacitive load, C L , and the load current, I L . It can[...]

ADSP-21020 REV. C –25– Capacitive Loading Output delays are based on standard capacitive loads: 100 pF on address, select, page and strobe pins, and 50 pF on all others (see Figure 14). For different loads, these timing parameters should be derated. See the Hardware Configuration chapter of the ADSP-21020 User’s Manual for further information[...]

ADSP-21020 REV. C –26– ENVIRONMENTAL CONDITIONS The ADSP-21020 is available in a Ceramic Pin Grid Array (CPGA). The package uses a cavity-down configuration which gives it favorable thermal characteristics. The top surface of the package contains a raised copper slug from which much of the die heat is dissipated. The slug provides a surface for[...]

ADSP-21020 REV. C –27– All GND pins should have a low impedance path to ground. A ground plane is required in ADSP-21020 systems to reduce this impedance, minimizing noise. The EVDD and IVDD pins should be bypassed to the ground plane using approximately 14 high-frequency capacitors (0.1 µ F ceramic). Keep each capacitor’s lead and trace len[...]

ADSP-21020 REV. C –28– TCK PMA21 PMPAGE TRST RCOMP DMACK TDO DMTS PMWR PMD47 PMD46 PMD44 PMD42 PMD41 PMD38 DMD22 EVDD DMD24 DMD25 DMD26 DMD23 DMD27 DMD28 DMD33 DMD29 DMD35 DMD36 DMD39 DMD34 NC DMS0 DMPAGE DMS2 DMA31 DMA27 DMA26 DMA29 DMA24 DMA19 DMA14 DMA17 PMA0 NC FLAG2 DMA1 DMA3 DMA7 DMA11 PMA20 PMA19 PMA14 PMA10 PMA9 PMA5 PMA4 BG IRQ0 PMACK [...]

ADSP-21020 REV. C –29– DMD7 DMD8 DMA14 DMA13 DMD12 DMD14 DMD18 DMD21 DMD22 DMD26 DMD32 DMD33 DMD37 DMD39 DMA21 DMA17 DMA16 EVDD DMD23 DMD29 DMD34 DMA22 BG BR BOTTOM VIEW (PINS UP) PMD31 PMD35 PMD39 PMD40 PMD44 PMWR PMACK RCOMP PMD27 PMD30 PMD32 PMD37 NC PMD42 PMTS NC NC CLKIN DMACK DMWR PMD11 PMA0 EGND PMD9 PMD8 NC EVDD PMD5 IRQ0 PMD4 PMD3 FLAG[...]

ADSP-21020 REV. C –30– PGA PIN PGA PIN PGA PIN PGA PIN LOCATION NAME LOCATION NAME LOCATION NAME LOCATION NAME G16 DMA0 B5 DMD25 K1 PMD9 L16 TIMEXP G17 DMA1 B6 DMD26 L3 PMD10 U12 RCOMP F18 DMA2 D6 DMD27 L2 PMD11 T11 CLKIN F17 DMA3 C6 DMD28 M1 PMD12 T14 TRST F16 DMA4 A8 DMD29 M2 PMD13 R12 TD0 F15 DMA5 C7 DMD30 M3 PMD14 S13 TDI E18 DMA6 D7 DMD31 [...]

ADSP-21020 REV. C –31– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 223-Pin Ceramic Pin Grid Array D D A A 1 L 3 b 1 φ e h b φ j 1 j 2 AB CD EFGH J KL M NP RS T U 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 TOP VIEW e 1 e 1 INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.084 0.102 2.11 2.59 A 1 0.40 0.60 1.02 1.52 φ b 0.018 TYP 0.4[...]

ADSP-21020 REV. C –32– C1601c–5–8/94 PRINTED IN U.S.A. ORDERING GUIDE Ambient Temperature Instruction Cycle Time Part Number* Range Rate (MHz) (ns) Package ADSP-21020KG-80 0 ° C to +70 ° C 20 50 223-Lead Ceramic Pin Grid Array ADSP-21020KG-100 0 ° C to +70 ° C 25 40 223-Lead Ceramic Pin Grid Array ADSP-21020KG-133 0 ° C to +70 ° C 33.[...]