Analog Devices HSC-ADC-EVALC manual

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

Go to page of

A good user manual

The rules should oblige the seller to give the purchaser an operating instrucion of Analog Devices HSC-ADC-EVALC, along with an item. The lack of an instruction or false information given to customer shall constitute grounds to apply for a complaint because of nonconformity of goods with the contract. In accordance with the law, a customer can receive an instruction in non-paper form; lately graphic and electronic forms of the manuals, as well as instructional videos have been majorly used. A necessary precondition for this is the unmistakable, legible character of an instruction.

What is an instruction?

The term originates from the Latin word „instructio”, which means organizing. Therefore, in an instruction of Analog Devices HSC-ADC-EVALC one could find a process description. An instruction's purpose is to teach, to ease the start-up and an item's use or performance of certain activities. An instruction is a compilation of information about an item/a service, it is a clue.

Unfortunately, only a few customers devote their time to read an instruction of Analog Devices HSC-ADC-EVALC. A good user manual introduces us to a number of additional functionalities of the purchased item, and also helps us to avoid the formation of most of the defects.

What should a perfect user manual contain?

First and foremost, an user manual of Analog Devices HSC-ADC-EVALC should contain:
- informations concerning technical data of Analog Devices HSC-ADC-EVALC
- name of the manufacturer and a year of construction of the Analog Devices HSC-ADC-EVALC item
- rules of operation, control and maintenance of the Analog Devices HSC-ADC-EVALC item
- safety signs and mark certificates which confirm compatibility with appropriate standards

Why don't we read the manuals?

Usually it results from the lack of time and certainty about functionalities of purchased items. Unfortunately, networking and start-up of Analog Devices HSC-ADC-EVALC alone are not enough. An instruction contains a number of clues concerning respective functionalities, safety rules, maintenance methods (what means should be used), eventual defects of Analog Devices HSC-ADC-EVALC, and methods of problem resolution. Eventually, when one still can't find the answer to his problems, he will be directed to the Analog Devices service. Lately animated manuals and instructional videos are quite popular among customers. These kinds of user manuals are effective; they assure that a customer will familiarize himself with the whole material, and won't skip complicated, technical information of Analog Devices HSC-ADC-EVALC.

Why one should read the manuals?

It is mostly in the manuals where we will find the details concerning construction and possibility of the Analog Devices HSC-ADC-EVALC item, and its use of respective accessory, as well as information concerning all the functions and facilities.

After a successful purchase of an item one should find a moment and get to know with every part of an instruction. Currently the manuals are carefully prearranged and translated, so they could be fully understood by its users. The manuals will serve as an informational aid.

Table of contents for the manual

  • Page 1

    High Speed Converter Evaluation Platform HSC-ADC-EV ALC Rev. 0 Evalua tion boards are only in tended for dev ice ev aluation and no t for production purposes. Evalua tion boards as supplied “as is ” and wi thout warran ties of any kind, exp ress, im plied, or statu tory includ ing, but n ot limit ed to , any implied warran ty of merch antabil i[...]

  • Page 2

    HSC-ADC-EVALC Rev. 0 | Page 2 of 32 T ABLE OF CONTENTS Fea tures .............................................................................................. 1 Equipm ent N eede d ........................................................................... 1 Product H ighli ghts .....................................................................[...]

  • Page 3

    HSC-ADC-EVALC Rev. 0 | Page 3 of 32 PRODUCT D ESCRIPTION The Analog Devices, In c. high speed con v erter evalua tion pla tform (HSC-ADC-EV ALC) inc ludes the la test v e rs i on o f V isual Analo g and an F PGA-base d buffer memor y bo ard to capture blocks o f digi tal data fro m the Analog Devices high speed analog-to-digi tal con verter (ADC) e[...]

  • Page 4

    HSC-ADC-EVALC Rev. 0 | Page 4 of 32 EV ALUA TION BOARD HARDW ARE HSC-ADC-EVALC ADC CAPTURE BOARD EASY START Requirements • HSC-ADC-EV ALC AD C capt ure board, V isualAnalog, 5 V wal l t ransfor mer, and USB cabl e • Hi gh speed ADC evalua tio n boar d and ADC data sh eet • Po wer supply for AD C e va luation bo ard • Analog signal sour ce a[...]

  • Page 5

    HSC-ADC-EVALC Rev. 0 | Page 5 of 32 ROHDE & S CH WARZ, SMHU, 2V p-p SIGN A L SYNTHESI ZER ROHDE & S CH WARZ, SMHU, 2V p -p SI G NAL SYNTHE SI ZER BAND- P ASS FIL TER USB CO NNEC TI O N 06676-0 04 HSC-ADC-E V ALC DA T A CA PTUR E BOARD PC RUNNING Visu al Anal og –+ PS GND V REG 5V DC 3A MAX W ALL OUTLE T 100V TO 240V AC 47Hz TO 63Hz DAT A [...]

  • Page 6

    HSC-ADC-EVALC Rev. 0 | Page 6 of 32 HSC-ADC-EVALC ADC CAPTURE BOARD FEATURES 06676-002 GEN ERAL PUR POSE I/O, USB/S P I CONT ROL DAT A BUS 1 DAT A BUS 2 FPGA LOA D SELECT ON BO ARD POW ER S UPPL Y 100MHz OSC ILLA TOR FPGA I/O VOL T AGE MODE FPGA CONF IG PROM XIL INX VIRTEX-4 FPGA DEBUG PINS EXT ERNAL SYNC I / O CYPRES S US B CO NTR OL L ER USB CO N[...]

  • Page 7

    HSC-ADC-EVALC Rev. 0 | Page 7 of 32 06676-003 Figure 4. HSC-ADC-EVALC Components (Bottom View) HSC-ADC-EVALC SUPPORTED ADC EVALUATION BOARDS Refer to the Analog Devices ADC capt ure board pr oduct page a t www .anal og.co m/F IFO for a lis t of HSC-AD C-EV ALC-com patible ADC evaluation boards. Some legacy ADC b oards ma y require in terposer cards[...]

  • Page 8

    HSC-ADC-EVALC Rev. 0 | Page 8 of 32 THEOR Y OF OPERA TION The HSC-AD C-EV ALC evaluation platform is based around the V irtex-4 FPGA (X C4VFX20-10FFG672C) from Xilinx®, which can be programmed through V isualAnalog to operate with a variety of data con verters. Another key co mponen t, the Cypr ess USB device (U3), communica tes with a host PC and[...]

  • Page 9

    HSC-ADC-EVALC Rev. 0 | Page 9 of 32 EV ALUA TION BOARD SCHEMA TICS AND ARTWORK HSC-ADC-EVALC SCHEMATICS 0 6676-0 05 TYC O A ND DS P EZ–K IT C ONN E CTOR TO FP GA XC4V FX20- 10FF G 672C XC4V FX 20-10F FG 672C XC4VF X20- 10FF G 672C XC4V FX20- 10FF G 672C R38 100 Ω R39 100 Ω R50 51.1 Ω Figure 5.[...]

  • Page 10

    HSC-ADC-EVALC Rev. 0 | Page 10 of 32 0 6676-00 6 SRAM ADDRESS AND CONTRO L FPGA CONT ROL S U21 NC7SZ 05M5X R1 100 Ω R40 3.74K Ω R44 3.74K Ω R42 3.74K Ω R41 3.74K Ω R43 3.74K Ω XC4VF X20- 10FF G 672C R28 3.74K Ω R27 249 Ω R33 249 Ω R25 3.74K Ω R31 3.74K Ω Figure 6.[...]

  • Page 11

    HSC-ADC-EVALC Rev. 0 | Page 11 of 32 FPG A TO S R AM D A T A XC4VF X20- 10FF G 672C 06676- 007 XC4VF X20- 10FF G 672C Figure 7.[...]

  • Page 12

    HSC-ADC-EVALC Rev. 0 | Page 12 of 32 A D19 T O BE USED WIT H HIGHER DENSI TY SRAM DE VICES 06676-008 Figure 8.[...]

  • Page 13

    HSC-ADC-EVALC Rev. 0 | Page 13 of 32 SRAM AND F PG A POWE R 06676-009 XC4VF X20- 10FF G 672C XC4VF X20- 10FF G 672C R66 499 Ω R64 499 Ω R65 499 Ω R63 499 Ω Figure 9.[...]

  • Page 14

    HSC-ADC-EVALC Rev. 0 | Page 14 of 32 06676-0 10 REFCLK Osc illator for I DELAYCTRL FPG A BYPASS CA P SRAM A BYPASS CA P SRAM B BYPASS CA P + + + + R15 24 Ω Figure 10.[...]

  • Page 15

    HSC-ADC-EVALC Rev. 0 | Page 15 of 32 06676-011 DEBU G PINS UNUSED ROCKET I /0 CONNECT IONS XC4VF X20- 10FF G 672C XC4V FX20- 10FF G 672C Figure 11.[...]

  • Page 16

    HSC-ADC-EVALC Rev. 0 | Page 16 of 32 06676-0 12 ROCKET I/0 CONNECTIONS Figure 12.[...]

  • Page 17

    HSC-ADC-EVALC Rev. 0 | Page 17 of 32 06676-013 USB CONNECTI ONS R49 3.74 Ω R71 3.74 Ω R48 100K Ω SDI & SDO DI RECTI O NS A RE WI T H RESPECT TO THE DE VI CE UNDER CO NTRO L. USB Dir ec t I/ O (3.3V ) Figure 13.[...]

  • Page 18

    HSC-ADC-EVALC Rev. 0 | Page 18 of 32 USB CONNECTI ONS (CONT INUED) 06676-014 4 5 2 1 3 6 R52 3.74K Ω R72 3.74K Ω R46 499 Ω XC4VF X20- 10FF G 672C XC4V FX20- 10F FG 672C J6 Figure 14.[...]

  • Page 19

    HSC-ADC-EVALC Rev. 0 | Page 19 of 32 06676-015 EZ–KI T EXPANSION INT ERFACE – F OR DSPs P1 P2 P3 Figure 15.[...]

  • Page 20

    HSC-ADC-EVALC Rev. 0 | Page 20 of 32 , 06676- 016 TYCO HM – Zd CONNECTOR S J1 HS- SERIAL/SPI/AUX J2 DATA B US 1 J3 DATA B US 2 Figure 16.[...]

  • Page 21

    HSC-ADC-EVALC Rev. 0 | Page 21 of 32 0 6676-01 7 CONFI GURATIO N EEPRO M JTAG CO NNECTOR EEPROM HARDWARE RECONFI GURATIO N PUSH BUTT O N R57 3.74K Ω R73 ZER O R77 100 Ω R78 100 Ω R75 3.74K Ω R76 3.74K Ω Figure 17.[...]

  • Page 22

    HSC-ADC-EVALC Rev. 0 | Page 22 of 32 POWER AND VOLT AGE REGULATO RS 06676-0 18 + + + + + + + + + TSW–102–0 8–G–D DO NO T REMO VE R68 147k Figure 18.[...]

  • Page 23

    HSC-ADC-EVALC Rev. 0 | Page 23 of 32 PCB LAYOUT 06676-019 GENERAL PU RPOSE I/O, USB/S P I CONT ROL DAT A BUS 1 DAT A BUS 2 XIL INX VIRTEX-4 FPGA DEBUG PINS EXTERNAL SYNC I/O CYPRE SS USB CONT ROL LE R USB CONNE C TO R FPGA JT AG CO NNEC TO R 5VDC P O W E R IN PU T FPGA LOAD SELECT ON BO ARD POWER SUPPL Y 100MHz OSCILL A TOR FPGA I/O VOL T AGE MODE [...]

  • Page 24

    HSC-ADC-EVALC Rev. 0 | Page 24 of 32 I/O CONNECTOR—J1, J2, AND J3 PIN MAPPING D C B A D C B A D C B A D17A– D16A– D14A– D12A– D10A – D8A– D6A– D4A– D2A– D0A– D17A+ D16A+ D14A+ D12A+ D10A + D8A+ D6A+ D4A+ D2A+ D0A+ DCLKA1– D15A– D13A– D11A– D9A– D7A– D5A– D3A– D1A– DCLKA2– DCLKA1+ D15A+ D13A+ D11A+ D9A+ D7A+[...]

  • Page 25

    HSC-ADC-EVALC Rev. 0 | Page 25 of 32 D C B A D C B A MGT CL K1– SD1– SD2– SD3– SD4– SD5– SD6 – SD7– SD 8– MG TCL K2– MGTCLK1+ SD1+ SD 2+ SD3+ SD4+ SD 5+ SD6+ SD7+ SD8+ MGTCLK2+ I/O_1 I/O_3 I/O_5 I/O_7 SCLK SD I SD O USB_ 1 US B_ 2 USB_ 4 I/O_2 I/O_4 I/O_6 I/O_8 CSB _1 C SB_ 2 C SB_ 3 CS B_4 U SB _3 USB_ 5 (J 1 ) HS- SERIAL /SPI [...]

  • Page 26

    HSC-ADC-EVALC Rev. 0 | Page 26 of 32 Table 3. HSC-ADC-EVALC J1 I/O Connections to FPG A (U1) Connector J1 (HS-Serial, SPI, AUX) Schematic Net Name FPGA Pin A1 USB_5 none B1 USB_4 none C1 MGTCLK2+ AF10 D1 MGTCLK2− AF11 A2 USB_3 none B2 USB_2 none C2 none none D2 none none A3 CSB_4 none B3 USB_1 none C3 none none D3 none none A4 CSB_3 none B4 SDO H[...]

  • Page 27

    HSC-ADC-EVALC Rev. 0 | Page 27 of 32 Table 5. HSC-ADC-EVALC J3 I/O Connections to FPG A (U1) Connector J3 (DA T A BUS 2) Schematic Net Name FPGA Pin A1 DCLKA2+ C14 B1 DCLKA2− B14 C1 D0A+ D6 D1 D0A− E6 A2 D1A+ H9 B2 D1A− G9 C2 D2A+ E8 D2 D2A− E7 A3 D3A+ L10 B3 D3A− L9 C3 D4A+ J9 D3 D4A− K10 A4 D5A+ C3 B4 D5A− D3 C4 D6A+ E3 D4 D6A− F3[...]

  • Page 28

    HSC-ADC-EVALC Rev. 0 | Page 28 of 32 ORDERING INFORMA TION BILL OF MATERIALS (RoHS COMPLIANT) Table 6. Qty Reference Designator Description Manufacturer Part Number 1 PCB PCB, ADC evalua tion platform MOOG/PCSM GS09156x8 0 BGA1, BGA2 IC, 18-bit DDRII SRAM 2-w ord burst operation (MOS integ rated circuit), do not install NEC PD44164362F5-EQ1 2 C1, C[...]

  • Page 29

    HSC-ADC-EVALC Rev. 0 | Page 29 of 32 Qty Reference Designator Description Manufacturer Part Number 17 L3 to L19 F errite chip, 220 Ω, 2 A, 0603, 100 MHz TDK MP Z1608S221A 3 P1 to P3 Connector , 0.050 in × 0.050 in, Samtec TFM se ries, 2R Samtec , Inc. TF M-145-32-S-D-A 13 R1, R3, R4, R34 to R39, R61, R67, R77, R78 Resistor , 100 Ω, 1/16 W , 1%, [...]

  • Page 30

    HSC-ADC-EVALC Rev. 0 | Page 30 of 32 Qty Reference Designator Description Manufacturer Part Number 2 U6, U7 IC, P-channel enhancement mode field effect transistor F air child Semiconductor NDT456P 1 U8 V oltage regulator , high accurac y ultralow IQ , 1.5 A Analog Devices ADP3339AKCZ -3.3 1 U9 Switch, 6 mm light touch SW , N .O. Alps SKHHAKA010 4 H[...]

  • Page 31

    HSC-ADC-EVALC Rev. 0 | Page 31 of 32 NOTES[...]

  • Page 32

    HSC-ADC-EVALC Rev. 0 | Page 32 of 32 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. EB06676-0-4/07(0)[...]