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Cypress Semiconductor CY7C0430CV manual

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  • Page 1

    10 Gb/s 3.3V QuadPort™ DSE Family CY7C0430BV CY7C0430CV Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-06027 Rev . *B Revised May 23, 2006 Features • QuadPort™ datapath switch ing element (DSE) family allows four independent ports of access for data p ath management an[...]

  • Page 2

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 2 of 37 Functional Description The Quadport Datapath Switching Element (DSE) family offers four ports that may be clocked at independ ent frequencies from one another . Each port can read or write up to 133 MHz [1] , giving the device up to 10 Gb/s of data throughput. The device is 1-Mb (64K [...]

  • Page 3

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 3 of 37 counter is loaded with an external address when the port’s Counter Load pin (CNTLD ) i s asserted LOW . When the port’s Counter Increment pin (CNTIN C ) is asserted, the addre ss counter will increment on each subsequent LOW-to- HIGH transition of that port’s clock signal. This [...]

  • Page 4

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 4 of 37 Addr . Read Port 1 Operation-Control Logic Block Diagram R/W P1 CE 0P1 CE 1P1 LB P1 OE P1 UB P1 I/O 9P1 –I/O 17P1 I/O 0P1 –I/O 8P1 I/O Control Counter/ A 0P1 –A 15P1 CLK P1 CNTLD P1 CNTINC P1 CNTRST P1 16 9 9 MKLD P1 CNTINT P1 MKRD P1 Mask Register Port-1 Port 1 Port 1 64K × 18[...]

  • Page 5

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 5 of 37 Pin Configuration 272-ball Gri d Array (BGA) To p V i e w Note: 4. Central Leads are for thermal dissi pation only . They are connected to device V SS . 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 A LB P1 I/O17 P2 I/O15 P2 I/O13 P2 I/O1 1 P2 I/O9 P2 I/O16 P1 I/O14 P1 I/O12 P[...]

  • Page 6

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 6 of 37 Selection Guide CY7C0430CV –133 CY7C0430CV –100 Unit f MAX2 133 [1] 100 MHz Max Access T ime (Clock to Data) 4.2 5.0 ns Max Operating Current I CC 750 600 mA Max S tandby Cu rrent for I SB1 (All ports TTL Level) 200 150 mA Max S tandby Cu rrent for I SB3 (All ports CMOS Level) 15 [...]

  • Page 7

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 7 of 37 CNTRD P1 CNTRD P2 CNTRD P3 CNTRD P4 Cou nter Readback Input . When asserted LOW , the internal address value of the counter will be read back on the address lines. During CNTRD ope ration, both CNTLD and CNTINC must be HIGH. Counter readback operation has higher priority over mask reg[...]

  • Page 8

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 8 of 37 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature .............. ................. . –65 ° C to + 150 ° C Ambient T emperature with Power Applied .............. .............. .............. ..–55 ° C to + 12[...]

  • Page 9

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 9 of 37 AC T est Load Note: 5. T est conditions: C = 10 pF . V TH =1 . 5 V OUTPUT C (a) Normal Load R = 50 Ω Z 0 = 50 Ω [5] 3.0V GND 90% 90% 10% t R t F 10% All Input Pulses (b) Three-St ate Delay V TH =1 . 5 V OUTPUT 5 pF R = 50 Ω Z 0 = 50 Ω (c) T AP Load TDO C = 10 pF Z 0 =50 Ω GN[...]

  • Page 10

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 10 of 37 Switching Characteristics Over the Industrial Operating Range [6] Parameter Description CY7C0430BV and CY7 C0430CV Unit –133 –100 Min. Max. Min. Max. f MAX2 [7] Maximum Frequency 133 100 MHz t CYC2 [7] Clock Cycle T ime 7.5 10 ns t CH2 Clock HIGH T ime 3 4 ns t CL2 Clock LOW T im[...]

  • Page 11

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 1 1 of 37 t CKLZ [9] Clock HIG H to Output Low-Z 1 1 ns t SINT Clock to INT Set T ime 1 7.5 1 10 ns t RINT Clock to INT Reset T ime 1 7.5 1 10 ns t SCINT Clock to CNTINT Set T ime 1 7.5 1 10 ns t RCINT Clock to CNTINT Reset T ime 1 7.5 1 10 ns Master Reset Timing t RS Master Reset Puls e Widt[...]

  • Page 12

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 12 of 37 Test Clock Test Mode Select TCK TMS Test Data-In TDI Test Data-Out TDO t TCYC t TMSH t TL t TH t TMSS t TDIS t TDIH t TDOX t TDOV Switching W aveforms Master Reset [10] Notes: 10. t S is the set-up time required for all input control signa ls. 1 1. T o Reset the test po rt without re[...]

  • Page 13

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 13 of 37 Read Cycle [12, 13, 14, 15, 16] Notes: 12. OE is asynchronousl y controlled; al l other inputs (exclud ing MRST ) are synchronous to the rising clock edge. 13. CNTLD = V IL , MKLD = V IH , CNTINC = x, and MRST = CNTRST = V IH . 14. The output is disabled (high-impedance state) by CE [...]

  • Page 14

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 14 of 37 Bank Select Read [17, 18] Read-to-Write -to-Read (OE = V IL ) [19, 20, 21, 22] Notes: 17. In this depth expansion example, B1 repr esen ts Bank #1 and B2 is Bank #2; Each bank co nsists of one QuadPo rt DSE device from this data sheet . ADDRESS (B1) = ADDRESS (B2) . 18. LB = UB = OE [...]

  • Page 15

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 15 of 37 Read-to-Write -to-Read (OE Controlled) [19, 20, 21, 22] Read with Address Counter Ad vance [23, 24] Notes: 23. CE 0 = OE = LB = UB = V IL ; CE 1 = R/W = CNTRST = MRST = MKLD = MKRD = CNTRD = V IH . 24. The “Internal Address” is equal to the “External Addr ess” when CNTLD = V [...]

  • Page 16

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 16 of 37 Write with Address Counter Advance [24, 25 ] Note: 25. CE 0 = LB = UB = R/W = V IL ; CE 1 = CNTRST = MRST = MKLD = MKRD = CNTRD = V IH. Switching W aveforms (continued) t CH2 t CL2 t CYC2 A n A n+1 A n+2 A n+3 A n+4 D n+1 D n+1 D n+2 D n+3 D n+4 A n D n t SCLD t HCLD t SCINC t HCIN C[...]

  • Page 17

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 17 of 37 Counter Reset [21, 26, 27] Notes: 26. CE 0 = LB = UB = V IL ; CE 1 = MRST = MKLD = MKRD = CNTRD = V IH . 27. No dead cycle exists during counter reset. A Read or W rite cycle may be coincidental with the counter reset. Switching W aveforms (continued) t CH2 t CL2 t CYC2 CLK ADDRESS I[...]

  • Page 18

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 18 of 37 Load and R ead Address Co unter [28] Notes: 28. CE 0 = OE = LB = UB = V IL ; CE 1 = R/W = CNTRST = MRST = MKLD = MKRD = V IH . 29. Address in output mode. Host must not be driving address bus af ter time t CKLZ in next clock cycle. 30. Address in input mode. Host can drive address bu[...]

  • Page 19

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 19 of 37 Load and R ead Mask Register [32] Notes: 32. CE 0 = OE = LB = UB = V IL ; CE 1 = R/W = CNTRST = MRST = CNTLD = CNTRD = CNTINC =V IH . 33. This is the value of the Mask Register read out on the address lines. Switching W aveforms (continued) t SA t HA t SMLD t HMLD t CH2 t CL2 t CYC2 [...]

  • Page 20

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 20 of 37 Port 1 Write to Port 2 Read [34, 35, 36] Notes: 34. CE 0 = OE = LB = UB = CNTLD =V IL ; CE 1 = CNTRST = MRST = M KLD = MKRD = CNTRD = CNTINC =V IH . 35. This timing is valid when one port is writing, and one or more of the three other ports is reading the same location at the same ti[...]

  • Page 21

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 21 of 37 Counter Interrupt [37, 38, 39] Mailbox Interrup t Timing [40, 41, 42, 43, 44] Notes: 37. CE 0 = OE = LB = UB = V IL ; CE 1 = R/W = CNTRST = MRST = CNTRD = MKRD = V IH . 38. CNTINT is always driven. 39. CNTINC goes LOW as the counter address mask ed p ortion is incremented from xx7F h[...]

  • Page 22

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 22 of 37 T able 1. Read /Write and Enable Operation (Any Port) [45, 46, 47] Input s Outputs Operation OE CLK CE 0 CE 1 R/W I/O 0 – I/O 17 X H X X High-Z Deselected X X L X High-Z Deselected XL H L D IN Wri te LL H H D OUT Read H X L H X High-Z Outputs Disabled T able 2. Ad dress Counter and[...]

  • Page 23

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 23 of 37 Master Reset The QuadPort DSE device underg oes a complete reset by taking its Master Reset (MRST ) input LOW . T he Master Reset input can switch asynchronously to the clocks. A Master Reset initializes the internal burst counte rs to zero, and the counter mask registers to all o ne[...]

  • Page 24

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 24 of 37 Address Counter Control Operations Counter enable inputs are provided to stall the operation of the address input and utilize the inte rnal address generated by the internal counter for the fast i nterleaved memory applications. A port’s burst counter is load ed with the port’s C[...]

  • Page 25

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 25 of 37 Counter-Mask Register The burst counter has a mask regi ster that controls when and where the counter wraps. An interrupt flag (CNTINT ) is asserted for one clock cycl e when the unmasked portion of the counter address wraps around from all one s (CNTINC must be asserted) to all zero[...]

  • Page 26

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 26 of 37 address the entire memory array (depend on the value of the mask register) and loop back to location 0. The increment operation is second in priority to load operation. 3. Readback: the internal value of either the burst counter or the mask register can be read out on the address lin[...]

  • Page 27

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 27 of 37 The EXTEST , and SAMPLE/PREL OAD instructions can be used to ca pture th e content s of t he Input and Outpu t ring. Identifica tion (ID) Register The ID register is loade d with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instr[...]

  • Page 28

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 28 of 37 number of TCK cycl es depending on the TC K and CLKBIST frequency . t CYC is total number of TCK cycles required to run MBIST . SPC is the Synchronizati on Padding Cycles (4–6 cycles). m is a constant represents the number of read and write opera- tions required to run MBIST algori[...]

  • Page 29

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 29 of 37 T AP Controller St ate Diagram (FSM) [53] Note: 53. The “0”/”1” next to each state rep resents the va lue at TMS at the rising edge of TCK. TEST -LOGIC RESET RUN_TEST/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT -DR EXIT1-DR P AUSE-DR EXIT2-DR UPDA TE-DR SELECT IR-SCAN CAPTURE-IR SH[...]

  • Page 30

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 30 of 37 JT AG/BIST T AP Controller Block Diagram T able 4. Identificatio n Register Definitions Instruction Field Va l u e Description Revision N umber (31: 28) 1h Re served for version number Cypress Device ID (27:12) C000h Defines Cypress part number Cypress JEDEC ID (1 1:1) 34h Allows un [...]

  • Page 31

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 31 of 37 T able 5. Scan Reg isters Sizes Register Name Bit Size Instruction (IR) 4 Bypass (BYR) 1 Identification (IDR) 32 MBIST Control (MCR) 2 MBIST Result (MRR) 25 MBIST Debug (MDR) 100 Boundary Scan (BSR) 39 2 T able 6. Ins truction Identificatio n Codes Instruction Code Description EXTEST[...]

  • Page 32

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 32 of 37 001001 chkr_r All ports read topological checkerboard data. 001000 n_ chkr_w Port 1 write inverse topological checkerboard data. 01 10 00 n_chkr_r All ports read inverse topological checkerboard data. 01 10 01 uaddr_zeros2 Port 2 write all zeros to memory usi ng Unique Address Algori[...]

  • Page 33

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 33 of 37 T able 9. Boundary Scan Order Cell # Signal Name Bump (Ball) ID 2 A0_P4 K20 4 A1_P4 J19 6 A2_P4 J18 8 A3_P4 H20 10 A4_P4 H19 12 A5_P4 G19 14 A6_P4 G18 16 A7_P4 F20 18 A8_P4 F19 20 A9_P4 F18 22 A10_P4 E20 24 A1 1_P4 E19 26 A12_P4 D19 28 A13_P4 D18 30 A14_P4 C20 32 A15_P4 C19 34 CNTINT[...]

  • Page 34

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 34 of 37 166 IO2_P1 Y5 168 IO3_P1 W5 170 IO4_P1 Y4 172 IO5_P1 W4 174 IO6_P1 Y3 176 IO7_P1 W3 178 IO8_P1 Y2 180 IO0_P2 V9 182 IO1_P2 Y10 184 IO2_P2 W9 186 IO3_P2 Y9 188 IO4_P2 W8 190 IO5_P2 Y8 192 IO6_P2 V6 194 IO7_P2 Y7 196 IO8_P2 W7 198 A0_P2 L1 200 A1_P2 M2 202 A2_P2 M3 204 A3_P2 N1 206 A4_[...]

  • Page 35

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 35 of 37 330 IO13_P2 A4 332 IO14_P2 B4 334 IO15_P2 A3 336 IO16_P2 B3 338 IO17_P2 A2 340 IO9_P1 C9 342 IO10_P1 A10 344 IO1 1_P1 B9 346 IO12_P1 A9 348 IO13_P1 B8 350 IO14_P1 A8 352 IO15_P1 C6 354 IO16_P1 A7 356 IO17_P1 B7 358 IO9_P3 A15 360 IO10_P3 B15 362 IO1 1_P3 A16 364 IO12_P3 B16 366 IO13_[...]

  • Page 36

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 36 of 37 © Cypress Semi conductor Corpora tion, 2006. The i nformation cont ained here in is subject to ch ange withou t notice. Cypress S emic onductor Corporation assu mes no responsibility for the use of any circuitry o ther than circui try embodied i n a Cypress prod uct. Nor does it con[...]

  • Page 37

    CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 37 of 37 Document History Page Document Title: CY7C0430BV , CY7C0430CV 10 Gb/s 3.3V QuadPort DSE Family Document Number: 38 -06027 REV . ECN NO. Issue Date Orig. of Change Description of Cha nge ** 10 9906 09/10/01 SZV Change from S p ec number: 38-01052 to 38-06027 *A 1 15042 05/23/02 FSG Re[...]