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Cypress Semiconductor CY7C1303BV25 manual

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Table of contents for the manual

  • Page 1

    18-Mbit Burst of 2 Pipelined SRAM with Q DR™ Ar c hi tectu r e CY7C1306BV25 CY7C1303BV25 Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05627 Rev . *A Revised April 3, 2006 Features • Separate independent Read and Write data ports — Supports concurrent transactions •[...]

  • Page 2

    CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev . *A Page 2 of 19 512Kx18 CLK A (18:0) Gen. K K Control Logic Address Register D [17:0] Read Add. Decode Read Data Reg. RPS WPS Q [17:0] Control Logic Address Register Reg. Reg. Reg. 18 19 18 36 Wri te 18 BWS 0 Vr e f Write Add. Decode Data Reg Writ e Dat a Reg Memory Array 512Kx18 Memory Array 18 [...]

  • Page 3

    CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev . *A Page 3 of 19 Pin Configuration 165-ball FBGA (13 x 15 x 1.4 mm ) Pinout CY7C1303BV25 (1M x 18 ) 1 2 3456 7 8 9 1 0 1 1 A NC Gnd/ 144M NC/ 36M WPS BWS 1 K NC RPS A Gnd/ 72M NC B NC Q9 D9 A NC K BWS 0 AN C N C Q 8 C NC NC D10 VSS A A A VSS NC Q7 D8 D NC D1 1 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC[...]

  • Page 4

    CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev . *A Page 4 of 19 Pin Definitions Name I/O Description D [x:0] Input- Synchronous Data input signals, sampled on the rising edge of K and K clocks during valid write opera- tions. CY7C1303BV25 – D [17:0] CY7C1306BV25 – D [35:0] WPS Input- Synchronous Write Port Select, active LOW . Sampled on t[...]

  • Page 5

    CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev . *A Page 5 of 19 Introduction Functional Overview The CY7C1303BV25/CY7C1306BV25 are synchro nous pipelined Burst SRAM equ ipped with both a Read port an d a Write port. The Read port is dedicated to Read operations and the Write port is dedicated to Write operations. Data flows into the SRAM throu[...]

  • Page 6

    CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev . *A Page 6 of 19 operation is identi cal to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same i n thi s mo de . T o use this mode of ope r a ti on , the user must tie C and C HIGH at power-up.This function is a strap option and not alte[...]

  • Page 7

    CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev . *A Page 7 of 19 Write Desc riptions (CY7C1303BV25) [2 , 8] BWS 0 BWS 1 KK Comment s L L L-H - During the Data portion of a W ri te sequence, both bytes (D [17:0] ) are written into the device. L L - L-H During the Data portion of a W rite sequence, both bytes (D [17:0] ) are written into the devi[...]

  • Page 8

    CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev . *A Page 8 of 19 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial bo undary scan test access port (T AP) in the FBGA package. This part is fully compliant with IEEE S tandard #1 149.1-1900. The T AP operates using JEDEC standard 2.5V I/O logi c levels. Disabling the JT AG[...]

  • Page 9

    CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev . *A Page 9 of 19 is loaded into the instruction register upon power-up or whenever the T AP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction caus es the b oundary scan register to be connected between th e TDI and TDO pins when th e T AP controller is in a Shift-DR s[...]

  • Page 10

    CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev . *A Page 10 of 19 T AP Controller S tate Diagram [9] Note: 9. The 0/1 next to each state re present s the value at TMS at the rising edge of TCK. TEST -LOGIC RESET TEST -LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT -DR EXIT1-DR P AUSE-DR EXIT2-DR UPDA TE-DR SELECT IR-SCAN CAPTURE-DR SHIFT -IR EXIT1[...]

  • Page 11

    CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev . *A Page 1 1 of 19 T AP Controller Block Diagram T AP Electrical Characteristi cs Over the Operating Rang e [10, 14, 17] Parameter Description T est Conditions Min. Max. Unit V OH1 Output HIGH V oltage I OH = − 2.0 mA 1.7 V V OH2 Output HIGH V oltage I OH = − 100 µ A2 . 1 V V OL1 Output LOW V[...]

  • Page 12

    CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev . *A Page 12 of 19 Output Times t TDOV TCK Clock LOW to TDO V alid 20 ns t TDOX TCK Clock LOW to TDO Invalid 0 ns T AP T iming and T est Conditions [1 2] T AP AC Switching Characte ristics Over the Operating Range [1 1, 12] (continued) Parameter Description Min. Max. Unit (a) TDO C L = 20 pF Z 0 = [...]

  • Page 13

    CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev . *A Page 13 of 19 Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 107 Instruction Codes Instruction Code Description EXTEST 000 Captures the In put/Output ring contents. IDCODE 001 Loads the ID register with the ve ndor ID code and places the re gister between[...]

  • Page 14

    CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev . *A Page 14 of 19 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11 H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 2 6N 29 9G 56 6A 83 1J 3 7P 30 11 F 57 5B 84 2J 4 7N 31 11 G 58 5A 85 3K 5 7R 32 9F 59 4A 86 3J 6 8R 33 10F 60 5C 87 2K 7 8P 34 11 E 61 4B 88 1K 8 9R 35 10[...]

  • Page 15

    CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev . *A Page 15 of 19 Maximum Ratings (Above which the useful life may be impaired.) S torage T emperature ............. .............. ..... –65°C to + 150°C Ambient T emperature with Power Applied ........... ............................ ..... – 55°C to + 125°C Supply V oltage on V DD Relati[...]

  • Page 16

    CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev . *A Page 16 of 19 Cap acit ance [23] Parameter Description T est Conditions Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 2.5V . V DDQ = 1.5V 5p F C CLK Clock Input Capacitance 6 pF C O Output Capacitance 7 pF AC T est Loads and W aveforms Switching Characteristics Over the Opera[...]

  • Page 17

    CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev . *A Page 17 of 19 Switching W aveforms [25, 26, 27] Notes: 24. t CHZ , t CLZ , are specified with a load capa cit ance of 5 pF as in part (b) of AC T est Loads. Transition is m easured ± 100 mV from steady-st ate voltag e. 25. Q00 refers to output from address A0. Q01 ref ers to output from the n[...]

  • Page 18

    CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev . *A Page 18 of 19 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress [...]

  • Page 19

    CY7C1306BV25 CY7C1303BV25 Document #: 38-05627 Rev . *A Page 19 of 19 Document History Page Document Title: CY7C1303BV25/CY7C1306BV25 18 -Mbit Burs t of 2 Pipelined SRAM with QDR™ Architecture Document Number: 38-05627 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 25301 0 See ECN SYT New Data Sheet *A 43686 4 See ECN NXR Conve[...]