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Cypress CY14B104N manual

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Table of contents for the manual

  • Page 1

    CY14B104L, CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-07102 Rev . *L Revised December 19, 2008 Features ■ 20 ns, 25 ns, and 45 ns Access Times ■ Internally organized as 512K x 8 (CY14B104L) or 256K x 16 (CY14B104N) ■ Hands[...]

  • Page 2

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 2 of 25 Pinout s Figure 1. Pin Diagram - 48 FBG A Figure 2. Pin Diag ram - 44 Pin TSOP II WE V CC A 11 A 10 V CAP A 6 A 0 A 3 CE NC NC DQ 0 A 4 A 5 NC DQ 2 DQ 3 NC V SS A 9 A 8 OE V SS A 7 NC NC NC A 17 A 2 A 1 NC V CC DQ 4 NC DQ 5 DQ 6 NC DQ 7 NC A 15 A 14 A 13 A 12 HSB 3 2 6 5 4 1 D E B A C[...]

  • Page 3

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 3 of 25 Figure 3. Pin Diagram - 54 Pi n TSOP II (x16) Pin Definitions Pin Name IO T ype Description A 0 – A 18 Input Address Inputs Used to Select one of the 524,288 bytes of the nvSRAM for x8 Co nfiguration . A 0 – A 17 Address Inputs Used to Select one of the 262,144 words of the n vSRA[...]

  • Page 4

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 4 of 25 Device Operation The CY14B104L/CY1 4B104N nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvola tile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to [...]

  • Page 5

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 5 of 25 Hardware RECALL (Power Up) During power up or after any low power condition (V CC <V SWITCH ), an internal RECALL re quest is latched. When V CC again exceeds the sense voltage of V SWITCH , a RECALL cycle is automatically initiated and takes t HRECALL to complete. During this time[...]

  • Page 6

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 6 of 25 Preventing AutoStore The AutoS t ore function is disabled by initiating an AutoS tore disable sequence. A sequence of read ope rations is performed in a manner similar to the software STORE initiation. T o initiate the AutoS tore disa ble sequence, the following sequence o f CE contro[...]

  • Page 7

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 7 of 25 Maximum Ratin gs Exceeding maximum ratings may impair the useful life of the device. These user guid elines are not tested. S torage T emperature ................ ................. –65 ° C to +150 ° C Maximum Accumulated Storage T ime At 150 ° C Ambient T emperature .............[...]

  • Page 8

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 8 of 25 AC T est Conditions Input Pulse Levels .... ............................ .................... 0V to 3V Input Rise and Fall T imes (10% - 90%).................... .... < 3 ns Input and Output T iming Reference Levels . ................... 1.5V Dat a Retention and Endurance Parameter[...]

  • Page 9

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 9 of 25 AC Switching Characteristics Parameters Descr iption 20 ns 25 ns 45 ns Unit Cypress Parameters Alt Parameters Min Max Min Ma x Min Max SRAM Read Cycle t ACE t ACS Chip Enable Access Time 20 25 45 ns t RC [14] t RC Read Cycle T ime 20 25 45 ns t AA [15] t AA Address Access T ime 20 25 [...]

  • Page 10

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 10 of 25 Figure 7. SRAM Rea d Cycle #2: CE and OE Controlle d [3, 14, 18] Figure 8. SRAM Write Cycle #1: WE Controlled [3, 17, 18, 19] $GGUHVV9D OLG $G GUH VV 'DWD2XWSXW 2XWS XW 'DWD9D OL G 6WDQG E $FWLYH +L JK ,P S HG DQFH &( 2( %+(%/ ( , && W +=&a[...]

  • Page 11

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 1 1 of 25 Figure 9. SRAM Write Cycle #2: CE Controlled [3 , 17, 18, 19] Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled [3, 17, 18, 19] D ata Ou tput Da ta Inpu t In put D ata Va li d High Impedance Ad d res s Va lid Ad dre ss t WC t SD t HD BHE , BLE WE CE t SA t SCE t HA t BW t PWE &[...]

  • Page 12

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 12 of 25 AutoStore/Power Up RECALL Parameters Description CY14B104L/CY14B1 04N Unit Min Max t HRECALL [20] Power Up RECALL Duration 20 ms t STORE [21] ST ORE Cycle Duration 8 ms t DELA Y [22] Time Allowed to Complete SRAM Cycle 1 70 μ s V SWITCH Low V oltage Trigger Level 2.65 V t VCCRISE VC[...]

  • Page 13

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 13 of 25 Sof tware Controlled STORE/RECALL Cycle In the following table, the so ftware c o ntrolled STORE/RECALL cycle p arameters are listed. [25, 26] Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t RC STORE/RECALL Initiation Cycle T ime 20 25 45 ns t SA Address Setup[...]

  • Page 14

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 14 of 25 Hardware STORE Cycle Parameters Description CY14 B104L/CY14B104N Unit Min Max t PHSB Hardware ST ORE Pulse Width 15 ns t HLBL Hardware ST ORE LOW to STORE Busy 500 ns Switching W aveforms Figure 14. Hardware STORE Cycle [21] Figure 15. Soft Sequence Processi ng [27, 28] W 3+6% W 3+6 [...]

  • Page 15

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 15 of 25 T ruth T able For SRAM Operations HSB should remain HIGH for SRAM Operations. For x8 Configuration CE WE OE Inputs/Outputs [2 ] Mode Power H X X High Z Deselect/Power down S tandby L H L Data Out (DQ 0 –DQ 7 ); Read Active L H H High Z Output Disabled Active L L X Data in (DQ 0 –[...]

  • Page 16

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 16 of 25 Ordering Information Speed (ns) Ordering Code Package Diagram Package T ype Operating Range 20 CY14B104L-ZS20XCT 51-85087 44-pin TSOP II Commercial CY14B104L-ZS20XIT 51-85087 44-pin TSOP II Industrial CY14B104L-ZS20XI 51-85087 44-pin TSOP II CY14B104L-BA20XCT 51-85128 48-ball FBGA Co[...]

  • Page 17

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 17 of 25 45 CY14B104L-ZS45XCT 51-85087 44-pin TSOP II Commercial CY14B104L-ZS45XIT 51-85087 44-pin TSOP II Industrial CY14B104L-ZS45XI 51-85087 44-p in TSOP II CY14B104L-BA45XCT 51-85128 48-ball FBGA Commercial CY14B104L-BA45XIT 51-85128 48-b all FBGA Industrial CY14B104L-BA45XI 51-85128 48-b[...]

  • Page 18

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 18 of 25 Part Numbering Nomenclature Option: T - T ape & Reel Blank - S td. S peed: 20 - 20 ns 25 - 25 ns Data Bus: L - x8 N - x16 Density: 104 - 4 Mb V oltage: B - 3.0V Cypress CY 14 B 104 L - ZS P 20 X C T NVSRAM 14 - Auto Store + Software Store + Hardware Store T emperature: C - Commer[...]

  • Page 19

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 19 of 25 Package Diagrams Figure 16. 44-Pin TSOP II (51-85087) MAX MIN. DIMENSION IN MM (INCH) 11.938 (0.470) PLANE SEATING PIN 1 I.D. 44 1 18.517 (0.729) 0.800 BSC 0° -5° 0.400(0.016) 0.300 (0.012) EJECTOR PIN R G O K E A X S 11.735 (0.462) 10.058 (0.396) 10.262 (0.404) 1.194 (0.047) 0.991[...]

  • Page 20

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 20 of 25 Figure 17. 48 -Ball FBGA - 6 mm x 10 m m x 1.2 mm (51 -85128) Package Diagrams (continued) A 1 A1 CORNER 0.75 0.75 Ø0.30±0.05(48X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.21±0.05 1.20 MAX C SEATING PLANE 0.53±0.05 0.25 C 0.15 C A1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 3.75 5.25 B C [...]

  • Page 21

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 21 of 25 Figure 18. 54-Pin TSOP II (51-85160) Package Diagrams (continued) 51-85160 -** [+] Feedback[...]

  • Page 22

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 22 of 25 Document History Page Document Title: CY14B104L/CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM Document Number: 001-07102 Rev . ECN No. Submission Date Orig. of Change Description of Cha nge ** 431039 See ECN TUP New Data Sheet *A 489096 See ECN TUP Removed 48 SSOP Package Added 48 FBG[...]

  • Page 23

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 23 of 25 *F 1889928 See ECN vsutmp8/AE- SA Added Footnotes 1, 2 and 3. Updated logi c block diagram Added 48-FBGA (X8) Pin Dia gram Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44-TSOP II (x8). Updated pin definitions table. Corrected typo in V IL min spec Changed the value of [...]

  • Page 24

    CY14B104L, CY14B104N Document #: 001-07102 Rev . *L Page 24 of 25 *J 2600941 1 1/04/08 GVCH/PYRS Removed 15 n s access speed Updated Logi c block diagra m Updated footnote 1 Added footnote 2 and 5 Pin definition: Updated WE , HSB and NC pin description Page 4:Updated SRAM READ, SRAM WRIT E, Autostore op eration description Page 4:Updated Hardware s[...]

  • Page 25

    Document #: 001-07102 Rev . *L Revised December 19, 2008 Page 25 of 25 AutoS tore and QuantumT rap are registered tradem arks of Cypress Semico nductor Corpora tion. All product s and company names mentio ned in this document are th e trad emarks of the ir resp ectiv e holders. CY14B104L, CY14B104N © Cypress Semicondu ctor Corpor ation, 2006-2008.[...]