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Cypress CY14E256L manual

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Table of contents for the manual

  • Page 1

    CY14E256L 256 Kbit (32K x 8) nvSRAM Cypress Semiconducto r Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-06968 Rev . *F Revised January 30, 2009 Features ■ 25 ns, 35 ns, and 45 ns acce ss times ■ Pin compatible with ST K14C88 ■ Hands off automatic STORE on power dow n with external 68 µ[...]

  • Page 2

    CY14E256L Document Number: 001-06968 Rev . *F Page 2 of 18 Pin Configurations Figure 1. Pin Diagram: 32-Pin SOIC/DIP Pin Definitions Pin Name Alt IO T ype Description A 0 –A 14 Input Address Input s. Used to select one of the 32,768 bytes of the nvSRAM. DQ 0 -DQ 7 Input or Output Bidirectiona l Data IO Lines . Used as input or output lines depend[...]

  • Page 3

    CY14E256L Document Number: 001-06968 Rev . *F Page 3 of 18 Device Operation The CY14E256L nvSRAM is made up of two functional compo - nents paired in the same physical cell. These ar e an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolati[...]

  • Page 4

    CY14E256L Document Number: 001-06968 Rev . *F Page 4 of 18 Hardware STORE (HSB ) Operation The CY14E256L p rovides the HSB pi n for controlling and acknowledging the STORE operations. The HSB pin is used to request a hardware ST OR E cycle. When the HSB pin is driven LOW , the CY14E256L conditionally initiates a STORE operation after t DELA Y . An [...]

  • Page 5

    CY14E256L Document Number: 001-06968 Rev . *F Page 5 of 18 Dat a Protection The CY14E256L pro tects data from corruption during low voltag e conditions by in hibiting all ex ternally initiated STORE and WRITE operations. The l ow voltage condition is detected when V CC is less than V SWITCH . If the CY14E256L is in a WRITE mode (both CE and WE are [...]

  • Page 6

    CY14E256L Document Number: 001-06968 Rev . *F Page 6 of 18 Best Practices nvSRAM products have been used effectively for over 15 years. While ease of use is one of t he product’s main system values, experience gained worki ng with hundreds of applic ations has resulted in the following suggestion s as be st practices: ■ The nonvolatile cell s i[...]

  • Page 7

    CY14E256L Document Number: 001-06968 Rev . *F Page 7 of 18 Maximum Ratin gs Exceeding maximum ratings may shorten the useful life of the device. These user g uidelines are not tested. S torage T emperature ............. ... .. ... ............ –65 ° C to +150 ° C Ambient T emperature with Power Applied ............ ... ....................... .[...]

  • Page 8

    CY14E256L Document Number: 001-06968 Rev . *F Page 8 of 18 V OL Output LOW Volt age I OUT = 8 mA 0.4 V V BL Logic ‘0’ V oltage on HSB Output I OUT = 3 mA 0.4 V V CAP S torage Capacitor Between V CAP pin and Vss, 6V rated. 68 µF + 20% nom. 54 260 uF Dat a Retention and Endurance Parameter Descr iption Min Unit DA T A R Data Retention 100 Y ears[...]

  • Page 9

    CY14E256L Document Number: 001-06968 Rev . *F Page 9 of 18 AC Switching Characteristics SRAM Read Cycle Parameter Description 25 ns 35 ns 45 n s Unit Min Max Min Max Min Max Cypress Parameter Alt t ACE t ELQV Chip Enable Access Time 25 35 45 ns t RC [9] t AVAV, t ELEH Read Cycle T ime 25 35 45 ns t AA [10] t AV Q V Address Access T ime 25 35 45 ns [...]

  • Page 10

    CY14E256L Document Number: 001-06968 Rev . *F Page 10 of 18 SRAM Writ e Cycle Parameter Descriptio n 25 ns 35 ns 45 ns Unit Min Max Min Max Min Max Cypress Parameter Alt t WC t AVAV Write Cycle T ime 25 35 45 ns t PWE t WL WH, t WLEH Write Pulse Width 20 25 30 ns t SCE t EL WH, t ELEH Chip Enable T o End of Write 20 25 3 0 ns t SD t DVWH, t DVEH Da[...]

  • Page 11

    CY14E256L Document Number: 001-06968 Rev . *F Page 1 1 of 18 AutoS tore or Power Up RECALL Parameter Alt Description CY14E256L Unit Min Max t HRECALL [15] t RESTORE Power up RECALL Duration 550 μ s t STORE [16] t HLHZ STORE Cycle Duration 10 ms t DELA Y [16] t HLQZ , t BLQZ T ime Allowe d to Complete SRAM Cycle 1 μ s V SWITCH Low V oltage T rigge[...]

  • Page 12

    CY14E256L Document Number: 001-06968 Rev . *F Page 12 of 18 Sof tware Controlled STORE/RECALL Cycle The software controlled ST ORE/RECALL cycle follows. [19] Parameter Al t Desc ription 25 ns 35 ns 45 ns Unit Min Max Min Max Min Max t RC [16] t AVAV STORE/RECALL Initiation Cycle T ime 25 35 45 ns t SA [18, 19] t A VEL Address Setup T ime 0 0 0 ns t[...]

  • Page 13

    CY14E256L Document Number: 001-06968 Rev . *F Page 13 of 18 Hardware STORE Cycle Parameter Alt Description CY14E256L Unit Min Max t DHSB [16, 20] t RECOVER, t HHQX Hardware STORE High to Inhibit Off 700 ns t PHSB t HLHX Hardware STORE Pulse Width 15 ns t HLBL Hardware STORE Low to ST ORE Bus y 300 ns Switching W aveforms Figure 13. Hardware STORE C[...]

  • Page 14

    CY14E256L Document Number: 001-06968 Rev . *F Page 14 of 18 Ordering Information Spe e d (ns) Ordering Code Package Diagram Package T ype Operating Range 25 CY14E256L-SZ25XCT 51-85127 32-pin SOIC (300 mil) Commercial CY14E256L-SZ25XC 51-85127 32-pin SOIC (300 mil) CY14E256L-SZ25XIT 51-85127 32-pi n SOIC (300 mil) Industrial CY14E256L-SZ25XI 51-8512[...]

  • Page 15

    CY14E256L Document Number: 001-06968 Rev . *F Page 15 of 18 Package Diagram Figure 14. 32-Pin (300 Mil) SOIC (51-85127) 51-85058 *A PIN 1 ID SEATING PLANE 1 16 17 32 DIMENSIONS IN INCHES[MM] MIN. MAX. 0.292[7.416] 0.299[7.594] 0.405[10.287] 0.419[10.642] 0.050[1.270] TYP. 0.090[2.286] 0.100[2.540] 0.004[0.101] 0.0100[0.254] 0.006[0.152] 0.012[0.304[...]

  • Page 16

    CY14E256L Document Number: 001-06968 Rev . *F Page 16 of 18 Figure 15. 32-Pin (300 Mil) CDIP (001-5169 4) Package Diagram (continued) 001-51694 ** [+] Feedback[...]

  • Page 17

    CY14E256L Document Number: 001-06968 Rev . *F Page 17 of 18 Document History Page Document Title: CY14E256L 256 Kbit (32K x 8) nvSRAM Document Number: 00 1-069 68 Rev . ECN No. Submission Date Orig. of Change Description o f Chan ge ** 427789 See ECN TUP New data sheet *A 437321 See ECN TUP Show data sheet on exte rnal Web *B 472053 See ECN TUP Upd[...]

  • Page 18

    Document Number: 001-06968 Rev . *F Revised January 30, 20 09 Pag e 18 of 18 AutoS tore and Qua ntumTr ap are registered tr ademarks of Cypress Se miconductor Corpor ation. All produ cts and comp any names mentio ned in this docum ent may be the trade marks of t heir respe ctive holders. CY14E256L © Cypress Semicondu ctor Corpor ation, 2006-200 9.[...]