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Cypress CY25822-2 manual

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Table of contents for the manual

  • Page 1

    CK-SSC Spread Spectru m Clock Genera to r CY25822- 2 Cypress Semicondu ctor Corporatio n • 3901 N ort h Fir st S tr eet • Sa n Jos e , CA 95134 • 408 -943-2600 Document #: 38-0753 1 Rev . ** Revi sed March 18 , 2003 Features • 3.3V oper ation • 48- and 6 6-MHz frequency s upport • Selec table slew rate control • 350-pS jitte r •I 2 [...]

  • Page 2

    CY25822 -2 Docum ent #: 38 -07531 Rev . ** Page 2 o f 9 Ser ial Da ta Inter face T o enhance the fl exibility an d function of the cl ock synthes izer , a two-signal serial in terface is provided. Thro ugh the Seri al Data In terface, va rious dev ice function s such as individual clock o utput buf fers, etc., c an be in dividual ly enabl ed or dis[...]

  • Page 3

    CY25822 -2 Docum ent #: 38 -07531 Rev . ** Page 3 o f 9 .... Data By te N –8 bits 56 Acknowledg e .... Acknow ledge from s lave .... Dat a bytes from slave/Ac knowledg e .... S top .... Data b yte N from sl ave – 8 bi ts .... Not Ackn owledge .... S top T able 2. Block Read and B lock W rite Protocol (conti nued) T able 3. Byte Read a nd Byte W[...]

  • Page 4

    CY25822 -2 Docum ent #: 38 -07531 Rev . ** Page 4 o f 9 Bytes 2 throu gh 5: Reserved Registers P WRDWN# (Power-down) Clarifi cation The PWR DWN# (Power-d own) pin i s used t o shut of f ALL clocks p rior to sh utting of f power to the devi ce. PWRDWN# i s an async hronous ac tive LOW inp ut. This signal is synchro- nized in ternally to the device p[...]

  • Page 5

    CY25822 -2 Docum ent #: 38 -07531 Rev . ** Page 5 o f 9 CLKOUT and REFOUT Enable Clarification The CLKOU T enable and REFOU T enable I 2 C register bit s are used t o shot-of f the CLKOUT and REFOUT cl ocks individ ually . The V CO and cry stal os cilla tor mus t rema in on. A shutdown clock is driven lo w . ALL clocks need to be stopp ed in a pred[...]

  • Page 6

    CY25822 -2 Docum ent #: 38 -07531 Rev . ** Page 6 o f 9 T able 5. Absolu te Maximum R atings Parameter De scription Condition Min. Max. Unit V DD Core Supply V oltage –0.5 4.6 V V DD_A An alo g S upp l y V oltag e –0.5 4.6 V V IN Input V olt age Relative t o V SS –0. 5 V DD + 0.5 VDC T S T emperature, S torag e Non Fun ctional –65 +15 0 °C[...]

  • Page 7

    CY25822 -2 Docum ent #: 38 -07531 Rev . ** Page 7 o f 9 t F ALLL1 Falling Ed ge Rate Measured from 2.4V to 0.4V REFOUT and CLOCKOUT 1.33 4.0 V/ns Low Buf fer S trength Refer to I 2 C Control t RISEH2 Rise T ime Measured from 0.4V to 2.4V REFOUT and CLOCKOUT 0.4 1.0 ns High Buffer S trength Refer to I 2 C Control t F ALLH2 Fall T i me Measured from [...]

  • Page 8

    CY25822- 2 Docum ent #: 38 -07531 Rev . ** Page 8 o f 9 © Cypress Semico nductor Corporati on, 2003. The information cont ained herein is su bject to change witho ut notice. Cypress S emico nductor Cor poration assumes no r esponsibility for the use of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semi conductor pr oduct. Nor does i[...]

  • Page 9

    CY25822 -2 Docum ent #: 38 -07531 Rev . ** Page 9 o f 9 Document History Page Doc ument Title : CY25 822 -2 CK- SSC S pre ad Sp ectr um Clo ck Ge nera tor Documen t Number: 3 8-07531 REV . ECN NO . Issue Dat e Orig. of Change Description of Ch ange ** 124462 0 3/19/03 RGL New Dat a Sheet [+] Feedback[...]