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Cypress CY7C027VN manual

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Table of contents for the manual

  • Page 1

    CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V 3.3V 32K/64K x 16/18 Dual-Port S tatic RAM Cypress Semiconducto r Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-06078 Rev . *B Revised December 09, 2008 Features ■ T rue Dual-Ported memory cells which allo w simultaneous access of the same memory loc[...]

  • Page 2

    CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 2 of 18 Pin Configurations Figure 1. 100-Pin TQ FP (T op V iew) 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 A9R A10R A1 1R A12R A13R A14R UBR NC LBR CE1R SEMR OER GND NC A15R GND[...]

  • Page 3

    CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 3 of 18 Pin Configurations (continued) Figure 2. 100-Pin TQ FP (T op V iew) 1 3 2 92 91 90 84 85 87 86 88 89 83 8 2 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 A8R A9R A10R A1 1R A12R A13R CE0R A15R UBR SEMR R/WR GND [...]

  • Page 4

    CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 4 of 18 Architecture The CY7C027V/027VN/027 A V/028V and CY7037V/037A V/038V consist of an array of 32K and 64K words of 16 and 18 bits each of dual-port RAM cells, I/O and addre ss lines, and control signals (C E , OE , R/W ). These control pins permit independent a[...]

  • Page 5

    CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 5 of 18 generated to the owner . The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Each port can read the other p ort ’s mailbox without resetting the interrupt. The active state of th e busy signal (to a port) pr[...]

  • Page 6

    CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 6 of 18 Maximum Ratin gs Exceeding maximum ratings may shorten the useful life of the device. User gui d elines are not teste d . S torage T emperature ............. ... .. ............... –65 ° C to +150 ° C Ambient T emperature with Power Applied ............ .[...]

  • Page 7

    CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 7 of 18 Figure 3. AC T est Loads and Waveforms 3.0V GND 90% 90% 10% 3n s 3 ns 10% ALL INPUT PULSES (a) Normal Load (Load 1) R1 = 590 Ω 3.3V OUTPUT R2 = 435 Ω C= 3 0 pF V TH =1 . 4 V OUTPUT C= 30 pF (b) Thévenin Equivalen t (Load 1) (c) Three-State Delay (Load 2) R[...]

  • Page 8

    CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 8 of 18 Dat a Retention Mode The CY7C027V/027VN/027 A V/028V and CY7037V/037A V/038V are designed with b attery backup in mind. Data retention volt age and supply current are guaranteed over temper ature. The fo llowing ru les ensure d ata reten tion: 1. Chip enable [...]

  • Page 9

    CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 9 of 18 Switching W aveforms Notes 15. R/W is HIGH for read cycles. 16. Device is continuously selected C E = V IL and UB or LB = V IL . This waveform cann ot be used for semaph ore reads. 17. OE = V IL . 18. Address valid prior to or coincident with C E transition L[...]

  • Page 10

    CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 10 of 18 Notes 20. R/W mu st be HIGH during al l address transitio ns. 21. A write occurs during the overlap (t SCE or t PWE ) of a LOW CE or SEM and a LOW UB or LB . 22. t HA is measured from t he earlier of CE or R/W or (SEM or R/W ) going HIGH at the end of write [...]

  • Page 11

    CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 1 1 of 18 Notes 29. CE = HIGH for the duration of the above timing (both write and re ad cycle). 30. I/O 0R = I/O 0L = LOW (request semaphore); CE R = CE L = HIGH. 31. Semaphores are reset (available to both ports) at cycle start. 32. If t SPS is violated, the semaph[...]

  • Page 12

    CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 12 of 18 Note 33. CE L = CE R = LOW . Switching W aveforms (continued) VA L I D t DDD t WDD MA TCH MA TCH R/W R DA T A IN R DA T A OUTL t WC ADDRESS R t PWE VA L I D t SD t HD ADDRESS L t PS t BLA t BHA t BDD BUSY L Figure 1 1. Timing Diag ram of Read w ith BUSY (M/S[...]

  • Page 13

    CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 13 of 18 Note 34. If t PS is violated, th e busy signal is asse rted on one side o r the other , but there is no g uarantee to which si de BUSY is asserted. Switching W aveforms (continued) ADDRESS MA TCH t PS t BLC t BHC ADDRESS MA TCH t PS t BLC t BHC CE R Va l i d[...]

  • Page 14

    CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 14 of 18 Figure 15. Interrup t Timing Diagrams Notes 35. t HA depends on whi ch enable pi n (CE L or R/W L ) is deasserted first. 36. t INS or t INR depends on which en able pin (CE L or R/W L ) is asserted last. Switching W aveforms (continued) WRITE 7FFF (FFFF for [...]

  • Page 15

    CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 15 of 18 T able 1 . Non-Cont ending Read /Write Inputs Outpu ts CE R/W OE UB LB SEM I/O 9 – I/O 17 I/O 0 – I/O 8 Operation H X X X X H High Z High Z Deselected: Power Down X X X H H H High Z High Z Deselected: Power Down L L X L H H Data In High Z Write to Upper [...]

  • Page 16

    CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 16 of 18 Ordering Information 32K x16 3.3V Asynchron ous Dual-Port SRAM Spee d (ns) Orderin g Co de Pack age Name Package T ype Operating Range 15 CY7C027V-15AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C027V -15 AXC A100 100-Pin Pb-Free Th in Qu ad Flat Pack Co[...]

  • Page 17

    CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 17 of 18 Package Diagram Figure 16. 100-Pin Pb-Free Thin Plastic Quad Fla t Pac k (T QF P) A100 51-85048-*C [+] Feedback[...]

  • Page 18

    Document #: 38-06078 Rev . *B Revised December 09, 2008 Page 18 of 18 All products and c ompany names men tioned in th is document m ay be the tr ademarks o f t h eir respect i v e holders. CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V © Cypress Semicondu ctor Corpor ation, 2001-200 8. The informati on cont ained herein is subject to change with[...]