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Cypress CY7C0852AV manual

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  • Page 1

    FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1 709 • 408-943-2600 Document #: 38-06070 Rev . *H Revised July 29, 2008 Features ■ T rue dual-ported memory cells that allo w simultaneous access of [...]

  • Page 2

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 2 of 32 Logic Block Diagram [1] A 0L –A 17L CLK L ADS L CNTEN L CNTRST L Tr u e RAM Array 18 Addr . Read Back CNTINT L Mask Register Counter/ Address Register CNT/MSK L Address Decode Dual-Ported Interrupt Logic INT L Reset Logic JT AG TDO TMS TCK TDI MRST DQ 9L [...]

  • Page 3

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 3 of 32 Pin Configurations Figure 1. 172-Ball BGA (T op View) 1 23456789 1 0 1 1 1 2 1 3 1 4 A DQ32L DQ30L CNTINTL VSS DQ13L VDD DQ1 1L DQ1 1 R VDD DQ13R VSS CNTINTR DQ30R DQ32R B A0L DQ33L DQ29L DQ17L DQ14L DQ12L DQ9L DQ9R DQ12R DQ14R DQ17R DQ2 9R DQ33R A0R C NC A[...]

  • Page 4

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 4 of 32 Figure 2. 172-Ball BGA (T op View) Pin Configurations (continued) 123456789 1 0 1 1 1 2 1 3 1 4 A DQ32L DQ30L NC VSS DQ13L VDD DQ1 1L DQ1 1R V DD DQ13R V SS NC DQ30R DQ32R B A0L DQ33L DQ 29L DQ17L DQ14L DQ12L DQ9L DQ9R DQ12R DQ14R DQ 17R DQ29R DQ33 R A0R C [...]

  • Page 5

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 5 of 32 Figure 3. 176-Pin Th in Quad Flat Pack (TQ FP) (T op View) Pin Configurations (continued) 132 131 130 129 128 127 126 125 124 123 122 104 121 120 119 118 117 116 115 114 113 112 111 110 109 103 108 107 106 105 NC A 6R A 5R A 4R V DD V SS DQ 35R DQ 34R A 1R [...]

  • Page 6

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 6 of 32 Pin Definitions Lef t Port Right Port Description A 0L –A 17L [1 ] A 0R –A 17R [1] Address Inputs . ADS L [3] ADS R [3] Address Strobe Input . Used as an address qua lifier . This signal shou ld be asserted LOW for the part using the externally supplied[...]

  • Page 7

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 7 of 32 Master Reset The FLEx36 family devices und ergo a complete reset by taking its MRST input LOW . The MRST input can switch asynchro- nously to the clocks. The MRST initializes the intern al burst counters to zero, and the counter mask registers to all ones ([...]

  • Page 8

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 8 of 32 Address Counter and Mask Register Operations This section [10] describes the features only apply to CY7C0850A V/CY7C0851A V/CY7C0852A V devices, but not to the CY7C0853A V device. Each port of these devic es has a programmable burst address coun ter . Th e [...]

  • Page 9

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 9 of 32 Counter Interrupt The counter interrupt (CNTINT ) is asserted LOW when an increment operation results in the unmasked portion of the counter register being a ll “1s.” It is deasse rted HIGH when a n Increment operation results in any o ther value. It is[...]

  • Page 10

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 10 of 32 Figure 4. Counter , Mask, and Mirror Logic Blo ck Diagram [1] From Mask Register Mirror Counter Address Decode RAM Array Wra p 1 0 Increment Logic 1 0 +1 +2 1 0 Wra p Detect From Mask From Counter To Counter Bit 0 Wra p 17 17 17 17 17 1 0 Load / Increment [...]

  • Page 11

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 1 1 of 32 Figure 5. Programmable Co unter-Mask Registe r Operation [1, 12] 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 H H L H 11 0s 1 0 1 0 1 01 00 Xs 1 X 0[...]

  • Page 12

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 12 of 32 IEEE 1 149.1 Serial Boundary Scan (JT AG) [13] Th e CY7C0850A V/CY7C0851A V/CY7C0852A V/CY7C0853A V incorporates an IEEE 1 149.1 serial boundary scan test access port (T AP). The T AP controller f unction s in a manner that does not conflict with t he oper[...]

  • Page 13

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 13 of 32 Maximum Ratings Exceeding maximum ratings [15] may impair the useful life of the device. These user guidelines are not teste d. S torage T emperature .............. .............. .... –65 ° C to + 150 ° C Ambient T emperatur e with Power Applied .....[...]

  • Page 14

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 14 of 32 Figure 6. AC T est Load and Waveforms Switching Characteristics Over the Operating Range Parameter Description -167 -133 -100 Unit CY7C0850A V CY7C0851A V CY7C0852A V CY7C0850A V CY7C0851A V CY7C0852A V CY7C0853A V CY7C0853A V Min Max Min Max Min Max Min M[...]

  • Page 15

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 15 of 32 t OE Output Enable to Data V alid 4.0 4.4 4.7 5.0 ns t OLZ [20, 21] OE to Low Z 0 0 0 0 ns t OHZ [20, 21] OE t o H i g h Z 04 . 004 . 404 . 705 . 0 n s t CD2 Clock to Data V alid 4.0 4.4 4.7 5.0 ns t CA2 Clock to Counter Address V alid 4.0 4.4 NA NA ns t C[...]

  • Page 16

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 16 of 32 JT AG Timing Parameter Description 167/133 /100 Unit Min Max f JT AG Maximum JT AG T AP Controller Freque ncy 10 MHz t TCYC TCK Clock Cycle T ime 100 ns t TH TCK Clock HIGH T ime 40 ns t TL TCK Clock LOW Time 40 ns t TMSS TMS Setup to TCK Clock Rise 10 ns [...]

  • Page 17

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 17 of 32 Switching W aveforms Figure 8. Master Rese t Figure 9. Read Cycle [4, 22, 23, 24, 25] MRST t RSR t RS INACTIVE ACTIVE TMS TDO INT CNTINT t RSF t RSS ALL ADDRESS/ DATA LINES ALL OTHER INPUTS t CH2 t CL2 t CYC2 t SC t HC t SW t HW t SA t HA A n A n+1 CLK CE [...]

  • Page 18

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 18 of 32 Figure 10. Bank Select Read [26, 27] Figure 1 1 . Read -to-Write-to-Read (OE = LOW) [25, 28, 29, 30, 31] Switching W aveforms (continued) Q 3 Q 1 Q 0 Q 2 A 0 A 1 A 2 A 3 A 4 A 5 Q 4 A 0 A 1 A 2 A 3 A 4 A 5 t SA t HA t SC t HC t SA t HA t SC t HC t SC t HC [...]

  • Page 19

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 19 of 32 Figure 12. Read -to-Write-to-Read (OE Cont rolled) [2 5, 28, 30, 31] Figure 13. Read with Address Counter Ad vance [30] Switching W aveforms (continued) t CYC2 t CL2 t CH2 t HC t SC t HW t SW t HA t SA A n A n+1 A n+2 A n+3 A n+4 A n+5 t HW t SW t SD t HD [...]

  • Page 20

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 20 of 32 Figure 14. W rite with Addre ss Counter Advance [31] Figure 15. Disabled-to-R ead-to-Read-to-Read-to-W rite Switching W aveforms (continu ed) t CH2 t CL2 t CYC2 A n A n+1 A n+2 A n+3 A n+4 D n+1 D n+1 D n+2 D n+3 D n+4 A n D n t SAD t HAD t SCN t HCN t SD [...]

  • Page 21

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 21 of 32 Figure 16. Disabled-to-Wri te-to-Read-to-W rite-to-Read Figure 17. Disabled-to- Read-to-Disab led-to-Write Switching W aveforms (continued) CLK CE R/W ADDRESS OE DATA IN A n A n+1 A n+2 A n+3 A n+4 t CL2 t CH2 t CYC2 t SC t HC t HW t SW t SA t HA t CD2 D n[...]

  • Page 22

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 22 of 32 Figure 18. Read-to-Readback -to-Read-to-Read (R/W = HIGH) Switching W aveforms (continued) CLK ADS ADDRESS OE DATA OUT CNTEN COUNTER INTERNAL ADDRESS t CL2 t CH2 t CYC2 A n+1 A n+2 A n+3 A n+4 A n A n+1 Q n+1 Q n+2 Q n+3 t SAD t HAD t SCN t HCN t SA t HA R[...]

  • Page 23

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 23 of 32 Figure 19. Co unter Reset [32, 3 3] Switching W aveforms (continued) CLK ADDRESS INTERNAL CNTEN ADS DATA IN ADDRESS CNTRST R/W DATA OUT A n A m A p A x 0 1 A n A m A p Q 1 Q n Q 0 D 0 t CH2 t CL2 t CYC2 t SA t HA t SW t HW t SRST t HRST t SD t HD t CD2 t C[...]

  • Page 24

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 24 of 32 Figure 20. Readback St ate of Address Counter or Mask Register [35, 36, 37, 38] Switching W aveforms (continued) CNTEN CLK t CH2 t CL2 t CYC2 ADDRESS ADS A n Q x-2 Q x-1 Q n t SA t HA t SAD t HAD t SCN t HCN LOAD ADDRESS EXTERNAL t CD2 INTERNAL ADDRESS A n[...]

  • Page 25

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 25 of 32 Figure 21. Lef t_Port (L _Port) W r ite to Right_Port (R_Port) Read [39, 40, 41 ] Switching W aveforms (continued) t SA t HA t SW t HW t CH2 t CL2 t CYC2 CLK L R/W L A n D n t CKHZ t HD t SA A n t HA Q n t DC t CCS t SD t CKLZ t CH2 t CL2 t CYC2 t CD2 L_PO[...]

  • Page 26

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 26 of 32 Figure 22. Counter In terrupt and Retransmit [34, 42, 43, 44, 45] Switching W aveforms (continued) t CH2 t CL2 t CYC2 CLK 1FFFD 1FF FF INTERNAL ADDRESS Last_Loaded Last_Loade d +1 t HCM COUNTER 1FFFE CNTINT t SCINT t RCINT 1FFFC CNTEN ADS CNT/MSK t SCM Not[...]

  • Page 27

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 27 of 32 Figure 23. MailBox In terrupt T iming [46, 47, 48, 49, 50] T able 7. Read/W rite and Enable Operation (Any Port) [1, 8, 51, 52] Inputs Outputs Op eration OE CLK CE 0 CE 1 R/W DQ 0 – DQ 35 X H X X High-Z Deselected X X L X High-Z Deselected XL H L D IN Wr[...]

  • Page 28

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 28 of 32 Ordering Information 256K × 36 (9M) 3.3V Synchronous CY7C0853A V Dual-Port SRAM Spee d (MHz) Ordering Code Package Diagram Package T ype Operating Range 133 CY7C0853A V-133BBC 51-851 14 172-Ball Grid Array (15 x 15 x 1.25 mm) with 1 mm pitch Commercial CY[...]

  • Page 29

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 29 of 32 Package Diagrams Figure 24. 172-Ball FBGA (15 x 15 x 1.25 mm) (51-85114 ) 51-85114-*B [+] Feedback[...]

  • Page 30

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 30 of 32 Figure 25. 176-Pin Thin Quad Flat Pack (24 × 24 × 1.4 mm) (51-85132) Package Diagrams 51-85132-** [+] Feedback[...]

  • Page 31

    CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V Document #: 38-06070 Rev . *H Page 31 of 32 Document History Page Document Title: CY7C0850A V/CY7C0851A V/CY7C0852A V/CY7C0853A V, FLEx36™ 3.3V 32K/64K/12 8K/256K x 36 Synchronous Dual-Po rt RAM Document Number: 38-06070 REV . ECN NO. Submis- sion Date Orig. of Change Description of Chang e ** 127[...]

  • Page 32

    Document #: 38-06070 Rev . *H Revised July 29, 2008 Page 32 of 32 FLEx36 is a trade mark of Cypr ess Semiconductor Corporatio n. All product and compa ny names mentio ned in this docum ent may be th e tradem arks of thei r respec tive hold ers. CY7C0850A V, CY7C0851A V CY7C0852A V, CY7C0853A V © Cypress Sem iconductor Corp oration, 200 3-2008. The[...]