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Cypress CY7C09179V manual

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Table of contents for the manual

  • Page 1

    CY7C09079V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port S t atic RAM Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-06043 Rev . *C Revised December 10, 2008 Features ■ T rue Dual-Ported memory cells which e nable simultaneous access of the same mem[...]

  • Page 2

    CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 2 of 21 Functional Description The CY7C09079V/89V/99V a nd CY7C 09179V/89V/99V are high speed synchrono us CMOS 32K, 64K, and 128K x 8/9 dual-port static RAMs. T wo ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory .[...]

  • Page 3

    CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 3 of 21 Pin Configurations (continued Figure 2. 100-Pin TQFP (T op View0 - CY7C09199V ( 128K x 9), CY7C09189 V (64K x 9),CY7C09179V (32K x 9) 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 NC[...]

  • Page 4

    CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 4 of 21 Notes 8. This pin is NC for CY7C09179V . 9. This pin is NC for CY7C09179V and CY7C09189V Selection Guide Description CY7C09079V/89V/9 9V CY7C09179V/89V/99V- 6 [1] CY7C09079V/89V/9 9V CY7C09179V/89V/99V-7 [1] CY7C09079V/89V/99V CY7C09179V/89V/99V -9 CY7C09079V/89V/99V C[...]

  • Page 5

    CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 5 of 21 Maximum Ratin gs Exceeding maximum ratings may impair the useful life of the device. These user guid elines are not tested. [10] S torage T emperature .............. .............. ..... –65 ° C to +150 ° C Ambient T emperature wit h Power Appl ied .. –55 ° C to[...]

  • Page 6

    CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 6 of 21 Figure 4. AC T est Loads (Applicable to -6 and -7 only) [13] Figure 5. Load Deratin g Curve Figure 3. AC T est Lo ads (a) Normal Load (Load 1) R1 = 590 Ω 3.3V OUTPUT R2 = 435 Ω C= 3 0 pF V TH =1 . 4 V OUTPUT C= 30 pF (b) Thévenin Equivalent (Load 1) (c) Three-State [...]

  • Page 7

    CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 7 of 21 Notes 14. T est conditions used are Load 2. 15. This parameter is guaranteed by design, but it is not production teste d. Switching Characteristics Over the Operating Range Parameter Descriptio n CY7C09079V/89V/99V CY7C09179V/89V/99V Unit -6 [1] -7 [1] -9 -12 Min Max M[...]

  • Page 8

    CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 8 of 21 Switching W aveforms (continued) Figure 6. Re ad Cycle fo r Flow-Throug h Output (FT /PIPE = V IL ) [16, 17, 18, 19] Notes 16. OE is asynchronously controlled; all other inp uts are synchrono us to the rising clock edg e. 17. ADS = V IL , CNTEN a nd CNTRST = V IH . 18.[...]

  • Page 9

    CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 9 of 21 Figure 7. Read Cycle for Pipe lined Operat ion (FT /PIPE = V IH ) [16, 17, 18, 19] Figure 8. Bank Select Pip elined Read [20, 21 ] - Switching W aveforms (continued) t CH2 t CL2 t CYC2 t SC t HC t SW t HW t SA t HA A n A n+1 CLK CE 0 CE 1 R/W ADDRESS DATA OUT OE A n+2 [...]

  • Page 10

    CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 10 of 21 Figure 9. Lef t Port Write to Flow-Through Right Port Read [22, 23, 24, 25] Notes 20. In this depth expansion example, B1 re pr esents B ank #1 and B2 is Bank #2; Each Ba nk consist s of one Cypress dual-port device from this dat asheet. ADDRESS (B1) = ADDRESS (B2) . [...]

  • Page 11

    CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 1 1 of 21 Figure 10. Pipeline d Read-to-W rite-t o-Read (OE = V IL ) [19, 26, 27, 2 8] Switching W aveforms (continued) t CYC2 t CL2 t CH2 t HC t SC t HW t SW t HA t SA t HW t SW t CD2 t CKHZ t SD t HD t CKLZ t CD2 NO OPERATION WRITE READ READ CLK CE 0 CE 1 R/W ADDRESS DATA IN[...]

  • Page 12

    CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 12 of 21 Figure 1 1. Pipelined R ead-to-W rite-to-Read (OE Controlled) [19, 26, 27, 28] Notes 26. Output state (HIGH, LOW , or high-impedance) is determined by t he previous cycle con trol signals. 27. CE 0 and ADS = V IL ; CE 1 , CNTEN , an d CNTRST = V IH . 28. During “No [...]

  • Page 13

    CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 13 of 21 Figure 12. Flow -Through Read-to-Write-to-Read (OE = V IL ) [17, 19, 26, 27, 28] Figure 13. Flow-Th rough Read-to-W rite-to-Read (OE Controlled) [1 7, 20, 26, 27, 28] Switching W aveforms (continued) t CH1 t CL1 t CYC1 t SC t HC t SW t HW t SA t HA t SW t HW t SD t HD[...]

  • Page 14

    CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 14 of 21 Figure 14. Pipeli ned Read with Addre ss Counter Advance [29] Figure 15. Flow-Th rough Read with Add ress Counter Advance [29] Note 29. CE 0 and OE = V IL ; CE 1 , R/W and CNTRST = V IH . Switching W aveforms (continued) COUNTE R HOLD READ WITH COUNTER t SA t HA t SAD[...]

  • Page 15

    CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 15 of 21 Figure 16. W rite with Address Co unter Advance (Flow-Thro ugh or Pipelined O utput s) [30, 31] Notes 30. CE 0 and R/W = V IL ; CE 1 and CNTRST = V IH . 31. The “Internal Address” is equal to the “External Address” when ADS = V IL and equals th e counter outpu[...]

  • Page 16

    CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 16 of 21 Figure 17. Counter Reset (Pip elined Output s) [19, 26, 32, 33] Notes 32. CE 0 = V IL ; CE 1 = V IH . 33. No dead c ycle exists durin g counter reset. A READ or WRITE cycle ma y be coincidental wit h the counter reset. Switching W aveforms (continued) t CH2 t CL2 t CY[...]

  • Page 17

    CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 17 of 21 T able 1. Read/Write and Enable Operation [34, 35, 36] Input s Ou tputs OE CLK CE 0 CE 1 R/W I/O 0 – I/O 9 Operatio n X H X X High-Z Deselected [37] X X L X High-Z Deselected [37] X L H L D IN Wri te L L H H D OUT Read [37] H X L H X High-Z Outputs Disabled T able 2[...]

  • Page 18

    CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 18 of 21 Ordering Information 32K x8 3.3V Synchronous Du al-Port SRAM Spee d ( ns) Ordering Co de Package Name Package T ype Operating Range 6.5 [1] CY7C09079V -6AC A100 100-Pin Thin Quad Flat Pack Commercial 7.5 [1] CY7C09079V -7AC A100 100-Pin Thin Quad Flat Pack Commercial [...]

  • Page 19

    CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 19 of 21 64K x9 3.3V Synchronous Du al-Port SRAM Speed (ns) Ordering Code Package Name Package T ype Operating Range 6.5 [1] CY7C09189V -6AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09189V -6AXC A100 100-Pin Pb-Free T hin Quad Flat Pack Commercial 7.5 [1] CY7C09189V -7A[...]

  • Page 20

    CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 20 of 21 Package Diagram Figure 18. 100-Pin Thin Plastic Quad Flat Pa ck (TQFP) A100 (51-8504 8) 51-85048-*B [+] Feedback[...]

  • Page 21

    Document #: 38-06043 Rev . *C Revised December 10, 2008 Page 21 of 21 All product s and company names ment ioned in thi s document may be the tra demarks of thei r respective h olders. CY7C09079V/89V/99V CY7C09179V/89V/99V © Cypress Semicondu ctor Corporati on, 2005-2008. The information cont ained herein i s subject to change witho ut notice. Cyp[...]