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Cypress CY7C1218H manual

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Table of contents for the manual

  • Page 1

    1-Mbit (32K x36) Pipelined Sync SRAM CY7C1218H Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05667 Rev . *B Revised July 6, 2006 Features • Registered inp uts and outputs for pipelined op er ation • 32K × 36 common I/O architecture • 3.3V core power supply (V DD ) ?[...]

  • Page 2

    CY7C1218H Document #: 38-05667 Rev . *B Page 2 of 16 Pin Configuration Selection Guide 166 MHz 133 MHz Unit Maximum Access T i me 3.5 4.0 ns Maximum Operating Current 240 225 mA Maximum CMOS S tandby Cu rrent 40 40 mA A A A A A 1 A 0 NC/72M NC/36M V SS V DD NC/18M NC/9M A A A A A NC/2M NC/4M DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V D[...]

  • Page 3

    CY7C1218H Document #: 38-05667 Rev . *B Page 3 of 16 Pin Definitions Name I/O Description A 0 , A 1 , A Input- Synchronous Address Inpu ts used to select one of the 32K addre ss locations . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW , and CE 1 , CE 2 , and CE 3 are sampled active. A 1 , A 0 feed the 2-bit counter . BW A , B[...]

  • Page 4

    CY7C1218H Document #: 38-05667 Rev . *B Page 4 of 16 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled b y the rising edge of the clock. The CY7C1218H supports secondary cache in systems utilizing either a linear or interleave[...]

  • Page 5

    CY7C1218H Document #: 38-05667 Rev . *B Page 5 of 16 Interleaved Burst Address T able (MODE = Floating or V DD ) First Address A 1 , A 0 Second Address A 1 , A 0 Third Address A 1 , A 0 Fourth Address A 1 , A 0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address T ab le (MODE = GND) First Address A 1 , A 0 Second Address A 1 , A 0 [...]

  • Page 6

    CY7C1218H Document #: 38-05667 Rev . *B Page 6 of 16 Continue Write Next L X X X H H H X Tri-S tate Write Continue Write Next L H X X X H H X T ri-S tate Write Suspend Write Current L X X X H H H X Tri-S tate Write Suspend Write Current L H X X X H H X Tri-S tate Write Z Z “ S l e e p ” N o n e H X X X XXXX T r i - S t a t e X T ruth T able for[...]

  • Page 7

    CY7C1218H Document #: 38-05667 Rev . *B Page 7 of 16 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. ... ... ... ... ....... –65 ° C to + 150 ° C Ambient T e mperature with Power Applied ........... ... ... ........... ... ... ... ....... –55 ° C to + 125 ?[...]

  • Page 8

    CY7C1218H Document #: 38-05667 Rev . *B Page 8 of 16 Cap acit ance [10] Parameter Description T est Con dition s 100 TQFP Max. Unit C IN Input Capacit ance T A = 25 ° C, f = 1 MHz, V DD = 3.3V . V DDQ = 2.5V 5p F C CLK Clock Input Capacit ance 5 pF C I/O Input/Output Capa citance 5 pF Thermal Resist ance [10] Parameter Description T est Condition [...]

  • Page 9

    CY7C1218H Document #: 38-05667 Rev . *B Page 9 of 16 Switching Characteristics Over the Operating Range [1 1, 12] Parameter Description 166 MHz 133 MHz Unit Min. Max. Min. Max. t POWER V DD (T ypical) to the First Access [13] 1 1 ms Clock t CYC Clock Cycle T ime 6.0 7.5 ns t CH Clock HIGH 2.5 3.0 ns t CL Clock LOW 2.5 3.0 ns Output Times t CO Data [...]

  • Page 10

    CY7C1218H Document #: 38-05667 Rev . *B Page 10 of 16 Switching W aveforms Read Cycle Timing [17] Note: 17. On this diagram, when CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES GW, BWE, BW [A:D] D ata[...]

  • Page 11

    CY7C1218H Document #: 38-05667 Rev . *B Page 1 1 of 16 Write Cycle Ti ming [17, 18] Note: 18. Full width Write can be initiate d by either GW LOW; or by GW HIGH, BWE LOW and BW [A: D] LOW. Switching W aveforms (continued) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES BWE, BW[A :D] D ata Out (Q) High-Z ADV BURST RE[...]

  • Page 12

    CY7C1218H Document #: 38-05667 Rev . *B Page 12 of 16 Read/Write Cycle Timing [17, 19, 20 ] Notes: 19. The data bus (Q) remains in High-Z following a Write cycle unl ess an ADSP , ADSC , or ADV cycle is performed. 20. GW is HIGH. Switching W aveforms (continued) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A2 t CEH t CES BWE, B[...]

  • Page 13

    CY7C1218H Document #: 38-05667 Rev . *B Page 13 of 16 ZZ Mode T iming [21, 22] Notes: 21. Device must be deselected when entering ZZ mode. See Cycle Descr iptions t able for all possible signal conditions to deselect the device. 22. DQs are in High-Z when exiting ZZ sleep mode. Switching W aveforms (continued) t ZZ I SUPPLY CLK ZZ t ZZREC A LL INPU[...]

  • Page 14

    CY7C1218H Document #: 38-05667 Rev . *B Page 14 of 16 Ordering Information Not all of the speed, package and temperature ranges are av ailable. Please contact your local sales representative or visit www .cyp ress.com for actual products offered. Speed (MHz) Ordering Code Pa ckage Diagram Package T ype Operating Range 100 CY7C1218H-100AXC 51-85050 [...]

  • Page 15

    CY7C1218H Document #: 38-05667 Rev . *B Page 15 of 16 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod uct. Nor do[...]

  • Page 16

    CY7C1218H Document #: 38-05667 Rev . *B Page 16 of 16 Document History Page Document Title: CY7C1218H 1-Mbit (32K x36) Pipelined Sy nc SRAM Document Number: 38-05667 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 343896 See ECN PCI New Data Sheet *A 4 30678 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page#[...]