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Cypress CY7C1257V18 manual

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Table of contents for the manual

  • Page 1

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 36-Mbit DDR-II+ SRAM 2-W ord Burst Architecture (2.0 Cycle Read Latency) Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-06348 Rev . *D Revised March 1 1 , 2008 Features ■ 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36[...]

  • Page 2

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 2 of 27 Logic Block Diagram (CY7C1246V18) Logic Block Diagram (CY7C1257V18) CLK A (20:0) Gen. K K Control Logic Address Register Read Add. Decode Read Data Reg. R/W DQ [7:0] Output Logic Reg. Reg. Reg. 8 8 16 8 NWS [1:0] V REF Write Add. Decode 8 8 LD Control[...]

  • Page 3

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 3 of 27 Logic Block Diagram (CY7C1248V18) Logic Block Diagram (CY7C1250V18) CLK A (19:0) Gen. K K Control Logic Address Register Read Add. Decode Read Data Reg. R/W DQ [17:0] Output Logic Reg. Reg. Reg. 18 18 36 18 BWS [1:0] V REF Write Add. Decode 18 18 LD C[...]

  • Page 4

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 4 of 27 Pin Configurations CY7C1246V18 ( 4M x 8) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout 234 56 7 1 A B C D E F G H J K L M N P R A CQ NC NC NC NC DOFF NC NC/72M A NWS 1 K R/W NC/144M NC NC NC NC NC TDO NC NC NC NC NC NC TCK NC NC A NC/288M K NWS 0 V SS AAA N[...]

  • Page 5

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 5 of 27 Pin Configurations (continued) CY7C1248V18 (2M x 18) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout 234 56 7 1 A B C D E F G H J K L M N P R A CQ NC NC NC NC DOFF NC NC/72M A BWS 1 K R/W NC/144M DQ9 NC NC NC NC TDO NC NC NC NC NC NC TCK NC NC A NC/288M K BWS[...]

  • Page 6

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 6 of 27 Pin Definitions Pin Name IO Pin Description DQ [x:0] Input/Output- Synchronous Data Input/Output Sign al s . Inputs are sampled on the rising edge of K and K clocks during valid write operations . These pins dri ve out the req uested da ta during a re[...]

  • Page 7

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 7 of 27 ZQ Input Output Impedanc e Matching Input . T his input is used to tune t he device outputs to the system data bus impedance. CQ, CQ , and Q [x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alterna ti[...]

  • Page 8

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 8 of 27 Functional Overview The CY7C1246V18, CY7C1257 V18, CY7C1248V18, and CY7C1250V18 are synch ronous pipelined Bu rst SRAMs equipped with a DDR inte rface. Accesses for both ports are initia ted on the Positive Input Clock (K). All synchronous input and o[...]

  • Page 9

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 9 of 27 V alid Data Indicator (QVLD) QVLD is provided on the DDR-II+ to simplify data capture on high speed systems. The QVLD is ge nerated by the DDR-II+ device along with data output. This signal i s also ed ge al igned with the echo clock and follows the t[...]

  • Page 10

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 10 of 27 Write Cycle Descriptions The write cycle descriptions table for CY7C1246V18 and CY7C 1248V18 follows. [2, 8] BWS 0 / NWS 0 BWS 1 / NWS 1 K K Comments L L L–H – During the dat a portion of a write sequence : CY7C1246V18 − both ni bbles (D [7:0] [...]

  • Page 11

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 1 1 of 27 Write Cycle Descriptions The write cycle descriptions ta ble for CY7C1250V18 follows. [2, 8] BWS 0 BWS 1 BWS 2 BWS 3 K K Comments LLLL L - H – D u r i n g t h e d a t a p o r t i o n o f a w r i t e s e q u e n c e , a l l f o u r b y t e s ( D [3[...]

  • Page 12

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 12 of 27 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan test access port (T AP) in the FBGA package. This part is fully compliant with IEEE S tandard #1 149. 1-2001. The T AP operates using JEDEC standard 1.8V IO logi[...]

  • Page 13

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 13 of 27 IDCODE The IDCODE instruction loads a vendor-sp ecific, 32-bit code into the instruction register . It also places the instruction register between the TDI and TDO pins an d shifts the IDCODE out of the device when the T AP controller enters the Shif[...]

  • Page 14

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 14 of 27 T AP Controller St ate Diagram The stat e di a g ram for the T AP controller follows. [9 ] TEST -LOGIC RESET TEST -LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT -DR EXIT1-DR P AUSE-DR EXIT2-DR UPDA TE-DR SELECT IR-SCAN CAPTURE-IR SHIFT -IR EXIT1-IR P A[...]

  • Page 15

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 15 of 27 T AP Controller Block Diagram T AP Electrical Ch aracteristics Over the Operatin g Range [10, 1 1, 12] Parameter Descriptio n T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.0 mA 1.4 V V OH2 Output HIGH V oltage I OH = − 100 ?[...]

  • Page 16

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 16 of 27 T AP AC Switchi ng Characteristics Over the Operatin g Range [13, 14] Parameter Descriptio n Min Max Unit t TCYC TCK Clock Cycle T ime 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK Clock LOW 20 ns Setup Times t TMSS TMS Set[...]

  • Page 17

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 17 of 27 Identification Regi ster Definitions Instruction Field Va l u e Description CY7C1246V18 CY7C1257V1 8 CY7C1248V18 CY7C1 250V18 Revision Number (31:29) 000 000 000 000 V ersion number . Cypress Device ID (28:12) 1 10101 1 1 1000001 1 1 1 1010 1111 0000[...]

  • Page 18

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 18 of 27 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6 P2 9 9 G 5 7 5 B8 5 2 J 2 6N 30 1 1F 58 5A 86 3K 3 7P 31 1 1G 59 4A 8 7 3J 4 7 N3 2 9 F 6 0 5 C8 8 2 K 5 7R 33 10F 61 4B 89 1K 6 8R 34 1 1E 62 3A [...]

  • Page 19

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 19 of 27 Power Up Sequence in DDR-II+ SRAM DDR-II+ SRAMs must be powered up and initialize d in a predefined manner to prevent undefined opera tions. During power up, when the DOFF is tied HIGH, the DLL is locked after 2048 cycles of stable clock. Power Up Se[...]

  • Page 20

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 20 of 27 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guid elines are not tested. S torage T emp erature ............. .............. ..... –65°C to + 150°C Ambient T emperature with Powe r Applied . –55[...]

  • Page 21

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 21 of 27 Cap acit ance T ested initially and after any design or proc ess change that may affect these parameters. Parameter Descriptio n T est Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.8V V DDQ = 1.5V 5p F C CLK Clock In[...]

  • Page 22

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 22 of 27 Switching Characteristics Over the Operatin g Range [20, 21] Cypress Parameter Consortium Parameter Description 375 MH z 333 MHz 300 MHz Unit Min Max Min Max Min Max t POWER V DD (T ypical) to the first Access [2 2] 1–1–1– m s t CYC t KHKH K Cl[...]

  • Page 23

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 23 of 27 Switching W aveforms Read/Write /Deselect Sequence [28, 29, 30] Figure 5. Waveform for 2.0 Cycle Read Latency DON’ T CARE UNDEFINED 1 2 3 4 5 6 7 8 9 10 READ READ READ NOP WRITE WRITE t NOP 11 K K LD R/W A t KH t KL t CYC t HC t SA t HA SC A0 A1 A2[...]

  • Page 24

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 24 of 27 Ordering Information Not all of the speed, package and temperat ure ranges are avail able. Please contact your local sales representative or visit www .cypress.com for actual products offered. Speed (MHz) Ordering Co de Package Diagram Package T ype [...]

  • Page 25

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 25 of 27 300 CY7C1246V18-300 BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial CY7C1257V18-300BZC CY7C1248V18-300BZC CY7C1250V18-300BZC CY7C1246V18-300BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY[...]

  • Page 26

    CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 26 of 27 Package Diagram Figure 6. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195 !  0).#/2.%2 ¼ ¼   [...]

  • Page 27

    Document Number: 001-06348 Rev . *D Revised March 1 1, 2008 Page 27 of 27 All product and company name s mentione d in this docume nt are the tr ademar ks of their res pective holders. CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 © Cypress Semicondu ctor Corpor ation, 2006-2008. The informatio n contai ned herei n is subject to chan ge withou[...]