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Cypress CY7C1334H manual

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Table of contents for the manual

  • Page 1

    2-Mbit (64K x 32) Pipelined SRAM with NoBL™ Architecture CY7C1334H Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05678 Rev . *B Revised February 6, 2006 Features • Pin comp atible and functio nally equivalent to ZBT™ devices • Internally self-time d output buffer co[...]

  • Page 2

    CY7C1334H Document #: 38-05678 Rev . *B Page 2 of 13 . Selection Guide 166 MHz 133 MHz Unit Maximum Access T ime (t CO ) 3.5 4.0 ns Maximum Operating Current (I DD ) 240 225 mA Maximum CMOS S tandby Current 40 40 mA Pin Configuration A A A A A 1 A 0 NC/288M NC/144M V SS V DD NC/36M A A A A A NC/4M NC DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ [...]

  • Page 3

    CY7C1334H Document #: 38-05678 Rev . *B Page 3 of 13 Pin Definitions Name I/O Description A0, A1, A Input- Synchronous Address Inputs used to select one of the 64K address loca tions . Sampled at the rising edge of the CLK. A [1:0] are fed to the two-bit burst counter . BW [A:D] Input- Synchronous Byte Write Inpu ts , active LOW . Qualified with WE[...]

  • Page 4

    CY7C1334H Document #: 38-05678 Rev . *B Page 4 of 13 Functional Overview The CY7C1334H is a synchronous-pipeli ned Burst SRAM designed specifically to el iminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with th e Clock Ena[...]

  • Page 5

    CY7C1334H Document #: 38-05678 Rev . *B Page 5 of 13 Interleaved Burst Address T able (MODE = Floating or V DD ) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address T able (MODE = GND) First Address A1, A0 Second Address A1, A0 Third Address A1, A[...]

  • Page 6

    CY7C1334H Document #: 38-05678 Rev . *B Page 6 of 13 Write Cycl e Description [2, 3] Function WE BW D BW C BW B BW A Read H X X X X Wri t e − No bytes written L H H H H Wri t e B y t e A − (DQ A ) L HHH L Wri t e B y t e B − (DQ B )L H H L H Write Bytes A, B L H H L L Wri t e B y t e C − (DQ C )L H L H H Write Bytes C,A L H L H L Write Byte[...]

  • Page 7

    CY7C1334H Document #: 38-05678 Rev . *B Page 7 of 13 Maximum Rating (Above which the useful life may be impaired. For user guide- lines not tested.) S torage T emperature ......... ............ ........... ..... − 65°C to +150°C Ambient T emperature with Power Applied ....... ........... ........... ........... .......... − 55°C to +125°C S[...]

  • Page 8

    CY7C1334H Document #: 38-05678 Rev . *B Page 8 of 13 Cap acit ance [1 1] Parameter Description T est Con ditions 100 TQFP Max. Unit C IN Input Capacitance T A = 25°C , f = 1 MHz, V DD = 3.3V , V DDQ = 2.5V 5p F C CLK Clock Input Capacitance 5 pF C I/O Input/Output Capacitance 5 pF Thermal Resist ance [1 1] Parameter Description T est Conditions 10[...]

  • Page 9

    CY7C1334H Document #: 38-05678 Rev . *B Page 9 of 13 Switching Characteristics Over the Operating Range [12, 13] 166 MHz 133 MHz Parameter Description Min. Max. Min. Max. Unit t POWER V DD (typical) to the First Access [14] 11 m s Clock t CYC Clock Cycle T ime 6.0 7.5 ns t CH Clock HIGH 2.5 3.0 ns t CL Clock LOW 2.5 3.0 ns Output Times t CO Data Ou[...]

  • Page 10

    CY7C1334H Document #: 38-05678 Rev . *B Page 10 of 13 Switching W aveforms Read/W rite Timing [18, 19, 20] Notes: 18. For this waveform ZZ is tied LOW. 19. When C E is LOW, CE 1 is LOW , C E 2 is HIGH and CE 3 is LOW . When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 20. Order of the Burst sequ ence is determined by the statu s of the [...]

  • Page 11

    CY7C1334H Document #: 38-05678 Rev . *B Page 1 1 of 13 NOP , ST ALL, and Des elect Cyc les [18, 19, 21] ZZ Mode Timing [22, 23] Notes: 21. The IGNORE CLOCK EDGE or ST ALL cycle (Clock 3) illustrated CEN being used to create a p ause. A write is not performed duri ng this cycle. 22. Device must be deselected when entering ZZ mode . See cycle descrip[...]

  • Page 12

    CY7C1334H Document #: 38-05678 Rev . *B Page 12 of 13 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod uct. Nor do[...]

  • Page 13

    CY7C1334H Document #: 38-05678 Rev . *B Page 13 of 13 Document History Page Document Title: CY7C1334H 2-Mbit (64K x 32 ) Pipelined SRAM with NoBL™ Architectu re Document Number: 38-05678 REV . ECN NO. Issue Date Orig. of Change Description of Chang e ** 347357 See ECN PCI New Data Sheet *A 424 820 See ECN RXU Changed address of Cypress Semiconduc[...]