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Cypress CY7C1352G manual

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Table of contents for the manual

  • Page 1

    4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture CY7C1352G Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05514 Rev . *D Revised July 4, 2006 Features • Pin comp atible and functio nally equivalent to ZBT™ devices • Internally self-time d output buffer cont [...]

  • Page 2

    CY7C1352G Document #: 38-05514 Rev . *D Page 2 of 12 Selection Guide 250 MHz 200 MHz 166 MHz 133 MHz Unit Maximum Access T ime 2.6 2.8 3.5 4.0 ns Maximum Operating Current 325 265 240 225 mA Maximum CMOS S tandby Cu rrent 40 40 40 40 mA Pin Configuration A A A A A 1 A 0 NC/288M NC/144M V SS V DD NC/36M A A A A A A A NC NC V DDQ V SS NC DQP A DQ A D[...]

  • Page 3

    CY7C1352G Document #: 38-05514 Rev . *D Page 3 of 12 Pin Definitions Name I/O Description A0, A1, A Input- Synchronous Address Inputs used to select one of the 25 6K address locations . Sampled at the rising edge of the CLK. A [1:0] are fed to the two-bit burst counter . BW [A:B] Input- Synchronous Byte Write Inputs, active LOW . Qualified with WE [...]

  • Page 4

    CY7C1352G Document #: 38-05514 Rev . *D Page 4 of 12 Functional Overview The CY7C1352G is a synchronous-pipelin ed Burst SRAM designed specifically to el iminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with th e Clock Ena[...]

  • Page 5

    CY7C1352G Document #: 38-05514 Rev . *D Page 5 of 12 Interleaved Burst Address T able (MODE = Floating or V DD ) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 1 1 01 00 1 1 10 10 1 1 00 01 1 1 10 01 00 Linear Burst Address T able (MODE = GND) First Address A1, A0 Second Address A1, A0 Third Address A[...]

  • Page 6

    CY7C1352G Document #: 38-05514 Rev . *D Page 6 of 12 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ......... ............ ........... ..... − 65°C to +150°C Ambient T emperature with Power Applied ....... ........... ........... ........... .......... − 55°C to +125°C[...]

  • Page 7

    CY7C1352G Document #: 38-05514 Rev . *D Page 7 of 12 I SB4 Automatic CE Power-down Current—TTL Inputs V DD = Max, Device Deselected, V IN ≥ V IH or V IN ≤ V IL , f = 0 All speeds 45 mA Cap acit ance [1 1] Parameter Description T es t Conditions 100 TQFP Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 3.3V , V DDQ = 3.3V 5p F C[...]

  • Page 8

    CY7C1352G Document #: 38-05514 Rev . *D Page 8 of 12 Switching Characteristics Over the Operating Range [16, 17] Parameter Description –250 –200 –166 –133 Unit Min. Max. Min. Max. Min. Max. Min. Max. t POWER V DD (typical) to the first Access [12] 11 11 m s Clock t CYC Clock Cycle T ime 4.0 5.0 6.0 7.5 n s t CH Clock HIGH 1.7 2.0 2.5 3.0 ns[...]

  • Page 9

    CY7C1352G Document #: 38-05514 Rev . *D Page 9 of 12 Switching W aveforms Read/W rite Timing [18, 19, 20] Notes: 18. For this waveform ZZ is tied low . 19. When C E is LOW: CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW . W h en CE is HIGH: CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 20. Order of the Burst sequ ence is determined by the st atus of the [...]

  • Page 10

    CY7C1352G Document #: 38-05514 Rev . *D Page 10 of 12 NOP , ST ALL, and DESELECT Cycles [18, 19, 21] ZZ Mode Timing [22, 23] Notes: 21. The IG NOR E CLO CK EDG E or ST ALL cycle (Clock 3) illustrated CEN being used to create a p a use. A write is not performed duri ng this cycle. 22. Device must be deselected when entering ZZ mode. See cycle descri[...]

  • Page 11

    CY7C1352G Document #: 38-05514 Rev . *D Page 1 1 of 12 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod uct. Nor d[...]

  • Page 12

    CY7C1352G Document #: 38-05514 Rev . *D Page 12 of 12 Document History Page Document Title: CY7C1352G 4-Mbit (256K x 18) Pipe lined SRAM with NoBL™ Arch itecture Document Number: 38-05514 REV . ECN NO. Issue Date Orig. of Change Description of Ch ange ** 2243 62 See ECN RKF New data sheet *A 288431 See ECN VBL Deleted 100 MHz and 225 MHz Changed [...]