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Cypress CY7C1382C manual

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  • Page 1

    18-Mb (512K x 36/1M x 18) Pipelined SRAM CY7C1380C CY7C1382C Cypress Semiconductor Corpora tion • 3901 North First S treet • San Jose , CA 95134 • 408-943-26 00 Document #: 38-05237 Rev . *D Revised February 26, 2004 Features • Supports bus operation up to 250 MHz • A vailable speed grades are 250, 225, 200,166 and 133MHz • Registered i[...]

  • Page 2

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 2 of 36 1 2 Logic Block Diagram – CY7C1380C (512K x 36) ADDRESS REGISTER ADV CLK BURST COUNTER AND LOGIC CLR Q1 Q0 ADSP ADSC MODE BWE GW CE 1 CE 2 CE 3 OE ENABLE REGISTER OUTPUT REGISTERS SENSE AMPS OUTPUT BUFFERS E PIPELINED ENABLE INPUT REGISTERS A 0, A1, A BW B BW C BW D BW A MEMORY ARRAY [...]

  • Page 3

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 3 of 36 Pin Configurations A A A A A 1 A 0 NC / 72M NC / 36M V SS V DD A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A DQP C DQ C DQc V DDQ V SSQ DQ C DQ C DQ C DQ C V SSQ[...]

  • Page 4

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 4 of 36 Pin Configurations (continued) 234 5 67 1 A B C D E F G H J K L M N P R T U V DDQ NC NC DQP C DQ C DQ D DQ C DQ D AA A A ADSP V DDQ AA DQ C V DDQ DQ C V DDQ V DDQ V DDQ DQ D DQ D NC NC V DDQ V DD CLK V DD V SS V SS V SS V SS V SS V SS V SS V SS NC NC NC NC TDO TCK TDI TMS NC / 36M NC / [...]

  • Page 5

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 5 of 36 Pin Configurations (continued) 165-ball fBGA CY7C1380C (512K x 36) 23 4 567 1 A B C D E F G H J K L M N P R TDO NC / 288M NC DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A CE2 DQ C DQ D DQ D MODE NC DQ C DQ C DQ D DQ D DQ D NC / 36M NC / 72M V DDQ BW D BW A CLK GW V SS V SS V SS V S[...]

  • Page 6

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 6 of 36 CY7C1380C–Pin Definitions Name TQFP BGA fBGA I/O Description A 0 , A 1 , A 37,36,32 , 33,34,35, 42,43,44,45, 46,47,48, 49,50,81, 82,99,100 P4,N4, A2,B2, C2,R2, A3,B3,C3, T3,T4,A5,B5, C5, T5,A6,B6,C6, R6 R6,P6,A2, A10,B2, B10,N6,P3,P4, P8,P9,P10, P1 1,R3,R4,R8, R9,R10,R1 1 Input- Synch[...]

  • Page 7

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 7 of 36 ADSP 84 A4 B9 Input- Synchronous Address Strobe from Proc ess or , sample d on the rising edge of CLK, active LOW . W hen asserted LOW , addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter . When ADSP and ADSC are both a[...]

  • Page 8

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 8 of 36 V SSQ 5,10,21,26,55, 60,71, 76 - - I/O Ground Ground for t he I/O circ uitry . V DDQ 4,1 1,20,27,54, 61,70, 77 A1,F1,J1,M1, U1, A7,F7,J7,M7, U7 C3,C9,D3,D9, E3,E9,F3,F9,G 3, G9,J3,J9, K3,K9,L3, L9,M3,M9,N3, N9 I/O Power Supply Power supply for the I/O ci rcuitry . MODE 31 R3 R1 In put- [...]

  • Page 9

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 9 of 36 CY7C1382C:Pin Definitions Name TQFP BGA fBGA I/O Description A 0 , A 1 , A 37,36,32, 33,34,35, 42,43,44, 45,46,47, 48,49,50, 80,81,82, 99,100 P4,N4, A2,B2, C2,R2, T2,A3, B3,C3, T3,A5, B5,C5, T5,A6, B6,C6, R6,T6 R6,P6,A2, A10,A1 1, B2,B10,P3,P4, N6,P8,P9, P10,P1 1, R3,R4,R8,R9, R10, R1 1[...]

  • Page 10

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 10 of 36 ADSP 84 A4 B9 Input- Synchronous Address Strobe from Process or , sampled on the rising edge of CLK, active LOW . When asserted LOW , addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter . When ADSP and ADSC are both ass[...]

  • Page 11

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 1 1 of 36 V DDQ 4,1 1,20,27,54, 61,70, 77 A1,A7,F1,F7, J1,J7,M1,M7, U1,U7 C3,C9,D3,D9, E3,E9, F3,F9,G3 , G9,J3,J9, K3,K9,L3, L9,M3,M9,N3, N9 I/O Power Sup- ply Power supply for the I/O circu itry . MODE 31 R3 R1 Input- St a t i c Select s B urst Order . When tied to GND selects linear burst seq[...]

  • Page 12

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 12 of 36 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CO ) is 3.0ns (200-MHz device). The[...]

  • Page 13

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 13 of 36 Asserting ADV LOW at clock rise will automatically increment the burst counter to the next ad dress in the burst sequence. Both Read and Write burst operatio ns are supported. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a po wer conservation ?[...]

  • Page 14

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 14 of 36 READ Cycle, Continue Burst Next H X X L X H L H H L-H T ri -S tate WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q READ Cycle, Suspend Burst Current X X X L H H H[...]

  • Page 15

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 15 of 36 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1380C incorporates a seri al boundary scan test access port (T AP). This port ope rates in accordance with IEEE S tandard 1 149.1-1990 but do es not have the set of functions required for full 1 149.1 compliance. These functions from th[...]

  • Page 16

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 16 of 36 TDI and TDO ba lls as show n in the T ap Contro ller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE in struction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in th e pre v i o us section. When[...]

  • Page 17

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 17 of 36 Note that since the PRELOAD part of the command is not implemented, putting the T AP to the Update-DR state while performing a SAMPLE/PRELOAD instruction w ill have the same effect as the Pause-DR command. BYP ASS When the BYP ASS instruction is lo aded in the instruction register and [...]

  • Page 18

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 18 of 36 3.3V T AP AC T est Conditions Input pulse levels ........ . .............. .............. ...........V SS to 3.3V Input rise and fall times ........... ......... .. ............ ........... .......1ns Input timing reference levels ............... .... ............. ........... 1.5V Out[...]

  • Page 19

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 19 of 36 Identification Register Definitions INSTRUCTION FIELD CY7C1380C (512KX36) CY7C1382C (1MX18) DESCRIPTION Revision Number (31:29) 010 0100 Describes the version number . Device Dept h (28:24) 01010 101 0 Reserved for Internal Use Device Wid th (23: 18) 000000 000000 Define s memory type [...]

  • Page 20

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 20 of 36 1 19-Ball BGA Boundary Scan Order CY7C1380C (512K x 36) BIT# BALL ID BIT# BALL ID 1 K4 37 B2 2 H4 38 P4 3M 4 3 9 N 4 4F 4 4 0 R 6 5B 4 4 1 T 5 6A 4 4 2 T 3 7G 4 4 3 R 2 8C 6 4 4 R 3 9A 6 4 5 P 2 10 D6 46 P1 11 D 7 4 7 N 2 12 E6 48 L2 13 G6 49 K1 14 H7 50 N1 15 E7 51 M2 16 F6 52 L1 17 G[...]

  • Page 21

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 21 of 36 CY7C1382C (1M x 18) BIT# BALL ID BIT# BALL ID 1 K4 37 B2 2 H4 38 P4 3M 4 3 9 N 4 4F 4 4 0 R 6 5B 4 4 1 T 5 6A 4 4 2 T 3 7G 4 4 3 R 2 8C 6 4 4 R 3 9 A6 45 Not Bonded (Preset to 0) 10 T6 46 Not Bonded (Preset to 0) 1 1 Not Bonded (Preset to 0) 47 Not Bonded (Preset to 0) 12 Not Bonded (P[...]

  • Page 22

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 22 of 36 165-Ball fBGA Boundary Scan Order CY7C1380C (512K x 36) BIT# BALL ID BIT# BALL ID 1B 6 3 7 N 6 2B 7 3 8 R 6 3A 7 3 9 P 6 4B 8 4 0 R 4 5A 8 4 1 R 3 6B 9 4 2 P 4 7A 9 4 3 P 3 8 B10 44 R1 9 A10 45 N1 10 C1 1 46 L2 11 E 1 0 4 7 K 2 12 F10 48 J2 13 G10 49 M2 14 D10 50 M1 15 D1 1 51 L1 16 E1[...]

  • Page 23

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 23 of 36 CY7C1382C (1M x 18) BIT# BALL ID BIT# BALL ID 0B 6 3 6 N 6 1B 7 3 7 R 6 2A 7 3 8 P 6 3B 8 3 9 R 4 4A 8 4 0 R 3 5B 9 4 1 P 4 6A 9 4 2 P 3 7 B10 43 R1 8 A10 44 Not Bonded (Preset to 0) 9 A1 1 45 Not Bonded (Preset to 0) 10 Not Bonded (Preset to 0) 46 Not Bonded (Preset to 0) 1 1 Not Bo n[...]

  • Page 24

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 24 of 36 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ......................... .. ... ... –65 ° C to +150 ° C Ambient T emp erature with Power Applied .................... ... .............. ........ –55 ° C to +[...]

  • Page 25

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 25 of 36 I SB3 Automatic CE Power-down Current—CMOS Inputs V DD = M ax, Device Deselected, or V IN ≤ 0.3V o r V IN > V DDQ – 0.3V f = f MAX = 1/t CYC 4.0-ns cycle, 250 MHz 105 mA 4.4-ns cycle, 225 MHz 100 mA 5.0-ns cycle, 200 MHz 95 mA 6.0-ns cycle, 167 MHz 85 mA 7.5-ns cycle, 133 MHz [...]

  • Page 26

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 26 of 36 AC T est Loads and W aveforms OUTPUT R = 317 Ω R = 351 Ω 5p F INCLUDING JIG AND SCOPE (a) (b) OUTPUT R L = 50 Ω Z 0 = 50 Ω V L = 1.5V 3.3V ALL INPUT PULSES V DD GND 90% 10% 90% 10% ≤ 1ns ≤ 1ns (c) OUTPUT R = 1667 Ω R =1538 Ω 5p F INCLUDING JIG AND SCOPE (a) (b) OUTPUT R[...]

  • Page 27

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 27 of 36 Switching Characteristics Over the Operating Range [19, 20] Parameter Description 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz Un it Min. Max Min. Max Min. Max t POWER V DD (T ypical) to the first Access [15] 1 1111 ms Clock t CYC Clock Cycle T ime 4.0 4.4 5 6 7.5 ns t CH Clock HIGH 1.7 2.0[...]

  • Page 28

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 28 of 36 Switching W aveforms Read Cycle Timing [21] Notes: 21. On this diagram, when CE is L OW: CE 1 is LOW , CE 2 is HIGH and CE 3 is LOW. When CE is HIGH: CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 22. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW X LOW[...]

  • Page 29

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 29 of 36 Write Cycle T iming [21, 22] Switching W aveforms (continued) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES BWE, BW X D ata Out (Q) High-Z ADV BURST READ BURST WRITE D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A3) D(A3 + 1) D(A3 + 2) D(A2 + 3) A2 A3 Data In (D)[...]

  • Page 30

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 30 of 36 Read/Write Cycle Timing [21, 23, 24 ] Note: 23. The data bus (Q) remain s in high-Z following a WRIT E cycl e, unless a new read access is initiated by ADSP or ADSC . 24. GW is HIGH. Switching W aveforms (continued) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A2 t[...]

  • Page 31

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 31 of 36 Notes: 25. Device must be deselected when ente ring ZZ mode. See Cycle Descr iptions t ab le for all possible signal conditi ons to deselect the device. 26. DQs are in high -Z when exiting ZZ sl eep mode Switching W aveforms (continued) Z Z Mode Timing [25 , 26] t ZZ I SUPPLY CLK ZZ t [...]

  • Page 32

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 32 of 36 Ordering Information Speed (MHz) Ordering Code Pa ckage Name Part and Package T ype Operating Range 250 CY7C1380C-250AC CY7C1382C-250AC A101 100-lead Thin Qu ad Flat Pack (14 x 20 x 1.4mm) Commercial CY7C1380C-250BGC CY7C1382C-250BGC BG1 19 11 9 P B G A CY7C1380C-250BZC CY7C1382C-250BZ[...]

  • Page 33

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 33 of 36 © Cypress Semico nductor Corpor ation, 2004. Th e information cont ained herein is subject to chan ge without noti ce. Cypress Semico nductor Corporation assumes no resp onsibility for the use of any circ uitry other than cir cuitry embodied i n a Cypress Semi conductor product. Nor d[...]

  • Page 34

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 34 of 36 Package Diagrams (continued) 51-851 15-*B 1 1 9-Lead PBGA (14 x 22 x 2.4 mm) BG1 19 [+] Feedback[...]

  • Page 35

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 35 of 36 Package Diagrams (continued) i486 is a trademark, and Intel and Pentium are registered trade marks of Intel Corporation. Po werPC is a trademark of IBM Corporation. All pro duct and company names mentioned in this document are the trademarks of their respective holder s. 165-Ball FBGA [...]

  • Page 36

    CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 36 of 36 Document History Page Document Title: CY7C1380C/CY7C1382C 18-Mb (512K x 36/1M x 18) Pipelined SRAM Document Number: 38-05237 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 1 16277 08/27 /0 2 SKX New Data Sheet *A 1 21540 1 1/21/02 DSG Updated package diagrams 51 -851[...]