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Cypress CY7C1446AV33 manual

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  • Page 1

    36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05383 Rev . *E Revised June 23, 2006 Features • Supports bus operation up to 250 MHz • A vailable speed grades are 250, 20 0 a[...]

  • Page 2

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 2 of 31 Logic Block Diagram – CY7C1440A V33 (1M x 36) ADDRESS REGISTER ADV CLK BURST COUNTER AND LOGIC CLR Q1 Q0 ADSP ADSC MODE BWE GW CE 1 CE 2 CE 3 OE ENABLE REGISTER OUTPUT REGISTERS SENSE AMPS OUTPUT BUFFERS E PIPELINED ENABLE INPUT REGISTERS A 0, A1, A BW B BW C BW [...]

  • Page 3

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 3 of 31 BW D BW C BW B BW A BWE GW CE1 CE2 CE3 OE ENABLE REGISTER PIPELINED ENABLE ADDRESS REGISTER ADV CLK BINARY COUNTER CLR Q1 Q0 ADSP ADSC MODE A 0, A1,A A[1:0] BW F BW E BW H BW G DQs DQP A DQP B DQP C DQP D DQP E DQP F DQP G DQP H OUTPUT REGISTERS MEMORY ARRAY OUTPUT[...]

  • Page 4

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 4 of 31 Pin Configurations DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A DQP C DQ C DQc V DDQ V SSQ DQ C DQ C DQ C DQ C V SSQ V DDQ DQ C DQ C V DD NC V SS DQ D DQ [...]

  • Page 5

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 5 of 31 Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.4 m m) Pinout CY7C1440A V33 (1M x 36) 234 56 7 1 A B C D E F G H J K L M N P R TDO NC/288M NC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A CE2 DQ C DQ D DQ D MODE NC DQ C DQ C DQ D DQ D DQ D A NC/[...]

  • Page 6

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 6 of 31 209-ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1446A V33 (512K × 72) Pin Configurations (continued) A B C D E F G H J K L M N P R T U V W 123456789 1 1 10 DQ G DQ G DQ G DQ G DQ G DQ G DQ G DQ G DQ C DQ C DQ C DQ C NC DQP G DQ H DQ H DQ H DQ H DQ D DQ D DQ D DQ D DQ[...]

  • Page 7

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 7 of 31 CE 2 Input- Synchronous Chip Enable 2 Inpu t, active HIGH . Sampled o n the rising edge of CLK. Used in conjunction with CE 1 and CE 3 to select/desele ct the device. CE 2 is sampled only when a new external address is loaded. CE 3 Input- Synchronous Chip Enable 3 [...]

  • Page 8

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 8 of 31 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CO ) is 2.6ns [...]

  • Page 9

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 9 of 31 Interleaved Burst Address T able (MODE = Floating or V DD ) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 1 1 01 00 1 1 10 10 1 1 00 01 1 1 1 0 01 00 Linear Burst Address T able (MODE = GND) First Address A1: A0 Seco[...]

  • Page 10

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 10 of 31 READ Cycle, Suspend Burst Current X X X L H H H H H L-H T ri-S tate READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q READ Cycle, Suspend Burst Current H X X L X H H H H L-H T ri-S tate WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D WRITE Cycle[...]

  • Page 11

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 1 1 of 31 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1440A V33/CY7C1442A V33/CY7C1446A V33 incor- porates a serial boundary scan test access port (T AP). This part is fully compliant with IEEE St andard 1 149.1. The T AP operates using JEDEC-standard 3. 3V or 2.5V I[...]

  • Page 12

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 12 of 31 Performing a T AP Re set A RESET is performed by forcing TMS HIGH (V DD ) for five rising edges of TCK. This RESE T does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the T AP is reset in ternally to ensure tha[...]

  • Page 13

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 13 of 31 The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, whil e data captured is shifted out, the preloaded data can be shifted in. BYP ASS When the BYP ASS instruction is loaded in the instruction register and the T A[...]

  • Page 14

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 14 of 31 3.3V T AP AC T est Conditions Input pulse levels ........... ........ ............ ........... ..... V SS to 3.3V Input rise and fall times ........... ........... .... ........... ........... ....1ns Input timing reference levels ................. .. ............[...]

  • Page 15

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 15 of 31 T AP DC Electrical Characteristics And Ope rating Conditions (0°C < T A < +70°C; V DD = 3.135 to 3.6V unless otherwise no ted) [12] Parameter Des cription T est Conditions Min. Ma x. Unit V OH1 Output HIGH V oltage I OH = –4.0 mA, V DDQ = 3.3V 2.4 V I OH[...]

  • Page 16

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 16 of 31 Notes: 14. Balls that are NC (No Connect) are preset LOW . 15. Bit# 89 is preset HIGH. SAMPLE/PRELOAD 100 Captu res I/O ring contents. Pl aces the boundary scan regi ster betwe en TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use: This instruct [...]

  • Page 17

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 17 of 31 Note: 16. Bit# 138 is preset HIGH. 209-ball FBGA Boundary Scan Order [14, 16] CY7C1446A V33 (512K x 72) Bit # ball ID Bit # ball ID Bit # ball ID Bit # ball ID 1 W6 36 F6 71 H6 106 K3 2 V6 37 K8 72 C6 107 K4 3 U6 38 K 9 73 B6 108 K6 4 W7 39 K10 74 A6 109 K2 5V 7 4[...]

  • Page 18

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 18 of 31 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ...... –65°C to +150°C Ambient T emperature with Power Applied ........... ............................ ...... [...]

  • Page 19

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 19 of 31 Cap acit ance [19] Parameter Description T est Cond itions 100 TQFP Max. 165 FBGA Max. 209 FBGA Max. Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.3V V DDQ = 2.5V 6.5 7 5 pF C CLK Clock Input Capacitance 3 7 5 pF C I/O Input/Output Capacitance 5.5[...]

  • Page 20

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 20 of 31 Switching Characteristics Over the Operating Range [24, 25] Parameter De scription –250 –200 –1 67 Unit Min. Max Min. Max. Min. Max t POWER V DD (T ypical) to the first Access [20] 111m s Clock t CYC Clock Cycle T ime 4.0 5 6 ns t CH Clock HIGH 1.5 2.0 2.4 n[...]

  • Page 21

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 21 of 31 Switching W aveforms Read Cycle Timing [26] Note: 26. On this diagram, when CE is LOW: CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH: CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t C[...]

  • Page 22

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 22 of 31 Write Cycle T iming [26, 27] Note: 27. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW X LOW. Switching W aveforms (continued) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES BWE, BW X D ata Out (Q[...]

  • Page 23

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 23 of 31 Read/Write Cycle Timing [26, 28, 29 ] Notes: 28. The data bus (Q) remains in high-Z foll owing a W rite cycle, unless a new read access is initiated by ADSP or ADSC . 29. GW is HIGH. Switching W aveforms (continued) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE [...]

  • Page 24

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 24 of 31 ZZ Mode T iming [30, 31] Notes: 30. Device must be deselected when entering ZZ mode. See Cycle Descr iptions table for all possible signal conditions to deselect the device. 31. DQs are in high-Z when e xiting ZZ sleep mode. Switching W aveforms (continued) t ZZ I[...]

  • Page 25

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 25 of 31 Ordering Information Not all of the speed, package and temperature ranges are available. Please con tact your local sale s rep resentative or visit www .cypress.com for actual pro duct s offered. Spee d (MHz) Ordering Code Package Diagram Part and Package T ype Op[...]

  • Page 26

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 26 of 31 250 C Y7C1440A V33-250AXC 51-85050 100-Pi n Thi n Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1442A V33-250AXC CY7C1440A V33-250BZC 51-85165 165-ball Fine -Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1442A V33-250BZC CY7C1440A V33-250BZXC 51-85165 [...]

  • Page 27

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 27 of 31 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE[...]

  • Page 28

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 28 of 31 Package Diagrams (continued) A 1 PIN 1 CORNER 17.00±0.10 15.00±0.10 7.00 1.00 Ø0.45±0.05(165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35 1.40 MAX. SEATING PLANE 0.53±0.05 0.25 C 0.15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10.00 14.00 B C D E[...]

  • Page 29

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 29 of 31 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodie[...]

  • Page 30

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 30 of 31 Document History Page Document Title: CY7C1440 A V33/CY7C1442A V33/CY7C1446A V33 36 -Mbit (1M x 36/2M x 18/51 2K x 72) Pipelined Sync SRAM Document Number: 38-05383 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 124437 03/04/03 C JM New dat a sh[...]

  • Page 31

    CY7C1440A V33 CY7C1442A V33 CY7C1446A V33 Document #: 38-05383 Rev . *E Page 31 of 31 *E 473650 See ECN VKN Added the Ma ximum Rating for Supply V oltage on V DDQ Re lative to GND. Changed t TH , t TL from 25 ns to 20 ns and t TDOV from 5 ns to 10 ns in T AP AC Switching Characteristics table. Updated the Ordering Information table. Document Title:[...]