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Cypress CY7C145 manual

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Table of contents for the manual

  • Page 1

    CY7C145, CY7C144 8K x 8/9 Dual-Port S t atic RAM with SEM, INT , BUSY Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-06034 Rev . *D Revised December 1 0, 2008 Features ■ T rue Dual -Ported memory cells that enable simultaneous reads of the same memory location ■ 8K x 8 orga[...]

  • Page 2

    CY7C145, CY7C144 Document #: 38-06034 Rev . *D Page 2 of 21 Pin Configurations Figure 1. 68-Pin PLCC (T op View) Figure 2. 64-Pin PLCC (T op View) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 67 60 59 58 57 56 55 54 53 52 51 50 49 48 3 1 3 2 3 33 43 53 63 73 83 94 04 14 24 3 5 4 3 2 1 6 8 6 66 56 46 36 2 6 1 A A 4L A 3L A 2L A 1L A 0L INT L BUSY L [...]

  • Page 3

    CY7C145, CY7C144 Document #: 38-06034 Rev . *D Page 3 of 21 Figure 3. 80- Pin TQFP Pin Configurations (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 37 36 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 44 45 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 64 65 63 62 61 /O 2L[...]

  • Page 4

    CY7C145, CY7C144 Document #: 38-06034 Rev . *D Page 4 of 21 Maximum Ratin gs Exceeding maximum ratings may impair the useful life of the device. These user guid elines are not tested. [5] S torage T emperature ........ ......... ........... ......... − 65 ° C to +150 ° C Ambient T emperature with Power Applied ..... ......... ......... ........[...]

  • Page 5

    CY7C145, CY7C144 Document #: 38-06034 Rev . *D Page 5 of 21 Electrical Characteristics Over the Operating Range (continued) Parameter Description T est Conditions 7C144-35 7C145-35 7C144-55 7C145-55 Unit Min Max Min Max V OH Output HIGH V oltage V CC = Min., I OH = − 4.0 mA 2.4 2.4 V V OL Output LOW V oltage V CC = Min., I OL = 4.0 mA 0.4 0.4 V V[...]

  • Page 6

    CY7C145, CY7C144 Document #: 38-06034 Rev . *D Page 6 of 21 Figure 4. AC T est Loads and Waveforms 3.0V GND 90% 90% 10% ≤ 3n s ≤ 3 ns 10% ALL INPUT PULSES (a) Normal Load (Load 1) 5V OUTPUT C= 3 0 pF V TH = 1.4V OUTPUT C = 30pF (b) Th évenin Equivalent (Load 1) (c) Three-State Delay (Load 3) C= 3 0p F OUTPUT Load (Loa d 2) 5V OUTPUT C= 5p F R1[...]

  • Page 7

    CY7C145, CY7C144 Document #: 38-06034 Rev . *D Page 7 of 21 t SD Data Set-Up to Write End 10 15 15 25 ns t HD Data Hold From Write End 0 0 0 0 ns t HZWE [1 1,12] R/W LOW to High Z 10 15 2 0 25 n s t LZWE [1 1,12] R/W HIGH to Low Z 3 3 3 3 ns t WDD [13] Wr ite Puls e to Dat a Delay 30 50 60 70 ns t DDD [13] W r ite Data V ali d to Read Data V alid 2[...]

  • Page 8

    CY7C145, CY7C144 Document #: 38-06034 Rev . *D Page 8 of 21 Switching W aveforms Figure 5. Read Cycle No. 1 (Either Por t Address Access) [15, 16] Figure 6. Read Cycle No. 2 (Either Port CE /OE Access) [15, 17, 18] Figure 7. Re ad Ti ming with Port- to-Port Delay (M/S =L ) [19, 20] Notes 15. R/W is HIGH for read cycle. 16. Device is continuously se[...]

  • Page 9

    CY7C145, CY7C144 Document #: 38-06034 Rev . *D Page 9 of 21 Figure 8. Write Cycle No. 1: OE Three-S tate Dat a I/Os (Either Port) [21, 22, 23] Figure 9. Write Cycle No. 2: R/W Three-S t ate Data I/Os (Either Port) [21, 23, 24 ] Notes 21. The internal write time of the memory is def ined by the overlap of CE or SEM LOW and R/W LOW . Both signals mus[...]

  • Page 10

    CY7C145, CY7C144 Document #: 38-06034 Rev . *D Page 10 of 21 Figure 10. Semaphore Read After Write T iming, Either Side [25] Figure 1 1. Semaphore Conte ntion [26, 27, 28] Notes 25. CE = HIG H for the duration of the abov e timing (both writ e and read cycle). 26. I/O 0R = I/O 0L = LOW (request semaphore); CE R = CE L = HIGH 27. Semapho res are res[...]

  • Page 11

    CY7C145, CY7C144 Document #: 38-06034 Rev . *D Page 1 1 of 21 Figure 12. Read with BUSY (M/S=HIGH) [20] Figure 13. Write Ti ming with Busy Input (M/S =LOW) Switching W aveforms (continued ) VALID t DDD t WDD MATCH MATCH R/W R DATAIN R DATA OUTL t WC ADDRESS R t PWE VALID t SD t HD ADDRESS L t PS t BLA t BHA t BDD BUSY L t PWE R/W BUSY t WB t WH [+][...]

  • Page 12

    CY7C145, CY7C144 Document #: 38-06034 Rev . *D Page 12 of 21 Figure 14. Busy Timing Diagram No. 1 (CE Arbitration) [29] Figure 15. Busy Timing Diagram No. 2 (Address Arbitration) [29] Note: 29. If t PS is violated, the busy signal will be asserted on one side o r the other , but there is no guarantee on which side BUSY will b e asserted Switching W[...]

  • Page 13

    CY7C145, CY7C144 Document #: 38-06034 Rev . *D Page 13 of 21 Figure 16. Interrupt Timing Diagrams Notes 30. t HA depends on which enable pin (CE L or R/W L ) is deasserted first. 31. t INS or t INR depends on which enable p in (CE L or R/W L ) is asserted last. Switching W aveforms (continued ) WRITE 1FFF t WC t HA Left Side Sets INT R : ADDRESS L [...]

  • Page 14

    CY7C145, CY7C144 Document #: 38-06034 Rev . *D Page 14 of 21 Architecture The CY7C1 44/5 consi sts of a an arra y of 8K words of 8/9 bi ts each of dual-port RAM cells, I/O and a ddress lines, and control signals (CE , OE , R/W ). These control pins pe rmit independent access for re ads or writes to any location in memory . T o handle simultaneous w[...]

  • Page 15

    CY7C145, CY7C144 Document #: 38-06034 Rev . *D Page 15 of 21 T able 3. Non-Cont ending Read /Write Input s Outputs CE R/W OE SEM I/O 0 − 7/8 Operation H X X H High Z Power-Down H H L L Data Out Read Data in Semaphore X X H X H igh Z I/O Lines Disabled H X L Data In Write to Semaphore LHL H D a t a O u t R e a d LL X H D a t a I n W r i t e L X X [...]

  • Page 16

    CY7C145, CY7C144 Document #: 38-06034 Rev . *D Page 16 of 21 Figure 17. T ypical DC and AC Chara cteristics 1.4 1.0 0.4 4.0 4.5 5.0 5. 5 6.0 − 55 25 125 1.2 1.0 120 80 0 1.0 2.0 3.0 4.0 OUTPUT SOURCE CURR ENT (mA) SUPPLY VOLTAGE (V) NORMALIZED SUPPLY CURRENT vs. SUPPL Y VOLTAGE NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE AMBIENT TEMPERATURE[...]

  • Page 17

    CY7C145, CY7C144 Document #: 38-06034 Rev . *D Page 17 of 21 Ordering Information 8K x8 Dual-Port SRAM Speed (ns) Ordering C ode Package Name Package T ype Operating Range 15 CY7C144-15 AC A65 64-Pin Th in Quad Flat Pack Commercial CY7C144-15AXC A65 64-Pin Pb-Free Thin Quad Flat Pack CY7C144-15JC J81 6 8-Pin Plastic Leaded Chip Carrier CY7C144-15JX[...]

  • Page 18

    CY7C145, CY7C144 Document #: 38-06034 Rev . *D Page 18 of 21 8K x9 Dual-Port SRAM Speed (ns) Ordering Code Package Name Package T ype Operating Range 15 CY7C145-15AC A80 80-Pin Thin Quad F lat Pack Commercial CY7C145-15AXC A80 80-Pin Pb-Free Thin Quad F lat Pack CY7C145-15JC J81 68-Pin Plastic Leaded Chip Carrier 25 CY7C145-25AC A80 80-Pin Thin Qua[...]

  • Page 19

    CY7C145, CY7C144 Document #: 38-06034 Rev . *D Page 19 of 21 Package Diagrams Figure 18. 64-Pin Th in Plastic Quad Fl at Pack (14 x 14 x 1.4 mm ) A65 (5 1-85046) 51-85046-* C [+] Feedback[...]

  • Page 20

    CY7C145, CY7C144 Document #: 38-06034 Rev . *D Page 20 of 21 Figure 19. 80-Pin Thi n Plasti c Quad Flat Pack A80 (51-850 65) Figure 20. 68-Pin Plastic Lead ed Chip Carrier J81 (51-8 5005) 51-85065-* B 51-85005-* A [+] Feedback[...]

  • Page 21

    Document #: 38-06034 Rev . *D Revised December 10, 2008 Page 21 of 21 All product s and company names ment ioned in thi s document may be the tra demarks of thei r respective h olders. CY7C145, CY7C144 © Cypress Semicondu ctor Corporati on, 2005-2008. The information cont ained herein i s subject to change witho ut notice. Cypress S emiconductor C[...]