English dropdown-ico

Cypress CY7C2565KV18 manual

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

Go to page of

Similar user manuals

A good user manual

The rules should oblige the seller to give the purchaser an operating instrucion of Cypress CY7C2565KV18, along with an item. The lack of an instruction or false information given to customer shall constitute grounds to apply for a complaint because of nonconformity of goods with the contract. In accordance with the law, a customer can receive an instruction in non-paper form; lately graphic and electronic forms of the manuals, as well as instructional videos have been majorly used. A necessary precondition for this is the unmistakable, legible character of an instruction.

What is an instruction?

The term originates from the Latin word „instructio”, which means organizing. Therefore, in an instruction of Cypress CY7C2565KV18 one could find a process description. An instruction's purpose is to teach, to ease the start-up and an item's use or performance of certain activities. An instruction is a compilation of information about an item/a service, it is a clue.

Unfortunately, only a few customers devote their time to read an instruction of Cypress CY7C2565KV18. A good user manual introduces us to a number of additional functionalities of the purchased item, and also helps us to avoid the formation of most of the defects.

What should a perfect user manual contain?

First and foremost, an user manual of Cypress CY7C2565KV18 should contain:
- informations concerning technical data of Cypress CY7C2565KV18
- name of the manufacturer and a year of construction of the Cypress CY7C2565KV18 item
- rules of operation, control and maintenance of the Cypress CY7C2565KV18 item
- safety signs and mark certificates which confirm compatibility with appropriate standards

Why don't we read the manuals?

Usually it results from the lack of time and certainty about functionalities of purchased items. Unfortunately, networking and start-up of Cypress CY7C2565KV18 alone are not enough. An instruction contains a number of clues concerning respective functionalities, safety rules, maintenance methods (what means should be used), eventual defects of Cypress CY7C2565KV18, and methods of problem resolution. Eventually, when one still can't find the answer to his problems, he will be directed to the Cypress service. Lately animated manuals and instructional videos are quite popular among customers. These kinds of user manuals are effective; they assure that a customer will familiarize himself with the whole material, and won't skip complicated, technical information of Cypress CY7C2565KV18.

Why one should read the manuals?

It is mostly in the manuals where we will find the details concerning construction and possibility of the Cypress CY7C2565KV18 item, and its use of respective accessory, as well as information concerning all the functions and facilities.

After a successful purchase of an item one should find a moment and get to know with every part of an instruction. Currently the manuals are carefully prearranged and translated, so they could be fully understood by its users. The manuals will serve as an informational aid.

Table of contents for the manual

  • Page 1

    72-Mbit QDR™-II+ SRAM 4-W ord Burst Architecture (2.5 Cycle Read Latency) with ODT PRELIMINARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1 709 • 408-943-2600 Document Number: 001-15887 Rev . *E Revised April 24, 2009 Features ■ Separate independent r[...]

  • Page 2

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 2 of 29 Logic Block Diagram (CY7C2561KV18) Logic Block Diagram (CY7C2576KV18) 2M x 8 Array CLK A (20:0) Gen. K K Control Logic Address Register D [7:0] Read Add. Decode Read Data Reg. RPS WPS Control Logic Address Register Reg. Reg. Reg. 16 2[...]

  • Page 3

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 3 of 29 Logic Block Diagram (CY7C2563KV18) Logic Block Diagram (CY7C2565KV18) 1M x 18 Array CLK A (19:0) Gen. K K Control Logic Address Register D [17:0] Read Add. Decode Read Data Reg. RPS WPS Control Logic Address Register Reg. Reg. Reg. 36[...]

  • Page 4

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 4 of 29 Pin Configuration The pin configuration for CY7C2561KV18, CY7C 2576 KV18, CY7C2563KV18, and CY7C2565KV18 follow . [2] 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C2561KV18 (8M x 8) 123456789 10 11 A CQ AA W P S NWS 1 K NC/144M RPS AA C[...]

  • Page 5

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 5 of 29 CY7C2563KV18 (4M x 18) 123456789 10 11 A CQ NC/144M A WPS BWS 1 K NC/288M RPS AA C Q B NC Q9 D9 A NC K BWS 0 AN C N C Q 8 C NC NC D10 V SS AN CA V SS NC Q7 D8 D NC D1 1 Q10 V SS V SS V SS V SS V SS NC NC D7 E NC NC Q1 1 V DDQ V SS V S[...]

  • Page 6

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 6 of 29 T able 2. Pin Definitions Pin Name IO Pin Descripti on D [x:0] Input- Synchronous Data Input Signals . Sampled on the rising edge of K and K clocks when valid write operations are active. CY7C2561KV18 − D [7:0] CY7C2576KV18 − D [8[...]

  • Page 7

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 7 of 29 K Input Clock Positive Input Clock Input . The rising edge of K is used to capture synchronous inputs to the device and to dri ve out data through Q [x:0] . All accesses are in itiated on th e rising edge of K. K Input Clock Negative [...]

  • Page 8

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 8 of 29 Functional Overview The CY7C2561KV18, CY7C257 6KV18, CY7C2563KV18, CY7C2565KV18 are synchronous pipelined Burst SRAMs equipped with a read port and a write p ort. The read port is dedicated to read operatio ns and the write port is d [...]

  • Page 9

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 9 of 29 Read access and write access must be scheduled such th at one transaction is initiated on any clock cycle. If both port s are selected on the same K clock rise, th e arbitration depends on the previous state of the SRAM. If both ports[...]

  • Page 10

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 10 of 29 Application Example Figure 1 shows two QDR-II+ used in an application. Figure 1. Application Example T able 3. T ru th T abl e The truth table for CY7C2561KV18, CY7C2576KV 18, CY7C2563KV18, and CY7C2565KV18 follo ws. [4, 5, 6, 7, 8, [...]

  • Page 11

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 1 1 of 29 T able 4. Write Cycle Descriptions The write cycle description table for CY7C2561KV18 and CY7C2563KV18 fo llows. [4, 12] BWS 0 / NWS 0 BWS 1 / NWS 1 K K Comments L L L–H – During the data portion of a write sequence : CY7C2561KV[...]

  • Page 12

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 12 of 29 T able 6. Write Cycle Descriptions The write cycle description tabl e for CY7C2565KV18 follows. [4, 1 2] BWS 0 BWS 1 BWS 2 BWS 3 K K Comments LLLL L – H – D u r i n g t h e d a t a p o r t i o n o f a w r i t e s e quence, all fo[...]

  • Page 13

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 13 of 29 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA package. This part is fully complia nt with IEEE S t andard #1 149.1 -2001. The T AP o perates using JEDEC [...]

  • Page 14

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 14 of 29 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister . It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the T AP controlle[...]

  • Page 15

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 15 of 29 Figure 2. T AP Controller St ate Diagram The stat e diagram for the T AP controller follows. [13] TEST -LOGIC RESET TEST -LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT -DR EXIT1-DR P AUSE-DR EXIT2-DR UPDA TE-DR 1 0 1 1 0 1 0 1 0 0 0 1 [...]

  • Page 16

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 16 of 29 Figure 3. T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [14, 15, 16] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V olt age I OH = − 2.0 mA 1.4 V V OH2 Output HIGH V[...]

  • Page 17

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 17 of 29 T AP AC Switching Characteristics Over the Operating Range [17, 18] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK Clock LOW 20 ns Setup Times t[...]

  • Page 18

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 18 of 29 T able 7. Identification Register Definitions Instruction Field Va l u e Description CY7C2561KV18 CY7C2576KV18 CY7 C2563KV18 CY7C2565KV18 Revision Numb er (31:29) 000 000 000 000 V ersion number . Cypress Device ID (28:12) 1 1010010 [...]

  • Page 19

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 19 of 29 T able 10. Boundary Scan Ord er Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bum p ID 0 6R 28 10G 56 6A 84 1J 1 6 P2 9 9 G 5 7 5 B8 5 2 J 2 6N 30 1 1F 58 5A 86 3K 3 7P 31 1 1G 59 4A 87 3J 4 7 N3 2 9 F 6 0 5 C8 8 2 K 5 7R 33 10F 61[...]

  • Page 20

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 20 of 29 Power Up Sequence in QDR-II+ SRAM QDR-II+ SRAMs must be powered up and initialized in a predefined manner to prevent unde fined operation s. Power Up Sequence ■ Apply power and drive DOFF either HIGH or LOW (All other inputs can be[...]

  • Page 21

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 21 of 29 Maximum Ratings Exceeding maximum ratin gs may impair the useful life of the device. These user guidelines are not teste d. S torage T emperature ..................... ............ –65°C to +150°C Ambient T empe rature with Pow e[...]

  • Page 22

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 22 of 29 I SB1 Automatic Power down Current Max V DD , Both Ports Deselected, V IN ≥ V IH or V IN ≤ V IL f = f MAX = 1/t CYC , Inputs S tatic 550 MHz (x8) 380 mA (x9) 380 (x18) 380 (x36) 380 500 MHz (x8) 360 mA (x9) 360 (x18) 360 (x36) 36[...]

  • Page 23

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 23 of 29 AC T est Loads and W aveforms 1.25V 0.25V R = 50 Ω 5p F INCLUDING JIG AND SCOPE ALL INPUT PULSES Device R L = 50 Ω Z 0 = 50 Ω V REF = 0.75V V REF = 0.75V [24] 0.75V Under Te s t 0.75V Device Under Te s t OUTPUT 0.75V V REF V REF O[...]

  • Page 24

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 24 of 29 Switching Characteristics Over the Operating Range [24, 25] Cypress Parameter Consorti um Parameter Description 550 MHz 500 MHz 450 MH z 400 MHz Unit Min Max Min Max Min Max Min Max t POWER V DD (T ypical) to the First Access [26] 11[...]

  • Page 25

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 25 of 29 Switching W aveforms Read/Writ e/Deselect Sequence [32, 33, 34] Figure 6. W aveform for 2.5 Cycle Read Latency t KH t KL t CYC t KHKH t t t t SA HA SC HC t HD t SC t HC A0 A1 A2 A3 t t SD HD t SD D1 1 D10 D12 D13 D30 D31 D32 D33 D A [...]

  • Page 26

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 26 of 29 Ordering Information The following table lists all possible speed, package and temperat ure range options supported fo r these devi ces. Note that some options listed may not be availabl e for order entry . T o verify th e availabi l[...]

  • Page 27

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 27 of 29 450 CY7C256 1KV18-450BZC 51-851 80 165-Ball Fine Pi tch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C2576KV18-450BZC CY7C2563KV18-450BZC CY7C2565KV18-450BZC CY7C2561KV18-450BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x[...]

  • Page 28

    PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 28 of 29 Package Diagram Figure 7. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø 0 . 2 5MCAB Ø0.05 M C B A 0.15(4X) 0.35±0.06 SEATING PLANE 0.53±0.05 0.25 C 0.15 C PIN 1 CORN[...]

  • Page 29

    Document Number: 001-15887 Rev . *E Revised April 24, 2009 Page 29 of 29 QDR RAMs an d Quad Dat a Rate RAMs co mprise a ne w family of products d eveloped by Cy press, IDT , NEC, Re nesas, and Sam sung. All pr oduct and co mpany names mentione d in this do cument are the tr ademark s of their re specti ve holders . PRELIMIN ARY CY7C2561KV18, CY7C25[...]